Semiconductor structure and forming method thereof

Abstract

The method includes patterning the stacked layers to form a first multilayer stack and a second multilayer stack, each including a plurality of sacrificial layers and a plurality of nanostructures positioned alternately. The second multilayer stack is wider than the first multilayer stack. A nanosheet transistor is formed based on the first multilayer stack. The nanosheet transistor includes: a first channel region having a first width; and a first gate stack on the first channel region. A nanowire transistor is formed based on the second multilayer stack. The nanowire transistor includes: a second channel region narrower than the first channel region; and a second gate stack on the second channel region. The embodiment of the invention also relates to a semiconductor structure and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] Technological advancements in integrated circuit (IC) materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation. During the development of ICs, typically the functional density (e.g., the number of interconnect devices per chip area) has increased while the geometric dimensions have decreased. This scaling process generally provides benefits by increasing production efficiency and reducing related costs.

[0003] This scaling has also increased the complexity of processing and manufacturing ICs. To achieve these advancements, similar developments in IC processing and manufacturing are needed. For example, gate-all-around (GAA) transistors have been introduced to replace planar transistors. The structure of GAA transistors and methods of manufacturing GAA transistors are under development. Summary of the Invention

[0004] Some embodiments of the present application provide a method of forming a semiconductor structure, including: patterning a stacked layer to form a first multi-layer stack and a second multi-layer stack, each including a plurality of sacrificial layers and a plurality of nanostructures alternately positioned, wherein the second multi-layer stack is wider than the first multi-layer stack; forming a nanosheet transistor based on the first multi-layer stack, wherein the nanosheet transistor includes: a first channel region having a first width; and a first gate stack located on the first channel region; and forming a nanowire transistor based on the second multi-layer stack, wherein the nanowire transistor includes: a second channel region narrower than the first channel region; and a second gate stack located on the second channel region.

[0005] Some other embodiments of the present application provide a semiconductor structure, including: a bulk semiconductor substrate; a nanosheet transistor located above the bulk semiconductor substrate, wherein the nanosheet transistor includes: a first channel region, wherein an upper one of the first channel region overlaps with a lower one of the first channel region; and a first gate stack located on the first channel region; and a nanowire transistor located above the bulk semiconductor substrate, wherein the nanowire transistor includes: a second channel region narrower than the first channel region, wherein an upper one of the second channel region overlaps with a lower one of the second channel region; and a second gate stack located on the second channel region.

[0006] Some additional embodiments of the present application provide a semiconductor structure, comprising: a nanowire transistor, comprising: a protruding structure, comprising: a plurality of channel regions; and a plurality of dielectric regions located between the plurality of channel regions; a first source / drain region and a second source / drain region located on opposite sides of the plurality of channel regions and the plurality of dielectric regions and joined to the plurality of channel regions and the plurality of dielectric regions; and a gate stack located on the protruding structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be increased or decreased arbitrarily.

[0008] Figures 1 - 4 to Figure 14A - 1 、 Figure 14A - 2 、 Figure 14B - 1 、and Figure 14B - 2 show views of intermediate stages in the formation of nanosheet transistors and nanowire transistors according to some embodiments;

[0009] Figure 15A - 1 、 Figure 15A - 2 、 Figure 15B - 1 、and Figures 15B - 2 to 17A - 1 、 Figure 17A - 2 、 Figure 17B - 1 、and Figure 17B - 2 show views of intermediate stages in the formation of nanosheet transistors and nanowire transistors according to alternative embodiments;

[0010] Figures 18 - 21 show a top view of some nanowires and nanosheets according to some embodiments;

[0011] Figure 22 show a circuit schematic of a static random access memory (SRAM) cell according to some embodiments;

[0012] Figure 23 show some nanosheet transistors having different channel widths according to some embodiments;

[0013] Figure 24 show some nanowire transistors having different channel widths according to some embodiments;

[0014] Figure 25 show a process flow for forming nanosheet transistors and nanowire transistors according to some embodiments. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming the first component above or on the second component may include embodiments where the first component and the second component are in direct contact, and may also include embodiments where additional components may be formed between the first component and the second component such that the first component and the second component may not be in direct contact. Additionally, the present invention may repeat reference numerals and / or letters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Moreover, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to easily describe the relationship of one element or component to another (or other) element or component as shown in the figures. In addition to the orientation shown in the figures, spatially relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0017] A hybrid structure including a nanosheet (NS) transistor and a nanowire (NW) transistor and a method of forming the same are provided. According to some embodiments of the present invention, the nanosheet transistor and the nanowire transistor share some common formation processes. The thickness of the nanowire in the nanowire transistor is increased by epitaxially growing a semiconductor material. By forming a hybrid structure in a circuit, the chip area occupied is reduced without sacrificing circuit performance.

[0018] The embodiments discussed herein are intended to provide examples to enable the making or using of the subject matter of the present disclosure, and those of ordinary skill in the art will readily understand that modifications can be made while remaining within the scope contemplated by the different embodiments. Throughout the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. Although method embodiments may be discussed as being implemented in a particular order, other method embodiments may be implemented in any logical order.

[0019] Figures 1 to 14A - 1 、 Figure 14A - 2 、 Figure 14B - 1 、and Figure 14B - 2 A cross-sectional view showing an intermediate stage in the formation of a hybrid structure including a nanosheet transistor and a nanowire transistor according to some embodiments of the present invention is shown. The corresponding processes are also schematically reflected in the process flow shown in Figure 25 as well.

[0020] Referring to Figure 1, a perspective view of the wafer 10 is shown. The wafer 10 includes a multi-layer structure, and the multi-layer structure includes a multi-layer stack 22 on a substrate 20. According to some embodiments, the substrate 20 is a semiconductor substrate, which can be a silicon substrate, a silicon germanium (SiGe) substrate, etc., while other substrates and / or structures can be used, such as semiconductor-on-insulator (SOI), strained SOI, silicon germanium-on-insulator, etc. The substrate 20 can be doped as a p-type semiconductor, although in other embodiments, it can be doped as an n-type semiconductor.

[0021] According to some embodiments, the multi-layer stack 22 is formed by a series of deposition processes for depositing alternating materials. The corresponding process is shown as process 202 in the process flow 200 shown in Figure 25 . According to some embodiments, the multi-layer stack 22 includes a first layer 22A formed of a first semiconductor material and a second layer 22B formed of a second semiconductor material different from the first semiconductor material.

[0022] According to some embodiments, the first semiconductor material of the first layer 22A is formed of SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, etc., or includes SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, etc. According to some embodiments, the deposition of the first layer 22A (e.g., SiGe) is carried out by epitaxial growth, and the corresponding deposition method can be vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low-pressure CVD (LPCVD), atomic layer deposition (ALD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), etc. According to some embodiments, the first layer 22A is formed to have a first thickness in the range between about and about . However, any suitable thickness within the scope of the embodiments can be used.

[0023] Once the first layer 22A is deposited over the substrate 20, a second layer 22B is deposited over the first layer 22A. According to some embodiments, the second layer 22B is formed of a second semiconductor material such as Si, SiGe, Ge, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations thereof, etc., or includes a second semiconductor material such as Si, SiGe, Ge, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations thereof, etc., where the second semiconductor material is different from the first semiconductor material of the first layer 22A. For example, according to some embodiments where the first layer 22A is silicon germanium, the second layer 22B can be formed of silicon, and vice versa. It should be understood that any suitable combination of materials can be used for the first layer 22A and the second layer 22B.

[0024] According to some embodiments, the second layer 22B is grown epitaxially on the first layer 22A using a deposition technique similar to that used to form the first layer 22A. According to some embodiments, the second layer 22B is formed to have a thickness similar to that of the first layer 22A. The second layer 22B can also be formed to have a thickness different from that of the first layer 22A. According to some embodiments, for example, the second layer 22B has a thickness in the range between about 4 nm and 7 nm, while the second layer 22B has a thickness in the range between about 8 nm and 12 nm.

[0025] Once the second layer 22B is formed over the first layer 22A, the deposition process is repeated to form the remaining layers in the multi-layer stack 22 until the desired topmost layer of the multi-layer stack 22 is formed. According to some embodiments, the first layers 22A have the same or similar thicknesses to each other, and the second layers 22B have the same or similar thicknesses to each other. The first layer 22A can also have the same thickness or a different thickness from the thickness of the second layer 22B. According to some embodiments, the first layer 22A is removed in a subsequent process and is alternatively referred to as the sacrificial layer 22A throughout the description. According to an alternative embodiment, the second layer 22B is sacrificial and is removed in a subsequent process.

[0026] According to some embodiments, there are some pad oxide layer and hard mask layer (not shown) formed over the multi-layer stack 22. These layers are patterned and are used for subsequent patterning of the multi-layer stack 22.

[0027] Referring Figure 2 , a portion of the multi-layer stack 22 and the underlying substrate 20 are patterned in an etching process to form trenches 23. The corresponding process is in Figure 25The process flow 200 shown therein shows the process as process 204. The trench 23 extends into the substrate 20. The remaining part of the multi-layer stack is hereinafter referred to as the multi-layer stack 22'. Below the multi-layer stack 22', some parts of the substrate 20 are left, hereinafter referred to as the substrate strip 20'. The multi-layer stack 22' includes semiconductor layers 22A and 22B. Hereinafter, the semiconductor layer 22A may alternatively be referred to as the sacrificial layer, and the semiconductor layer 22B may alternatively be referred to as the nanostructure. The part of the multi-layer stack 22' and the underlying substrate strip 20' are collectively referred to as the semiconductor strip 24.

[0028] In the embodiment shown above, the GAA transistor structure can be patterned by any suitable method. For example, one or more lithography processes, including double patterning or multiple patterning processes, can be used to pattern the structure. Generally, double patterning or multiple patterning processes can combine lithography and self-alignment processes, allowing the creation of patterns with smaller pitch, for example, compared to the pitch obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a lithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-alignment process. Then the sacrificial layer is removed, and the remaining spacers can then be used to pattern the GAA structure.

[0029] Figure 3 The formation of the isolation region 26 is shown, which is also referred to as the shallow trench isolation (STI) region throughout the description. The corresponding process is shown as process 206 in the Figure 25 process flow 200 shown therein. The STI region 26 may include a liner oxide (not shown), which may be a thermal oxide formed by thermal oxidation of the surface layer of the substrate 20. The liner oxide may also be a deposited silicon oxide layer formed using, for example, ALD, high-density plasma chemical vapor deposition (HDPCVD), CVD, etc. The STI region 26 may also include a dielectric material over the liner oxide, where the dielectric material can be formed using flowable chemical vapor deposition (FCVD), spin coating, HDPCVD, etc. Then a planarization process such as a chemical mechanical polishing (CMP) process or a mechanical grinding process can be implemented to planarize the top surface of the dielectric material, and the remaining part of the dielectric material is the STI region 26.

[0030] Then, the STI region 26 is recessed such that the top of the semiconductor strip 24 protrudes above the top surface 26T of the remaining portion of the STI region 26 to form a protruding fin 28. The protruding fin 28 includes the top of the multi-layer stack 22' and the substrate strip 20'. The recessing of the STI region 26 can be implemented by a dry etching process, where, for example, NF3 and NH3 are used as etching gases. During the etching process, a plasma may be generated. Argon may also be included. According to an alternative embodiment of the present invention, the recessing of the STI region 26 is implemented by a wet etching process. The etching chemical can include, for example, HF.

[0031] Next, Figure 4 Two device regions 100-NS and 100-NW are shown, which are respectively used to form nanosheet transistors and nanowire transistors, both also referred to as all-around gate transistors. The structures formed in the device regions 100-NS and 100-NW can share the same formation process, including Figures 1 to 3 the processes shown in. The width W1 of the multi-layer stack 22' in the device region 100-NS is greater than the width W2 of the multi-layer stack 22' in the device region 100-NW. Accordingly, the thickness and material in the device region 100-NS can be the same as those of the corresponding components in the device region 100-NW.

[0032] According to some embodiments, the width W1 (also referenced Figure 5A - 2 ) can be in the range between about 8 nm and about 30 nm, and can be within the range between about 8 and about 13 nm. The width W2 (also referenced Figure 5B - 2 ) can be in the range between about 4 nm and about 6 nm. According to some embodiments, the ratio W1 / W2 can be in the range between about 1.5 and about 7.5.

[0033] Further referring to Figure 4 , a dummy gate stack 30 and gate spacers 38 are formed on the top surface and sidewalls of the (protruding) fin 28. The corresponding process is shown as process 208 in the process flow 200 shown in Figure 25 . The dummy gate stack 30 can include a dummy gate dielectric 32 and a dummy gate electrode 34 located above the dummy gate dielectric 32. The dummy gate dielectric 32 can be formed by oxidizing a surface portion of the protruding fin 28 to form an oxide layer, or by depositing a dielectric layer such as a silicon oxide layer. For example, polysilicon or amorphous silicon can be used, and other materials such as amorphous carbon can also be used, to form the dummy gate electrode 34.

[0034] Each pseudo-gate stack 30 may further include one (or more) hard mask layers 36 located above the pseudo-gate electrode 34. The hard mask layer 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, or a multi-layer thereof. The pseudo-gate stack 30 may pass through a single or multiple protruding fins 28 and the STI region 26 between the protruding fins 28. The pseudo-gate stack 30 also has a length direction perpendicular to the length direction of the protruding fins 28. The formation of the pseudo-gate stack 30 includes forming a pseudo-gate dielectric layer, depositing a pseudo-gate electrode layer above the pseudo-gate dielectric layer, depositing one or more hard mask layers, and then patterning the formed layers through a patterning process.

[0035] Next, a gate spacer 38 is formed on the sidewalls of the pseudo-gate stack 30. According to some embodiments of the present invention, the gate spacer 38 is formed of a dielectric material such as silicon nitride (SiN), silicon oxide (SiO), silicon carbide (SiC), silicon dioxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), etc., and may have a single-layer structure or a multi-layer structure including multiple dielectric layers. The formation process of the gate spacer 38 may include depositing one or more dielectric layers and then performing an anisotropic etching process on the dielectric layers. The remaining part of the dielectric layer is the gate spacer 38.

[0036] Figure 5A - 1 and Figure 5A - 2 shows Figure 4 a cross-sectional view of the structure shown in the device region 100-NS, where a nanosheet transistor will be formed. Figure 5A - 1 shows Figure 4 the reference cross-section CL-CL (where "CL" represents the channel length) in, which cross-section passes through the protruding fin 28. Figure 5A - 2 shows Figure 4 the reference cross-section GL-GL (where "GL" represents the gate longitudinal direction) in, which reference cross-section is parallel to the gate length direction. Throughout the description, the figures with graphic numbers including "A-1" or "A-2" are obtained from the device region 100-NS and are obtained from the cross-sections CL-CL and GL-GL, respectively. The figures with graphic numbers including "B-1" or "B-2" are obtained from the device region 100-NW and are obtained from the cross-sections CL-CL and GL-GL, respectively.

[0037] Reference Figure 5A - 1 , Figure 5A - 2 , Figure 5B - 1 , and Figure 5B - 2 , the portion of the protruding fin 28 ( Figure 4 ) that is not directly located below the pseudo-gate stack 30 and the gate spacer 38 is recessed through an etching process to form a recess 42. The corresponding process is inFigure 25 The process shown in Figure 25 is shown as process 210 in process flow 200. For example, a mixture of C2F6, CF4, SO2, HBr, Cl2, and O2, a mixture of HBr, Cl2, O2, and CH2F2, etc. can be used to perform a dry etching process to etch the multi-layer semiconductor stack 22' and the underlying substrate strip 20'. The bottom of the recess 42 is at least flush with the bottom of the multi-layer semiconductor stack 22', or can be lower than the bottom of the multi-layer semiconductor stack 22'. The etching can be anisotropic such that the sidewalls of the multi-layer semiconductor stack 22' facing the recess 42 are vertical and straight.

[0038] In Figure 4 the X-axis, Y-axis, and Z-axis are marked. The X-axis, Y-axis, and Z-axis are also marked in subsequent figures to clearly see the orientation of the components.

[0039] Figure 6A - 1 and Figure 6A - 2 shows the formation of the hard mask 39 in the device region 100-NS. The corresponding process is shown as process 212 in process flow 200 shown in Figure 25 According to some embodiments, the hard mask 39 is deposited as a blanket layer and can be formed using a conformal deposition process such as ALD, CVD, etc. Then a patterning process is performed to remove the portion of the hard mask 39 in the device region 100-NW, leaving the hard mask 39 in the device region 100-NS. The hard mask 39 can be formed of Al2O3, TiO2, TiN, etc., or can be formed of a low-k dielectric material such as SiOCN.

[0040] Next, the sacrificial semiconductor layer 22A in the device region 100-NW is removed by an isotropic etching process, leaving the structure shown in Figure 6B - 1 and Figure 6B - 2 The corresponding process is shown as process 214 in process flow 200 shown in Figure 25 The etching is performed through the recess 42. The space left by the removed sacrificial semiconductor layer 22A is the gap 41 between the nanostructures 22B.

[0041] The etching of the sacrificial semiconductor layer 22A can be achieved by a dry etching process or a wet etching process using an etchant that is more selective for the material of the sacrificial semiconductor layer 22A (e.g., silicon germanium (SiGe)) than for the materials of the nanostructures 22B and the substrate 20 (e.g., silicon (Si)). For example, in an embodiment where the sacrificial semiconductor layer 22A is formed of silicon germanium and the nanostructures 22B are formed of silicon, an etchant such as hydrochloric acid (HCl) can be used to perform a wet etching process. The wet etching process can be performed using an immersion process, a spraying process, a spin coating process, etc.

[0042] Reference Figure 7B - 1 and Figure 7B - 2 ,by selective epitaxy, an epitaxial semiconductor layer 44 is grown on the exposed semiconductor material. The corresponding process is shown as process 216 in the process flow 200 shown in Figure 25 . Accordingly, the semiconductor layer 44 is formed on the nanostructure 22B. The material of the semiconductor layer 44 may be the same as or different from the material of the nanostructure 22B. Accordingly, the semiconductor layer 44 may or may not be distinguishable from the nanostructure 22B. The thickness of the semiconductor layer 44 is well controlled, and the semiconductor layer 44 cannot be too thick or too thin. If the semiconductor layer 44 is too thick, there is a risk of adjacent channels contacting each other. If the semiconductor layer 44 is too thin, the subsequently formed replacement gate stack may extend between adjacent semiconductor layers 44, resulting in an increase in parasitic capacitance. The thickness of the semiconductor layer 44 may be in the range between about 1.5 nm and about 3.5 nm.

[0043] According to some embodiments, the semiconductor layer 44 is a silicon layer that contains little or no germanium, for example, where germanium has an atomic percentage of less than about 1%. The semiconductor layer 44 may also include germanium, for example, where the germanium atomic percentage is in the range between 0% and 100%, and includes 0% and 100%. In the structure shown in Figure 7B - 2 , the semiconductor layer 44 is formed on the upper and lower surfaces of the semiconductor nanostructure facing the recess 41.

[0044] The epitaxy is selective, and the semiconductor layer 44 is not formed on the exposed dielectric materials including the gate spacer 38 and the hard mask 36. This is achieved by adding an etching gas such as HCl to the precursor gas for epitaxy. Selective deposition can also be implemented by performing an etch-back process after deposition. Deposition and etch-back processes can also be implemented, including multiple repeated deposition and etch-back cycles. An etch-back process can also be performed using an etching gas such as HCl. Accordingly, the semiconductor layer 44 does not grow on the hard mask 39, and during and after the epitaxy, the device region 100-NS may also have a structure the same as that shown in Figure 6A - 1 and Figure 6A - 2 .

[0045] Figure 8A - 1 , Figure 8A - 2 , Figure 8B - 1 , and Figure 8B - 2 show the deposition of the dielectric layer 46 according to some embodiments. The corresponding process is shown as process 218 in the process flow 200 shown in Figure 25 . The dielectric layer 46 may include silicon oxide, silicon oxycarbide, silicon oxynitride, etc. The formation process may include a conformal deposition process, such as ALD, CVD, etc.

[0046] In device region 100-NS, as shown in Figure 8A - 1 and Figure 8A - 2 , a dielectric layer 46 is conformally formed on a hard mask 36. As shown in Figure 8B - 1 and Figure 8B - 2 , the dielectric layer 46 includes a portion that fills the recesses / gaps 41 ( Figure 7B - 1 ), and also includes some other portions on the exposed dielectric material.

[0047] In a subsequent process, an isotropic etching process is implemented to etch the dielectric layer 46. The corresponding process is shown as process 220 in process flow 200 shown in Figure 25 . Accordingly, as shown in Figure 9A - 1 and Figure 9A - 2 , a portion of the dielectric layer 46 in device region 100-NS is removed, and the hard mask layer 39 is exposed.

[0048] In device region 100-NW, as shown in Figure 9B - 1 and Figure 9B - 2 , at least most or all of the portion of the dielectric layer 46 in the gap between the semiconductor layers 44 (and nanostructures 22B) remains as a discrete dielectric layer (also referred to as dielectric layer 46), while the portion of the dielectric layer 46 outside the gap is removed. The etching process can be implemented by dry etching or wet etching, and the etching chemical is selected to etch the dielectric layer 46 but not the gate spacers 38 and the hard mask 36. For example, when the dielectric layer 46 includes silicon oxide, a mixture of NF3 and NH3 or a mixture of HF and NH3 can be used to implement dry etching. When wet etching is used, an HF solution can be used.

[0049] Depending on the control of the etching process, some portions of the dielectric layer 46 in the gap between the semiconductor layers 44 can be recessed to form recesses. The dashed line 47 ( Figure 9B - 1 ) schematically shows the position of the outer surface of the dielectric layer 46 when the dielectric layer 46 is recessed. The dielectric layer 46 can be recessed less than, equal to, or greater than the thickness of the sidewall portions of the semiconductor layers 44.

[0050] Figure 10A - 1 and Figure 10A - 2 show the removal of the hard mask layer 39 in device region 100-NS, for example, by a wet etching process or a dry etching process. The corresponding process is shown as process 222 in process flow 200 shown in Figure 25 . The sidewalls of the sacrificial layer 22A and the nanostructures 22B are thus exposed. The structure in device region 100-NW is shown in Figure 10B - 1 and 10B-2 .

[0051] Refer to Figure 11B - 1 andFigure 11B - 2 , a protection region 51 is formed. The formation process may include depositing the protection region 51 into both the device regions 100-NS and 100-NW, and removing a portion of the protection region 51 in the device region 100-NS, leaving a portion in the device region 100-NW. The corresponding process is shown as process 224 in the process flow 200 shown in Figure 25 . According to some embodiments, the protection region 51 may be formed of silicon nitride, or other materials different from the exposed materials of the structure shown in Figure 11A - 1 and Figure 11A - 2 . The top surface of the protection region 51 may have a height difference in the range of about 5 nm to about 10 nm higher than the topmost surface of the nanostructure 22B. If the height difference is too large, it will be more difficult to remove the protection region 51 in subsequent processes.

[0052] After forming the protection region 51 to protect the device region 100-NW, an internal spacer 50-NS is formed, as shown in Figure 11A - 1 and Figure 11A - 2 . The corresponding process is shown as process 226 in the process flow 200 shown in Figure 25 . According to some embodiments, for example, through an isotropic etching process, the process may be a dry etching process or a wet etching process, to recess the sacrificial layer 22A in the device region 100-NS to form a lateral recess.

[0053] The lateral recess of the sacrificial semiconductor layer 22A can be achieved by a wet etching process using an etchant that is more selective for the material of the sacrificial semiconductor layer 22A (e.g., silicon germanium (SiGe)) than for the materials of the nanostructure 22B and the substrate 20 (e.g., silicon (Si)). For example, in an embodiment where the sacrificial semiconductor layer 22A is formed of silicon germanium and the nanostructure 22B is formed of silicon, an etchant such as hydrochloric acid (HCl) can be used to perform the wet etching process. The wet etching process can be performed using an immersion process, a spraying process, a spin coating process, etc.

[0054] Then the internal spacer 50-NS is formed. According to some embodiments, the formation of the internal spacer 50-NS includes depositing a conformal dielectric layer that extends into the lateral recess. Next, an etching process (also referred to as a spacer trimming process) is performed to trim a portion of the spacer layer outside the lateral recess, leaving a portion of the spacer layer in the lateral recess. The remaining portion of the spacer layer is referred to as the internal spacer 50-NS. Then the protection layer 51 is removed. According to some embodiments, when the internal spacer 50-NS is formed in the device region 100-NS, no internal spacer is formed in the device region 100-NW.

[0055] After removing the protective layer 51, a structure for epitaxy is prepared by implementing a cleaning process configured to remove the oxide on the future channel region. The exterior of the semiconductor layer 44 on the sidewalls of the nanostructure 22B can also be removed / recessed (refer to Figure 11B - 1 ). For example, an HF gas can be used to implement the cleaning process. During the cleaning process, the dielectric layer 46 can also be slightly recessed, for example, recessed by about 1 nm and about 2 nm. The structure obtained in the device region 100-NW will be as shown in Figure 12B - 1 and Figure 12B - 2 .

[0056] When implementing the cleaning process, the structure in the device region 100-NS is as shown in Figure 12A - 1 and Figure 12A - 2 , and this structure is substantially the same as the structure shown in Figure 11A - 1 and Figure 11A - 2 .

[0057] Figure 13A - 1 and Figure 13A - 2 show the formation of the source / drain regions 48-NS in the device region 100-NS, Figure 13B - 1 and Figure 13B - 2 show the formation of the source / drain regions 48-NW in the device region 100-NW. The source / drain regions can refer to the source or the drain individually or jointly, depending on the context. The corresponding process is shown as process 230 in the process flow 200 shown in Figure 25 .

[0058] When the source / drain regions 48-NS and 48-NW are n-type regions, they can include silicon or SiC and n-type dopants such as As, P, Sb, etc., or combinations thereof. For example, the n-type source / drain regions 48-NS and 48-NW can include SiAs, SiP, SiCP, SiAsP, SiSb, etc. When the source / drain regions 48-NS and 48-NW are p-type regions, they can include silicon, SiGe, or Ge, and also include p-type dopants such as boron, indium, or combinations thereof. For example, the p-type semiconductor layers 48-NS and 48-NW can include SiGeB, GeB, etc.

[0059] The source / drain regions 48-NS and 48-NW can be formed by an epitaxial process. Additionally, when the source / drain regions 48-NS and 48-NW have the same conductivity type, the source / drain regions 48-NS and 48-NW can be grown epitaxially by the same epitaxial process. According to some embodiments, the source / drain regions 48-NS and 48-NW can include multiple sub-layers, such as L0, L1, L2, etc., where different sub-layers have different compositions. For example, the concentration of the n-type or p-type dopant (depending on the conductivity type) in the sub-layer L0 can be lower than the concentration of the n-type or p-type dopant in the sub-layer L1.

[0060] As Figure 13B - 1 and Figure 13B - 2 shown in, the source / drain region 48-NW can contact the dielectric layer 46 to form an interface. According to some embodiments, the interface can be recessed and covered by the overlying nanostructure 22B, and / or overlap with the underlying nanostructure 22B. Accordingly, the source / drain region 48-NW (e.g., sub-layer L0) can extend slightly between the overlying and underlying semiconductor layers 44. Figure 13B - 1 Region 54 is shown, into which the source / drain region 48-NW can extend. The extension distance can be equal to, slightly greater than, or slightly less than the lateral dimension of the inner spacer 50-NS ( Figure 13A - 1 ). According to an alternative embodiment, the interface between the source / drain region 48-NW and the dielectric layer 46 can be vertically aligned with the outer edge of the nanostructure 22B.

[0061] According to some embodiments, the semiconductor layer 44 and the nanostructure 22B together act as the channel region of the transistor obtained in the device region 100-NW, collectively referred to as the nanostructure (or channel region) 22B'. Due to the skin effect, the current density in the semiconductor layer 44 and the nanostructure 22B can be higher. Therefore, it may be advantageous to form a germanium-containing semiconductor layer 44 in terms of conducting higher currents.

[0062] Figure 14A - 1 、 Figure 14A - 2 、 Figure 14B - 1 、and Figure 14B - 2 show the formation of the contact etch stop layer (CESL) 66 and the interlayer dielectric (ILD) 68. The corresponding process is in Figure 25The process flow 200 shown therein shows it as process 232. CESL 66 can be formed of silicon oxide, silicon nitride, silicon carbonitride, etc., and can be formed using CVD, ALD, etc. The ILD 68 can include a dielectric material formed using, for example, FCVD, spin coating, CVD, or any other suitable deposition method. The ILD 68 can be formed of an oxygen-containing dielectric material, which can be silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0063] A planarization process such as a CMP process or a mechanical polishing process is implemented to planarize the top surface of the ILD 68. According to some embodiments, the planarization process can remove the hard mask 36 to expose the pseudo-gate electrode 34, or can stop on the hard mask 36. According to some embodiments, after the planarization process, the pseudo-gate electrode 34 (or the hard mask 36, Figure 13A - 1 , Figure 13A - 2 , Figure 13B - 1 , and Figure 13B - 2 ), the gate spacers 38, and the top surface of the ILD 68 are flush within the process variation range.

[0064] Then, in one or more etching processes, the pseudo-gate electrode 34 (and the hard mask 36, if any remains) and the pseudo-gate dielectric 32 in the device region 100-NS are removed to form recesses. In the device region 100-NS, each recess exposes and / or covers a portion of the multi-layer stack 22' (refer to Figure 13A - 1 and Figure 13A - 2 ), which includes the future channel regions in the subsequently completed nano-FETs. The corresponding process is shown as process 234 in the process flow 200 shown in Figure 25 . The portion of the multi-layer stack 22' that serves as the channel region is located between adjacent pairs of the epitaxial source / drain regions 48-NS.

[0065] Then, by etching, the recesses extend downward between the nanostructures 22B by removing the sacrificial layer 22A. As can be appreciated from Figure 13A - 2 , after removing the pseudo-gate dielectric 32 and the pseudo-gate electrode 34, the sidewalls of the sacrificial layer 22A are exposed, so the sacrificial layer 22A can be removed.

[0066] In the device region 100-NW, the pseudo-gate stack 30 shown in Figure 13B - 1 and Figure 13B - 2 is also removed. The sidewalls of the dielectric layer 46 and the semiconductor layer 44 can be exposed. The semiconductor layer 44 can be slightly recessed or not recessed, and due to its small material and thickness, it can not be removed.

[0067] Next, a replacement gate stack is formed as shown in Figure 14A - 1 , Figure 14A - 2 , Figure 14B - 1 , and Figure 14B - 2 . The corresponding process is shown as process 236 in process flow 200 shown in Figure 25 . As shown in Figure 14A - 1 and Figure 14A - 2 , a dielectric 60 including an IL and a high-k dielectric layer (not shown separately) is formed, which extends into the recess formed due to the removal of the dummy gate stack 30 and the sacrificial layer 22A. According to some embodiments, the IL is formed of silicon oxide, which can be formed by an oxidation process or a deposition process. The high-k dielectric layer is conformally deposited, for example, by a conformal deposition process such as ALD, CVD, etc. The high-k dielectric layer can be formed of a high-k dielectric material or include a high-k dielectric material, which can have a k value greater than about 7.0 and can include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof.

[0068] A gate electrode 62 is deposited over the high-k dielectric layer. The gate electrode 62 can include a metal-containing material, such as TiN, TaN, TiAl, TiAlC, cobalt, ruthenium, aluminum, tungsten, combinations thereof, and / or multilayers thereof. The material may be related to whether the obtained nanosheet transistor is a p-type transistor or an n-type transistor, and the work function layer of the gate electrode 62 is selected to have a corresponding p-type or n-type work function. Thus, a nanosheet transistor 70-NA is formed, which has a sheet width W1' ( Figure 14A - 2 ). The width W1' is close to the width W1 shown in Figure 4 and Figure 5A - 2 (e.g., the variation is less than 20%).

[0069] Referring to Figure 14B - 1 and Figure 14B - 2 , a replacement gate stack 64-NW is also formed. The replacement gate stacks 64-NS and 64-NW can share a common formation process, such as removing the dummy gate stack, and depositing and planarizing the replacement gate dielectric and the replacement gate electrode, to form.

[0070] Different from forming the replacement gate stack 64-NS in the device region 100-NS, since the sacrificial layer 22A has been removed in the processing process and has been replaced by the dielectric layer 46 and the semiconductor layer 44, the recess does not significantly extend between the nanostructures 22B.

[0071] In some embodiments in which the semiconductor layer 44 is formed of silicon or SiGe having a low percentage of germanium atoms, the semiconductor layer 44 (and the nanostructures 22B) are not etched. When the semiconductor layer 44 is formed of Ge or SiGe having a high percentage of germanium atoms, the semiconductor layer 44 may be slightly recessed laterally due to its small thickness.

[0072] As Figure 14B - 1 and Figure 14B - 2 shown, the replacement gate stack 64-NW does not include a portion that separates the nanostructures 22B from each other. Instead, the nanostructures 22B, the dielectric layer 46, and the semiconductor layer 44 together form a protruding fin, and the replacement gate stack 64-NW is formed on the sidewalls and the top of the protruding fin. Thus, a nanowire transistor 70-NW is formed, which has a sheet width W2' ( Figure 14B - 2 ), which is close to the width W1 as Figure 4 and Figure 5B - 2 shown (e.g., the variation is less than 20%). The channel region of the nanowire transistor 70-NW includes nanostructures 22B', which include the nanostructures 22B and the semiconductor layer 44.

[0073] Figure 15A - 1 , Figure 15A - 2 , Figure 15B - 1 , and Figures 15B - 2 to 17A - 1 , Figure 17A - 2 , Figure 17B - 1 , and Figure 17B - 2 illustrate the formation of nanowire transistors 70-NS and 70-NW according to alternative embodiments. The nanowire transistors 70-NS and 70-NW according to these embodiments are substantially the same as those in Figure 14A - 1 , Figure 14B - 1 , Figure 14A - 2 , and Figure 14B - 2 . The difference is that in Figure 17B - 1 and Figure 17B - 2 , an additional internal spacer 50-NW is formed in the nanowire transistor 70-NW, while in Figure 14B - 1 and Figure 14B - 2 , no internal spacer is formed in the nanowire transistor 70-NW. Unless otherwise specified, the reference numerals in these embodiments represent the same elements as those in the embodiments shown in Figures 1 to 14A - 1 , Figure 14A - 2 , Figure 14B - 1 , and Figure 14B - 2 .

[0074] The initial steps of this embodiment are substantially the same as those shown in Figures 1 to 10A - 1 , Figure 10A - 2 , Figure 10B - 1 , and Figure 10B - 2 . Next, implement as Figure 15A - 1 ,Figure 15A - 2 , Figure 15B - 1 , and Figure 15B - 2 The processes shown in. A protective layer 51' is formed in both device regions 100-NS and 100-NW, then removed from device region 100-NW and retained in device region 100-NS. Then, the dielectric layer 46 ( Figure 15B - 1 and Figure 15B - 2 ) is recessed, and then a dielectric material is filled into the recess to form an inner spacer 50-NW, as shown in Figure 15B - 1 . Then, the protective layer 51' is removed.

[0075] Next, the processes shown in Figure 16A - 1 , Figure 16A - 2 , Figure 16B - 1 , and Figure 16B - 2 are implemented to form an inner spacer 50-NS in device region 100-NS. A protective layer 51'' is formed in both device regions 100-NS and 100-NW, then removed from device region 100-NS and retained in device region 100-NW. Then, the sacrificial layer 22B is recessed, and then a dielectric material is filled into the recess to form an inner spacer 50-NS, as shown in Figure 16A - 1 . Then, the protective layer 51'' is removed. It should be understood that the process sequence for forming the inner spacers 50-NW and 50-NS can be reversed.

[0076] Next, Figure 12B - 1 and Figure 12B - 2 (which may or may not be implemented) are implemented to Figure 14A - 1 , Figure 14A - 2 , Figure 14B - 1 , and Figure 14B - 2 The processes shown in. Figure 17A - 1 , Figure 17A - 2 , Figure 17B - 1 , and Figure 17B - 2 show the obtained structures, which are substantially the same as the structures shown in Figure 14A - 1 , Figure 14A - 2 , Figure 14B - 1 , and Figure 14B - 2 , except that an inner spacer 50-NW is also formed.

[0077] In Figure 14A - 2 and Figure 17A - 2In [a certain structure], the width W1’ of the nanosheet can be greater than about 8 nm and less than about 80 nm, and the spacing between adjacent nanostructures 22B can range between about 8 nm and about 10 nm. The thickness H1 of the nanostructure 22B can range between about 4 nm and about 7 nm. The width W1’ is greater than the thickness H1, and the ratio W1’ / H1 ranges between about 1.6 and about 16. When the ratio W1’ / H1 is too high, it is difficult to form the structure and fill the gaps between the nanosheets. When the ratio W1’ / H1 is too small, the current is not large enough.

[0078] In Figure 14B-2 and Figure 17B-2 In [another structure], the width W2’ of the nanosheet can range between about 4 nm and about 6 nm, and the spacing between adjacent nanostructures 22B can range between about 3 nm and about 5 nm. The thickness H2 of the nanostructure 22B’ can range between about 9 nm and about 11 nm. The width W2’ is closer to the thickness H2 and may be less than the thickness H2, where the ratio W2’ / H2 ranges between about 0.3 and about 0.7. When the ratio W2’ / H2 is too high, the replacement gate stack may extend between the nanostructures 22B. When the ratio W2’ / H2 is too small, the current is not large enough.

[0079] Figures 18-22 The top views of some nanosheets and nanowires are shown, which are used to form nanosheet transistors and nanowire transistors as discussed. Figure 18 and Figure 19 respectively show the top views of the nanowire (22B or 22B’) and the nanosheet 22B. By using a hybrid of nanosheet transistors and nanowire transistors, the chip area usage can be reduced without sacrificing circuit performance. For example, Figure 20 shows that the nanowires 22B / 22B’ (assuming two nanowires 22B / 22B’ form a nanowire crystal) used to form three nanowire transistors may occupy the chip area of two nanosheet transistors (assuming two nanosheets 22B form a nanosheet transistor). When there is no requirement for drive current, nanowire transistors can be used to reduce the chip area usage. Figure 21 shows that nanosheet transistors and nanowire transistors can be arranged in the same column.

[0080] Nanosheet transistors have a higher (drive) current but occupy more chip area. Nanowire transistors have a lower chip area usage but have a lower (drive) current. A hybrid of nanosheet transistors and nanowire transistors can be used to meet customization requirements. For example, Figure 22Shows a static random access memory (SRAM) cell 74, which includes pull-up transistors PU-1 and PU-2, pull-down transistors PD-1 and PD-2, and transmission gate transistors PG-1 and PG-2. According to some embodiments, when it is desired that the circuit is a high-density circuit, all transistors in the SRAM cell 74 are formed as nanowire transistors 70-NW because the current requirements are not high. In this case, the transistor density in the SRAM can be increased by more than 15% compared to a circuit formed by nanosheet transistors.

[0081] Nanosheet transistors in the same device die (and in the same wafer) may have different channel widths, such that they can have different drive currents to accommodate customized circuit requirements. For example, Figure 23 Shows a nanosheet transistor 70'-NS in a device region 100'-NS having a channel width W1", while a nanosheet transistor 70"-NS in a device region 100"-NS has a channel width W1"'. According to some embodiments, the channel width W1" is less than the channel width W1' ( Figure 17A-2 ), and the channel width W1"' is greater than the channel width W1'.

[0082] Figure 24 Shows a nanowire transistor 70'-NW in a device region 100'-NW having a channel width W2", while a nanowire transistor 70"-NW in a device region 100"-NW has a channel width W2"'. According to some embodiments, the channel width W2" is less than the channel width W2' ( Figure 17B-2 ), and the channel width W2"' is greater than the channel width W2'. Transistors with a larger channel width can have a higher drive current.

[0083] According to an alternative embodiment, when it is desired that the circuit is a high-current circuit, the pull-down transistors PD-1 and PD-2 are formed as nanosheet transistors to meet the high-current requirements of the pull-down transistors. On the other hand, the pull-up transistors PU-1 and PU-2 and the transmission gate transistors PG-1 and PG-2 do not require high current and are therefore formed as nanowire transistors. In this case, the transistor density in the SRAM can be increased by more than 5% compared to a circuit formed by nanosheet transistors, while still meeting or exceeding the circuit performance requirements.

[0084] In addition, the gate stack of the nanowire transistor does not extend between the channels, the parasitic capacitance between the source / drain regions and the gate stack is reduced, and the AC gain is increased. The nanowire is also thickened by epitaxy, and the strain is improved.

[0085] Embodiments of the present invention have some advantageous features. By forming a hybrid device including both nanosheet transistors and nanowire transistors, chip area usage can be reduced and device density can be increased without sacrificing circuit performance. The nanosheet transistors and nanowire transistors can share a common formation process, thereby reducing manufacturing costs.

[0086] According to some embodiments of the present invention, a method includes: patterning a stacked layer to form a first multi-layer stack and a second multi-layer stack, each including a plurality of sacrificial layers and a plurality of nanostructures alternately positioned, wherein the second multi-layer stack is wider than the first multi-layer stack; forming a nanosheet transistor based on the first multi-layer stack, wherein the nanosheet transistor includes: a first channel region having a first width; and a first gate stack located on the first channel region; and forming a nanowire transistor based on the second multi-layer stack, wherein the nanowire transistor includes: a second channel region narrower than the first channel region; and a second gate stack located on the second channel region.

[0087] In one embodiment, forming the nanowire transistor includes: removing a plurality of sacrificial layers in the second multi-layer stack to leave a gap; and epitaxially growing a semiconductor layer in the gap. In one embodiment, forming the nanowire transistor further includes: after growing the semiconductor layer in the gap, filling the gap with a dielectric layer, wherein the dielectric layer physically contacts one above and one below the semiconductor layer. In one embodiment, epitaxially growing the semiconductor layer includes growing a silicon layer.

[0088] In one embodiment, epitaxially growing the semiconductor layer includes growing a germanium-containing layer. In one embodiment, forming the nanosheet transistor includes: removing a plurality of sacrificial layers in the first multi-layer stack; and forming a first gate stack including a portion between the plurality of nanostructures in the first multi-layer stack. In one embodiment, the first channel region of the nanosheet transistor has a smaller height than the second channel region of the nanowire transistor. In one embodiment, the method further includes: forming a first inner spacer for the nanosheet transistor, wherein the first gate stack includes a portion in a region between the first inner spacers, and the nanowire transistor has no inner spacer.

[0089] In one embodiment, the method further includes: forming a first inner spacer for the nanosheet transistor, wherein the first gate stack includes a portion in a region between the first inner spacers; and forming a second inner spacer for the nanowire transistor, wherein a dielectric layer is located between the second inner spacers. In one embodiment, the method includes: forming a static random access memory cell, wherein the nanosheet transistor is formed as a pull-down transistor of the static random access memory cell, and wherein the nanowire transistor is formed as a pull-up transistor of the static random access memory cell.

[0090] According to some embodiments of the present invention, a structure includes: a bulk semiconductor substrate; a nanosheet transistor located above the bulk semiconductor substrate, wherein the nanosheet transistor includes: a first channel region, where an upper one of the first channel regions overlaps a lower one of the first channel regions; and a first gate stack located on the first channel region; and a nanowire transistor located above the bulk semiconductor substrate, wherein the nanowire transistor includes: a second channel region, narrower than the first channel region, where an upper one of the second channel regions overlaps a lower one of the second channel regions; and a second gate stack located on the second channel region.

[0091] In one embodiment, the first channel region has a first thickness, and the second channel region has a second thickness greater than the first thickness. In one embodiment, the first channel region includes a first semiconductor material; and one of the second channel regions includes: a first layer including the first semiconductor material; and a second layer including a second semiconductor material different from the first semiconductor material. In one embodiment, the first channel region and the second channel region include the same semiconductor material.

[0092] In one embodiment, the first gate stack includes: an intermediate portion between adjacent first channel regions; and the second gate stack includes: a dielectric layer between adjacent second channel regions. In one embodiment, the nanosheet transistor includes: a first inner spacer contacting a first opposite sidewall of the intermediate portion of the first gate stack; and the nanowire transistor includes: a second inner spacer contacting a second opposite sidewall of the dielectric layer. In one embodiment, the structure includes a static random access memory cell including: a nanosheet transistor as a pull-down transistor; and a nanowire transistor as a pull-up transistor.

[0093] According to some embodiments of the present invention, a structure includes: a nanowire transistor including a protruding structure, the protruding structure including a plurality of channel regions; and a plurality of dielectric regions located between the plurality of channel regions; a first source / drain region and a second source / drain region located on opposite sides of the plurality of channel regions and the plurality of dielectric regions and joined to the plurality of channel regions and the plurality of dielectric regions; and a gate stack located on the protruding structure. In one embodiment, the plurality of dielectric regions includes: a plurality of dielectric layers; and a plurality of inner spacers located on opposite sides of the plurality of dielectric layers and contacting the plurality of dielectric layers.

[0094] In one embodiment, the plurality of channel regions includes: a first plurality of semiconductor layers including a first semiconductor material; and a second plurality of semiconductor layers including a second dielectric material different from the first semiconductor material, wherein the second plurality of conductor layers is located on the first plurality of semiconductor layers.

[0095] Some embodiments of the present application provide a method for forming a semiconductor structure, including: patterning a stacked layer to form a first multi-layer stack and a second multi-layer stack, each including a plurality of sacrificial layers and a plurality of nanostructures alternately positioned, wherein the second multi-layer stack is wider than the first multi-layer stack; forming a nanosheet transistor based on the first multi-layer stack, wherein the nanosheet transistor includes: a first channel region having a first width; and a first gate stack located on the first channel region; and forming a nanowire transistor based on the second multi-layer stack, wherein the nanowire transistor includes: a second channel region narrower than the first channel region; and a second gate stack located on the second channel region.

[0096] In some embodiments, forming the nanowire transistor includes: removing the plurality of sacrificial layers in the second multi-layer stack to leave a gap; and epitaxially growing a semiconductor layer in the gap. In some embodiments, forming the nanowire transistor further includes: after growing the semiconductor layer in the gap, filling the gap with a dielectric layer, wherein the dielectric layer physically contacts one above and one below the semiconductor layer. In some embodiments, epitaxially growing the semiconductor layer includes growing a silicon layer. In some embodiments, epitaxially growing the semiconductor layer includes growing a germanium-containing layer. In some embodiments, forming the nanosheet transistor includes: removing the plurality of sacrificial layers in the first multi-layer stack; and forming the first gate stack including a portion between the plurality of nanostructures in the first multi-layer stack. In some embodiments, the first channel region of the nanosheet transistor has a smaller height than the second channel region of the nanowire transistor. In some embodiments, the method further includes: forming a first internal spacer for the nanosheet transistor, wherein the first gate stack includes a portion in a region between the first internal spacers, and the nanowire transistor has no internal spacer. In some embodiments, the method further includes: forming a first internal spacer for the nanosheet transistor, wherein the first gate stack includes a portion in a region between the first internal spacers; and forming a second internal spacer for the nanowire transistor, wherein a dielectric layer is located between the second internal spacers. In some embodiments, the method includes: forming a static random access memory cell, wherein the nanosheet transistor is formed as a pull-down transistor of the static random access memory cell, and wherein the nanowire transistor is formed as a pull-up transistor of the static random access memory cell.

[0097] Some other embodiments of the present application provide a semiconductor structure, including: a bulk semiconductor substrate; a nanosheet transistor located above the bulk semiconductor substrate, wherein the nanosheet transistor includes: a first channel region, wherein an upper one of the first channel regions overlaps a lower one of the first channel regions; and a first gate stack located on the first channel region; and a nanowire transistor located above the bulk semiconductor substrate, wherein the nanowire transistor includes: a second channel region, narrower than the first channel region, wherein an upper one of the second channel regions overlaps a lower one of the second channel regions; and a second gate stack located on the second channel region.

[0098] In some embodiments, the first channel region has a first thickness, and the second channel region has a second thickness greater than the first thickness. In some embodiments, the first channel region includes a first semiconductor material; and one of the second channel regions includes: a first layer including the first semiconductor material; and a second layer including a second semiconductor material different from the first semiconductor material. In some embodiments, the first channel region and the second channel region include the same semiconductor material. In some embodiments, the first gate stack includes: an intermediate portion between adjacent first channel regions; and the second gate stack includes: a dielectric layer between adjacent second channel regions. In some embodiments, the nanosheet transistor includes: a first internal spacer contacting a first opposite sidewall of the intermediate portion of the first gate stack; and the nanowire transistor includes: a second internal spacer contacting a second opposite sidewall of the dielectric layer. In some embodiments, the semiconductor structure includes a static random access memory cell, including: the nanosheet transistor as a pull-down transistor; and the nanowire transistor as a pull-up transistor.

[0099] Some further embodiments of the present application provide a semiconductor structure, including: a nanowire transistor, including: a protruding structure, including: a plurality of channel regions; and a plurality of dielectric regions located between the plurality of channel regions; a first source / drain region and a second source / drain region located on opposite sides of the plurality of channel regions and the plurality of dielectric regions and joined to the plurality of channel regions and the plurality of dielectric regions; and a gate stack located on the protruding structure. In some embodiments, the plurality of dielectric regions includes: a plurality of dielectric layers; and a plurality of internal spacers located on opposite sides of the plurality of dielectric layers and contacting the plurality of dielectric layers. In some embodiments, the plurality of channel regions includes: a first plurality of semiconductor layers including a first semiconductor material; and a second plurality of semiconductor layers including a second dielectric material different from the first semiconductor material, wherein the second plurality of conductor layers is located on the first plurality of semiconductor layers.

[0100] The features of several embodiments were outlined above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also realize that such equivalent structures do not depart from the spirit and scope of the present disclosure and that various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A method of forming a semiconductor structure, comprising: Patterning a stacked layer to form a first multi-layer stack and a second multi-layer stack, each including a plurality of sacrificial layers and a plurality of nanostructures alternately positioned, wherein the second multi-layer stack is wider than the first multi-layer stack; Forming a nanosheet transistor based on the first multi-layer stack, wherein the nanosheet transistor includes: A first channel region having a first width; and A first gate stack located on the first channel region; and Forming a nanowire transistor based on the second multi-layer stack, wherein the nanowire transistor includes: A second channel region narrower than the first channel region; and A second gate stack located on the second channel region.

2. The method according to claim 1, wherein The forming of the nanowire transistor includes: Removing the plurality of sacrificial layers in the second multi-layer stack to leave a gap; and Epitaxially growing a semiconductor layer in the gap.

3. The method according to claim 2, wherein The forming of the nanowire transistor further includes: After growing the semiconductor layer in the gap, filling the gap with a dielectric layer, wherein the dielectric layer physically contacts one above and one below the semiconductor layer.

4. The method according to claim 2, wherein, The epitaxially growing of the semiconductor layer includes growing a silicon layer.

5. The method according to claim 2, wherein The epitaxially growing of the semiconductor layer includes growing a germanium-containing layer.

6. The method according to claim 1, wherein The forming of the nanosheet transistor includes: Removing the plurality of sacrificial layers in the first multi-layer stack; and Forming the first gate stack including a portion between the plurality of nanostructures in the first multi-layer stack.

7. The method according to claim 1, wherein The first channel region of the nanosheet transistor has a smaller height than the second channel region of the nanowire transistor.

8. The method according to claim 1, further comprising: Forming a first internal spacer for the nanosheet transistor, wherein the first gate stack includes a portion in a region between the first internal spacers, and the nanowire transistor has no internal spacer.

9. A semiconductor structure, comprising: A bulk semiconductor substrate; A nanosheet transistor located above the bulk semiconductor substrate, wherein the nanosheet transistor includes: A first channel region, wherein an upper one of the first channel region overlaps a lower one of the first channel region; and A first gate stack located on the first channel region; and A nanowire transistor located above the bulk semiconductor substrate, wherein the nanowire transistor includes: A second channel region narrower than the first channel region, wherein an upper one of the second channel region overlaps a lower one of the second channel region; and A second gate stack located on the second channel region.

10. A semiconductor structure, comprising: A nanowire transistor, including: A protruding structure, including: A plurality of channel regions; and A plurality of dielectric regions located between the plurality of channel regions; A first source / drain region and a second source / drain region located on opposite sides of the plurality of channel regions and the plurality of dielectric regions and joined to the plurality of channel regions and the plurality of dielectric regions; and A gate stack located on the protruding structure.

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