Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a substrate which comprises a substrate with a projection structure; the channel structure layer is suspended on the convex structure, the channel structure layer comprises one or more channel layers which are sequentially arranged at intervals from bottom to top, and the length of the channel layers is larger than that of the convex structure; the source-drain doping layer is located on the substrate on the two sides of the channel structure layer along the length direction of the channel layer and is connected with the two ends of the channel layer; and the gate structure is located between the source and drain doping layers, the gate structure stretches across the channel structure layer and surrounds the channel layer, and the gate structure further covers the tops of the protruding structures and the side walls of the protruding structures. According to the embodiment of the invention, the length of the gate structure and the length of the channel are increased, the control force of the gate structure on the channel is correspondingly increased, the short channel effect is improved, and the leakage current of a sub-threshold device is reduced, so that larger driving current can be obtained, and the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher element density and higher integration, and semiconductor process nodes are continuously reduced following Moore's law. As the most basic semiconductor device, transistors are currently widely used. Therefore, with the increase in the element density and integration of semiconductor devices, in order to adapt to the reduction of process nodes, it is necessary to continuously reduce the size of transistors.

[0003] As the size of transistors gets smaller and smaller, fin field-effect transistors (FinFETs) emerge as the times require. However, to maintain the original drive current performance, this structure is no longer suitable for smaller nodes. Thus, gate-all-around field-effect transistors (GAAFETs) appear. Their control of short-channel effects and excellent electrical properties enable them to replace FinFETs as the mainstream at smaller process nodes.

[0004] However, the performance of current gate-all-around field-effect transistors still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same to improve the performance of the semiconductor structure.

[0006] To solve the above problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate, the substrate includes a substrate having a raised structure; a channel structure layer suspended on the raised structure, the channel structure layer includes one or more channel layers sequentially arranged at intervals from bottom to top, and the length of the channel layer is greater than the length of the raised structure; source-drain doping layers located on the substrates on both sides of the channel structure layer along the length direction of the channel layer and connected to both ends of the channel layer; a gate structure located between the source-drain doping layers, the gate structure straddles the channel structure layer and surrounds the channel layer, and the gate structure also covers the top and the side walls of the raised structure.

[0007] Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a substrate having a raised structure, a first sacrificial layer being formed on the substrate on the side of the raised structure, the first sacrificial layer covering the sidewall of the raised structure, one or more channel stacks being formed on the first sacrificial layer and the raised structure and being stacked in sequence longitudinally, each channel stack including a second sacrificial layer and a channel layer located on the second sacrificial layer; forming a dummy gate structure across the channel stack on the channel stack at the top of the raised structure, the dummy gate structure covering a part of the top and a part of the sidewall of the channel stack, in a direction perpendicular to the extending direction of the dummy gate structure, the length of the dummy gate structure being greater than the length of the raised structure; forming source-drain doping layers connected to both ends of the channel layer in the channel stack and the first sacrificial layer on both sides of the dummy gate structure; after forming the source-drain doping layers, removing the dummy gate structure, forming an opening at the position of the dummy gate structure, the opening exposing the top and the sidewall of the channel stack; through the opening, removing the first sacrificial layer and the second sacrificial layer, forming a through hole between the raised structure and the channel layer, or through holes between the raised structure and the channel layer and between adjacent channel layers; forming a gate structure in the opening and the through hole.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] In the semiconductor structure provided by the embodiment of the present invention, it includes a substrate, the substrate including a substrate having a raised structure, a channel structure layer suspended on the raised structure, the length of the channel layer being greater than the length of the raised structure, a gate structure located between the source-drain doping layers, and the gate structure further covering the top of the raised structure and the sidewall in the length direction of the raised structure. Since the length of the channel layer is greater than the length of the raised structure, and the gate structure covers the top of the raised structure and the sidewall in the length direction of the raised structure, correspondingly, the increased channel length is twice the height of the raised structure. Compared with the solution where the substrate at the bottom of the channel layer does not have a raised structure, the length of the gate structure and the length of the channel are increased. Correspondingly, the control force of the gate structure on the channel is increased, the short-channel effects (SCE) are improved, the leakage current of the subthreshold device is reduced, so that a larger drive current can be obtained, and thus the performance of the semiconductor structure is improved.

[0010] In a method for forming a semiconductor structure provided by an embodiment of the present invention, a substrate is provided, wherein the substrate includes a substrate having a protruding structure, a first sacrificial layer covering a side wall of the protruding structure is formed on the substrate at a side of the protruding structure, one or more channel stacks stacked in sequence along a longitudinal direction are formed on the first sacrificial layer and the protruding structure, a dummy gate structure spanning the channel stack is formed on the channel stack at the top of the protruding structure, the length of the dummy gate structure is greater than the length of the protruding structure in a direction perpendicular to the extension direction of the dummy gate structure, and the length of the protruding structure is greater than the length of the protruding structure at the position of the dummy gate structure, at the top of the protruding structure, and at the length of the protruding structure. A gate structure is formed on the side wall in the length direction. Since the length of the pseudo gate structure is greater than the length of the protruding structure, and the gate structure covers the top of the protruding structure and the side wall in the length direction of the protruding structure, the increased channel length is twice the height of the protruding structure. Compared with the solution in which the substrate at the bottom of the channel layer does not have a protruding structure, the length of the gate structure and the length of the channel are increased, and the control of the gate structure over the channel is correspondingly increased, thereby improving the short channel effect and reducing the leakage current of the subthreshold device, so that a larger driving current can be obtained, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figures 1 to 9 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0012] Figure 10 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0013] Figures 11 to 23 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0014] At present, the performance of semiconductor structures still needs to be improved. Now, combined with a method for forming a semiconductor structure, the reasons why the performance of semiconductor structures needs to be improved are analyzed. Figures 1 to 9 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0015] refer to Figure 1 A substrate 10 is provided, on which one or more channel stacks 11 stacked in sequence along the longitudinal direction are formed, and each channel stack 11 includes a sacrificial layer 12 and a channel layer 13 located on the sacrificial layer 12.

[0016] refer to Figure 2 , forming a dummy gate structure 14 across the channel stack 11 , wherein the dummy gate structure 14 covers a portion of the top and a portion of the sidewall of the channel stack 11 .

[0017] refer to Figures 3 to 6, source / drain doping layers 18 connected to both ends of the channel layer 13 are formed in the channel stack 11 on both sides of the dummy gate structure 14.

[0018] Reference Figures 7 to 8 , after forming the source / drain doping layers 18, the dummy gate structure 14 is removed, and an opening 15 is formed at the position of the dummy gate structure 14, and the opening 15 exposes the top and sidewalls of the channel stack 11.

[0019] Continue to refer to Figure 8 , via the opening, the sacrificial layer 12 is removed to form a through groove 16 between the substrate 10 and the channel layer 13, or a through groove 16 between the substrate 10 and the channel layer 13 and between adjacent channel layers 13.

[0020] Reference Figure 9 , a gate structure 17 is formed in the opening 15 and the through groove 16.

[0021] It has been found through research that as the semiconductor process node continues to shrink, the channel length also decreases accordingly, resulting in poor control of the gate structure 17 over the channel, which easily leads to the short-channel effect and thus affects the performance of the semiconductor structure.

[0022] To solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, the substrate includes a substrate having a convex structure; a channel structure layer suspended on the convex structure, the channel structure layer includes one or more channel layers sequentially arranged at intervals from bottom to top, and the length of the channel layer is greater than the length of the convex structure; source / drain doping layers located on the substrate on both sides of the channel structure layer along the length direction of the channel layer and connected to both ends of the channel layer; a gate structure located between the source / drain doping layers, the gate structure straddles the channel structure layer and surrounds the channel layer, and the gate structure also covers the top and sidewalls of the convex structure.

[0023] In the semiconductor structure provided by an embodiment of the present invention, a substrate is included. The substrate includes a substrate having a raised structure, a channel structure layer suspended on the raised structure. The length of the channel layer is greater than the length of the raised structure. A gate structure is located between the source-drain doping layers, and the gate structure also covers the top of the raised structure and the side walls in the length direction of the raised structure. Since the length of the channel layer is greater than the length of the raised structure, and the gate structure covers the top of the raised structure and the side walls in the length direction of the raised structure, correspondingly, the increased channel length is twice the height of the raised structure. Compared with the solution where the substrate at the bottom of the channel layer does not have a raised structure, the length of the gate structure and the length of the channel are increased. Correspondingly, the control force of the gate structure on the channel is increased, the short-channel effect is improved, the leakage current of the sub-threshold device is reduced, so that a larger drive current can be obtained, and further the performance of the semiconductor structure is improved.

[0024] In order to make the above objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0025] Figure 10 It is a schematic structural diagram of an embodiment of the semiconductor structure of the present invention.

[0026] Refer to Figure 10 , in this embodiment, the semiconductor structure includes: a substrate 100, the substrate 100 includes a substrate 101 having a raised structure 102; a channel structure layer 110 suspended on the raised structure 102. The channel structure layer 110 includes one or more channel layers 111 arranged at intervals from bottom to top in sequence, and the length l3 of the channel layer 111 is greater than the length l1 of the raised structure 102; source-drain doping layers 140 are located on the substrates 101 on both sides of the channel structure layer 110 along the length l3 direction of the channel layer 111 and are connected to both ends of the channel layer 111; a gate structure 160 is located between the source-drain doping layers 140, the gate structure 160 straddles the channel structure layer 110 and surrounds the channel layer 111, and the gate structure 160 also covers the top of the raised structure 102 and the side walls of the raised structure 102.

[0027] The substrate 100 provides a process platform for the formation of the semiconductor structure. In this embodiment, the substrate 500 is used to form a fully surrounding gate transistor.

[0028] In this embodiment, the substrate 100 includes a substrate 101, and the substrate is a silicon substrate. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0029] The raised structure 102 provides a process basis for forming the gate structure 160 on the top of the raised structure 102 and on the sidewalls of the raised structure 102 in the length direction l1 of the raised structure 102.

[0030] It should be noted that the ratio of the height h1 to the length l1 of the raised structure 102 should not be too small or too large. If the ratio of the height h1 to the length l1 of the raised structure 102 is too small, it is likely that the effect of increasing the channel length is not good, resulting in poor improvement of the short-channel effect and poor reduction of the leakage current of the subthreshold device; if the ratio of the height h1 to the length l1 of the raised structure 102 is too large, it is likely that the height h1 of the raised structure 102 is too large, so that the current needs to flow from a higher position to a lower position, thereby affecting the flow of the current. Therefore, in this embodiment, the relationship between the height h1 and the length l1 of the raised structure 102 satisfies: 1 < h1 / l1 < 100.

[0031] Wherein, h1 is the height of the raised structure, l1 is the length of the raised structure, and the length direction l1 of the raised structure is parallel to the length direction of the channel.

[0032] The channel layer 111 serves as the conductive channel of the fully-depleted surround gate transistor.

[0033] The length l3 of the channel layer 111 is greater than the length l1 of the raised structure 102, which facilitates the gate structure 160 to cover the top of the raised structure 102 and the sidewalls of the raised structure 102 in the length direction l1 of the raised structure 102.

[0034] Specifically, the material of the channel layer 111 can be one or more of silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.

[0035] It should be noted that the number of the channel layers 111 should not be too many. If the number of the channel layers 111 is too many, it is likely that the overall height of the semiconductor structure is too high, which is not conducive to further reducing the size of the semiconductor structure. Therefore, in this embodiment, the number of the channel layers 111 is less than or equal to 10.

[0036] In this embodiment, the semiconductor structure further includes: a shallow trench isolation structure (Shallow Trench Isolation, STI) (not shown in the figure), and the top of the shallow trench isolation structure on the substrate 101 between adjacent channel structure layers 110 is lower than the bottom of the raised structure 102.

[0037] The shallow trench isolation structure is used to achieve electrical isolation between adjacent channel structure layers 110, and can also isolate the substrate 101 and the gate structure 160.

[0038] It should be noted that the material of the shallow trench isolation structure includes one or several of silicon oxide, silicon nitride, and silicon oxynitride.

[0039] In this embodiment, the semiconductor structure further includes: a sidewall structure 121, which is located on the sidewalls of the gate structure 160 on top of the channel layer 111.

[0040] The sidewall structure 121 is used to protect the sidewalls of the gate structure 160 during the formation of the semiconductor structure, and is also used to define the positions of the source-drain doping layers 140.

[0041] It should be noted that the sidewall structure 121 can be a single-layer structure or a stacked structure, and the material of the sidewall structure 121 includes one or more of SiN, SiC, SiCO, SiCON, and SiBN.

[0042] In this embodiment, the semiconductor structure further includes: an inner sidewall 122, which is located between the source-drain doping layer 140 and the gate structure 160 at the bottom of the channel layer 111.

[0043] The inner sidewall 122 increases the distance between the source-drain doping layer 140 and the gate structure 160, thereby facilitating the reduction of the parasitic capacitance between the source-drain doping layer 140 and the gate structure 160.

[0044] Specifically, the material of the inner sidewall 122 includes one or more of SiN, SiC, SiCO, SiCON, and SiBN.

[0045] It should be noted that the ratio of the length l2 of the gate structure 160 between the inner sidewall 122 and the protrusion structure 102 to the length l3 of the channel layer 111 should not be too small or too large. If the ratio of the length l2 of the gate structure 160 between the inner sidewall 122 and the protrusion structure 102 to the length l3 of the channel layer 111 is too small, it is easy for the length l2 of the gate structure 160 to be too large, and correspondingly, it is easy for the thickness of the inner sidewall 122 on the sidewalls of the gate structure 160 to be small, thereby making it difficult to effectively reduce the parasitic capacitance between the source-drain doping layer 140 and the gate structure 160; if the ratio of the length l2 of the gate structure 160 between the inner sidewall 122 and the protrusion structure 102 to the length l3 of the channel layer 111 is too large, it is easy for the length l2 of the gate structure 160 to be too small, thereby increasing the difficulty of forming the gate structure 160 between the inner sidewall 122 and the protrusion structure 102. In this embodiment, the relationship between the length l2 of the gate structure 160 between the inner sidewall 122 and the protrusion structure 102 and the length l3 of the channel layer 111 satisfies: 4 < l3 / l2 < 10.

[0046] Wherein, l2 is the length of the gate structure 160 between the inner sidewall 122 and the protrusion structure 102, and l3 is the length of the channel layer 111.

[0047] The source / drain doping layer 140 is used as the source or drain of the fully-depleted surround gate transistor. When the fully-depleted surround gate transistor is operating, the source / drain doping layer 140 is used to provide a carrier source.

[0048] In this embodiment, the semiconductor structure further includes: an interlayer dielectric layer 150, which is located on the shallow trench isolation structure on the side of the gate structure 160, and the interlayer dielectric layer 150 covers the source / drain doping layer 140.

[0049] The interlayer dielectric layer 150 is used to achieve electrical isolation between adjacent semiconductor structures.

[0050] Specifically, the material of the interlayer dielectric layer 150 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer can also be other suitable dielectric materials.

[0051] The gate structure 160 is a device gate structure, which is used to form a field effect transistor together with the conductive channel and the source / drain doping layer 140.

[0052] Since the length l3 of the channel layer 111 is greater than the length l1 of the raised structure 102, and the gate structure 160 covers the top of the raised structure 102 and the sidewalls in the direction of the length l1 of the raised structure 102, correspondingly, the increased channel length is twice the height h1 of the raised structure 102. Compared with the scheme where the substrate at the bottom of the channel layer does not have a raised structure, the length of the gate structure 160 and the length of the channel are increased. Correspondingly, the control force of the gate structure 160 on the channel is increased, the short-channel effect is improved, the leakage current of the subthreshold device is reduced, so that a larger drive current can be obtained, and thus the performance of the semiconductor structure is improved.

[0053] Specifically, the gate structure 160 straddles the channel structure layer 110, and is also filled on the top and sidewalls of the raised structure 102 between the channel layer 111 and the substrate 101, or filled on the top and sidewalls of the raised structure 102 between the channel layer 111 and the substrate 101, and between adjacent channel layers 111.

[0054] In this embodiment, the sidewalls of the raised structure 102 covered by the gate structure 160 are the sidewalls in the direction of the length l1 of the raised structure 102.

[0055] Generally, in the step of providing the substrate 100, a first sacrificial layer (not shown in the figure) covering the sidewalls of the raised structure 102 needs to be formed on the substrate 101 on the side of the raised structure 102. By occupying the positions of the sidewalls of the raised structure 102 with the first sacrificial layer, it is convenient for the gate structure 160 to cover the sidewalls of the raised structure 102.

[0056] The sidewalls of the raised structure 102 covered by the gate structure 160 are the sidewalls in the length direction l1 of the raised structure 102. In the step of providing the substrate 100, only the sidewalls in the length direction l1 of the raised structure 102 need to be covered with the first sacrificial layer, thereby reducing the process difficulty. Also, in the process of forming the gate structure 160, the through - slot space between the raised structure 102 and the channel layer 111 is not likely to be too large, which is convenient for improving the quality of the gate structure 160 formed in the through - slot between the raised structure 102 and the channel layer 111, that is, improving the quality of the gate structure 160 covering the sidewalls of the raised structure 102.

[0057] In other embodiments, the gate structure may also cover the sidewalls in the length direction of the raised structure and the sidewalls in the width direction of the raised structure.

[0058] In this embodiment, the gate structure 160 includes a gate dielectric layer (not labeled) and a gate electrode layer (not labeled) covering the gate dielectric layer.

[0059] The gate dielectric layer is used to isolate the gate electrode layer from the channel.

[0060] The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0061] Specifically, the gate structure 160 is a metal gate structure. Therefore, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. The gate electrode layer includes a work - function layer and an electrode layer covering the work - function layer, or may only include the work - function layer.

[0062] Correspondingly, the gate dielectric layer includes a high - k gate dielectric layer. The material of the high - k gate dielectric layer is a high - k dielectric material, and a high - k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high - k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the high - k gate dielectric layer is HfO2.

[0063] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 11 to 23 It is a schematic diagram of the structures corresponding to the steps in an embodiment of the method for forming a semiconductor structure of the present invention.

[0064] Reference Figures 11 to 14, a substrate 500 is provided. The substrate 500 includes a substrate 501 having a raised structure 502. A first sacrificial layer 503 is formed on the substrate 501 at the side of the raised structure 502. The first sacrificial layer 503 covers the sidewalls of the raised structure 502. One or more channel stacks 510 are formed on the first sacrificial layer 503 and the raised structure 502 and are stacked in sequence longitudinally. Each channel stack 510 includes a second sacrificial layer 512 and a channel layer 511 located on the second sacrificial layer 512.

[0065] Here, the longitudinal direction refers to the normal direction along the top surface of the substrate 500.

[0066] The substrate 500 provides a process platform for subsequent process steps. In this embodiment, the substrate 500 is used to form a fully surrounding gate transistor.

[0067] In this embodiment, the substrate 500 includes a substrate 501, and the substrate is a silicon substrate. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0068] The raised structure 502 is used to provide a process basis for the subsequent gate structure to be formed on the top of the raised structure 502 and the sidewalls in the length L1 direction of the raised structure 502.

[0069] It should be noted that the ratio between the height H1 and the length L1 of the raised structure 502 should not be too small or too large. If the ratio between the height H1 and the length L1 of the raised structure 502 is too small, it is likely that the effect of increasing the channel length is not good, thereby resulting in poor improvement of the short-channel effect and poor reduction of the leakage current of the sub-threshold device; if the ratio between the height H1 and the length L1 of the raised structure 502 is too large, it is likely that the height H1 of the raised structure 502 is too large, so that the current needs to flow from a higher position to a lower position, thereby affecting the flow of the current. Therefore, in this embodiment, in the step of providing the substrate 500, the relationship between the height H1 and the length L1 of the raised structure 502 satisfies: 1 < H1 / L1 < 100.

[0070] Wherein, H1 is the height of the raised structure 502, L1 is the length of the raised structure 502, and the length L1 direction of the raised structure 502 is parallel to the length direction of the channel.

[0071] The first sacrificial layer 503 is used to occupy a spatial position for the subsequent gate structure to be formed on the top of the raised structure 502 and the sidewalls in the length direction of the raised structure 502.

[0072] In this embodiment, in the step of providing the substrate 500, the material of the first sacrificial layer 503 includes one or more of silicon germanide (SiGe), germanium (Ge), silicon carbide (SiC), cobalt silicide (CoSi), nickel silicide (NiSi), gallium arsenide (GaAs), indium arsenide (InAs), indium gallium arsenide (InGaAs), and indium phosphide (InP). In other embodiments, the material of the first sacrificial layer may further include other suitable III-V semiconductor materials.

[0073] As an example, the material of the first sacrificial layer 503 is silicon germanide.

[0074] In the subsequent process of removing the first sacrificial layer 503, the etching selectivity between silicon germanide and silicon is relatively high. Therefore, by setting the material of the first sacrificial layer 503 as silicon germanide and the material of the substrate 501 as silicon, it is easy to achieve a better effect of reducing the influence of the first sacrificial layer 503 removal process on the substrate 501, thereby making the quality of the substrate 501 relatively better, and further being beneficial to improving the performance of the semiconductor device. In other embodiments, the material of the substrate may also be silicon germanide, and the material of the first sacrificial layer is correspondingly silicon.

[0075] In this embodiment, in the step of providing the substrate 500, along the preset channel length direction, the first sacrificial layer 503 protrudes on the substrate 501 on both sides of the protruding structure 502.

[0076] Along the preset channel length direction, the first sacrificial layer 503 protrudes on the substrate 501 on both sides of the protruding structure 502. That is to say, along the preset channel width direction, there is no first sacrificial layer 503 on both sides of the protruding structure 502, thereby reducing the process difficulty of forming the protruding structure 502 and correspondingly reducing the process difficulty of forming the first sacrificial layer 503.

[0077] Moreover, it is also convenient for the subsequent step of forming the gate structure. The through-channel space between the protruding structure 502 and the channel layer 511 is not likely to be too large, thereby facilitating the improvement of the quality of the gate structure formed in the through-channel between the protruding structure 502 and the channel layer 511.

[0078] In other embodiments, in the step of providing the substrate, along the preset channel length direction, the first sacrificial layer protrudes on the substrate on both sides of the protruding structure, and along the preset channel width direction, the first sacrificial layer protrudes on the substrate on both sides of the protruding structure.

[0079] The first sacrificial layers 503 on both sides of adjacent protruding structures 502 are separated from each other, thereby facilitating the isolation of adjacent channel stacks 510.

[0080] The channel stack 510 is used to provide a process basis for subsequently forming the channel layer 511 with a suspended space setting.

[0081] Specifically, the channel layer 511 serves as the conductive channel of the fully surrounding gate transistor, and the second sacrificial layer 512 is used to support the channel layer 511, thereby providing a process basis for the subsequent implementation of the spaced and suspended arrangement of the channel layer 511. The second sacrificial layer 512 is also used to occupy the spatial position for the subsequent formation of the device gate structure between the raised structure 502 and the channel layer 511, or between the raised structure 502 and the channel layer 511 and between adjacent channel layers 511.

[0082] The material of the channel layer 511 can be one or more of silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.

[0083] It should be noted that in the step of providing the substrate 500, the number of the channel layers 511 should not be too large. If the number of the channel layers 511 is too large, it is easy to make the overall height of the semiconductor structure too high, which is not conducive to further reducing the size of the semiconductor structure. Therefore, in this embodiment, in the step of providing the substrate 500, the number of the channel layers 511 is less than or equal to 10.

[0084] In a specific embodiment, the material of the channel layer 511 is silicon, and the material of the second sacrificial layer 512 is silicon germanide. In the subsequent process of removing the second sacrificial layer 512, the etching selectivity between silicon germanide and silicon is relatively high. Therefore, by setting the material of the second sacrificial layer 512 as silicon germanide and the material of the channel layer 511 as silicon, it is easy to achieve a better effect of reducing the influence of the second sacrificial layer 512 removal process on the channel layer 511, so that the quality of the channel layer 511 is correspondingly better, which is conducive to improving the performance of the semiconductor device. In other embodiments, the material of the channel layer can also be silicon germanide, and the material of the second sacrificial layer is correspondingly silicon. Or, according to the material of the channel layer, a suitable material with an etching selectivity ratio to the channel layer can be selected to reduce the damage to the channel layer when removing the second sacrificial layer subsequently.

[0085] In this embodiment, the step of providing the substrate 500 includes: as Figure 11 shown, providing an initial substrate 501'; as Figure 12 shown, in some regions, removing a partial thickness of the initial substrate 501' to form a raised structure 502, and the remaining thickness of the initial substrate 501' serves as the substrate 501; as Figure 13 shown, forming a first sacrificial layer 503 on the substrate 501 on the side of the raised structure 502, and the first sacrificial layer 503 covers the sidewalls of the raised structure 502; forming one or more channel material stacks (not shown in the figure) stacked longitudinally in sequence on the first sacrificial layer 503 and the raised structure 502, and each channel material stack includes a second sacrificial material layer (not shown in the figure) and a channel material layer (not shown in the figure) located on the second sacrificial material layer; as Figure 14As shown, the channel material stack is patterned, and the remaining channel material stack is used as the channel stack 510.

[0086] After providing the initial substrate 501', a part of the thickness of the initial substrate 501' is removed to form a substrate 501 with a raised structure 502. Then, a first sacrificial layer 503 is formed on the substrate 501 on the side of the raised structure 502, which is convenient for reducing the difficulty of forming the substrate 501 with the raised structure 502 and the first sacrificial layer 503. Moreover, after forming the first sacrificial layer 503, a channel material stack is formed on the first sacrificial layer 503 and the raised structure 502, and then the channel material stack is patterned to form the channel stack 510, which is convenient for the channel stack 510 to be located on the first sacrificial layer 503 and the raised structure 502.

[0087] Specifically, after forming the channel stack 510, it further includes: patterning the raised structure 502 and the first sacrificial layer 503 along the channel stack 510.

[0088] Patterning the raised structure 502 and the first sacrificial layer 503 along the channel stack 510 is conducive to corresponding combination with the existing process, reducing the difficulty of the patterning process; moreover, it is also convenient to provide process space for forming the shallow trench isolation structure subsequently.

[0089] More specifically, during the process of patterning the raised structure 502 and the first sacrificial layer 503 along the channel stack 510, a part of the thickness of the substrate 501 at the bottom of the raised structure 502 and the first sacrificial layer 503 is also patterned.

[0090] In this embodiment, in the step of providing the substrate 500, the material of the first sacrificial layer 503 is the same as that of the second sacrificial layer 512.

[0091] The material of the first sacrificial layer 503 being the same as that of the second sacrificial layer 512 is convenient for reducing the difficulty of removing the first sacrificial layer 503 and the second sacrificial layer 512 subsequently.

[0092] Correspondingly, in the step of providing the substrate 500, the material of the second sacrificial layer 512 includes one or more of silicon germanide, germanium, silicon carbide, cobalt silicide, nickel silicide, gallium arsenide, indium arsenide, indium gallium arsenide, and indium phosphide.

[0093] In this embodiment, in the step of providing the substrate 500, a shallow trench isolation structure (not shown in the figure) is formed on the substrate 501 between adjacent channel stacks 510, and the shallow trench isolation structure exposes the raised structure 502, the first sacrificial layer 503, and the sidewalls of the channel stack 510.

[0094] The shallow trench isolation structure is used to achieve electrical isolation between adjacent channel stacks 510, and can also isolate the substrate 501 and the subsequently formed gate structure.

[0095] It should be noted that the material of the shallow trench isolation structure includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0096] Refer to Figure 15 , a dummy gate structure 520 spanning the channel stack 510 is formed on the channel stack 510 at the top of the raised structure 502. The dummy gate structure 520 covers a part of the top and part of the sidewalls of the channel stack 510. Along the direction perpendicular to the extending direction of the dummy gate structure 520, the length L4 of the dummy gate structure 520 is greater than the length L1 of the raised structure 502.

[0097] The dummy gate structure 520 is used to occupy the spatial position for the subsequent formed device gate structure.

[0098] The length L4 of the dummy gate structure 520 is greater than the length L1 of the raised structure 502, which is convenient for the subsequent gate structure to cover the top of the raised structure 502 and the sidewalls in the direction of the length L1 of the raised structure 502.

[0099] Specifically, the material of the dummy gate structure 520 includes polysilicon or amorphous silicon.

[0100] In this embodiment, in the step of forming the dummy gate structure 520, a hard mask structure 530 is further formed on the top of the dummy gate structure 520.

[0101] The hard mask structure 530 is used as an etching mask for forming the dummy gate structure 520 and also plays a role in protecting the top of the dummy gate structure 520.

[0102] Specifically, the hard mask structure 530 includes a first hard mask layer 531 covering the top of the dummy gate structure 520, a second hard mask layer 532 covering the first hard mask layer 531, and a third hard mask layer 533 covering the second hard mask layer 532.

[0103] More specifically, the material of the first hard mask layer 531 is silicon oxide, the material of the second hard mask layer 532 is silicon nitride, and the material of the third hard mask layer 533 is silicon oxide, that is, the hard mask structure 530 is an (Oxide - Nitride - Oxide) structure.

[0104] Continue to refer to Figure 15 , in this embodiment, after forming the dummy gate structure 520 and before forming the source - drain doping layer, it further includes: forming a sidewall structure 521 on the sidewalls of the dummy gate structure 520.

[0105] The sidewall structure 521 is used to protect the sidewalls of the dummy gate structure 520 during the formation of the semiconductor structure and also to define the position of the source - drain doping layer.

[0106] Specifically, the sidewall structure 521 is used as an etching mask during the process of forming the source-drain recess.

[0107] It should be noted that the sidewall structure 521 can be a single-layer structure or a stacked structure, and the material of the sidewall structure 521 includes one or more of SiN, SiC, SiCO, SiCON, and SiBN.

[0108] Correspondingly, in this embodiment, the sidewall structure 521 also covers the sidewalls of the hard mask structure 530.

[0109] Refer to Figures 16 to 18 , in this embodiment, before forming the source-drain doping layer, the forming method further includes: removing the channel stack 510 and the first sacrificial layer 503 on both sides of the pseudo-gate structure 520 to form a source-drain recess 545 surrounded by the channel stack 510, the first sacrificial layer 503, and the substrate 501 (as Figure 16 shown); after forming the source-drain recess 545, in a direction perpendicular to the extension direction of the pseudo-gate structure 520, laterally removing a part of the width of the first sacrificial layer 503 and the second sacrificial layer 512 to form an inner trench 523 between the channel layer 511 and the substrate 501, or forming an inner trench 523 between the channel layer 511 and the substrate 501 and between adjacent channel layers 511 (as Figure 17 shown); forming an inner spacer 522 in the inner trench 523 (as Figure 18 shown).

[0110] Here, the lateral direction refers to the direction perpendicular to the sidewalls of the pseudo-gate structure 520.

[0111] Removing the channel stack 510 and the first sacrificial layer 503 on both sides of the pseudo-gate structure 520, and the source-drain recess 545 surrounded by the channel stack 510, the first sacrificial layer 503, and the substrate 501 provides space for the subsequent formation of the source-drain doping layer. Moreover, after removing the channel stack 510 and the first sacrificial layer 503 on both sides of the pseudo-gate structure 520, the sidewalls of the first sacrificial layer 503 and the second sacrificial layer 512 are exposed, facilitating the lateral removal of a part of the width of the first sacrificial layer 503 and the second sacrificial layer 512.

[0112] The inner trench 523 is used to provide a spatial position for forming the inner spacer 522.

[0113] The inner spacer 522 is used to protect the source-drain doping layer during the subsequent process of removing the first sacrificial layer 503 and the second sacrificial layer 512, reducing the probability of damage to the source-drain doping layer, and is also used to increase the distance between the source-drain doping layer and the device gate structure, thereby facilitating the reduction of the parasitic capacitance between the source-drain doping layer and the device gate structure.

[0114] Specifically, the material of the inner sidewall 522 includes one or more of SiN, SiC, SiCO, SiCON, and SiBN.

[0115] It should be noted that in the step of forming the inner trench 523, in the direction perpendicular to the extension direction of the pseudo-gate structure 520, the ratio of the length L2 of the first sacrificial layer 503 on the sidewall of the protruding structure 502 to the length L3 of the channel layer 511 should not be too small or too large. If the ratio of the length L2 of the first sacrificial layer 503 on the sidewall of the protruding structure 502 to the length L3 of the channel layer 511 is too small, it is easy for the length L2 of the first sacrificial layer 503 on the sidewall of the protruding structure 502 to be too large, and correspondingly, it is easy for the thickness of the inner sidewall 522 on the first sacrificial layer 503 to be small, resulting in poor effect of reducing the parasitic capacitance between the source-drain doping layer and the device gate structure; if the ratio of the length L2 of the first sacrificial layer 503 on the sidewall of the protruding structure 502 to the length L3 of the channel layer 511 is too large, it is easy for the length L2 of the first sacrificial layer 503 on the sidewall of the protruding structure 502 to be too small, thus increasing the difficulty of forming the gate structure between the subsequent inner sidewall 522 and the protruding structure 502. Therefore, in this embodiment, in the step of forming the inner trench 523, in the direction perpendicular to the extension direction of the pseudo-gate structure 520, the relationship between the length of the first sacrificial layer 503 on the sidewall of the protruding structure 502 and the length of the channel layer 511 satisfies: 4 < L3 / L2 < 10.

[0116] Wherein, L2 is the length of the first sacrificial layer 503 on the sidewall of the protruding structure 502, and L3 is the length of the channel layer 511 at the bottom of the pseudo-gate structure 520.

[0117] Reference Figure 19 and in combination with reference Figure 18 , a source-drain doping layer 540 connected to both ends of the channel layer 511 is formed in the channel stack 510 and the first sacrificial layer 503 on both sides of the pseudo-gate structure 520.

[0118] The source-drain doping layer 540 is used as the source or drain of the fully-depleted surround gate transistor. When the fully-depleted surround gate transistor operates, the source-drain doping layer 540 is used to provide a carrier source.

[0119] Correspondingly, in this embodiment, after the inner sidewall 522 is formed, the source-drain doping layer 540 is formed in the source-drain grooves 545 on both sides of the pseudo-gate structure 520.

[0120] Reference Figure 20 , in this embodiment, after the source-drain doping layer 540 is formed and before the pseudo-gate structure 520 is removed, the forming method further includes: forming an interlayer dielectric layer 550 on the shallow trench isolation structure on the side of the pseudo-gate structure 520, and the interlayer dielectric layer 550 covers the source-drain doping layer 540.

[0121] The interlayer dielectric layer 550 is used to achieve electrical isolation between adjacent semiconductor structures.

[0122] Specifically, the material of the interlayer dielectric layer 550 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be other suitable dielectric materials.

[0123] Reference Figure 21 , in this embodiment, after forming the source / drain doping layer 540 and before removing the dummy gate structure 520, the forming method further includes: removing the hard mask structure 530 to expose the top of the dummy gate structure 520.

[0124] Removing the hard mask structure 530 to expose the top of the dummy gate structure 520 facilitates subsequent removal of the dummy gate structure 520 from the top of the dummy gate structure 520.

[0125] Specifically, after forming the interlayer dielectric layer 550, the hard mask structure 530 is removed, and during the process of removing the hard mask structure 530, a part of the thickness of the interlayer dielectric layer 550 is also removed.

[0126] Reference Figure 22 , after forming the source / drain doping layer 540, the dummy gate structure 520 is removed, and an opening 561 is formed at the position of the dummy gate structure 520. The opening 561 exposes the top and sidewalls of the channel stack 510.

[0127] The opening 561 provides a process basis for subsequent formation of the gate structure, and forming the opening 561 at the position of the dummy gate structure 520 also facilitates subsequent removal of the first sacrificial layer 503 and the second sacrificial layer 512 via the opening 561.

[0128] Continuing to refer to Figure 22 , via the opening 561, the first sacrificial layer 503 and the second sacrificial layer 512 are removed to form a through groove 562 between the raised structure 502 and the channel layer 511, or, a through groove 562 between the raised structure 502 and the channel layer 511 and between adjacent channel layers 511.

[0129] The through groove 562 provides a process basis for subsequent formation of a gate structure between the raised structure 502 and the channel layer 511, or, a gate structure between the raised structure 502 and the channel layer 511 and between adjacent channel layers 511.

[0130] In this embodiment, the process of removing the first sacrificial layer 503 and the second sacrificial layer 512 includes an isotropic etching process. In the isotropic etching process, there is an etching selectivity between the first sacrificial layer 503 and the channel layer 511 and the substrate 501, and between the second sacrificial layer 512 and the channel layer 511 and the substrate 501.

[0131] The isotropic etching process has isotropic etching characteristics, so it is convenient to completely remove the first sacrificial layer 503 and the second sacrificial layer 512 by exposing the tops and sidewalls of the exposed first sacrificial layer 503 and the second sacrificial layer 512.

[0132] It should be noted that the etching selectivity between the first sacrificial layer 503 and the channel layer 511 and the substrate 501 should not be too small. If the etching selectivity between the first sacrificial layer 503 and the channel layer 511 and the substrate 501 is too small, it is easy to result in poor effect of reducing damage to the channel layer 511 and the substrate 501. Therefore, in this embodiment, the etching selectivity between the first sacrificial layer 503 and the channel layer 511 and the substrate 501 is greater than 100:1.

[0133] It should also be noted that the etching selectivity between the second sacrificial layer 512 and the channel layer 511 and the substrate 501 should not be too small. The reason why the etching selectivity between the second sacrificial layer 512 and the channel layer 511 and the substrate 501 should not be too small is similar to the reason why the etching selectivity between the first sacrificial layer 503 and the channel layer 511 and the substrate 501 should not be too small, so it will not be elaborated here. Therefore, in this embodiment, the etching selectivity between the second sacrificial layer 512 and the channel layer 511 and the substrate 501 is greater than 100:1.

[0134] In this embodiment, the process of removing the first sacrificial layer 503 and the second sacrificial layer 512 includes an isotropic wet etching process; the process parameters of the wet etching process include: the etching solution includes a mixed solution of acetic acid, hydrogen peroxide, ammonium hydroxide, ammonium fluoride, hydrogen fluoride and water, wherein the volume percentage concentration of acetic acid is 0.1% to 10%, the volume percentage concentration of hydrogen peroxide is 1% to 5%, the volume percentage concentration of ammonium hydroxide is 0.1% to 5%, the volume percentage concentration of ammonium fluoride is 5% to 20%, the volume percentage concentration of hydrogen fluoride is less than or equal to 2%, and the volume percentage concentration of distilled water is greater than 70%, the temperature of the etching solution is 0 degrees Celsius to 90 degrees Celsius, and the process time is 30 seconds to 720 seconds.

[0135] The cost of the wet etching process is relatively low, the operation steps are simple, and a large etching selectivity can also be achieved. The oxidation rates of acetic acid and hydrogen peroxide for different materials are different. The etching solution includes acetic acid and hydrogen peroxide, so that when oxidizing the first sacrificial layer 503 and the second sacrificial layer 512 of different materials, the oxidation effect is better. Ammonium hydroxide and ammonium fluoride are used to remove the oxidized first sacrificial layer 503 and the second sacrificial layer 512.

[0136] By setting the process parameters of the wet etching process within the above ranges, it is beneficial to further improve the etching selectivity between the first sacrificial layer 503 and the channel layer 511 and the substrate 501, as well as the etching selectivity between the second sacrificial layer 512 and the channel layer 511 and the substrate 501. It is also beneficial to improve the etching uniformity and reduce the probability of residues in the first sacrificial layer 503 and the second sacrificial layer 512.

[0137] As an example, the water is specifically distilled water.

[0138] Reference Figure 23 , and in combination with reference Figure 22 , a gate structure 560 is formed in the opening 561 and the through groove 562.

[0139] The gate structure 560 is a device gate structure and is used to form a field effect transistor together with the conductive channel and the source-drain doping layer 540.

[0140] Since the length L4 of the pseudo-gate structure 520 is greater than the length L1 of the convex structure 502, and the gate structure 560 covers the top of the convex structure 502 and the sidewalls in the direction of the length L1 of the convex structure 502, correspondingly, the increased channel length is twice the height H1 of the convex structure 502. Compared with the scheme where the substrate at the bottom of the channel layer does not have a convex structure, the length of the gate structure 560 and the length of the channel are increased. Correspondingly, the control force of the gate structure 560 on the channel is increased, the short-channel effect is improved, the leakage current of the sub-threshold device is reduced, so that a larger drive current can be obtained, and thus the performance of the semiconductor structure is improved.

[0141] Specifically, the gate structure 560 fills the opening 561 and the through groove 562, that is, the gate structure 560 is located at the position of the pseudo-gate structure 520, and fills the top and sidewalls of the convex structure 502 between the channel layer 511 and the substrate 501, or fills the top and sidewalls of the convex structure 502 between the channel layer 511 and the substrate 501 and between adjacent channel layers 511.

[0142] In this embodiment, the gate structure 560 includes a gate dielectric layer (not labeled) and a gate electrode layer (not labeled) covering the gate dielectric layer.

[0143] The gate dielectric layer is used to isolate the gate electrode layer from the channel.

[0144] The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0145] Specifically, the gate structure 560 is a metal gate structure. Therefore, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. The gate electrode layer includes a work function layer and an electrode layer covering the work function layer, or may only include the work function layer.

[0146] Correspondingly, the gate dielectric layer includes a high-k gate dielectric layer. The material of the high-k gate dielectric layer is a high-k dielectric material, which refers to a dielectric material with a relative dielectric constant greater than that of silicon dioxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the high-k gate dielectric layer is HfO2.

[0147] It should be noted that the semiconductor structure can be formed by the formation method described in the foregoing embodiments, or can be formed by other formation methods. For a specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the foregoing embodiments, and details are not repeated herein.

[0148] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate, the substrate including a substrate having a raised structure; A channel structure layer, suspended on the raised structure, the channel structure layer including one or more channel layers sequentially arranged at intervals from bottom to top, and the length of the channel layer being greater than the length of the raised structure; Source-drain doping layers, located on the substrate on both sides of the channel structure layer along the length direction of the channel layer, and connected to both ends of the channel layer; A gate structure, located between the source-drain doping layers, the gate structure spanning the channel structure layer and surrounding the channel layer, and the gate structure further covering the top and the sidewalls of the raised structure.

2. The semiconductor structure according to claim 1, wherein The semiconductor structure further includes: an inner sidewall, located between the source-drain doping layer and the gate structure at the bottom of the channel layer.

3. The semiconductor structure according to claim 2, wherein The relationship between the length of the gate structure located between the inner sidewall and the raised structure and the length of the channel layer satisfies: 4 < l3 / l2 < 10, where l2 is the length of the gate structure located between the inner sidewall and the raised structure, and l3 is the length of the channel layer.

4. The semiconductor structure according to claim 1, wherein The relationship between the height and the length of the raised structure satisfies: 1 < h1 / l1 < 100, where h1 is the height of the raised structure, l1 is the length of the raised structure, and the length direction of the raised structure is parallel to the length direction of the channel.

5. The semiconductor structure according to claim 1, wherein, The number of the channel layers is less than or equal to 10.

6. The semiconductor structure according to claim 1, wherein The sidewall of the raised structure covered by the gate structure is the sidewall in the length direction of the raised structure.

7. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate, the substrate including a substrate having a raised structure, a first sacrificial layer being formed on the substrate on the side of the raised structure, the first sacrificial layer covering the sidewalls of the raised structure, and one or more channel stacks being sequentially stacked in the longitudinal direction on the first sacrificial layer and the raised structure, each channel stack including a second sacrificial layer and a channel layer located on the second sacrificial layer; Forming a dummy gate structure spanning the channel stack on the channel stack at the top of the raised structure, the dummy gate structure covering a part of the top and a part of the sidewalls of the channel stack, and in a direction perpendicular to the extending direction of the dummy gate structure, the length of the dummy gate structure being greater than the length of the raised structure; Forming source-drain doping layers connected to both ends of the channel layer in the channel stack and the first sacrificial layer on both sides of the dummy gate structure; After forming the source-drain doping layer, removing the dummy gate structure, forming an opening at the position of the dummy gate structure, and the opening exposing the top and the sidewalls of the channel stack; Via the opening, removing the first sacrificial layer and the second sacrificial layer to form a through groove between the raised structure and the channel layer, or a through groove between the raised structure and the channel layer and between adjacent channel layers; Forming a gate structure in the opening and the through groove.

8. The method for forming a semiconductor structure according to claim 7, wherein Before forming the source / drain doping layer, the forming method further includes: removing the channel stack and the first sacrificial layer on both sides of the dummy gate structure to form a source / drain groove surrounded by the channel stack, the first sacrificial layer, and the substrate; after forming the source / drain groove, transversely removing a partial width of the first sacrificial layer and the second sacrificial layer in a direction perpendicular to the extending direction of the dummy gate structure to form an inner trench between the channel layer and the substrate, or forming inner trenches between the channel layer and the substrate and between adjacent channel layers; forming inner sidewalls in the inner trenches; After forming the inner sidewalls, form source / drain doping layers in the source / drain grooves on both sides of the dummy gate structure.

9. The method for forming a semiconductor structure according to claim 7, wherein In the step of providing the substrate, the material of the first sacrificial layer is the same as that of the second sacrificial layer.

10. The method for forming a semiconductor structure according to claim 7, wherein, The number of the channel layers is less than or equal to 10.

11. The method for forming a semiconductor structure according to claim 7, wherein, In the step of providing the substrate, the material of the first sacrificial layer includes one or more of silicon germanide, germanium, silicon carbide, cobalt silicide, nickel silicide, gallium arsenide, indium arsenide, indium gallium arsenide, and indium phosphide.

12. The method for forming a semiconductor structure according to claim 7, wherein The process of removing the first sacrificial layer and the second sacrificial layer includes an isotropic etching process, in which an etching selectivity exists between the first sacrificial layer and the channel layer and the substrate, and between the second sacrificial layer and the channel layer and the substrate.

13. The method for forming a semiconductor structure according to claim 12, wherein, The etching selectivity between the first sacrificial layer and the channel layer and the substrate is greater than 100:

1.

14. The method for forming a semiconductor structure according to claim 12, wherein, The etching selectivity between the second sacrificial layer and the channel layer and the substrate is greater than 100:

1.

15. The method for forming a semiconductor structure according to claim 12, wherein The process of removing the first sacrificial layer and the second sacrificial layer includes an isotropic wet etching process; The process parameters of the wet etching process include: the etching solution includes a mixed solution of acetic acid, hydrogen peroxide, ammonium hydroxide, ammonium fluoride, hydrogen fluoride, and water, wherein the volume percentage concentration of acetic acid is 0.1% to 10%, the volume percentage concentration of hydrogen peroxide is 1% to 5%, the volume percentage concentration of ammonium hydroxide is 0.1% to 5%, the volume percentage concentration of ammonium fluoride is 5% to 20%, the volume percentage concentration of hydrogen fluoride is less than or equal to 2%, and the volume percentage concentration of distilled water is greater than 70%. The temperature of the etching solution is 0 degrees Celsius to 90 degrees Celsius, and the process time is 30 seconds to 720 seconds.

16. The method for forming a semiconductor structure according to claim 7, wherein, The step of providing the substrate includes: Providing an initial substrate; In a partial area, removing a partial thickness of the initial substrate to form a raised structure, and the remaining thickness of the initial substrate serves as the substrate; Forming a first sacrificial layer on the substrate on the side of the raised structure, and the first sacrificial layer covers the sidewall of the raised structure; Forming one or more channel material stacks stacked longitudinally in sequence on the first sacrificial layer and the raised structure, and each channel material stack layer includes a second sacrificial material layer and a channel material layer located on the second sacrificial material layer; Performing a patterning process on the channel material stack, and the remaining channel material stack is used as the channel stack.

17. The method for forming a semiconductor structure according to claim 16, wherein, After forming the channel stack, it further includes: patterning the raised structure and the first sacrificial layer along the channel stack.

18. The method for forming a semiconductor structure according to claim 7 or 17, wherein, In the step of providing the substrate, along the preset channel length direction, the first sacrificial layer protrudes on the substrate on both sides of the protruding structure.

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