Semiconductor device and manufacturing method, power module, power conversion circuit and vehicle

Abstract

The present invention discloses a semiconductor device and a preparation method, a power module, a power conversion circuit and a vehicle, wherein the semiconductor device includes: a semiconductor body, the semiconductor body including a well region, a first region and a second region, the first region is arranged on the first surface of the semiconductor body, and the well region is arranged on a side of the first region away from the first surface; the first surface is also provided with a gate trench and a source trench, the second region is arranged on the first surface and extends to the bottom and sidewall of the source trench, and the gate is located in the gate trench; the source trench structure is located in the source trench; a first ohmic contact layer is located on the first surface, the first ohmic contact layer at least covers a portion of the second region; a second ohmic contact layer is located on a side of the first ohmic contact layer away from the semiconductor body, the second ohmic contact layer at least covers the area of ​​the first surface not covered by the first ohmic contact layer, thereby reducing the on-resistance of the semiconductor device and improving the conductive efficiency of the device.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle. Background Art

[0002] Silicon carbide (SiC) has excellent physical and electrical properties. Currently, semiconductor devices made of SiC have advantages such as high current density and small cell pitch, and are widely used.

[0003] However, since the work functions of silicon carbide of different conductivity types in semiconductor devices vary greatly, the resistance values ​​in some conductivity type regions will be relatively large, thereby affecting the on-resistance of the semiconductor device. Summary of the Invention

[0004] The present invention provides a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, which reduce the on-resistance of the semiconductor device and improve the conductive efficiency of the device.

[0005] In a first aspect, an embodiment of the present invention provides a semiconductor device, including:

[0006] A semiconductor body, the semiconductor body further comprising a well region, a first region, and a second region, wherein the first region is disposed on a first surface of the semiconductor body, and the well region is disposed on a side of the first region away from the first surface; the first surface is further provided with a gate trench and a source trench, and the second region is disposed on the first surface and extends to the sidewalls and bottom of the source trench; the first region is of a first conductivity type, and the well region and the second region are of a second conductivity type;

[0007] a gate, located in the gate trench;

[0008] a source trench structure, located in the source trench;

[0009] a first ohmic contact layer, located on the first surface, wherein the first ohmic contact layer at least covers a portion of the second region;

[0010] A second ohmic contact layer is located on the first surface, wherein at least a portion of the second ohmic contact layer is arranged in the same layer as the first ohmic contact layer, and the second ohmic contact layer at least covers the area of ​​the first surface not covered by the first ohmic contact layer.

[0011] Optionally, the first ohmic contact layer is located on the first surface between the gate and the source trench structure, and the orthographic projection of the first ohmic contact layer on the first surface does not overlap with the orthographic projection of the source trench structure on the first surface.

[0012] Optionally, in a first direction, the distance between the first ohmic contact layer and the gate is a first distance to prevent the first ohmic contact layer from contacting and reacting with the gate, and the first direction is perpendicular to the first surface and points toward the second surface.

[0013] Optionally, in the first direction, the distance between the first ohmic contact layer and the source trench structure is a second distance to avoid the first ohmic contact layer from contacting and reacting with the source trench structure, and the first direction is perpendicular to the direction pointing from the first surface to the second surface.

[0014] Optionally, the material of the first ohmic contact layer includes at least one of nickel, aluminum and tungsten, or any combination thereof; and the material of the second ohmic contact layer includes one of titanium and titanium nitride, or any combination thereof.

[0015] In a second aspect, an embodiment of the present invention provides a power module, comprising a substrate and the semiconductor device according to any embodiment of the present invention, wherein the substrate is used to support the semiconductor device.

[0016] In a third aspect, an embodiment of the present invention provides a power conversion circuit, wherein the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction;

[0017] The power conversion circuit includes a circuit board and the semiconductor device according to any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0018] In a fourth aspect, an embodiment of the present invention provides a vehicle, comprising a load and the power conversion circuit described in an embodiment of the present invention, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0019] In a fifth aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising:

[0020] A semiconductor body is provided, the semiconductor body comprising a well region, a first region, and a second region, wherein the first region is disposed on a first surface of the semiconductor body, and the well region is disposed on a side of the first region away from the first surface; the first surface is further provided with a gate trench and a source trench, and the second region is disposed on the first surface and extends to the sidewalls and bottom of the source trench; the first region is of a first conductivity type, and the well region and the second region are of a second conductivity type;

[0021] forming a gate in the gate trench;

[0022] forming a source trench structure in the source trench;

[0023] forming a first ohmic contact layer on the first surface, wherein the first ohmic contact layer at least covers a portion of the second region;

[0024] A second ohmic contact layer is formed on the first surface, at least a portion of the second ohmic contact layer is disposed on the same layer as the first ohmic contact layer, and the second ohmic contact layer at least covers the area of ​​the first surface not covered by the first ohmic contact layer.

[0025] Optionally, forming a first ohmic contact layer on the first surface includes:

[0026] forming a sacrificial layer on the first surface;

[0027] removing a portion of the sacrificial layer so that the remaining sacrificial layer at least covers a portion of the second region;

[0028] forming a second ohmic contact first sub-layer on the same layer as the sacrificial layer, wherein the second ohmic contact first sub-layer at least covers the area of ​​the first surface not covered by the sacrificial layer;

[0029] removing the remaining sacrificial layer;

[0030] The first ohmic contact layer is formed at the position of the remaining sacrificial layer.

[0031] Optionally, forming the first ohmic contact layer at the position of the remaining sacrificial layer includes:

[0032] Laying the first ohmic contact layer on a side of the second ohmic contact first sub-layer away from the semiconductor body, wherein the first ohmic contact layer at least covers the position of the remaining sacrificial layer;

[0033] After high-temperature annealing, a portion of the first ohmic contact layer is removed, and the first ohmic contact layer at the position of the remaining sacrificial layer is retained.

[0034] Optionally, forming a second ohmic contact layer on the first surface includes:

[0035] A second ohmic contact second sublayer is formed on a side of the first ohmic contact layer away from the semiconductor body, and the second ohmic contact first sublayer and the second ohmic contact second sublayer constitute the second ohmic contact layer, wherein at least part of the second ohmic contact layer is arranged in the same layer as the first ohmic contact layer.

[0036] Optionally, the thickness of the second ohmic contact first sub-layer is smaller than the thickness of the sacrificial layer.

[0037] A semiconductor device provided in an embodiment of the present invention comprises a well region and a first region disposed on a first surface of a semiconductor body, wherein the first region is disposed on the first surface, and the well region is disposed on a side of the first region away from the first surface; a gate trench and a source trench are further disposed on the first surface, and a second region is disposed on the first surface and extends to the sidewalls and bottom of the source trench; the first region is of a first conductivity type, and the well region and the second region are of a second conductivity type; a first ohmic contact layer is further disposed on the first surface of the semiconductor body, the first ohmic contact layer covering at least a portion of the second region, and a second ohmic contact layer is located on the first surface, covering at least the area of ​​the first surface not covered by the first ohmic contact layer. The first ohmic contact layer is used to reduce the ohmic contact resistance of the second region, thereby reducing the impact of the large difference in work function between the first region and the second region, thereby reducing the on-resistance of the semiconductor device and improving the conductive efficiency of the device. The second ohmic contact layer is used to cover the source trench structure, thereby preventing the reaction consumption of the source trench structure material and the formation of structural defects such as voids. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0039] Figure 2 A schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0040] Figure 3 A flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0041] Figure 4 1 is a flow chart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0042] Figures 5 to 15 Schematic diagram of the intermediate structure of the preparation process provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0043] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0044] Figure 1 A schematic diagram of the structure of a semiconductor device provided by an embodiment of the present invention is shown in FIG. Figure 1 ,include:

[0045] A semiconductor body 100 includes a well region 10, a first region 20, and a second region 30. The first region 20 is disposed on a first surface of the semiconductor body 100, and the well region 10 is disposed on a side of the first region 20 away from the first surface. The first surface is further provided with a gate trench 50 and a source trench 40. The second region 30 is disposed on the first surface and extends to the sidewalls and bottom of the source trench 40. The first region 20 is of a first conductivity type, and the well region 10 and the second region 30 are of a second conductivity type.

[0046] a gate 52 located in the gate trench 50;

[0047] a source trench structure 42 located in the source trench 40;

[0048] A first ohmic contact layer 60 is located on the first surface, and the first ohmic contact layer 60 at least covers a portion of the second region 30;

[0049] The second ohmic contact layer 70 is located on the first surface, wherein at least a portion of the second ohmic contact layer 70 is disposed in the same layer as the first ohmic contact layer 60 , and the second ohmic contact layer 70 at least covers the area of ​​the first surface not covered by the first ohmic contact layer 60 .

[0050] Specifically, the semiconductor device is a silicon carbide trench metal oxide semiconductor field effect transistor (MOSFET). Exemplarily, the semiconductor body 100 may include a substrate 80, an epitaxial layer 90, a well region 10, a first region 20, and a second region 30. The material of the substrate 80 and the epitaxial layer 90 may be the same or different. Exemplarily, the materials of the substrate 80 and the epitaxial layer 90 may include silicon or silicon carbide. An epitaxial layer 90 is formed on one side of the substrate 80. Exemplarily, the epitaxial layer 90 may be formed on the surface of the substrate 80 by epitaxial growth. The surface of the epitaxial layer 90 facing away from the substrate 80 serves as the first surface. The first region 20 is disposed on the first surface, and the well region 10 is disposed on the side of the first region 20 facing away from the first surface. The well region 10 and the first region 20 may be formed by epitaxial growth, ion implantation, or vapor deposition. The well region 10 and the first region 20 form the conductive channel of the semiconductor device. The first region 20 is of the first conductivity type, and the well region 10 is of the second conductivity type.

[0051] The gate trench 50 and the source trench 40 are formed on the first surface by an etching process, wherein the gate trench 50 and the source trench 40 can be formed by simultaneous etching in the same preparation process. In some embodiments, in order to make the gate trench 50 and the source trench 40 have different depths and shapes, the gate trench 50 and the source trench 40 can also be formed by step-by-step etching. The gate trench 50 and the source trench 40 extend from the first surface to the inside of the epitaxial layer 90, passing through the first region 20 and the well region 10. The source trench 40 is located on one side of the gate trench 50, and the source trench 40 here can be an annular trench, which is arranged to be a structure surrounding the gate trench 50. The source trench 40 can also be an independent trench, with multiple source trenches 40 distributed on both sides of the gate trench 50. For example, see Figure 1 The source trench 40 is disposed on both sides of the gate trench 50. The two source trenches 40 can be symmetrical or asymmetrical relative to the gate trench 50. The second region 30 is disposed in an area where the sidewalls and / or bottom of the source trench 40 extend into the semiconductor body 100, extending to the first surface in the thickness direction of the semiconductor body 100. Exemplarily, the second region 30 can be formed by ion implantation. The conductivity type of the second region 30 is the same as that of the well region 10. A depletion region can be formed between the second region 30 and the epitaxial layer 90, which can shield the electric field of the gate, thereby improving the problem of gate oxide breakdown and ensuring the reliability of the device.

[0052] It should be noted that in the embodiment of the present invention, the first conductivity type may be an N-type conductivity type, and the second conductivity type may be a P-type conductivity type, or the first conductivity type may be a P-type conductivity type, and the second conductivity type may be an N-type conductivity type. P+ and N+ shown in the drawings indicate that the ion doping concentration in the region is high, and P- and N- indicate that the ion doping concentration in the region is low. The N-type conductivity type can be obtained by doping ions, for example, the doping ions can be P (phosphorus) or N (nitrogen) ions, and the P-type conductivity type can be obtained by doping ions, for example, the doping ions can be Al (aluminum) ions or B (boron) ions. For example, in the embodiment of the present invention, the first conductivity type is an N-type conductivity type and the second conductivity type is a P-type conductivity type. When the semiconductor device is an N-type device, the substrate 80 is an N+ conductivity type, for example, it can be an N+ silicon carbide substrate 80; the epitaxial layer 90 is an N- conductivity type, for example, it can be an N-silicon carbide epitaxial layer 90; when the semiconductor device is a P-type device, the substrate 80 is a P+ conductivity type and the epitaxial layer 90 is a P- conductivity type.

[0053] A source trench structure 42 is disposed within the source trench 40. Exemplarily, a first insulating layer 41 is disposed between the source trench 40 and the source trench structure 42. The first insulating layer 41 can be formed by oxidizing the inner wall and bottom of the source trench 40. The source trench structure 42 can be made of polysilicon or a metal material. In other embodiments, the source trench structure 42 may not be disposed within the source trench 40, or a portion of the source trench structure 42 may be disposed within the source trench 40.

[0054] A gate 52 is disposed within the gate trench 50. Exemplarily, a second insulating layer 51 is disposed between the gate trench 50 and the gate 52. The second insulating layer 51 can be obtained by oxidizing the inner wall and bottom of the gate trench 50 and can be referred to as a gate oxide layer. The gate oxide layer can be made of a high dielectric constant (K) material. The gate 52 can be made of polysilicon. The well regions 10 on both sides of the gate can form vertical conductive channels, eliminating the junction field-effect transistor (JFET) region and lowering the on-resistance of the semiconductor device. The first insulating layer 41 in the source trench 40 can be the same insulating layer as the second insulating layer 51 in the gate trench 50. Therefore, during fabrication, the first insulating layer 41 in the source trench 40 and the second insulating layer 51 in the gate trench 50 can be formed simultaneously.

[0055] A source electrode 110 is provided on the first surface of the semiconductor body 100. Exemplarily, the source electrode 110 can be formed by sputtering or other methods. The source electrode 110 is a metal conductive layer, which can be titanium (Ti), nickel (Ni), or silver (Ag). A third insulating layer 120 is also provided between the source electrode 110 and the gate 52. The third insulating layer 120 can be an interlayer dielectric (ILD). The third insulating layer 120 covers the surface of the gate 52 and isolates the gate 52 from the source electrode 110. To reduce the contact resistance between the first region 20 and the second region 30 of the source electrode 110 on the first surface, an ohmic contact layer can be provided between the source electrode 110 and the first surface, where the first surface has adjacent first and second regions 20 and 30. A first ohmic contact layer 60 is provided on the first surface, wherein the first ohmic contact layer 60 at least covers a portion of the second region 30 , that is, the first ohmic contact layer 60 is in contact with at least the second region 30 , and the first ohmic contact layer 60 is utilized to reduce the contact resistance between the source 110 and the second region 30 .

[0056] The second ohmic contact layer 70 is disposed on a side of the first ohmic contact layer 60 away from the semiconductor body 100. At least a portion of the second ohmic contact layer 70 is disposed in the same layer as the first ohmic contact layer 60. The second ohmic contact layer 70 covers areas of the first surface not covered by the first ohmic contact layer 60. In other words, depending on the contact range between the first ohmic contact layer 60 and the second region 30, the second ohmic contact layer 70 may cover a portion of the first region 20 and a portion of the second region 30 on the first surface. The second ohmic contact layer 70 may also cover the source trench structure. The second ohmic contact layer 70 may be made of a material that does not react with the source trench structure 42, thereby preventing the second ohmic contact layer 70 from reacting with the source trench structure 42 and consuming the material, thereby preventing structural defects such as voids.

[0057] For example, the first region 20 may be an N+ doped region, and the second region 30 may be a P+ doped region. For the first region 20, the material of the first ohmic contact layer 60 may include one or any combination of nickel, aluminum, and tungsten. For the second region 30, the metal material of the second ohmic contact layer 70 may include one or any combination of titanium and titanium nitride. The material of the first ohmic contact layer 60 may form a good ohmic contact with both the first region 20 and the second region 30. Therefore, the first ohmic contact layer 60 may be in contact with both the first region 20 and the second region 30, such as Figure 1 As shown in FIG, the first ohmic contact layer 60 covers a portion of the second region 30, and the first ohmic contact layer 60 covers a portion of the first region 20. For example, Figure 2 A schematic diagram of the structure of another semiconductor device provided by an embodiment of the present invention is shown in FIG. Figure 2 ,and Figure 1 The difference is that the first ohmic contact layer 60 may also only cover the entire or part of the second region 30. In some embodiments, depending on the conductive channel position of the semiconductor device, the first ohmic contact layer 60 may also cover the second region 30 on the side of the source trench structure 42 close to the gate 52. Figure 1 and Figure 2 The second ohmic contact layer 70 can cover part of the first region 20 and part of the second region 30 on the first surface. The second ohmic contact layer 70 can form a good ohmic contact with the first region 20, and the second ohmic contact layer 70 is used to reduce the contact resistance between the source 110 and the first region 20.

[0058] The second ohmic contact layer 70 may cover the source trench structure 42 , thereby preventing the second ohmic contact layer 70 from reacting and consuming the material of the source trench structure 42 and generating structural defects such as voids.

[0059] In a semiconductor device provided in an embodiment of the present invention, a well region 10 and a first region 20 are provided on a first surface of a semiconductor body 100, wherein the first region 20 is provided on the first surface, and the well region 10 is provided on a side of the first region 20 away from the first surface; a gate trench 50 and a source trench 40 are also provided on the first surface, and the second region 30 is provided on the first surface and extends to the sidewall and bottom of the source trench 40; the first region 20 is of a first conductivity type, and the well region 10 and the second region 30 are of a second conductivity type; a first ohmic contact layer 60 is also provided on the first surface of the semiconductor body 100, and the first ohmic contact layer 60 covers at least a portion of the second region 30, and a second ohmic contact layer 70 is located on the first surface, and the second ohmic contact layer 70 covers at least the area of ​​the first surface not covered by the first ohmic contact layer 60. Therefore, the first ohmic contact layer 60 is used to reduce the ohmic contact resistance of the second region 30, thereby reducing the impact of the large difference in work function between the first region 20 and the second region 30, thereby reducing the on-resistance of the semiconductor device and improving the conductive efficiency of the device. The second ohmic contact layer 70 is used to cover the source trench structure 42 to prevent the source trench structure 42 material from being consumed by reaction and forming structural defects such as voids.

[0060] Combine Figure 1 Optionally, the first ohmic contact layer 60 is located on the first surface between the gate 52 and the source trench structure 42 , and the orthographic projection of the first ohmic contact layer 60 on the first surface does not overlap with the orthographic projection of the source trench structure 42 on the first surface.

[0061] Specifically, the first region 20 and the well region 10 on both sides of the gate 52 can form a vertical conductive channel. The first ohmic contact layer 60 is disposed on the first surface between the gate 52 and the source trench structure 42, covering at least a portion of the second region 30. The first ohmic contact layer 60 is used to reduce the contact resistance between the source 110 and the second region 30. When the first region 20 is an N+ doped region and the second region 30 is a P+ doped region, to prevent the polysilicon of the source trench structure 42 from reacting with metals such as aluminum or nickel in the first ohmic contact layer 60 and generating voids, the first ohmic contact layer 60 on the first surface does not overlap with the source trench structure 42 in a projected position. In other words, the first ohmic contact layer 60 does not contact the source trench structure 42, thereby preventing the polysilicon from reacting with the first ohmic contact layer 60.

[0062] Optionally, in the first direction X, the distance between the first ohmic contact layer 60 and the gate 52 is a first distance D2 to prevent the first ohmic contact layer 60 from contacting and reacting with the gate 52 . The first direction X is perpendicular to the first surface and points toward the second surface.

[0063] Specifically, when the first ohmic contact layer 60 is too close to the gate 52 on the sidewall of the source trench 40, the first ohmic contact layer 60 and the gate 52 react, causing material migration and resulting in leakage. For example, when the first ohmic contact layer 60 includes nickel, the nickel easily reacts with the polysilicon material of the gate 52, causing material migration and thus leakage, which in turn affects the performance of the semiconductor device. Therefore, the distance between the first ohmic contact layer 60 and the gate 52 should be limited to a first distance D2. Exemplarily, the first distance D2 is at least greater than 10 nm.

[0064] Combine Figure 1 Optionally, in the first direction X, the distance between the first ohmic contact layer 60 and the source trench structure 42 is a second distance D1 to prevent the first ohmic contact layer 60 from contacting and reacting with the source trench structure 42 .

[0065] Specifically, when the first ohmic contact layer 60 is too close to the source trench structure 42, the first ohmic contact layer 60 is likely to react with the source trench structure 42, causing material migration and leading to leakage, thereby affecting the performance of the semiconductor device. Therefore, the distance between the second ohmic contact layer 70 and the source trench structure 42 should be limited to a second distance D1. Exemplarily, the second distance D1 is at least greater than 10 nm.

[0066] An embodiment of the present invention provides a power module based on the above embodiments, including a substrate and a semiconductor device according to any embodiment of the present invention, wherein the substrate is used to support the semiconductor device.

[0067] The power module provided by the technical solution of the embodiment of the present invention has the same beneficial effects as the semiconductor device of any embodiment of the present invention.

[0068] An embodiment of the present invention provides a power conversion circuit based on the above embodiments, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device as in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0069] The power conversion circuit provided by the technical solution of the embodiment of the present invention has the same beneficial effects as the semiconductor device of any embodiment of the present invention.

[0070] An embodiment of the present invention provides a vehicle based on the above embodiment, including a load and a power conversion circuit as in any embodiment of the present invention, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0071] An embodiment of the present invention provides a method for manufacturing a semiconductor device based on the above embodiment. Figure 3 A flowchart of a method for preparing a semiconductor device provided by an embodiment of the present invention, combined with Figure 1-2 ,refer to Figure 3 , the preparation method comprises:

[0072] S110. Provide a semiconductor body 100, wherein the semiconductor body 100 includes a well region 10, a first region 20, and a second region 30. The first region 20 is disposed on a first surface of the semiconductor body 100, and the well region 10 is disposed on a side of the first region 20 away from the first surface. The first surface is further provided with a gate trench 50 and a source trench 40. The second region 30 is disposed on the first surface and extends to the sidewalls and bottom of the source trench 40. The first region 20 is of a first conductivity type, and the well region 10 and the second region 30 are of a second conductivity type.

[0073] In the embodiment of the present invention, the first conductivity type may be an N-type conductivity type, and the second conductivity type may be a P-type conductivity type, or the first conductivity type may be a P-type conductivity type, and the second conductivity type may be an N-type conductivity type. P+ and N+ shown in the figures indicate that the ion doping concentration in the region is high, and P- and N- indicate that the ion doping concentration in the region is low. The N-type conductivity type can be obtained by doping ions, for example, the doping ions can be P (phosphorus) or N (nitrogen) ions, and the P-type conductivity type can be obtained by doping ions, for example, the doping ions can be Al (aluminum) ions or B (boron) ions. For example, in the embodiment of the present invention, the first conductivity type is an N-type conductivity type and the second conductivity type is a P-type conductivity type. When the semiconductor device is an N-type device, the substrate 80 is an N+ conductivity type, for example, an N+ silicon carbide substrate 80; the epitaxial layer 90 is an N- conductivity type, for example, an N-silicon carbide epitaxial layer 90; when the semiconductor device is a P-type device, the substrate 80 is a P+ conductivity type and the epitaxial layer 90 is a P- conductivity type.

[0074] Specifically, the semiconductor body 100 may include a substrate 80, an epitaxial layer 90, a well region 10, a first region 20, and a second region 30. The material of the substrate 80 and the epitaxial layer 90 may be the same or different. For example, the materials of the substrate 80 and the epitaxial layer 90 may include silicon or silicon carbide. An epitaxial layer 90 is formed on one side of the substrate 80. For example, the epitaxial layer 90 may be formed on the surface of the substrate 80 by epitaxial growth. The surface of the epitaxial layer 90 away from the substrate 80 serves as the first surface. The first region 20 is provided on the first surface, and the well region 10 is provided on the side of the first region 20 away from the first surface. The well region 10 and the first region 20 may be formed by epitaxial growth, ion implantation, or vapor deposition. The well region 10 and the first region 20 are used to form a conductive channel of the semiconductor device. The first region 20 is of the first conductivity type, and the well region 10 is of the second conductivity type.

[0075] The gate trench 50 and the source trench 40 are formed on the first surface by an etching process, wherein the gate trench 50 and the source trench 40 can be formed by simultaneous etching in the same preparation process. In some embodiments, in order to make the gate trench 50 and the source trench 40 have different depths and shapes, the gate trench 50 and the source trench 40 can also be formed by step-by-step etching. The gate trench 50 and the source trench 40 extend from the first surface to the inside of the epitaxial layer 90, passing through the first region 20 and the well region 10. The source trench 40 is located on one side of the gate trench 50, and the source trench 40 here can be an annular trench, which is arranged to be a structure surrounding the gate trench 50. The source trench 40 can also be an independent trench, with multiple source trenches 40 distributed on both sides of the gate trench 50. For example, see Figure 1 The source trench 40 is disposed on both sides of the gate trench 50. The two source trenches 40 can be symmetrical or asymmetrical relative to the gate trench 50. The second region 30 is disposed in an area where the sidewalls and / or bottom of the source trench 40 extend into the semiconductor body 100, extending to the first surface in the thickness direction of the semiconductor body 100. Exemplarily, the second region 30 can be formed by ion implantation. The conductivity type of the second region 30 is the same as that of the well region 10. A depletion region can be formed between the second region 30 and the epitaxial layer 90, which can shield the electric field of the gate, thereby improving the problem of gate oxide breakdown and ensuring the reliability of the device.

[0076] S120, forming a gate 52 in the gate trench 50;

[0077] Specifically, a gate 52 is disposed in the gate trench 50. The gate 52 is deposited by atomic layer deposition (ALD) or low pressure chemical vapor deposition (LPCVD). The material of the gate 52 may be polysilicon. Exemplarily, a second insulating layer 51 is further disposed between the gate trench 50 and the gate 52. The second insulating layer 51 may be obtained by oxidizing the inner wall and bottom of the gate trench 50. The second insulating layer 51 in the gate trench 50 may be a gate oxide layer. The gate oxide layer may be a high-K material, which may improve electron mobility at the gate 52 interface and reduce the on-resistance of the device.

[0078] S130 , forming a source trench structure 42 in the source trench 40 ;

[0079] Specifically, the material of the source trench structure 42 can be polysilicon or a metal material. When the material of the source trench structure 42 is the same as that of the gate, the source trench structure 42 can be formed simultaneously with the gate 52. In some other embodiments, the source trench structure 42 may not be provided in the source trench 40, or a portion of the source trench structure 42 may be provided in the source trench 40. Exemplarily, a first insulating layer 41 is further provided between the source trench 40 and the source trench structure 42. The first insulating layer 41 can be obtained by oxidizing the inner wall and bottom of the source trench 40. When the second insulating layer 51 is formed, the first insulating layer 41 can also be formed on the inner wall and bottom of the source trench 40 by the same process. In other words, the first insulating layer 41 and the second insulating layer 51 are formed simultaneously.

[0080] S140, forming a first ohmic contact layer 60 on the first surface, wherein the first ohmic contact layer 60 at least covers a portion of the second region 30;

[0081] Specifically, a source electrode is provided on the first surface of the semiconductor body 100. Exemplarily, the source electrode 110 can be formed by sputtering or other methods. The source electrode 110 is a metal conductive layer, which can be titanium (Ti), nickel (Ni), or silver (Ag). To reduce the contact resistance between the first region 20 and the second region 30 of the source electrode on the first surface, an ohmic contact layer can be provided between the source electrode and the first surface, wherein the first surface has adjacent first and second regions 20, 30. A first ohmic contact layer 60 is formed on the first surface by atomic layer deposition or other methods, wherein the first ohmic contact layer 60 at least covers a portion of the second region 30. That is, the first ohmic contact layer 60 is in contact with at least the second region 30. The first ohmic contact layer 60 is used to reduce the contact resistance between the source electrode and the second region 30.

[0082] S150 , forming a second ohmic contact layer 70 on the first surface, wherein at least a portion of the second ohmic contact layer 70 is disposed on the same layer as the first ohmic contact layer 60 , and the second ohmic contact layer 70 at least covers the area of ​​the first surface not covered by the first ohmic contact layer 60 .

[0083] Specifically, a second ohmic contact layer 70 is formed through a deposition process on a side of the first ohmic contact layer 60 distal from the semiconductor body 100. The second ohmic contact layer 70 covers the area of ​​the first surface not covered by the first ohmic contact layer 60. That is, depending on the contact range between the first ohmic contact layer 60 and the second region 30, the second ohmic contact layer 70 can cover a portion of the first region 20 and a portion of the second region 30 on the first surface. The second ohmic contact layer 70 can also cover the source trench structure. By covering the first region 20 and the second region 30 with different ohmic contact layers, the corresponding contact resistance is reduced, thereby reducing the impact of the significant difference in work function between the first region 20 and the second region 30, thereby reducing the on-resistance of the semiconductor device and improving the device's conductive efficiency.

[0084] The technical solution provided in the embodiment of the present invention includes providing a semiconductor body 100, wherein a well region 10 and a first region 20 are provided on the first surface of the semiconductor body 100, wherein the first region 20 is provided on the first surface, and the well region 10 is provided on the side of the first region 20 away from the first surface; the first surface is also provided with a gate trench 50 and a source trench 40, and the second region 30 is provided on the first surface and extends to the sidewall and bottom of the source trench 40; the first region 20 is of a first conductivity type, and the well region 10 and the second region 30 are of a second conductivity type; a first ohmic contact layer 60 is formed on the first surface of the semiconductor body 100, the first ohmic contact layer 60 covers at least a portion of the second region 30, and a second ohmic contact layer 70 is formed on the side of the first ohmic contact layer 60 away from the semiconductor body 100, and the second ohmic contact layer 70 covers at least the area of ​​the first surface not covered by the first ohmic contact layer 60. The first ohmic contact layer 60 is used to reduce the ohmic contact resistance of the second region 30, thereby reducing the impact of the large difference in work function between the first region 20 and the second region 30, thereby reducing the on-resistance of the semiconductor device and improving the conductive efficiency of the device. The second ohmic contact layer 70 is used to cover the source trench structure 42 to prevent the source trench structure 42 material from being consumed by reaction and forming structural defects such as voids.

[0085] The embodiment of the present invention is Figure 1 Taking the semiconductor device structure in as an example, a method for preparing a semiconductor device is introduced. Figure 4 is a flow chart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention. Figures 5 to 15 is a schematic diagram of an intermediate structure of a preparation process provided by an embodiment of the present invention, and the preparation method includes:

[0086] S210, forming an epitaxial layer 90 on one side of the substrate 80;

[0087] In the embodiment of the present invention, the first conductivity type is N-type conductivity type and the second conductivity type is P-type conductivity type. When the semiconductor device is an N-type device, the substrate 80 is N+ conductivity type, for example, it can be an N+ silicon carbide substrate 80; the epitaxial layer 90 is N- conductivity type, for example, it can be an N-silicon carbide epitaxial layer 90; when the semiconductor device is a P-type device, the substrate 80 is P+ conductivity type and the epitaxial layer 90 is P- conductivity type. The structure is as follows: Figure 5 shown.

[0088] S220 , forming a first region 20 on a side of the epitaxial layer 90 away from the substrate 80 as a first surface, and forming a well region 10 on a side of the first region 20 away from the first surface;

[0089] The well region 10 and the first region 20 are used to form a conductive channel of the semiconductor device. The well region 10 and the first region 20 can be formed by epitaxial growth, ion implantation or vapor deposition. Figure 6 shown.

[0090] S230 , forming a gate trench 50 and a source trench 40 on the first surface, respectively. Both the gate trench 50 and the source trench 40 extend from the first surface into the epitaxial layer 90 .

[0091] Specifically, the gate trench 50 and the source trench 40 can be set to different depths and shapes. The gate trench 50 and the source trench 40 are etched step by step in different preparation processes. The gate trench 50 and the source trench 40 pass through the first region 20 and the well region 10 and extend from the first surface to the epitaxial layer 90. Its structure is as follows Figure 7 shown.

[0092] S240 , forming a second region 30 on the sidewall and / or bottom of the source trench 40 ;

[0093] The second region 30 is formed on the sidewall and / or bottom of the source trench 40 by ion implantation. The first region 20 is of the first conductivity type, the well region 10 and the second region 30 are of the second conductivity type; the structure is as follows Figure 8 shown.

[0094] S250 , forming a gate 52 in the gate trench 50 , and forming a source trench structure 42 in the source trench 40 ;

[0095] Specifically, the gate trench 50 and the source trench 40 are provided with a gate 52 and a source trench structure 42 correspondingly. During preparation, the first insulating layer 41 in the source trench 40 and the second insulating layer 51 in the gate trench 50 can be formed simultaneously by a thermal oxidation process. After forming the first insulating layer 41, polysilicon can be deposited and then the entire surface of the polysilicon is etched back to fill the gate trench 50 with polysilicon to form the gate 52. At this time, the source trench 40 is also filled with polysilicon to form the source trench structure 42. Its structure is as follows Figure 9 shown.

[0096] S260, forming a third insulating layer 120 on the surface of the gate 52, the third insulating layer 120 covers the surface of the gate, exposing the ohmic contact area. The ohmic contact area includes the first area 20 and the second area 30 of the first surface. Its structure is as follows Figure 10 shown.

[0097] S270, forming a sacrificial layer 130 on the first surface; its structure is as follows Figure 11 shown.

[0098] Specifically, the sacrificial layer 130 may be made of SiN material and may be deposited on the first surface by atomic layer deposition or other methods.

[0099] S280 , removing a portion of the sacrificial layer 130 , so that the remaining sacrificial layer 130 at least covers a portion of the second region 30 ;

[0100] Specifically, the sacrificial layer 130 at the preset position can be removed by etching process, leaving the sacrificial layer 130 at the target position. In order to improve the accuracy of the etching position, a dry etching process can be used. The target position is the setting position of the first ohmic contact layer 60. Figure 1 and Figure 2 The first ohmic contact layer 60 may be disposed in a position that is in contact with both the first region 20 and the second region 30. Figure 1 As shown in FIG, the first ohmic contact layer 60 covers part of the second region 30, and the first ohmic contact layer 60 covers part of the first region 20. The first ohmic contact layer 60 may also be arranged to cover only all or part of the second region 30, as shown in FIG. Figure 2 In the embodiment of the present invention, Figure 1 As an example, the target position is set between the gate and source trench structures, covering part of the second region 30 and part of the first region 20. The intermediate structure is as follows Figure 12 shown.

[0101] S290 , forming a second ohmic contact first sub-layer 71 on the same layer as the sacrificial layer 130 , wherein the second ohmic contact first sub-layer 71 at least covers the area of ​​the first surface not covered by the sacrificial layer 130 ;

[0102] Specifically, the second ohmic contact first sub-layer 71 is formed by a deposition process. The second ohmic contact first sub-layer 71 is made of the same material as the second ohmic contact layer 70. By pre-laying the second ohmic contact first sub-layer 71, after removing the sacrificial layer 130, there will be a vacant area in the second ohmic contact first sub-layer 71. The vacant area can be used as a positioning area to subsequently position and set the first ohmic contact layer 60. Its structure is as follows: Figure 13 shown.

[0103] S300, removing the remaining sacrificial layer 130;

[0104] Specifically, when depositing the second ohmic contact first sublayer 71, the remaining sacrificial layer 130 will also have a small amount of second ohmic contact layer 70 material. When removing the remaining sacrificial layer 130, it can be removed by wet etching. The etching solution can be a phosphoric acid solution, which will not affect the second ohmic contact first sublayer 71.

[0105] It should be noted that when depositing the second ohmic contact first sublayer 71, the thickness of the second ohmic contact first sublayer 71 needs to be less than the thickness of the remaining sacrificial layer 130. Therefore, there is a step height difference between the second ohmic contact first sublayer 71 and the remaining sacrificial layer 130. The etching solution can remove the sacrificial layer 130 at the step, and can also remove the material of the second ohmic contact layer 70 attached to the sacrificial layer 130.

[0106] S310 , forming a first ohmic contact layer 60 at the position of the remaining sacrificial layer 130 .

[0107] Optionally, S310 forms a first ohmic contact layer 60 at the position of the remaining sacrificial layer 130 , including:

[0108] S311 , laying a first ohmic contact layer 60 on a side of the second ohmic contact first sub-layer 71 away from the semiconductor body 100 , wherein the first ohmic contact layer 60 at least covers the remaining position of the sacrificial layer 130 ;

[0109] Specifically, the first ohmic contact layer 60 is laid on the side of the second ohmic contact first sublayer 71 away from the semiconductor body 100 by evaporation or sputtering, wherein part of the first ohmic contact layer 60 will cover the position of the remaining sacrificial layer 130, and part of the first ohmic contact layer 60 also covers the second ohmic contact first sublayer 71.

[0110] S312 , after high-temperature annealing, removing a portion of the first ohmic contact layer, and retaining the first ohmic contact layer at the position of the remaining sacrificial layer.

[0111] Specifically, the first ohmic contact layer 60 is brought to or close to an equilibrium state by rapid thermal annealing (RTA). The first ohmic contact layer 60 can be alloyed with the SiC material of the first region 20 and / or the second region 30 by heating to a temperature of 500°C to 700°C, and then cleaned with a corrosive solution, such as a piranha corrosive solution, to remove the material of the first ohmic contact layer 60 attached to the second ohmic contact first sub-layer 71. Optionally, after removing the material of the first ohmic contact layer 60 attached to the second ohmic contact first sub-layer 71, rapid thermal annealing can be performed again to improve the stability of the first ohmic contact layer 60. Its structure is as follows: Figure 14 shown.

[0112] S320. Form a second ohmic contact second sublayer 72 on a side of the first ohmic contact layer 60 away from the semiconductor body 100. The second ohmic contact first sublayer 71 and the second ohmic contact second sublayer 72 constitute a second ohmic contact layer 70. At least part of the second ohmic contact layer 70 is arranged on the same layer as the first ohmic contact layer 60.

[0113] Specifically, a second ohmic contact second sublayer 72 is formed again through a deposition process, and the second ohmic contact first sublayer 71 and the second ohmic contact second sublayer 72 constitute a second ohmic contact layer 70. The second ohmic contact layer 70 covers the area of ​​the first surface that is not covered by the first ohmic contact layer 60. That is to say, according to the contact range between the first ohmic contact layer 60 and the second area 30, the second ohmic contact layer 70 can cover part of the first area 20 and part of the second area 30 on the first surface, and the second ohmic contact layer 70 can also cover the source trench structure. By covering the first area 20 and the second area 30 with different ohmic contact layers, the corresponding contact resistance is reduced, thereby reducing the impact of the large difference in work function between the first area 20 and the second area 30, thereby reducing the on-resistance of the semiconductor device and improving the conductive efficiency of the device. Its structure is as shown in FIG. Figure 15 shown.

[0114] S330, forming a source electrode on the first surface of the semiconductor body and a drain electrode 140 on the second surface of the semiconductor body, the first surface and the second surface are opposite surfaces, wherein the surface of the substrate 80 away from the epitaxial layer 90 is the second surface. Figure 1 shown.

[0115] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body, the semiconductor body comprising a well region, a first region, and a second region, wherein the first region is disposed on a first surface of the semiconductor body, and the well region is disposed on a side of the first region away from the first surface; the first surface is further provided with a gate trench and a source trench; the second region is disposed on the first surface and extends to the sidewall and bottom of the source trench; The first region is of a first conductivity type, and the well region and the second region are of a second conductivity type; a gate, located in the gate trench; a source trench structure, located in the source trench; a first ohmic contact layer, located on the first surface, wherein the first ohmic contact layer at least covers a portion of the second region; In a first direction, the distance between the first ohmic contact layer and the source trench structure is a second distance to prevent the first ohmic contact layer from contacting and reacting with the source trench structure, and the first direction is perpendicular to the direction pointing from the first surface to the second surface; A second ohmic contact layer is located on the first surface, wherein at least a portion of the second ohmic contact layer is arranged in the same layer as the first ohmic contact layer, and the second ohmic contact layer at least covers the area of ​​the first surface not covered by the first ohmic contact layer.

2. The semiconductor device according to claim 1, wherein The first ohmic contact layer is located on the first surface between the gate and the source trench structure, and an orthographic projection of the first ohmic contact layer on the first surface does not overlap with an orthographic projection of the source trench structure on the first surface.

3. The semiconductor device according to claim 2, wherein In a first direction, the first ohmic contact layer is at a first distance from the gate to prevent the first ohmic contact layer from contacting and reacting with the gate. The first direction is perpendicular to the first surface and points to the second surface.

4. The semiconductor device according to any one of claims 1 to 3, wherein: The material of the first ohmic contact layer includes at least one of nickel, aluminum and tungsten or any combination thereof; the material of the second ohmic contact layer includes one of titanium and titanium nitride or any combination thereof.

5. A power module, characterized in that: The method comprises a substrate and at least one semiconductor device according to any one of claims 1 to 4, wherein the substrate is used to carry the semiconductor device.

6. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 1 to 4, wherein the semiconductor device is electrically connected to the circuit board.

7. A vehicle, characterized in that: The invention comprises a load and a power conversion circuit as claimed in claim 6, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

8. A method for preparing a semiconductor device, characterized in that: include: A semiconductor body is provided, the semiconductor body comprising a well region, a first region, and a second region, wherein the first region is disposed on a first surface of the semiconductor body, and the well region is disposed on a side of the first region away from the first surface; a gate trench and a source trench are further disposed on the first surface, and the second region is disposed on the first surface and extends to the sidewalls and bottom of the source trench; The first region is of a first conductivity type, and the well region and the second region are of a second conductivity type; forming a gate in the gate trench; forming a source trench structure in the source trench; forming a first ohmic contact layer on the first surface, wherein the first ohmic contact layer at least covers a portion of the second region; In a first direction, the distance between the first ohmic contact layer and the source trench structure is a second distance to prevent the first ohmic contact layer from contacting and reacting with the source trench structure, and the first direction is perpendicular to the direction pointing from the first surface to the second surface; A second ohmic contact layer is formed on the first surface, at least a portion of the second ohmic contact layer is disposed on the same layer as the first ohmic contact layer, and the second ohmic contact layer at least covers the area of ​​the first surface not covered by the first ohmic contact layer.

9. The method for preparing a semiconductor device according to claim 8, wherein: Forming a first ohmic contact layer on the first surface includes: forming a sacrificial layer on the first surface; removing a portion of the sacrificial layer so that the remaining sacrificial layer at least covers a portion of the second region; forming a second ohmic contact first sub-layer on the same layer as the sacrificial layer, wherein the second ohmic contact first sub-layer at least covers the area of ​​the first surface not covered by the sacrificial layer; removing the remaining sacrificial layer; The first ohmic contact layer is formed at the position of the remaining sacrificial layer.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: Forming the first ohmic contact layer at the position of the remaining sacrificial layer includes: Laying the first ohmic contact layer on a side of the second ohmic contact first sub-layer away from the semiconductor body, wherein the first ohmic contact layer at least covers the position of the remaining sacrificial layer; After high-temperature annealing, a portion of the first ohmic contact layer is removed, and the first ohmic contact layer at the position of the remaining sacrificial layer is retained.

11. The method for manufacturing a semiconductor device according to claim 9, wherein: Forming a second ohmic contact layer on the first surface includes: A second ohmic contact second sublayer is formed on a side of the first ohmic contact layer away from the semiconductor body, and the second ohmic contact first sublayer and the second ohmic contact second sublayer constitute the second ohmic contact layer, wherein at least part of the second ohmic contact layer is arranged in the same layer as the first ohmic contact layer.

12. The method for preparing a semiconductor device according to claim 9, wherein: The thickness of the second ohmic contact first sub-layer is smaller than the thickness of the sacrificial layer.

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