Preparation method of phase inverter based on zinc tin oxide thin film transistor

Abstract

The invention relates to a preparation method of an inverter based on a zinc tin oxide thin film transistor, and relates to the technical field of integrated circuits. According to the invention, preparation of a load tube (depletion mode transistor) and a driving tube (enhancement mode transistor) is adopted, and independent adjustment of threshold voltage of the load tube and the driving tube is realized through thickness control in the preparation process of ZTO thin film active layers of the load tube and the driving tube, so that the threshold voltage of the driving tube is a positive value, and the threshold voltage of the load tube is a negative value; and thus, the oxide-based depletion type load inverter is formed. According to the preparation method, the used ZTO thin film transistor has good electron mobility and stability, and high-performance inverter operation can be provided. Due to the characteristics of the ZTO material, the inverter may have relatively low power consumption during operation, which is very important for application of mobile equipment, Internet of Things equipment and the like. The ZTO thin film transistor allows the threshold voltage to be adjusted by adjusting preparation process parameters, which makes the inverter design more flexible.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly relates to a method for preparing an inverter based on zinc tin oxide thin film transistors. Background Art

[0002] Currently, the research on oxide semiconductors such as InGaZnO as the active layer material of thin film transistors has been on the rise. Such transistors have attracted the technology layout of global panel companies with their advantages of high mobility, low off-state current, visible light transparency, good uniformity, and low preparation temperature. Oxide thin film transistor inverters are not only used in display technology but also extended to multiple fields such as flexible electronics and sensors.

[0003] An inverter is the core building block of digital very large scale integrated circuits. Along with the progress and innovation of electronic technology, the application scope of various digital electronic products, such as mobile phones and computers, has been expanding day by day. At the same time, they must also cope with increasingly complex electromagnetic interference. Due to its characteristics such as broad noise tolerance, high input impedance, and tiny static power consumption, the inverter has low sensitivity to noise and interference, so it has been widely used in the field of digital integrated circuits. In addition, the inverter also plays an important role in many fields such as precision digital components, signal shaping, amplification driving, and audio amplification. With the continuous progress of inverter manufacturing technology, its integration degree has been continuously improved. Whether in the civilian or military fields, the inverter shows great development prospects. However, the traditional inverter structure usually consists of two or more transistors, which leads to the complexity of the manufacturing process, the inconvenience of integration, and the increase in production costs. At the same time, since each thin film transistor may have defects, using an inverter composed of multiple transistors will increase the risk of failure, thus affecting its overall stability.

[0004] Due to the lack of P-type and N-type oxide semiconductors with matching performance, most oxide-based inverters in the market adopt the NMOS structure. NMOS inverters can be divided into three types according to the load type: resistive load, enhancement load, and depletion load. Among them, the resistive load type is less used due to its large space occupation. The depletion load inverter has become a research hotspot due to its superior voltage transfer characteristics, noise tolerance, and area requirements.

[0005] The depletion load inverter needs to adjust the threshold voltages of the driving transistor and the load transistor to positive and negative values respectively. However, oxide-based transistors are usually enhancement type, and it is difficult to achieve such threshold voltage adjustment. The existing method is to control the carrier concentration by growing the semiconductor layer twice, but this requires a high sensitivity to the growth process conditions, has a large difficulty in precise control, and may lead to unstable device performance. In addition, methods such as changing the device structure, such as depositing a passivation layer or a multi-gate structure, can regulate the threshold voltage, but they increase the cost and process complexity and reduce the technology compatibility. Summary of the Invention

[0006] The present invention aims to solve the technical problems in the prior art that the preparation of depletion load inverters is difficult to control the growth process conditions, has high costs, complex processes, unstable device performance, and low compatibility. A method for preparing an inverter based on zinc tin oxide (ZTO) thin film transistors is provided. The present invention uses the preparation of a load transistor (depletion transistor) and a driving transistor (enhancement transistor). By controlling the thickness during the preparation process of the active layers of the load transistor and the driving transistor, the threshold voltages of the load transistor and the driving transistor are separately adjusted, so that the threshold voltage of the driving transistor is positive and the threshold voltage of the load transistor is negative, thereby forming an oxide-based depletion load inverter.

[0007] To solve the above technical problems, the technical solution of the present invention is specifically as follows:

[0008] A method for preparing an inverter based on zinc tin oxide thin film transistors, comprising the following steps:

[0009] Step 1, Preparation of an enhancement transistor

[0010] Step 1.1, Clean and dry the substrate;

[0011] A first SiO2 layer is provided on the substrate, and the first SiO2 layer does not completely cover the substrate. The area not covered by the first SiO2 layer is the gate region;

[0012] The thickness of the first SiO2 layer is 285 nm;

[0013] Step 1.2, Coat glue, pre-bake, expose, and develop on the first SiO2 layer;

[0014] Step 1.3, Use room-temperature magnetron sputtering to co-sputter and deposit a 40-nm-thick first zinc tin oxide thin film active layer on the developed first SiO2 layer. The first zinc tin oxide thin film active layer does not completely cover the first SiO2 layer; Anneal the sample after de-gluing;

[0015] Step 1.4, Define the source region and the drain region at the upper and lower ends of the first zinc tin oxide thin film active layer respectively by coating glue, pre-baking, exposing, and developing, and evaporate and deposit a first power supply terminal Al electrode layer in the source region and the drain region by electron beam evaporation to prepare an enhancement transistor with a positive threshold voltage;

[0016] Step 2, Preparation of a depletion transistor

[0017] Step 2.1, Clean and dry the substrate;

[0018] A second SiO2 layer is disposed on the substrate, and the second SiO2 layer does not completely cover the substrate. The area not covered by the second SiO2 layer is the gate area;

[0019] The thickness of the second SiO2 layer is 285 nm;

[0020] Step 2.2: Coating, pre-baking, exposing, and developing on the second SiO2 layer;

[0021] Step 2.3: Magnetron sputtering co-sputtering deposition of a 50-nm-thick second indium zinc oxide thin film active layer on the developed second SiO2 layer. The second indium zinc oxide thin film active layer does not completely cover the second SiO2 layer; annealing the sample after removing the glue;

[0022] Step 2.4: Define the upper and lower ends of the second indium zinc oxide thin film active layer as the drain area and the source area respectively by coating, pre-baking, exposing, and developing, and evaporate the second power supply terminal Al electrode layer in the drain area and the source area by electron beam evaporation to prepare a depletion-type transistor with a negative threshold voltage;

[0023] Step 3: Preparation of an inverter

[0024] Connect the first power supply terminal Al electrode layer in the source area of the enhancement-type transistor to the second power supply terminal Al electrode layer in the drain area of the depletion-type transistor as the output terminal electrode. The first power supply terminal Al electrode layer in the drain area is configured as the ground terminal electrode, and the second power supply terminal Al electrode layer in the source area is configured as the power supply terminal electrode; the gate area is configured as the input terminal electrode;

[0025] Connect the input terminal electrode, the output terminal electrode, and the power supply terminal electrode to form an inverter.

[0026] In the above technical solution, preferably, the substrate in steps 1.1 and 2.1 is a P-type silicon wafer.

[0027] In the above technical solution, preferably, the steps of cleaning and drying the substrate in steps 1.1 and 2.1 are as follows:

[0028] Put the substrate into acetone, ethanol, and deionized water for cleaning in sequence, then blow it dry with high-purity nitrogen, and put it into an oven at 90 °C for drying for 5 minutes.

[0029] In the above technical solution, preferably, the conditions for magnetron sputtering co-sputtering in steps 1.3 and 2.3 are: radio frequency power is 90 W, sputtering pressure is 8 mTorr, sputtering time is 8.5 min, the partial pressure of O2 in the Ar and O2 mixed gas is 10, and the volume ratio of Ar and O2 gases is 90:10.

[0030] In the above technical solution, it is further preferred that in steps 1.3 and 2.3, the first zinc tin oxide thin film active layer and the second zinc tin oxide thin film active layer are deposited respectively by using a zinc tin oxide (ZTO) target with a purity of 99.99%, and the molar ratio of Zn to Sn is 7:3.

[0031] In the above technical solution, it is preferred that the annealing conditions in steps 1.3 and 2.3 are as follows:

[0032] Anneal at 600 °C for 1 h in an air atmosphere.

[0033] In the above technical solution, it is preferred that the thickness of the first power supply terminal Al electrode layer and the second power supply terminal Al electrode layer is 50 nm.

[0034] The beneficial effects of the present invention are as follows:

[0035] 1. A method for fabricating an inverter based on zinc tin oxide (ZTO) thin film transistors of the present invention adopts the fabrication of a load transistor (depletion-type transistor) and a driving transistor (enhancement-type transistor). By controlling the thickness during the fabrication process of the ZTO thin film active layers of the load transistor and the driving transistor, the threshold voltages of the load transistor and the driving transistor can be adjusted separately, so that the threshold voltage of the driving transistor is positive and the threshold voltage of the load transistor is negative, thereby forming an oxide-based depletion load inverter.

[0036] 2. The ZTO thin film transistors have good electron mobility and stability, and can provide high-performance inverter operation.

[0037] 3. Due to the characteristics of the ZTO material, this inverter may have lower power consumption during operation, which is very important for applications such as mobile devices and Internet of Things devices.

[0038] 4. The ZTO thin film transistors allow the threshold voltage to be adjusted by adjusting the fabrication process parameters, which makes the inverter design more flexible. Description of the Drawings

[0039] The present invention will be further described in detail below in conjunction with the drawings and specific embodiments.

[0040] Figure 1 It is the circuit schematic diagram of the inverter based on zinc tin oxide thin film transistors fabricated by the present invention.

[0041] Figure 2 It is the overall structure schematic diagram of the inverter based on zinc tin oxide thin film transistors fabricated by the present invention.

[0042] Figure 3 It is the structure schematic diagram of the load transistor (depletion-type transistor) of the present invention.

[0043] Figure 4 This is the transfer characteristic curve of the load transistor (depletion-type transistor) in the embodiment of the present invention.

[0044] Figure 5 This is the transfer characteristic curve of the driving transistor (enhancement-type transistor) in the embodiment of the present invention.

[0045] Figure 6 This is the gain curve graph of the inverter based on zinc tin oxide thin film transistors prepared in the embodiment of the present invention.

[0046] The reference numerals in the figure are represented as:

[0047] 1 is the substrate, 2-1 is the first SiO2 layer, 2-2 is the second SiO2 layer, 3-1 is the first zinc oxide tin thin film active layer, 3-2 is the second zinc oxide tin thin film active layer, 4-1 is the first power supply terminal Al electrode layer, 4-2 is the second power supply terminal Al electrode layer, 5-1 is the input terminal electrode, 5-2 is the output terminal electrode, 5-3 is the power supply terminal electrode, 5-4 is the ground terminal electrode. Detailed implementation manners

[0048] The inventive concept of the present invention is as follows: The present invention aims to solve the technical problems in the prior art that the preparation of depletion load inverters is difficult to control the growth process conditions, has high costs, complex processes, unstable device performance and low compatibility. It provides a method for preparing an oxide-based depletion load inverter. By optimizing the channel material, gate dielectric and metal electrode of the depletion-type transistor, the switching performance and stability of the inverter are significantly improved, enabling it to achieve fast response and low-power operation at low voltages, and being suitable for high-performance and low-power integrated circuit designs. Using advanced micro-nano processing technologies, the structure of the thin film transistor depletion inverter is realized, improving the integration and performance density of the inverter, and providing high-performance logic units for fields such as flexible electronics and wearable devices. It broadens the application scope of thin film transistors in digital integrated circuits and other electronic systems.

[0049] A method for fabricating an oxide-based depletion-load inverter (an inverter based on zinc tin oxide (ZTO) thin film transistors) proposed by the present invention adopts the fabrication of a load transistor (a depletion-type transistor) and a driving transistor (an enhancement-type transistor). By controlling the thickness during the fabrication process of the active layers of the load transistor and the driving transistor, separate adjustment of the threshold voltages of the load transistor and the driving transistor is achieved, such that the threshold voltage of the driving transistor is positive and the threshold voltage of the load transistor is negative, thereby forming an oxide-based depletion-load inverter. The present invention first selects a P-type silicon wafer with a high-purity silicon dioxide (SiO2) layer having a thickness of 285 nm as a substrate to provide good insulation and stable mechanical support. Then, a ZnSnO thin film is grown on the SiO2 substrate by magnetron sputtering. During the growth process, by precisely controlling the process parameters, it is ensured that the ZnSnO thin film has an ideal amorphous structure and electronic characteristics. For the enhancement-type transistor, by controlling the growth conditions of the ZnSnO thin film, it has a positive threshold voltage. For the depletion-type transistor, the thickness of the active layer is adjusted by the process to make it have a negative threshold voltage. To improve the performance of the transistor, the ZnSnO thin film is subjected to appropriate annealing treatment. The annealing process helps to optimize the electronic characteristics of the transistor, reduce defects, and improve the overall reliability of the device. At the same time, the annealing treatment also helps to release the stress in the thin film. The source, drain, and gate regions of the transistor are defined on the ZnSnO thin film by photolithography technology. Etching processes are used to form source-drain electrodes in these defined regions, and the structures of the enhancement-type and depletion-type transistors are specially designed so that they can work together in the inverter. After the fabrication of the enhancement-type and depletion-type transistors is completed, they are connected through an interconnect process to form an inverter. The interconnect process needs to ensure the stability and conductivity of the connection while avoiding damage to the ZnSnO thin film. In particular, the interconnect design should consider the operating characteristics of the enhancement-type and depletion-type transistors to ensure that the inverter can effectively invert the input signal.

[0050] The following will give a detailed description of the present invention in conjunction with the accompanying drawings.

[0051] In conjunction with Figure 2 and 3 , a method for fabricating an inverter based on zinc tin oxide thin film transistors of the present invention will be specifically described, including the following steps:

[0052] Step 1: Fabrication of the enhancement-type transistor

[0053] Step 1.1: The P-type silicon wafer substrate 1 is successively placed in acetone, ethanol, and deionized water for cleaning, then dried with high-purity nitrogen gas, and placed in an oven at 90 °C for drying for 5 minutes.

[0054] A first SiO2 layer 2-1 with a thickness of 285 nm is provided on the substrate 1. The first SiO2 layer 2-1 does not completely cover the substrate, and the area not covered by the first SiO2 layer 2-1 is the gate region. The substrate 1 is purchased from Hefei Kejing Materials Technology Co., Ltd., Crystal: Si N-type doped with P Orient <100> / <110><110>, Size: dia 100×0.5 mm single-sided + 285 nm SiO2, Polish: 1sp.

[0055] Step 1.2: Coating, pre-baking, exposing, and developing on the first SiO2 layer 2-1;

[0056] Step 1.3: Using a high-purity (99.99%) ZTO target (molar ratio Zn:Sn = 7:3) (the ZTO target is purchased from Beijing Zhongcheng Xincai Technology Co., Ltd.), a first zinc tin oxide thin film active layer 3-1 with a thickness of 40 nm is deposited on the first SiO2 layer 2-1 by room-temperature magnetron sputtering co-sputtering. The radio frequency power is 90 W, the sputtering pressure is 8 mTorr, the sputtering time is 8.5 min, and the first zinc tin oxide thin film active layer 3-1 is deposited under the condition that the partial pressure of O2 in the Ar / O2 mixed gas is 10 (gas volume ratio Ar:O2 = 90:10). The sample after de-gluing is placed in an annealing furnace and annealed at 600 °C for 1 h in an air atmosphere. The first zinc tin oxide thin film active layer 3-2 does not completely cover the first SiO2 layer 2-1;

[0057] Step 1.4: By coating, pre-baking, exposing, and developing, the source region and the drain region are respectively defined at the upper and lower ends of the first zinc tin oxide thin film active layer 3-2. The developed sample is placed on a tray and put into an electron beam evaporation device. In a chamber at 60 °C, a first power supply end Al electrode layer 4-1 with a thickness of 50 nm is deposited by electron beam evaporation in the source region and the drain region respectively, and an enhancement-type transistor with a positive threshold voltage is prepared;

[0058] Step 2: Preparation of depletion-type transistor

[0059] Step 2.1: Clean and dry the P-type silicon wafer substrate 1;

[0060] A second SiO2 layer 2-2 with a thickness of 285 nm is deposited on the substrate. The second SiO2 layer 2-2 does not completely cover the substrate, and the area not covered by the second SiO2 layer 2-2 is the gate region;

[0061] Step 2.2: Coating, pre-baking, exposing, and developing on the second SiO2 layer 2-2;

[0062] Step 2.3: Using a high-purity (99.99%) ZTO target (molar ratio of Zn:Sn = 7:3), a second zinc oxide tin thin film active layer 3-2 with a thickness of 50 nm is co-sputter deposited on the second SiO2 layer 2-2 at room temperature by magnetron sputtering. The RF power is 90 W, the sputtering pressure is 8 mTorr, the sputtering time is 10.5 min, and the second zinc oxide tin thin film active layer 3-2 is deposited under the condition that the partial pressure of O2 in the Ar / O2 mixed gas is 10 (gas volume ratio of Ar:O2 = 90:10). The degummed sample is placed in an annealing furnace and annealed at 600 °C for 1 h in an air atmosphere; the second zinc oxide tin thin film active layer 3-2 does not completely cover the second SiO2 layer 2-2;

[0063] Step 2.4: By spin-coating, pre-baking, exposure, and development, the drain region and the source region are respectively defined at the upper and lower ends of the second zinc oxide tin thin film active layer 3-2. The developed sample is placed on a tray and put into an electron beam evaporation device. In a chamber at 60 °C, a second power supply terminal Al electrode layer 4-2 with a thickness of 50 nm is evaporated by electron beam evaporation in the drain region and the source region, and a depletion-mode transistor with a negative threshold voltage is prepared;

[0064] Step 3: Preparation of the inverter

[0065] Connect the source region first power supply terminal Al electrode layer 4-1 of the enhancement-mode transistor to the drain region second power supply terminal Al electrode layer 4-2 of the depletion-mode transistor as the output terminal electrode 5-2. The drain region first power supply terminal Al electrode layer 4-1 is configured as the ground terminal electrode 5-4, and the source region second power supply terminal Al electrode layer 4-2 is configured as the power supply terminal electrode 5-3; the gate regions of the enhancement-mode transistor and the depletion-mode transistor are configured as the input terminal electrode 5-1; connect the input terminal electrode 5-1, the output terminal electrode 5-2, and the power supply terminal electrode 5-3 to form an inverter.

[0066] For the inverter based on zinc tin oxide thin film transistors prepared by the present invention, performance tests are carried out. The test results are shown in Figures 4 - 6 , and the circuit schematic diagram of the inverter of the present invention is shown in Figure 1 . The working principle of the inverter of the present invention is as follows:

[0067] When V IN is at a low level (0 V):

[0068] When the input voltage (V IN ) is 0 V, the gate-source voltage of the transistor is not sufficient to turn it on (remains off).

[0069] Because the transistor is off, the output (V OUT) will be pulled to the supply voltage (usually integrated in the design) through a pull-up resistor (V DD ).

[0070] Therefore, when V IN is at a low level, V OUT is at a high level (V DD ).

[0071] When V IN is at a high level (V DD ):

[0072] When the input voltage (V IN ) is at a high level (V DD ), the input voltage is high enough to turn on the transistor and apply enough voltage to the gate of the MOSFET.

[0073] After turning on, a low-impedance path is formed between the drain and the source.

[0074] As a result, V OUT is pulled down to 0V.

[0075] Therefore, when V IN is at a high level, V OUT is at a low level (0V).

[0076] As shown in Figure 6 , the gain curves of the load transistor (depletion-mode transistor) in the inverter based on zinc tin oxide thin film transistor of the present invention at VDD = 30, 25, 20, 15, 10V are shown. The gain is maximum at 10.1 at 30V. In the inverter based on zinc tin oxide thin film transistor of the present invention, Figure 4 it can be seen from the transfer characteristic curve of the load transistor (depletion-mode transistor) at Vds = 20V that the load transistor presents a depletion state and the threshold voltage is -2.51V. From Figure 5 it can be seen that the driving transistor (enhancement-mode transistor) presents an enhancement state and the threshold voltage is 11.48V. The test results prove that the threshold voltage regulation of the load transistor (depletion-mode transistor) and the driving transistor (enhancement-mode transistor) can be realized by adopting the preparation method of the present invention, so that the threshold voltage of the driving transistor (enhancement-mode transistor) is positive and the threshold voltage of the load transistor (depletion-mode transistor) is negative, thereby forming a depletion-load inverter.

[0077] Obviously, the above embodiments are only examples given for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or variations can be made based on the above description. It is not necessary and impossible to enumerate all the implementation manners here. And the obvious changes or variations derived therefrom are still within the protection scope of the present invention.

Claims

1. A method for fabricating an inverter based on zinc tin oxide thin film transistors, characterized in that, It includes the following steps: Step 1: Preparation of enhancement-mode transistor Step 1.1: Clean and dry the substrate; A first SiO2 layer is provided on the substrate, and the first SiO2 layer does not completely cover the substrate. The area not covered by the first SiO2 layer is the gate region; The thickness of the first SiO2 layer is 285 nm; Step 1.2: Apply photoresist on the first SiO2 layer, pre-bake, expose, and develop; Step 1.3: At room temperature, magnetron sputtering is used to co-sputter deposit a 40-nm-thick first indium zinc oxide thin-film active layer on the developed first SiO2 layer. The first indium zinc oxide thin-film active layer does not completely cover the first SiO2 layer; Anneal the sample after removing the photoresist; Step 1.4: Define the upper and lower ends of the first indium zinc oxide thin-film active layer as the source region and the drain region respectively by applying photoresist, pre-baking, exposing, and developing, and evaporate and deposit a first power supply terminal Al electrode layer on the source region and the drain region by electron beam evaporation to prepare an enhancement-mode transistor with a positive threshold voltage; Step 2: Preparation of depletion-mode transistor Step 2.1: Clean and dry the substrate; A second SiO2 layer is provided on the substrate, and the second SiO2 layer does not completely cover the substrate. The area not covered by the second SiO2 layer is the gate region; The thickness of the second SiO2 layer is 285 nm; Step 2.2: Apply photoresist on the second SiO2 layer, pre-bake, expose, and develop; Step 2.3: At room temperature, magnetron sputtering is used to co-sputter deposit a 50-nm-thick second indium zinc oxide thin-film active layer on the developed second SiO2 layer. The second indium zinc oxide thin-film active layer does not completely cover the second SiO2 layer; Anneal the sample after removing the photoresist; Step 2.4: Define the upper and lower ends of the second indium zinc oxide thin-film active layer as the drain region and the source region respectively by applying photoresist, pre-bake, expose, and develop, and evaporate and deposit a second power supply terminal Al electrode layer on the drain region and the source region by electron beam evaporation to prepare a depletion-mode transistor with a negative threshold voltage; Step 3: Preparation of inverter Connect the first power supply terminal Al electrode layer in the source region of the enhancement-mode transistor to the second power supply terminal Al electrode layer in the drain region of the depletion-mode transistor as the output terminal electrode. The first power supply terminal Al electrode layer in the drain region is configured as the ground terminal electrode, and the second power supply terminal Al electrode layer in the source region is configured as the power supply terminal electrode; The gate region is configured as the input terminal electrode; Connect the input terminal electrode, the output terminal electrode, and the power supply terminal electrode to form an inverter.

2. The method for preparing an inverter based on a zinc tin oxide thin film transistor according to claim 1, wherein, The substrate in Step 1.1 and Step 2.1 is a P-type silicon wafer.

3. The method for preparing an inverter based on a zinc tin oxide thin film transistor according to claim 1, characterized in that, The steps of cleaning and drying the substrate in Step 1.1 and Step 2.1 are specifically as follows: Put the substrate into acetone, ethanol, and deionized water for cleaning in sequence, then blow it dry with high-purity nitrogen, and put it into an oven at 90 °C for drying for 5 minutes.

4. The method for preparing an inverter based on a zinc tin oxide thin film transistor according to claim 1, wherein The conditions for co-sputtering by magnetron sputtering in Step 1.3 and Step 2.3 are as follows: the radio frequency power is 90 W, the sputtering pressure is 8 mTorr, the sputtering time is 8.5 min, the partial pressure of O2 in the Ar and O2 mixed gas is 10, and the volume ratio of Ar and O2 gas is 90:

10.

5. The method for fabricating an inverter based on a zinc tin oxide thin film transistor according to claim 1, wherein Depositing the first zinc tin oxide thin film active layer and the second zinc tin oxide thin film active layer in Step 1.3 and Step 2.3 respectively uses a zinc tin oxide target with a purity of 99.99%, where the molar ratio of Zn and Sn is 7:

3.

6. The method for preparing an inverter based on a zinc tin oxide thin film transistor according to any one of claims 1-5, characterized in that The conditions for annealing treatment in Step 1.3 and Step 2.3 are as follows: annealing at 600 °C for 1 h in an air atmosphere.

7. The method for fabricating an inverter based on a zinc tin oxide thin film transistor according to claim 6, wherein, The thickness of the first power supply terminal Al electrode layer and the second power supply terminal Al electrode layer is 50 nm.

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