Dislocations in GAA transistors and methods of forming same

Abstract

The invention relates to dislocations in GAA transistors and methods of forming the same. A method includes forming a protruding feature. The protruding features include a first sacrificial nanosheet over the bulk semiconductor substrate, a first semiconductor nanosheet over the first sacrificial nanosheet, a second sacrificial nanosheet over the first semiconductor nanosheet, and a second semiconductor nanosheet over the second sacrificial nanosheet. The method further includes forming a dummy gate stack on the protruding feature; etching the protruding feature to form a recess; forming a source / drain region in the recess wherein a dislocation is formed in the source / drain region; removing the first sacrificial nanosheets and the second sacrificial nanosheets; and forming a replacement gate stack to replace the dummy gate stack.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor devices, and more particularly to dislocations in Gate-All-Around (GAA) transistors and methods for forming the same. Background Art

[0002] Technological advances in integrated circuit (IC) materials and design have produced several generations of ICs, each of which has smaller and more complex circuits than the previous generations. During the evolution of ICs, the functional density (e.g., the number of interconnected devices per chip area) generally increases while the geometric size decreases. Such scaling processes typically provide benefits by increasing production efficiency and reducing related costs.

[0003] This scaling also increases the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are needed to achieve these advancements. For example, Gate-All-Around (GAA) transistors have been introduced to replace planar transistors. The structure of GAA transistors and methods for manufacturing GAA transistors are being developed. Summary of the Invention

[0004] According to an embodiment of the present disclosure, a method of forming a semiconductor device is provided, including: forming a protruding feature, the protruding feature including: a first sacrificial nanosheet above a bulk semiconductor substrate; a first semiconductor nanosheet above the first sacrificial nanosheet; a second sacrificial nanosheet above the first semiconductor nanosheet; and a second semiconductor nanosheet above the second sacrificial nanosheet; forming a dummy gate stack on the protruding feature; etching the protruding feature to form a recess; forming source / drain regions in the recess, wherein dislocations are formed in the source / drain regions; removing the first sacrificial nanosheet and the second sacrificial nanosheet; and forming a replacement gate stack to replace the dummy gate stack.

[0005] According to an embodiment of the present disclosure, a semiconductor device is provided, including: a first semiconductor nanostructure; a second semiconductor nanostructure above the first semiconductor nanostructure; a gate stack including a portion between the first semiconductor nanostructure and the second semiconductor nanostructure; source / drain regions beside and coupled to the first semiconductor nanostructure and the second semiconductor nanostructure, wherein the first semiconductor nanostructure, the second semiconductor nanostructure, the gate stack, and the source / drain regions form respective parts of a transistor; and a first dislocation in the source / drain regions.

[0006] According to an embodiment of the present disclosure, a semiconductor device is provided, including: a plurality of first semiconductor nanostructures, wherein an upper semiconductor nanostructure among the plurality of first semiconductor nanostructures overlaps with a corresponding lower semiconductor nanostructure among the plurality of first semiconductor nanostructures; a first gate stack including a portion between the plurality of first semiconductor nanostructures; a plurality of second semiconductor nanostructures, wherein an upper semiconductor nanostructure among the plurality of second semiconductor nanostructures overlaps with a corresponding lower semiconductor nanostructure among the plurality of second semiconductor nanostructures; a second gate stack including a portion between the plurality of second semiconductor nanostructures; source / drain regions between the plurality of first semiconductor nanostructures and the plurality of second semiconductor nanostructures; a plurality of first dislocations in the source / drain regions and parallel to each other, wherein the plurality of first dislocations includes a first lower end close to the plurality of first semiconductor nanostructures; and a plurality of second dislocations in the source / drain regions and parallel to each other, wherein the plurality of second dislocations includes a second lower end close to the plurality of second semiconductor nanostructures. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for the sake of clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0008] Figures 1 to 4 、 Figure 5A 、 Figure 5B 、 Figure 6A 、 Figure 6B 、 Figure 7A 、 Figure 7B 、 Figure 8A 、 Figure 8B 、 Figure 9A 、 Figure 9B 、 Figure 10A 、 Figure 10B 、 Figure 11A 、 Figure 11B 、 Figure 12A 、 Figure 12B 、 Figure 13A 、 Figure 13B 、 Figure 14A and Figure 14B show views of intermediate stages of forming gate-all-around (GAA) transistors according to some embodiments.

[0009] Figures 15 to 20A and Figure 20B show cross-sectional views of intermediate stages of forming source / drain regions and some overlying features according to some embodiments.

[0010] Figure 21 A process flow for forming a dielectric region and an overlying source / drain region according to some embodiments is shown. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, spatially relative terms (such as "below", "beneath", "lower", "above", "upper", etc.) may be used herein to facilitate describing the relationship of one element or feature shown in the figures to another (one or more) element or (one or more) feature. These spatially relative terms are also intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented in other directions (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0013] A gate-all-around (GAA) transistor including a source / drain region having dislocations is provided. According to some embodiments, the process for forming the source / drain region is adjusted such that dislocations are formed in the source / drain region. Although GAA transistors are used as examples to discuss the concepts of the present disclosure, these embodiments may be applied to other types of transistors, including but not limited to, fin field-effect transistors (FinFETs), planar transistors, etc. The purpose of the embodiments discussed herein is to provide examples to enable the fabrication or use of the subject matter of the present disclosure, and those of ordinary skill in the art will readily understand the modifications that can be made while remaining within the scope of the different embodiments. In the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0014] Figures 1 to 4 、 Figure 5A 、 Figure 5B 、 Figure 6A 、 Figure 6B 、 Figure 7A 、 Figure 7B 、Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A and Figure 14B show a cross-sectional view of an intermediate stage of forming a GAA transistor according to some embodiments of the present disclosure. The corresponding processes are also schematically reflected in the Figure 21 process flow shown.

[0015] Referring to Figure 1 , a perspective view of a wafer 10 is shown. The wafer 10 includes a multi-layer structure that includes a multi-layer stack 22 on a substrate 20. According to some embodiments, the substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon germanium (SiGe) substrate, etc., but other substrates and / or structures may be used, e.g., semiconductor-on-insulator (SOI), strained SOI, silicon germanium-on-insulator, etc. The substrate 20 may be doped as a p-type semiconductor, but in other embodiments, it may be doped as an n-type semiconductor.

[0016] According to some embodiments, the multi-layer stack 22 is formed by a series of deposition processes for depositing alternating materials. The corresponding processes are shown as process 202 in the process flow 200 shown in Figure 21 . According to some embodiments, the multi-layer stack 22 includes a first layer 22A formed of a first semiconductor material and a second layer 22B formed of a second semiconductor material, the second semiconductor material being different from the first semiconductor material.

[0017] According to some embodiments, the first semiconductor material of the first layer 22A is formed of or includes any of the following: SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, etc. According to some embodiments, the deposition of the first layer 22A (e.g., SiGe) is by epitaxial growth, and the corresponding deposition method may be vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer deposition (ALD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), etc. According to some embodiments, the first layer 22A is formed to have a first thickness in the range between about and about . However, any suitable thickness may be used while remaining within the scope of the embodiments.

[0018] Once the first layer 22A has been deposited over the substrate 20, the second layer 22B is deposited over the first layer 22A. According to some embodiments, the second layer 22B is formed of or includes a second semiconductor material, such as, Si, SiGe, Ge, GaAs, InSb, GasB, InAlAs, InGaAs, GasB, GaAsSB, combinations of the foregoing, etc., and the second semiconductor material is different from the first semiconductor material of the first layer 22A. For example, according to some embodiments, where the first layer 22A is silicon germanium, the second layer 22B may be formed of silicon, and vice versa. It should be understood that any suitable combination of materials may be used for the first layer 22A and the second layer 22B.

[0019] According to some embodiments, using a deposition technique similar to the deposition technique used to form the first layer 22A, the second layer 22B is epitaxially grown on the first layer 22A. According to some embodiments, the second layer 22B is formed to have a thickness similar to that of the first layer 22A. The second layer 22B may also be formed to have a thickness different from that of the first layer 22A. According to some embodiments, for example, the second layer 22A has a thickness in the range between about 4 nm and 7 nm, while the second layer 22B has a thickness in the range between about 8 nm and 12 nm.

[0020] Once the second layer 22B has been formed over the first layer 22A, the deposition process is repeated to form the remaining layers in the multi-layer stack 22 until the desired topmost layer of the multi-layer stack 22 is formed. According to some embodiments, the first layers 22A have the same or similar thicknesses to each other, and the second layers 22B have the same or similar thicknesses to each other. The first layer 22A may also have the same or different thickness from the second layer 22B. According to some embodiments, the first layer 22A is removed in a subsequent process and is alternatively referred to as the sacrificial layer 22A throughout the specification. According to an alternative embodiment, the second layer 22B is sacrificed and removed in a subsequent process.

[0021] According to some embodiments, there may be one or more liner oxide layers and one or more hard mask layers (not shown) formed over the multi-layer stack 22. These layers are patterned and are used for subsequent patterning of the multi-layer stack 22.

[0022] Reference Figure 2 , in an etching process, a portion of the multi-layer stack 22 and the underlying substrate 20 are patterned such that trenches 23 are formed. A corresponding process is performed in Figure 21The process flow shown in

[0023] In the above embodiments, the GAA transistor structures can be patterned by any suitable method. For example, one or more lithography processes (including double patterning or multi-patterning processes) can be used to pattern these structures. Generally, double patterning or multi-patterning processes combine lithography and self-alignment processes, thus allowing the generation of patterns with, for example, pitches smaller than those achievable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate, and the sacrificial layer is patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0024] Figure 3 The formation of isolation regions 26 is shown, which are also referred to as shallow trench isolation (STI) regions throughout the specification. The corresponding process is shown as process 206 in the process flow 200 shown in Figure 21 The STI regions 26 can include a liner oxide (not shown), which can be a thermal oxide formed by thermal oxidation of the surface layer of the substrate 20. The liner oxide can also be a deposited silicon oxide layer formed using, for example, ALD, high density plasma chemical vapor deposition (HDPCVD), CVD, etc. The STI regions 26 can also include a dielectric material over the liner oxide, where the dielectric material can be formed using flowable chemical vapor deposition (FCVD), spin coating, HDPVCD, etc. A planarization process (such as a chemical mechanical polishing (CMP) process or a mechanical grinding process) can then be performed to make the top surface of the dielectric material flush, and the remaining portion of the dielectric material is the STI region 26.

[0025] Then, the STI region 26 is recessed such that the top of the semiconductor strip 24 protrudes above the top surface 26T of the remaining portion of the STI region 26 to form a protruding fin 28. The protruding fin 28 includes the top of the multi-layer stack 22' and the substrate strip 20'. The recessing of the STI region 26 can be performed by a dry etching process, where, for example, NF3 and NH3 are used as etching gases. During the etching process, a plasma can be generated. Argon can also be included. According to an alternative embodiment of the present disclosure, the recessing of the STI region 26 is performed by a wet etching process. For example, the etching chemical can include HF.

[0026] Reference Figure 4 , a dummy gate stack 30 and gate spacers 38 are formed on the top surface and sidewalls of the (protruding) fin 28. The corresponding process is shown as process 208 in the process flow 200 shown in Figure 21 . The dummy gate stack 30 can include a dummy gate dielectric 32 and a dummy gate electrode 34 located above the dummy gate dielectric 32. The dummy gate dielectric 32 can be formed by oxidizing a surface portion of the protruding fin 28 to form an oxide layer, or by depositing a dielectric layer such as a silicon oxide layer. For example, polysilicon or amorphous silicon can be used to form the dummy gate electrode 34, and other materials such as amorphous carbon can also be used.

[0027] Each dummy gate stack 30 can also include one (or more) hard mask layers 36 located above the dummy gate electrode 34. The hard mask layer 36 can be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, or a multi-layer thereof. The dummy gate stack 30 can span a single protruding fin 28 or multiple protruding fins 28 and the STI region 26 between the protruding fins 28. The dummy gate stack 30 also has a length direction perpendicular to the length direction of the protruding fin 28. The formation of the dummy gate stack 30 includes: forming a dummy gate dielectric layer, depositing a dummy gate electrode layer above the dummy gate dielectric layer, depositing one or more hard mask layers and then patterning the formed layers by one (or more) patterning processes.

[0028] Next, a gate spacer 38 is formed on the sidewalls of the dummy gate stack 30. According to some embodiments of the present disclosure, the gate spacer 38 is formed of a dielectric material (e.g., silicon nitride (SiN), silicon monoxide (SiO), silicon carbide (SiC), silicon dioxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), etc.), and may have a single-layer structure or a multi-layer structure including multiple dielectric layers. The formation process of the gate spacer 38 may include: depositing one or more dielectric layers, and then performing one or more anisotropic etching processes on the (one or more) dielectric layers. The remaining portions of the (one or more) dielectric layers are the gate spacer 38.

[0029] Figure 5A and Figure 5B shows Figure 4 a cross-sectional view of the structure shown. Figure 5A shows Figure 4 the reference cross-section A1-A1 in, which cuts through the portion of the protruding fin 28 that is not covered by the gate stack 30 and the gate spacer 38, and is perpendicular to the gate length direction. Figure 5B shows Figure 4 the reference cross-section B-B in, which is parallel to the length direction of the protruding fin 28.

[0030] Referring to Figure 6A and Figure 6B , the portion of the protruding fin 28 that is not directly under the dummy gate stack 30 and the gate spacer 38 is recessed by an etching process to form a recess 42. The corresponding process is shown as process 210 in the process flow 200 shown in Figure 21 . For example, a dry etching process can be performed using a mixture of C2F6, CF4, SO2, HBr, Cl2, and O2, a mixture of HBr, Cl2, O2, and CH2F2, etc., to etch the multi-layer semiconductor stack 22' and the underlying substrate strip 20'. The bottom of the recess 42 is at least flush with the bottom of the multi-layer semiconductor stack 22', or may be lower than the bottom of the multi-layer semiconductor stack 22' (as shown in Figure 6B ). The etching can be anisotropic such that the sidewalls of the multi-layer semiconductor stack 22' facing the recess 42 are vertical and straight, as shown in Figure 6B .

[0031] Referring to Figure 7A and Figure 7B , the sacrificial semiconductor layer 22A is laterally recessed to form a lateral recess 41, and the lateral recess 41 is recessed from the edges of the corresponding upper nanostructure 22B and the corresponding lower nanostructure 22B. The corresponding process is shown in Figure 21The process shown in the process flow 200 is shown as process 212. The lateral recess of the sacrificial semiconductor layer 22A can be achieved by a wet etching process that uses an etchant that is more selective for the material of the sacrificial semiconductor layer 22A (e.g., silicon germanium (SiGe)) than for the materials of the nanostructure 22B and the substrate 20 (e.g., silicon (Si)). For example, in an embodiment where the sacrificial semiconductor layer 22A is formed of silicon germanium and the nanostructure 22B is formed of silicon, an etchant such as hydrochloric acid (HCl) can be used to perform the wet etching process. The wet etching process can be performed using an immersion process, a spraying process, a spin coating process, etc.

[0032] According to an alternative embodiment, the lateral recess of the sacrificial semiconductor layer 22A is performed by an isotropic dry etching process or a combination of a dry etching process and a wet etching process.

[0033] Reference Figure 8A and Figure 8B , an internal spacer 44 is formed. The corresponding process is shown as process 214 in the process flow 200 shown in Figure 21 . According to some embodiments, the formation of the internal spacer 44 includes depositing a conformal dielectric layer that extends into the lateral recess 41 ( Figure 7B ). Next, an etching process (also referred to as a spacer trimming process) is performed to trim the portion of the spacer layer outside the lateral recess 41, thereby leaving a portion of the spacer layer in the lateral recess 41. The remaining portion of the spacer layer is referred to as the internal spacer layer 44.

[0034] Reference Figure 9A and Figure 9B , the dielectric layer 46 can be formed before the source / drain regions 48 are formed. The corresponding process is shown as process 215 in the process flow 200 shown in Figure 21 . Alternatively, the dielectric layer 46 is not formed. Therefore, the dielectric layer 46 is shown as a dashed line to indicate that the dielectric layer 46 can be formed or not formed. Next, an epitaxial source / drain region 48 and a dislocation 49 are formed in the recess 42 (reference Figure 17 ). The corresponding process is shown as process 216 in the process flow 200 shown in Figure 21 . Figure 17 Shows the details of the source / drain region 48 and the dislocation 49.

[0035] Figures 15 to 17 Shows the details in the formation of the dielectric layer and the source / drain region according to some embodiments (as shown in Figure 9A and Figure 9B ). Figure 15 Shows Figure 8B the region 45 in Figure 8BIn [the structure], the recess 42 and the internal spacer 44 have been formed. Next, according to some embodiments, a dielectric layer 46 is formed at the bottom of the recess 42. The dielectric layer 46 may include silicon nitride (SiN). The process gas may include silane (SiH4), ammonia (NH3), etc. The dielectric layer 46 may also be formed of silicon oxide (SiO), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), etc., or include them. According to some embodiments, the dielectric layer 46 has a multilayer structure, which includes, for example, a conformal silicon oxide liner and a silicon nitride region on the silicon oxide liner.

[0036] According to some embodiments, the formation of the dielectric layer 46 includes: a deposition process, then etching sidewall portions of the dielectric layer in the recess 42, and removing a top portion above the top surface of the dummy gate stack 30 (also refer to Figure 8B ). A directed deposition process may be used to deposit the dielectric layer 46, which includes both anisotropic and isotropic components.

[0037] The sidewall portions of the dielectric layer 46 in the recess and on the sidewalls of the structures protruding above the substrate 20 may be thinner than the bottom portion at the bottom of the recess 42 and the top portion above the dummy gate stack 30. Then an isotropic etching process is performed to remove the thin sidewall portions. The top portion of the dielectric layer on the top of the dummy gate stack 30 may be removed by: using a sacrificial layer to fill the recess 42 and protect the bottom portion, and performing an etching process. According to an alternative embodiment, the dielectric layer 46 is not formed. Thus, the semiconductor layer 46 is shown as a dashed line to indicate that the semiconductor layer 46 may or may not be formed.

[0038] Figure 16 and Figure 17 The selective formation of an epitaxial region 48 (source / drain region) according to some embodiments is shown. The (one or more) source / drain regions may refer to the source or the drain alone, or may collectively refer to the source and the drain, depending on the context. Figure 16 The epitaxy of a semiconductor layer 48A (also referred to as layer 1 or L1) by a selective epitaxial growth process is shown. The resulting semiconductor layer 48A is selectively grown from the sidewalls of the nanostructures 22B. When the dielectric layer 46 is not formed, the semiconductor layer 48A is also grown from the exposed top surface of the semiconductor substrate 20. On the other hand, portions of the semiconductor layer 48A are not grown from dielectric features such as the internal spacer 44, the gate spacer 38, and the hard mask 36 (refer to FIG. 9).

[0039] The selective formation process may include a plurality of cycles, each cycle including a deposition process and an etch-back process. In the deposition process, the thickness of the semiconductor layer 48A increases, while in the etch-back process, the thickness of the semiconductor layer 48A decreases. The plurality of cycles are also referred to as deposition and etch cycles.

[0040] When the source / drain region is the n-type region of an n-type transistor, the semiconductor layer 48A may include silicon or SiC (and may or may not include a small amount of germanium) and an n-type dopant (such as As, P, Sb, or a combination thereof, etc.). For example, the semiconductor layer 48A may include SiAs, SiP, SiCP, SiAsP, SiSb, etc. The semiconductor layer 48A may have an n-type dopant concentration in the range between about 1E20 / cm 3 and about 2E21 / cm 3 . The thickness of the semiconductor layer 48A may be less than about 10 nm.

[0041] In the deposition, the process gas for forming the n-type semiconductor layer 48A may include SiH4, dichlorosilane (DCS), HCl, GeH4, PH3, etc. The wafer temperature may be in the range between about 500 °C and about 850 °C, and the chamber pressure may be in the range between about 4 torr and about 300 torr.

[0042] When the source / drain region is the p-type region of a p-type transistor, the semiconductor layer 48A may include silicon, SiGe, or Ge, and also includes a p-type dopant (such as boron, indium, or a combination thereof). For example, the semiconductor layer 48A may include SiGeB, GeB, etc. The semiconductor layer 48A may have a p-type dopant concentration in the range below about 5E20 / cm 3 (for example, in the range between about 1E20 / cm 3 and about 5E20 / cm 3 ). The thickness of the semiconductor layer 48A may be less than about 10 nm.

[0043] In the deposition of the p-type semiconductor layer 48A, the process gas may include SiH4, DCS, HCl, GeH4, BH3, BCl3, etc. The wafer temperature may be in the range between about 400 °C and about 850 °C, and the chamber pressure may be in the range between about 4 torr and about 300 torr.

[0044] According to some embodiments, as discussed in the previous paragraphs, the process gas can include an etch gas for etching the semiconductor layer 48A. For example, the etch gas can include HCl. The etch gas helps remove the semiconductor layer 48A deposited on dielectric features such as inner spacers 44, gate spacers 38, hard mask 36, and dielectric layer 46 (if any). To form a high-quality semiconductor layer 48A, a low deposition rate of the semiconductor layer 48A is maintained, for example, less than about

[0045] After depositing a layer of the semiconductor layer 48A, a etch-back process is performed to etch back the semiconductor layer 48A. This helps remove any semiconductor deposited on the dielectric features. According to some embodiments, if any dislocations are formed in the semiconductor layer 48A, the portion of the semiconductor layer 48A having the dislocations is etched. Thus, the remaining semiconductor layer 48A after the etch-back process does not include dislocations. As a result of the etch-back process and the low growth rate, the semiconductor layer 48A may be free of dislocations or may have a small number of dislocations.

[0046] Figure 17 Epitaxial growth of the semiconductor layer 48B (also referred to as semiconductor layer 2 or L2) and dislocations 49 therein is shown. The resulting semiconductor layer 48B is grown from the semiconductor layer 48A, and the resulting semiconductor layer 48B is different from the semiconductor layer 48A. For example, the semiconductor layer 48B can be deposited to have an element (such as arsenic (As)) that is not in the semiconductor layer 48A, or vice versa. The semiconductor layers 48A and 48B can have the same element (such as Si), but have different percentages of the element(s). The deposition process can be selective such that no semiconductor layer 48B is directly grown from dielectric features such as inner spacers 44, gate spacers 38, and hard mask 36.

[0047] However, it should be understood that as Figure 16 shown, some dielectric features (such as the northern spacer 44 and the dielectric layer 46) can still have surfaces exposed to the recess 42, and the semiconductor layer 48B can grow from the semiconductor layer 48A and grow onto the dielectric features such that the semiconductor layer 48B can contact the dielectric features. When the deposition of the semiconductor layer 48B is complete, the top surface of the semiconductor layer 48B can be higher than the top surface of the topmost nanostructure 22B.

[0048] When the source / drain region 48 is an n-type region of an n-type transistor, the semiconductor layer 48B may include silicon or SiC (and may or may not include a small amount of germanium) and an n-type dopant (such as phosphorus). For example, the semiconductor layer 48B may include SiP, SiCP, etc., and may be free of n-type dopants such as As, Sb, etc. (doped in the semiconductor layer 48B). The semiconductor layer 48B may have a higher n-type dopant concentration than the n-type dopant concentration in the semiconductor layer 48A. For example, the n-type dopant concentration in the semiconductor layer 48B may be in the range between about 5E20 / cm 3 and about 5E21 / cm 3 in the range.

[0049] In the deposition of the n-type semiconductor layer 48B, the process gas may include SiH4, DCS, HCl, GeH4, PH3, etc. The wafer temperature may be in the range between about 500 °C and about 850 °C, and the chamber pressure may be in the range between about 4 Torr and about 300 Torr.

[0050] When the source / drain region is a p-type region of a p-type transistor, the semiconductor layer 48B may include SiGe or Ge, and may also include a p-type dopant, such as boron, indium, or a combination thereof. For example, the semiconductor layer 48B may include SiGeB, GeB, etc. The percentage of germanium atoms may be greater than the percentage of germanium atoms in the semiconductor layer 48A, for example, having a difference greater than about 20% or 30%. For example, the percentage of germanium atoms in the semiconductor layer 48B may be in the range between about 50% and about 60%. The p-type dopant concentration in the semiconductor layer 48B may be higher than the p-type dopant concentration in the semiconductor layer 48A. For example, the p-type dopant concentration in the semiconductor layer 48B may be in the range between about 7E20 / cm 3 and about 1E21 / cm 3 in the range.

[0051] In the deposition of the p-type semiconductor layer 48B, the process gas may include SiH4, DCS, HCl, GeH4, BH3, BCl3, etc. The wafer temperature may be in the range between about 400 °C and about 850 °C, and the chamber pressure may be in the range between about 4 Torr and about 300 Torr.

[0052] According to some embodiments, the deposition process gas may further include an etching gas such as HCl, such that the semiconductor layer 48B is not grown on the gate spacers 38 and the hard mask 36 ( Figure 8B ).

[0053] During the formation of the semiconductor layer 48B, dislocations 49 (including dislocations 49A and 49B) are formed and grow as the semiconductor layer 48B is deposited. The length of the dislocations 49 can range between about 1 nm and about 70 nm. The total number of dislocations 49 can range from 1 to several hundred. The dislocations can include dislocations with opposite slopes, such as dislocations in the lower left to upper right direction and dislocations in the lower right to upper left direction.

[0054] To form the dislocations 49, the formation process of the semiconductor layer 48B is adjusted to be different from the formation process of the semiconductor layer 48A. According to some embodiments, the growth of the semiconductor layer 48B is performed continuously, without an etch-back process. In other words, the formation of the semiconductor layer 48B can be a continuous growth process until the top surface of the semiconductor layer 48B is higher than the top surface of the top semiconductor nanostructure 22B, without an etch-back process. Thus, during growth, the dislocations 49 have the opportunity to grow further rather than being removed in an etch-back process. If an etch-back is performed, the semiconductor layer 48B may not have dislocations.

[0055] It should be understood that when the growth rate of the semiconductor layer 48B is low, dislocations may not be formed even if an etch-back is not performed during the formation of the semiconductor layer 48B. To ensure the formation of the dislocations 49, the growth rate of the semiconductor layer 48B is increased. According to some embodiments, the deposition rate of the semiconductor layer 48B is relatively high, such as higher than about and can be in the range of about and about According to some embodiments, to increase the deposition rate of the semiconductor layer 48B, the process conditions are adjusted. For example, the pressure in the deposition chamber, the flow rate (and / or partial pressure) of the precursors (such as silicon-containing precursors and / or dopant-containing precursors), the wafer temperature, etc. can be increased.

[0056] According to some embodiments, the partial pressure P2 of the silicon-containing gas in the formation of the semiconductor layer 48B is higher than the partial pressure P1 of the silicon-containing gas in the formation of the semiconductor layer 48A. For example, according to some embodiments, the ratio P2 / P1 is higher than 1.0 and can be in the range of about 1.1 and 5.

[0057] According to some embodiments, the wafer temperature T2 in the formation of the semiconductor layer 48B is higher than the temperature T1 in the formation of the semiconductor layer 48A. For example, according to some embodiments, the temperature difference (T2 - T1) can be greater than about 25 °C and can be in the range of about 5 °C and 250 °C, or in the range of about 100 °C and 250 °C.

[0058] According to some embodiments, the flow rate FR2 of the silicon-containing gas in the formation of the semiconductor layer 48B is higher than the pressure flow rate FR1 of the silicon-containing gas in the formation of the semiconductor layer 48A. For example, according to some embodiments, the ratio FR2 / FR1 is higher than 1.0 and can be in the range between about 1 and about 5.

[0059] According to some embodiments, the growth (deposition) rate GR2 of the semiconductor layer 48B (the increase in thickness per unit time) is higher than the growth rate GR1 of the semiconductor layer 48A (during the deposition process of the deposition and etch-back cycles). For example, according to some embodiments, the ratio GR2 / GR1 is greater than 1.0 and can be in the range between about 2 and about 10.

[0060] According to some embodiments, in order to find the optimal range of process conditions for generating dislocations without causing other problems (such as the growth of a semiconductor on a dielectric material), a plurality of sample wafers will be formed to have the same structure as Figure 8B and Figure 15 . Different combinations of process conditions are used to grow the source / drain regions 48 (including layer 48A and layer 48B) in the sample wafers. These process conditions include but are not limited to, different growth rates, different wafer temperatures, different chamber pressures, and different flow rates. For example, the resulting wafers are inspected using a transmission electron microscope (TEM) to determine whether dislocations are formed and to find the number of dislocations. The process conditions that generate the desired dislocations are used for the manufacture of the wafers.

[0061] The dislocation 49 can include a dislocation 49A, which starts to be formed when the semiconductor layer 48B starts to grow. Thus, the starting end of the dislocation 49A can be at the interface between the semiconductor layers 48A and 48B. On the other hand, the semiconductor layer 48A may not have dislocations. Alternatively, both the semiconductor layers 48A and 48B have dislocations 49, and the number of dislocations in the dielectric layer 48A is significantly lower than the number of dislocations 49 in the semiconductor layer 48B (e.g., less than 5%). According to these embodiments, some dislocations 49 start to be formed in the dielectric layer 48A, and other dislocations 49 start to be formed from the interface between the semiconductor layers 48A and 48B.

[0062] The dislocation 49 can also include a dislocation 49B, which has its starting end at the surface of a dielectric feature (such as the dielectric layer 46, the inner spacer 44, the gate spacer 38, etc.). Thus, each dislocation 49B can have an end in contact with the dielectric feature.

[0063] According to an alternative embodiment, instead of starting with the process conditions for generating the dislocations 49 (which do not include a re-etch process and include a higher growth rate), the process conditions for generating the dislocations 49 can be employed during the formation of the semiconductor layer 48A or during the formation of the semiconductor layer 48B. For example, the formation of the lower portion of the semiconductor layer 48A (or 48B) can employ a re-etch process and / or a lower wafer temperature such that dislocations are not formed. However, the formation of the upper portion of the semiconductor layer 48A (or 48B) employs different process conditions (e.g., no re-etch process and a higher wafer temperature / flow rate) such that the dislocations 49 start to be formed when depositing the upper portion of the semiconductor layer 48A (or 48B).

[0064] According to some embodiments, the substrate 20 has a top surface facing a horizontal direction in the

[001] and

[110] directions (e.g., facing right). According to some embodiments, the dislocations 49 grow in the

[111] direction. The tilt angle θ of the dislocations 49 can be in the range between about 20 degrees and about 70 degrees and can be about 54.7 degrees.

[0065] Figure 10A and Figure 10B FIG. shows a cross-sectional view of the structure after the formation of the contact etch stop layer (CESL) 50 and the interlayer dielectric (ILD) 52. The corresponding process is shown as process 218 in the process flow 200 shown in Figure 21 The corresponding structure is also shown in Figure 18 The CESL 50 can be formed of silicon oxide, silicon nitride, silicon carbonitride, etc., and can be formed using CVD, ALD, etc. The ILD 52 can include a dielectric material formed using, for example, FCVD, spin coating, CVD, or any other suitable deposition method. The ILD 52 can be formed of an oxygen-containing dielectric material, which can be a silicon oxide-based material formed using tetraethyl orthosilicate (TEOS) as a precursor, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0066] The CESL 50 and the ILD 52 are planarized by a planarization process (e.g., a CMP process or a mechanical polishing process). The corresponding process is shown as process 220 in the process flow 200 shown in Figure 21 According to some embodiments, the planarization process can remove the hard mask 36 to expose the dummy gate electrode 34, as Figure 10A shown. According to an alternative embodiment, the planarization process can expose the hard mask 36 and be stopped on the hard mask 36. According to some embodiments, after the planarization process, the top surfaces of the dummy gate electrode 34 (or the hard mask 36), the gate spacers 38, and the ILD 52 are flush within process variations.

[0067] Next, the dummy gate electrode 34 and the dummy gate dielectric 32 (and the hard mask 36, if remaining) are removed in one or more etching processes, thereby forming recesses 58, as Figure 11A and Figure 11B shown. The corresponding process is shown as process 222 in the process flow 200 shown in Figure 21 . According to some embodiments, the dummy gate electrode 34 and the dummy gate dielectric 32 are removed by an (one or more) anisotropic dry etching process. For example, the etching process can be performed using (one or more) reactive gases that selectively etch the dummy gate electrode 34 and the dummy gate dielectric 32 at a faster rate than the etching of the ILD 52. Each recess 58 exposes and / or covers some portions of the multilayer stack 22', which portions include future channel regions in the subsequently completed transistors.

[0068] Then, the sacrificial layer 22A is removed to cause the recesses 58 to extend between the nanostructures 22B. The corresponding process is shown as process 224 in the process flow 200 shown in Figure 21 . The sacrificial layer 22A can be removed by performing an isotropic etching process (e.g., a wet etching process) using an etchant that is selective to the material of the sacrificial layer 22A, while the nanostructures 22B, the substrate 20, and the STI regions 26 remain relatively unetched compared to the sacrificial layer 22A. According to some embodiments where the sacrificial layer 22A includes, for example, SiGe and the nanostructures 22B include, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. can be used to remove the sacrificial layer 22A.

[0069] Referring to Figure 12A and Figure 12B , a gate dielectric 62 and a gate electrode 68 are formed, thereby forming a replacement gate stack 70. The corresponding process is shown as process 226 in the process flow 200 shown in Figure 21 . The corresponding structure is also shown in Figure 19 . According to some embodiments, each gate dielectric 62 includes an interface layer and a high-k dielectric layer on the interface layer. The interface layer can be formed of or include silicon oxide, which can be deposited by a conformal deposition process (e.g., ALD or CVD) or by an oxidation process. According to some embodiments, the high-k dielectric layer includes one or more dielectric layers. For example, the (one or more) high-k dielectric layers can include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations of the foregoing.

[0070] A gate electrode 68 is also formed. During formation, a conductive layer is first formed on the high-k dielectric layer and fills the remaining portion of the recess 58. The gate electrode 68 may include a metal-containing material, for example, TiN, TaN, TiAl, TiAlC, cobalt, ruthenium, aluminum, tungsten, a combination of the foregoing, and / or a multi-layer of the foregoing. For example, the gate electrode 68 may include any number of layers, any number of work function layers, and may include a filling material. The gate dielectric 62 and the gate electrode 68 also fill the space between adjacent nanostructures 22B and the space between the bottom nanostructure 22B and the underlying substrate strip 20'. After filling the recess 58, a planarization process (e.g., a CMP process or a mechanical polishing process) may be performed to remove the excess portions of the gate dielectric and the gate electrode 68 above the top surface of the ILD 52. The gate electrode 68 and the gate dielectric 62 are collectively referred to as the gate stack 70 of the resulting transistor.

[0071] In Figure 13A and Figure 13B the process shown, the gate stack 70 is recessed such that a recess is formed between directly above the gate stack 70 and the opposing portions of the gate spacers 38. A gate mask 74 including one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled in each recess, followed by a planarization process to remove the excess dielectric material extending above the ILD 52. The corresponding process is shown as process 228 in the process flow 200 shown in Figure 21 .

[0072] As Figure 13A and Figure 13B further shown, an ILD 76 is deposited over the ILD 52 and the gate mask 74. The corresponding process is shown as process 230 in the process flow 200 shown in Figure 21 . An etch stop layer (not shown) may (or may not) be deposited prior to the formation of the ILD 76. According to some embodiments, the ILD 76 is formed by FCVD, CVD, PECVD, etc. The ILD 76 is formed of a dielectric material that may be selected from silicon oxide, PSG, BSG, BPSG, USG, etc.

[0073] In Figure 14A and Figure 14B , the ILD 76, the ILD 52, the CESL 50, and the gate mask 74 are etched to form recesses (used by the contact plugs 80A and 80B) that expose the source / drain regions 48 and / or the surface of the gate stack 70. The recesses may be formed by etching using an anisotropic etching process (e.g., RIE, NBE, etc.). Although Figure 14BThe contact plugs 80A and 80B are shown in the same cross-section, but in various embodiments, the contact plugs 80A and 80B may be formed in different cross-sections to reduce the risk of shorting to each other.

[0074] After forming the recess, a silicide region 78 is formed over the epitaxial source / drain region 48. The corresponding process is shown as process 232 in the process flow 200 shown in Figure 21 . Then a contact plug 80B is formed over the silicide region 78. Additionally, a contact 80A (which may also be referred to as a gate contact plug) is formed in the recess, over the gate electrode 68, and in contact with the gate electrode 68. The corresponding process is shown as process 234 in the process flow 200 shown in Figure 21 . The corresponding structure is also shown in Figure 20A . Thus, the transistor 82 is formed. It should be noted that the details of the source / drain region 48 and the dislocation 49 are not shown in Figure 14A and Figure 14B , and these details can be found by referring to Figure 20A .

[0075] Due to the formation of the dislocation 49, the metal used in the processes after the formation of the source / drain region 48 has a greater chance of diffusing into and through the dislocation 49, so the metal ions have a higher concentration at the dislocation 49 than in the part of the source / drain region 48 adjacent to the dislocation 49. For example, Figure 20A schematically shows the concentrated metal ions 84 along and at the dislocation 49, and these metal ions 84 may include ions of (one or more) alkali metals (such as lithium, sodium, potassium), tungsten, cobalt, nickel, titanium, tantalum, etc. Thus, the concentrated metal ions 84 have a higher concentration than the part of the source / drain region 48 away from the dislocation 49. The diffusion of the metal ions 84 may occur during the subsequent formation (such as deposition and CMP) of the contact plug 80B. The concentration of the metal ions 84 can be observed using elemental analysis such as Electron Dispersive X-ray Spectroscopy (EDX) or Atom Probe Tomography (APT).

[0076] Figure 20B shows some parts of a GAA transistor 82' according to some embodiments. The GAA transistor 82' may have substantially the same structure as the GAA transistor 82 in Figure 20A , and may be fabricated using the same processes as those in Figure 20AThe GAA transistor 82' is formed by substantially the same process as the GAA transistor 82. The GAA transistors 82' and 82 can be formed in the same device die and on the same semiconductor substrate 20. The source / drain regions 48 of the GAA transistor 82' do not have source / drain regions, so the GAA transistor 82' has a lower drive current than the GAA transistor 82 to suit customized design requirements.

[0077] According to some embodiments, except for the formation of the source / drain regions 48, most of the formation processes of the GAA transistor 82' can be shared with the GAA transistor 82. The formation of the source / drain regions 48 of the GAA transistor 82 is adjusted to form dislocations, while the formation of the source / drain regions 48 of the GAA transistor 82' is adjusted to avoid dislocations. According to some embodiments, the semiconductor layers 48A of the GAA transistor 82 and the GAA transistor 82' share one or more common formation processes, while the semiconductor layers 48B of the GAA transistor 82 and the GAA transistor 82' are formed by separate processes, such that the GAA transistor 82 has dislocations 49 while the GAA transistor 82' has no dislocations.

[0078] Embodiments of the present disclosure have some advantageous features. By adjusting process conditions, dislocations can be formed in the source / drain regions. The dislocations cause an increase in stress on the channel region. Therefore, the current of the resulting GAA transistor is increased.

[0079] According to some embodiments of the present disclosure, a method includes: forming a protruding feature including a first sacrificial nanosheet over a bulk semiconductor substrate; forming a first semiconductor nanosheet over the first sacrificial nanosheet; forming a second sacrificial nanosheet over the first semiconductor nanosheet; forming a second semiconductor nanosheet over the second sacrificial nanosheet; forming a dummy gate stack over the protruding feature; etching the protruding feature to form a recess; forming source / drain regions in the recess, wherein dislocations are formed in the source / drain regions; removing the first sacrificial nanosheet and the second sacrificial nanosheet; and forming a replacement gate stack to replace the dummy gate stack.

[0080] In an embodiment, the method further includes forming a dielectric layer at the bottom of the recess before the source / drain regions are formed in the recess. In an embodiment, some dislocations are formed starting from the dielectric layer. In an embodiment, forming the source / drain regions includes: epitaxially growing a first semiconductor layer; and epitaxially growing a second semiconductor layer different from the first semiconductor layer, wherein the dislocations start to grow when the second semiconductor layer is grown.

[0081] In an embodiment, growing the first semiconductor layer includes a plurality of cycles, each cycle including depositing a layer of the first semiconductor layer; and etch-back etching the layer of the first semiconductor layer, and wherein growing the second semiconductor layer is a continuous process that ends after the second semiconductor layer has a first top surface that is higher than a second top surface of the second semiconductor nanosheet. In an embodiment, growing the second semiconductor layer is performed without an etch-back process. In an embodiment, growing the first semiconductor layer is performed at a first wafer temperature, and growing the second semiconductor layer is performed at a second wafer temperature that is higher than the first wafer temperature.

[0082] In an embodiment, growing the first semiconductor layer is performed at a first flow rate of a silicon-containing precursor, and growing the second semiconductor layer is performed at a second flow rate of the silicon-containing precursor, and wherein the second flow rate is greater than the first flow rate. In an embodiment, growing the first semiconductor layer is performed at a first partial pressure of the silicon-containing precursor, and growing the second semiconductor is performed at a second partial pressure of the silicon-containing precursor, and the second partial pressure is greater than the first partial pressure. In an embodiment, all dislocations in the source / drain regions are spaced apart from all semiconductor nanosheets in the protruding features.

[0083] According to some embodiments of the present disclosure, a device includes: a first semiconductor nanostructure; a second semiconductor nanostructure over the first semiconductor nanostructure; a gate stack including a portion between the first semiconductor nanostructure and the second semiconductor nanostructure; source / drain regions adjacent to and coupled to the first semiconductor nanostructure and the second semiconductor nanostructure, wherein the first semiconductor nanostructure, the second semiconductor nanostructure, the gate stack, and the source / drain regions form portions of a transistor; and a first dislocation in the source / drain region.

[0084] In an embodiment, the device further includes a second dislocation in the source / drain region and parallel to the first dislocation. In an embodiment, the device further includes metal ions concentrated at the first dislocation, wherein the metal ions have a higher metal ion concentration at the first dislocation than in the surrounding portion of the source / drain region. In an embodiment, the device further includes a dielectric layer under and in contact with the source / drain region, wherein the first dislocation has an end in contact with the dielectric layer.

[0085] In an embodiment, the first dislocation is spaced apart from all semiconductor nanostructures in the transistor. In an embodiment, the source / drain region includes a first semiconductor layer in contact with the first semiconductor nanostructure; and a second semiconductor layer different from the first semiconductor layer, wherein the end of the first dislocation is at an interface between the first semiconductor layer and the second semiconductor layer. In an embodiment, the device further includes an inner spacer in contact with a portion of the gate stack, wherein the first dislocation has an end in contact with the inner spacer.

[0086] According to some embodiments of the present disclosure, a device includes a plurality of first semiconductor nanostructures, wherein an upper semiconductor nanostructure among the plurality of first semiconductor nanostructures overlaps with a corresponding lower semiconductor nanostructure among the plurality of first semiconductor nanostructures; a first gate stack including a portion between the plurality of first semiconductor nanostructures; a plurality of second semiconductor nanostructures, wherein an upper semiconductor nanostructure among the plurality of second semiconductor nanostructures overlaps with a corresponding lower semiconductor nanostructure among the plurality of second semiconductor nanostructures; a second gate stack including a portion between the plurality of second semiconductor nanostructures; source / drain regions between the plurality of first semiconductor nanostructures and the plurality of second semiconductor nanostructures; a plurality of first dislocations in the source / drain regions and parallel to each other, wherein the plurality of first dislocations includes a first lower end close to the plurality of first semiconductor nanostructures; and a plurality of second dislocations in the source / drain regions and parallel to each other, wherein the plurality of second dislocations includes a second lower end close to the plurality of second semiconductor nanostructures.

[0087] In an embodiment, the plurality of first dislocations are spaced apart from the plurality of first semiconductor nanostructures by a portion of the source / drain regions. In an embodiment, a portion of the source / drain regions that separates the plurality of first dislocations from the plurality of first semiconductor nanostructures has a different composition from a portion of the source / drain regions that includes the dislocations.

[0088] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructs do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of the present disclosure.

[0089] Example 1 is a method of forming a semiconductor device, including: forming a protruding feature, the protruding feature including: a first sacrificial nanosheet over a bulk semiconductor substrate; a first semiconductor nanosheet over the first sacrificial nanosheet; a second sacrificial nanosheet over the first semiconductor nanosheet; and a second semiconductor nanosheet over the second sacrificial nanosheet; forming a dummy gate stack over the protruding feature; etching the protruding feature to form a recess; forming source / drain regions in the recess, wherein dislocations are formed in the source / drain regions; removing the first sacrificial nanosheet and the second sacrificial nanosheet; and forming a replacement gate stack to replace the dummy gate stack.

[0090] Example 2 is the method described in Example 1, further comprising: forming a dielectric layer at the bottom of the recess before the source / drain region is formed in the recess.

[0091] Example 3 is the method described in Example 2, wherein some of the dislocations are formed starting from the dielectric layer.

[0092] Example 4 is the method described in Example 1, wherein forming the source / drain region includes: epitaxially growing a first semiconductor layer; and epitaxially growing a second semiconductor layer different from the first semiconductor layer, wherein the dislocations start to grow when the second semiconductor layer is grown.

[0093] Example 5 is the method described in Example 4, wherein growing the first semiconductor layer includes a plurality of cycles, each cycle including: depositing a layer of the first semiconductor layer; and back-etching the layer of the first semiconductor layer, and wherein growing the second semiconductor layer is a continuous process that ends after the second semiconductor layer has a first top surface that is higher than the second top surface of the second semiconductor nanosheet.

[0094] Example 6 is the method described in Example 5, wherein growing the second semiconductor layer is performed without a back-etching process.

[0095] Example 7 is the method described in Example 4, wherein growing the first semiconductor layer is performed at a first wafer temperature, and growing the second semiconductor layer is performed at a second wafer temperature higher than the first wafer temperature.

[0096] Example 8 is the method described in Example 4, wherein growing the first semiconductor layer is performed at a first flow rate of a silicon-containing precursor, and growing the second semiconductor layer is performed at a second flow rate of the silicon-containing precursor, and wherein the second flow rate is greater than the first flow rate.

[0097] Example 9 is the method described in Example 4, wherein growing the first semiconductor layer is performed at a first partial pressure of a silicon-containing precursor, and growing the second semiconductor is performed at a second partial pressure of the silicon-containing precursor, and the second partial pressure is greater than the first partial pressure.

[0098] Example 10 is the method described in Example 1, wherein all of the dislocations in the source / drain region are spaced apart from all of the semiconductor nanosheets in the protruding feature.

[0099] Example 11 is a semiconductor device, comprising: a first semiconductor nanostructure; a second semiconductor nanostructure over the first semiconductor nanostructure; a gate stack including a portion between the first semiconductor nanostructure and the second semiconductor nanostructure; source / drain regions beside and coupled to the first semiconductor nanostructure and the second semiconductor nanostructure, wherein the first semiconductor nanostructure, the second semiconductor nanostructure, the gate stack and the source / drain regions form respective parts of a transistor; and a first dislocation in the source / drain region.

[0100] Example 12 is the device of Example 11, further comprising: a second dislocation in the source / drain region and parallel to the first dislocation.

[0101] Example 13 is the device of Example 11, further comprising: metal ions concentrated at the first dislocation, wherein the metal ions have a higher metal ion concentration at the first dislocation than in a surrounding portion of the source / drain region.

[0102] Example 14 is the device of Example 11, further comprising: a dielectric layer under and in contact with the source / drain region, wherein the first dislocation has an end in contact with the dielectric layer.

[0103] Example 15 is the device of Example 11, wherein the first dislocation is spaced apart from all semiconductor nanostructures in the transistor.

[0104] Example 16 is the device of Example 11, wherein the source / drain region includes: a first semiconductor layer in contact with the first semiconductor nanostructure; and a second semiconductor layer different from the first semiconductor layer, wherein an end of the first dislocation is at an interface between the first semiconductor layer and the second semiconductor layer.

[0105] Example 17 is the device of Example 11, further comprising: an internal spacer in contact with the portion of the gate stack, wherein the first dislocation has an end in contact with the internal spacer.

[0106] Example 18 is a semiconductor device, comprising: a plurality of first semiconductor nanostructures, wherein an upper semiconductor nanostructure among the plurality of first semiconductor nanostructures overlaps with a corresponding lower semiconductor nanostructure among the plurality of first semiconductor nanostructures; a first gate stack including a portion between the plurality of first semiconductor nanostructures; a plurality of second semiconductor nanostructures, wherein an upper semiconductor nanostructure among the plurality of second semiconductor nanostructures overlaps with a corresponding lower semiconductor nanostructure among the plurality of second semiconductor nanostructures; a second gate stack including a portion between the plurality of second semiconductor nanostructures; source / drain regions between the plurality of first semiconductor nanostructures and the plurality of second semiconductor nanostructures; a plurality of first dislocations in the source / drain regions and parallel to each other, wherein the plurality of first dislocations includes a first lower end close to the plurality of first semiconductor nanostructures; and a plurality of second dislocations in the source / drain regions and parallel to each other, wherein the plurality of second dislocations includes a second lower end close to the plurality of second semiconductor nanostructures.

[0107] Example 19 is the device of Example 18, wherein the plurality of first dislocations are spaced apart from the plurality of first semiconductor nanostructures by a portion of the source / drain regions.

[0108] Example 20 is the device of Example 19, wherein the portion of the source / drain regions separating the plurality of first dislocations from the plurality of first semiconductor nanostructures has a composition different from that of the portion of the source / drain regions including the dislocations.

Claims

1. A method of forming a semiconductor device, comprising: Forming a protruding feature, the protruding feature comprising: A first sacrificial nanosheet, on a bulk semiconductor substrate; A first semiconductor nanosheet, on the first sacrificial nanosheet; A second sacrificial nanosheet, on the first semiconductor nanosheet; and A second semiconductor nanosheet, on the second sacrificial nanosheet; Forming a dummy gate stack on the protruding feature; Etching the protruding feature to form a recess; Forming source / drain regions in the recess, wherein dislocations are formed in the source / drain regions; Removing the first sacrificial nanosheet and the second sacrificial nanosheet; and Forming a replacement gate stack to replace the dummy gate stack.

2. The method according to claim 1, further comprising: Before the source / drain regions are formed in the recess, a dielectric layer is formed at the bottom of the recess.

3. The method according to claim 2, wherein, Some of the dislocations are formed starting from the dielectric layer.

4. The method according to claim 1, wherein, Forming the source / drain regions includes: Epitaxially growing a first semiconductor layer; and Epitaxially growing a second semiconductor layer different from the first semiconductor layer, wherein the dislocations start to grow when growing the second semiconductor layer.

5. The method according to claim 4, wherein Growing the first semiconductor layer includes a plurality of cycles, each cycle comprising: Depositing a layer of the first semiconductor layer; and Back-etching the layer of the first semiconductor layer, and wherein growing the second semiconductor layer is a continuous process that ends after the second semiconductor layer has a first top surface that is higher than a second top surface of the second semiconductor nanosheet.

6. The method according to claim 5, wherein, Growing the second semiconductor layer is performed without a back-etching process.

7. The method according to claim 4, wherein Growing the first semiconductor layer is performed at a first wafer temperature, and growing the second semiconductor layer is performed at a second wafer temperature higher than the first wafer temperature.

8. The method according to claim 4, wherein Growing the first semiconductor layer is performed at a first flow rate of a silicon-containing precursor, and growing the second semiconductor layer is performed at a second flow rate of the silicon-containing precursor, and wherein the second flow rate is greater than the first flow rate.

9. A semiconductor device, comprising: A first semiconductor nanostructure; A second semiconductor nanostructure, on the first semiconductor nanostructure; A gate stack, including a portion between the first semiconductor nanostructure and the second semiconductor nanostructure; Source / drain regions, beside and coupled to the first semiconductor nanostructure and the second semiconductor nanostructure, wherein the first semiconductor nanostructure, the second semiconductor nanostructure, the gate stack, and the source / drain regions form parts of a transistor; And A first dislocation, in the source / drain region.

10. A semiconductor device, comprising: A plurality of first semiconductor nanostructures, wherein upper semiconductor nanostructures among the plurality of first semiconductor nanostructures overlap corresponding lower semiconductor nanostructures among the plurality of first semiconductor nanostructures; A first gate stack, including a portion between the plurality of first semiconductor nanostructures; A plurality of second semiconductor nanostructures, wherein an upper semiconductor nanostructure among the plurality of second semiconductor nanostructures overlaps with a corresponding lower semiconductor nanostructure among the plurality of second semiconductor nanostructures; A second gate stack, including a portion between the plurality of second semiconductor nanostructures; Source / drain regions, between the plurality of first semiconductor nanostructures and the plurality of second semiconductor nanostructures; A plurality of first dislocations, in the source / drain regions and parallel to each other, wherein the plurality of first dislocations includes a first lower end close to the plurality of first semiconductor nanostructures; and A plurality of second dislocations, in the source / drain regions and parallel to each other, wherein the plurality of second dislocations includes a second lower end close to the plurality of second semiconductor nanostructures.

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