Array substrate and display panel

Abstract

The invention discloses an array substrate and a display panel. The array substrate comprises a pixel circuit, wherein the pixel circuit comprises a first switch transistor and a driving transistor; the first switch transistor is connected with the driving transistor, the first switch transistor is used for controlling a gate potential and a first pole potential of the driving transistor, and the driving transistor is used for forming a driving current according to the gate potential and the first pole potential; a threshold voltage of the driving transistor is greater than a threshold voltage of the first switching transistor. It can be guaranteed that the driving transistor can achieve gray scale expansion, and the adaptability of the electrical interval of the driving transistor and the pixel circuit is improved. Meanwhile, the switching rate of the first switching transistor is guaranteed, the adaptability of the electrical interval of the first switching transistor and the pixel circuit is guaranteed, the pixel circuit can give consideration to the switching rate of the first switching transistor and the driving capacity of the driving transistor at the same time, and the display effect of the display panel is improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technologies, and particularly to an array substrate and a display panel. Background Art

[0002] A display panel can form a circuit using all-oxide thin-film transistors to drive a light-emitting device to emit light, enabling the display panel to have the characteristics of low cost and excellent large-area uniformity. Since the electrical property range adapted to the circuit by the all-oxide thin-film transistors is relatively small, during the process of forming the display panel, it is easy for the electrical property range of the all-oxide thin-film transistors not to match the circuit, resulting in a relatively poor display effect of the display panel. Summary of the Invention

[0003] The present invention provides an array substrate and a display panel to improve the adaptability between the electrical property range of the transistors and the circuit, and improve the display effect of the display panel.

[0004] In a first aspect, embodiments of the present invention provide an array substrate, including a pixel circuit, where the pixel circuit includes a first switching transistor and a driving transistor; the first switching transistor is connected to the driving transistor, the first switching transistor is configured to control the gate potential and the first pole potential of the driving transistor, and the driving transistor is configured to form a driving current according to the gate potential and the first pole potential; the threshold voltage of the driving transistor is greater than the threshold voltage of the first switching transistor.

[0005] According to an embodiment of the first aspect of the present application, the array substrate further includes:

[0006] A substrate;

[0007] A gate layer disposed on one side of the substrate, where the gate layer includes a first gate of the first switching transistor and a second gate of the driving transistor;

[0008] A gate insulating layer disposed on one side of the gate layer, where the gate insulating layer includes a first gate insulating layer and a second gate insulating layer, the orthographic projection of the first gate on the substrate is located within the orthographic projection of the first gate insulating layer on the substrate, and the orthographic projection of the second gate on the substrate is located within the orthographic projection of the second gate insulating layer on the substrate; the thickness of the second gate insulating layer is greater than the thickness of the first gate insulating layer;

[0009] A semiconductor layer disposed on the side of the gate insulating layer away from the gate layer, where the semiconductor layer includes a first active region and a second active region, the orthographic projection of the first active region on the substrate overlaps with the orthographic projection of the first gate on the substrate, and the orthographic projection of the second active region on the substrate overlaps with the orthographic projection of the second gate on the substrate;

[0010] According to any of the foregoing embodiments of the first aspect of the present application, the ratio of the thickness of the second gate insulating layer to the thickness of the first gate insulating layer ranges from 1.5 to 2.

[0011] According to any of the foregoing embodiments of the first aspect of the present application, the gate layer includes a top gate layer and a bottom gate layer, and the gate insulating layer includes a top gate insulating layer and a bottom gate insulating layer; the bottom gate layer is disposed on one side of the substrate, the bottom gate insulating layer is disposed on the side of the bottom gate layer away from the substrate, the semiconductor layer is disposed on the side of the bottom gate insulating layer away from the substrate, the top gate insulating layer is disposed on the side of the semiconductor layer away from the substrate, and the top gate layer is disposed on the side of the top gate insulating layer away from the substrate;

[0012] The first gate includes a first bottom gate and a first top gate, and the second gate includes a second bottom gate and a second top gate; the bottom gate layer includes the first bottom gate and the second bottom gate, and the top gate layer includes the first top gate and the second top gate; the first gate insulating layer includes a first top gate insulating layer and a first bottom gate insulating layer, and the second gate insulating layer includes a second top gate insulating layer and a second bottom gate insulating layer; the first active region includes a first source region, a first channel region, and a first drain region, and the second active region includes a second source region, a second channel region, and a second drain region;

[0013] The first bottom gate is connected to the first source region, and the second top gate is connected to the second source region; the thickness of the bottom gate insulating layer is greater than the thickness of the top gate insulating layer; or, the first top gate is connected to the first source region, and the second bottom gate is connected to the second source region; the thickness of the top gate insulating layer is greater than the thickness of the bottom gate insulating layer;

[0014] According to any of the foregoing embodiments of the first aspect of the present application, the array substrate further includes:

[0015] A source-drain layer, the source-drain layer is disposed on the side of the top gate layer away from the semiconductor layer, and the source-drain layer includes a first source, a first drain, a second source, and a second drain; the first source is connected to the first source region, the first drain is connected to the first drain region, the second source is connected to the second source region, and the second drain is connected to the second drain region;

[0016] According to any of the foregoing embodiments of the first aspect of the present application, the source-drain layer further includes a first connection structure and a second connection structure, and the first bottom gate or the first top gate is connected to the first source region through the first connection structure, and the second top gate or the second bottom gate is connected to the second source region through the second connection structure;

[0017] According to any of the foregoing embodiments of the first aspect of the present application, the array substrate further includes:

[0018] An interlayer insulating layer disposed between the top gate layer and the source-drain layer.

[0019] According to any of the foregoing embodiments of the first aspect of the present application, the channel length of the driving transistor is greater than the channel length of the first switching transistor;

[0020] According to any of the foregoing embodiments of the first aspect of the present application, the channel length of the driving transistor is 2-10 times the channel length of the first switching transistor.

[0021] According to any of the foregoing embodiments of the first aspect of the present application, the array substrate further includes:

[0022] A substrate;

[0023] A gate layer disposed on one side of the substrate, the gate layer including a first gate of the first switching transistor and a second gate of the driving transistor;

[0024] A gate insulating layer disposed on one side of the gate layer, the gate insulating layer including a first gate insulating layer and a second gate insulating layer, a positive projection of the first gate on the substrate being located within a positive projection of the first gate insulating layer on the substrate, and a positive projection of the second gate on the substrate being located within a positive projection of the second gate insulating layer on the substrate;

[0025] A semiconductor layer disposed on a side of the gate insulating layer away from the gate layer, the semiconductor layer including a first active region and a second active region, a positive projection of the first active region on the substrate overlapping a positive projection of the first gate on the substrate, and a positive projection of the second active region on the substrate overlapping a positive projection of the second gate on the substrate; the first active region includes a first source region, a first channel region, and a first drain region, and the second active region includes a second source region, a second channel region, and a second drain region; the length of the second channel region is greater than the length of the first channel region;

[0026] According to any of the foregoing embodiments of the first aspect of the present application, the gate layer includes a top gate layer and a bottom gate layer, and the gate insulating layer includes a top gate insulating layer and a bottom gate insulating layer; the bottom gate layer is disposed on one side of the substrate, the bottom gate insulating layer is disposed on a side of the bottom gate layer away from the substrate, the semiconductor layer is disposed on a side of the bottom gate insulating layer away from the substrate, the top gate insulating layer is disposed on a side of the semiconductor layer away from the substrate, and the top gate layer is disposed on a side of the top gate insulating layer away from the substrate;

[0027] The first gate includes a first bottom gate and a first top gate, and the second gate includes a second bottom gate and a second top gate; the bottom gate layer includes the first bottom gate and the second bottom gate, and the top gate layer includes the first top gate and the second top gate; the first gate insulating layer includes a first top gate insulating layer and a first bottom gate insulating layer, and the second gate insulating layer includes a second top gate insulating layer and a second bottom gate insulating layer;

[0028] The first bottom gate is connected to the first source region, and the second bottom gate is connected to the second source region; or, the first top gate is connected to the first source region, and the second top gate is connected to the second source region;

[0029] According to any of the foregoing embodiments of the first aspect of the present application, the thickness of the bottom gate insulating layer is equal to the thickness of the top gate insulating layer.

[0030] According to any of the foregoing embodiments of the first aspect of the present application, the first switching transistor is an N-type transistor, and the driving transistor is an N-type transistor.

[0031] According to any of the foregoing embodiments of the first aspect of the present application, the array substrate further includes a gate driving circuit, the gate driving circuit includes a second switching transistor and an output transistor, the second switching transistor is connected to the output transistor, the output transistor is connected to the first switching transistor, the second switching transistor is used to control the gate driving signal of the output transistor, and the gate driving signal is used to control the on state of the first switching transistor; the output transistor includes a third top gate and a third bottom gate; the third top gate is connected to the second switching transistor, and the third bottom gate is used to input a first voltage; wherein, the first voltage is adjustable;

[0032] According to any of the foregoing embodiments of the first aspect of the present application, the bottom gate layer of the array substrate includes the third bottom gate;

[0033] The bottom gate insulating layer of the array substrate includes a third bottom gate insulating layer, and the third bottom gate insulating layer covers the third bottom gate;

[0034] The semiconductor layer of the array substrate includes a third active region, and the third active region covers the third bottom gate insulating layer;

[0035] The top gate insulating layer of the array substrate includes a third top gate insulating layer, and the third top gate insulating layer covers the third active region;

[0036] The top gate layer of the array substrate includes a third top gate, and the orthographic projection of the third top gate on the substrate overlaps with the orthographic projection of the third top gate insulating layer on the substrate;

[0037] According to any of the foregoing embodiments of the first aspect of the present application, the second switching transistor includes a fourth top gate and a fourth bottom gate. The fourth top gate is located in the top gate layer, the fourth bottom gate is located in the bottom gate layer, and the potentials of the fourth top gate and the fourth bottom gate are equal.

[0038] According to any of the foregoing embodiments of the first aspect of the present application, the fourth top gate and the fourth bottom gate are connected.

[0039] According to any of the foregoing embodiments of the first aspect of the present application, the bottom gate insulating layer includes a fourth bottom gate insulating layer that covers the fourth bottom gate; the semiconductor layer includes a fourth active region that covers the fourth bottom gate insulating layer; the top gate insulating layer includes a fourth top gate insulating layer that covers the fourth active region; the orthographic projection of the fourth top gate on the substrate overlaps with the orthographic projection of the fourth top gate insulating layer on the substrate; the third active region includes a third source region, a third channel region, and a third drain region; the fourth active region includes a fourth source region, a fourth channel region, and a fourth drain region.

[0040] The source-drain layer of the array substrate includes a third source, a third drain, a fourth source, and a fourth drain; the third source is connected to the third source region, the third drain is connected to the third drain region, the fourth source is connected to the fourth source region, and the fourth drain is connected to the fourth drain region.

[0041] According to any of the foregoing embodiments of the first aspect of the present application, the source-drain layer further includes a third connection structure, and the fourth top gate is connected to the fourth bottom gate through the third connection structure.

[0042] In a second aspect, an embodiment of the present invention further provides an array substrate, including a gate driving circuit; the gate driving circuit includes a second switching transistor and an output transistor. The second switching transistor is connected to the output transistor, and the output transistor is configured to output a gate driving signal; the output transistor includes a third top gate and a third bottom gate; the third top gate is connected to the second switching transistor, and the third bottom gate is configured to input a first voltage; wherein, the first voltage is adjustable.

[0043] According to the embodiment of the second aspect of the present application, the array substrate further includes:

[0044] A substrate;

[0045] A bottom gate layer disposed on one side of the substrate, and the bottom gate layer includes the third bottom gate.

[0046] A bottom gate insulating layer is disposed on a side of the bottom gate layer away from the substrate. The bottom gate insulating layer includes a third bottom gate insulating layer, and the third bottom gate insulating layer covers the third bottom gate;

[0047] A semiconductor layer is disposed on a side of the bottom gate insulating layer away from the substrate. The semiconductor layer includes a third active region, and the third active region covers the third bottom gate insulating layer;

[0048] A top gate insulating layer is disposed on a side of the semiconductor layer away from the substrate. The top gate insulating layer includes a third top gate insulating layer, and the third top gate insulating layer covers the third active region;

[0049] A top gate layer is disposed on a side of the top gate insulating layer away from the substrate. The top gate layer includes a third top gate, and a positive projection of the third top gate on the substrate overlaps with a positive projection of the third top gate insulating layer on the substrate;

[0050] According to any of the foregoing embodiments of the second aspect of the present application, the second switching transistor includes a fourth top gate and a fourth bottom gate. The fourth top gate is located in the top gate layer, the fourth bottom gate is located in the bottom gate layer, and the potentials of the fourth top gate and the fourth bottom gate are equal;

[0051] According to any of the foregoing embodiments of the second aspect of the present application, the fourth top gate and the fourth bottom gate are connected;

[0052] According to any of the foregoing embodiments of the second aspect of the present application, the bottom gate insulating layer includes a fourth bottom gate insulating layer, and the fourth bottom gate insulating layer covers the fourth bottom gate; the semiconductor layer includes a fourth active region, and the fourth active region covers the fourth bottom gate insulating layer; the top gate insulating layer includes a fourth top gate insulating layer, and the fourth top gate insulating layer covers the fourth active region; a positive projection of the fourth top gate on the substrate overlaps with a positive projection of the fourth top gate insulating layer on the substrate; the third active region includes a third source region, a third channel region, and a third drain region; the fourth active region includes a fourth source region, a fourth channel region, and a fourth drain region;

[0053] The array substrate further includes:

[0054] A source-drain layer is disposed on a side of the top gate layer away from the semiconductor layer. The source-drain layer includes a third source, a third drain, a fourth source, and a fourth drain; the third source is connected to the third source region, the third drain is connected to the third drain region, the fourth source is connected to the fourth source region, and the fourth drain is connected to the fourth drain region;

[0055] According to any of the foregoing embodiments of the second aspect of the present application, the source-drain layer further includes a third connection structure, and the fourth top gate is connected to the fourth bottom gate through the third connection structure.

[0056] In a third aspect, an embodiment of the present invention further provides a display panel, including the array substrate described in the first aspect and the second aspect.

[0057] In the technical solution of the embodiment of the present invention, by setting the threshold voltage of the driving transistor to be greater than the threshold voltage of the first switching transistor, the driving ability of the driving transistor can be made greater than that of the first switching transistor, ensuring that the driving transistor can achieve gray-scale expansion and improving the adaptability of the electrical range of the driving transistor to the pixel circuit. At the same time, the switching speed of the first switching transistor is ensured, and the adaptability of the electrical range of the first switching transistor to the pixel circuit is ensured, so that the pixel circuit can take into account both the switching speed of the first switching transistor and the driving ability of the driving transistor, improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 FIG. is a top view structural schematic diagram of an array substrate provided by an embodiment of the present invention;

[0059] Figure 2 FIG. is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0060] Figure 3 FIG. is a cross-sectional structural schematic diagram of an array substrate provided by an embodiment of the present invention;

[0061] Figure 4 FIG. is a cross-sectional structural schematic diagram of another array substrate provided by an embodiment of the present invention;

[0062] Figure 5 FIG. is a cross-sectional structural schematic diagram of another array substrate provided by an embodiment of the present invention;

[0063] Figure 6 FIG. is a cross-sectional structural schematic diagram of another array substrate provided by an embodiment of the present invention;

[0064] Figure 7 FIG. is a cross-sectional structural schematic diagram of another array substrate provided by an embodiment of the present invention;

[0065] Figure 8 FIG. is a top view structural schematic diagram of another array substrate provided by an embodiment of the present invention;

[0066] Figure 9 FIG. is a structural schematic diagram of a gate driving circuit provided by an embodiment of the present invention;

[0067] Figure 10Schematic cross-sectional structure diagram of another array substrate provided by an embodiment of the present invention;

[0068] Figure 11 Schematic diagram showing the correlation between the threshold voltage of an output transistor and the performance of a gate driving circuit provided by an embodiment of the present invention;

[0069] Figure 12 Schematic diagram showing the correlation between the threshold voltage of a second switching transistor and the performance of a gate driving circuit provided by an embodiment of the present invention;

[0070] Figure 13 Schematic structure diagram of a display panel provided by an embodiment of the present invention. Detailed implementation manners

[0071] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present invention, rather than limiting the present invention. Additionally, it should be noted that for the sake of description, only parts related to the present invention are shown in the drawings rather than all the structures.

[0072] Figure 1 Top view structure diagram of an array substrate provided by an embodiment of the present invention, Figure 2 Schematic structure diagram of a pixel circuit provided by an embodiment of the present invention. As Figure 1 and Figure 2 shown, the array substrate includes a pixel circuit 10, and the pixel circuit 10 includes a first switching transistor T1 and a driving transistor Tdr; the first switching transistor T1 is connected to the driving transistor Tdr, and the first switching transistor T1 is used to control the gate potential and the first pole potential of the driving transistor Tdr, and the driving transistor Tdr is used to form a driving current according to the gate potential and the first pole potential; the threshold voltage of the driving transistor Tdr is greater than the threshold voltage of the first switching transistor T1.

[0073] Specifically, as Figure 1 shown, the array substrate may include a display area AA, and the pixel circuit 10 is disposed in the display area AA. When the display area AA includes a plurality of pixel circuits 10, the plurality of pixel circuits 10 may be regularly arranged in the display area AA, for example, they may be arranged in an array. The pixel circuit 10 includes a first switching transistor T1 and a driving transistor Tdr, and the first switching transistor T1 is connected to the driving transistor Tdr, and can control the gate potential and the first pole potential of the driving transistor Tdr according to the input driving signal, so that the driving transistor Tdr can form a driving current according to the input driving signal. When the array substrate forms a display panel, a light-emitting device is further disposed in the display area AA, and the driving transistor Tdr is connected to the light-emitting device and is used to provide a driving current for the light-emitting device to drive the light-emitting device to emit light, thereby realizing the display of the display panel.

[0074] Exemplarily, Figure 2 Exemplarily, it is shown that the pixel circuit 10 includes five first switching transistors T1, a driving transistor Tdr, and two capacitors. The five first switching transistors T1, the driving transistor Tdr, and the two capacitors form a 6T2C pixel circuit. The five first switching transistors T1 can be respectively a first initialization transistor M1, a second initialization transistor M2, a data writing transistor M3, a threshold compensation transistor M4, and a light emission control transistor M5. The two capacitors are respectively a first capacitor C1 and a second capacitor C2. During the operation of the pixel circuit 10, in the first stage, the first scan signal S1 can control the first initialization transistor M1 and the threshold compensation transistor M4 to conduct. The first initialization signal Vint is transmitted to the first node n through the first initialization transistor M1, and the gate of the driving transistor Tdr is initialized through the second capacitor C2, so that the driving transistor Tdr conducts. Then, the driving transistor Tdr is subjected to threshold compensation through the threshold compensation transistor M4. In the second stage, the second scan signal S2 controls the data writing transistor M3 to conduct. The data signal Data is written into the first capacitor C1 and the second capacitor C2 through the data writing transistor M3, and is coupled to the gate of the driving transistor Tdr according to the first capacitor C1 and the second capacitor C2, so that the gate potential of the driving transistor Tdr is the data signal after threshold compensation. In the third stage, the light emission control signal EM controls the light emission control transistor M5 to conduct. The first power supply VDD is transmitted to the first pole of the driving transistor Tdr through the light emission control transistor M5. The driving transistor Tdr forms a driving current according to the gate potential and the first pole potential, and drives the light emitting device D1 to emit light. In the fourth stage, the third scan signal S3 controls the second initialization transistor M2 to conduct. The second initialization signal Vref initializes the anode of the light emitting device D1 through the second initialization transistor M2. The cathode of the light emitting device D1 inputs the second power supply VSS, and the second power supply VSS is less than the first power supply VDD. It can be seen from the above process that by controlling different first switching transistors T1 to conduct or turn off through the scan signal and the light emission control signal, the gate potential and the first pole potential of the driving transistor Tdr can be controlled, so that the driving transistor Tdr can form a driving current according to the data signal and drive the light emitting device D1 to emit light.

[0075] During the operation of the pixel circuit 10, the first switching transistor T1, as a switching transistor, can control whether a signal is transmitted. The driving transistor Tdr, as a driving transistor, can form a driving current according to a data signal. By setting the threshold voltage of the driving transistor Tdr to be greater than the threshold voltage of the first switching transistor T1, the driving ability of the driving transistor Tdr can be made greater than that of the first switching transistor T1, ensuring that the driving transistor Tdr can achieve gray-scale expansion and improving the adaptability of the electrical range of the driving transistor Tdr to the pixel circuit 10. At the same time, the switching speed of the first switching transistor T1 is ensured, and the adaptability of the electrical range of the first switching transistor T1 to the pixel circuit 10 is ensured, enabling the pixel circuit 10 to take into account both the switching speed of the first switching transistor T1 and the driving ability of the driving transistor Tdr, thereby improving the display effect of the display panel.

[0076] In the technical solution of this embodiment, by setting the threshold voltage of the driving transistor to be greater than the threshold voltage of the first switching transistor, the driving ability of the driving transistor can be made greater than that of the first switching transistor, ensuring that the driving transistor can achieve gray-scale expansion and improving the adaptability of the electrical range of the driving transistor to the pixel circuit. At the same time, the switching speed of the first switching transistor is ensured, and the adaptability of the electrical range of the first switching transistor to the pixel circuit is ensured, enabling the pixel circuit to take into account both the switching speed of the first switching transistor and the driving ability of the driving transistor, thereby improving the display effect of the display panel.

[0077] Figure 3 This is a schematic cross-sectional structure diagram of an array substrate provided by an embodiment of the present invention. As Figure 3 shown, the array substrate further includes:

[0078] A substrate 110;

[0079] A gate layer 120, disposed on one side of the substrate 110, and the gate layer 120 includes a first gate G1 of the first switching transistor T1 and a second gate G2 of the driving transistor Tdr;

[0080] A gate insulating layer 130, disposed on one side of the gate layer 120, and the gate insulating layer 130 includes a first gate insulating layer 131 and a second gate insulating layer 132. The orthographic projection of the first gate G1 on the substrate 110 is located within the orthographic projection of the first gate insulating layer 131 on the substrate 110, and the orthographic projection of the second gate G2 on the substrate 110 is located within the orthographic projection of the second gate insulating layer 132 on the substrate 110; the thickness of the second gate insulating layer 132 is greater than the thickness of the first gate insulating layer 131;

[0081] The semiconductor layer 140 is disposed on a side of the gate insulating layer 130 away from the gate layer 120. The semiconductor layer 140 includes a first active region 141 and a second active region 142. A positive projection of the first active region 141 on the substrate 110 overlaps a positive projection of the first gate G1 on the substrate 110, and a positive projection of the second active region 142 on the substrate 110 overlaps a positive projection of the second gate G2 on the substrate 110.

[0082] Specifically, the first switching transistor T1 and the driving transistor Tdr can be formed synchronously by the same process. At this time, the same film layer structures of the first switching transistor T1 and the driving transistor Tdr share the same film layer for formation. During the manufacturing process of the array substrate, the gate layer 120 can be first formed on the substrate 110, and then the gate layer 120 is patterned to synchronously form the first gate G1 of the first switching transistor T1 and the second gate G2 of the driving transistor Tdr. When the gate insulating layer 130 is disposed on a side of the gate layer 120 away from the substrate 110, after the first gate G1 of the first switching transistor T1 and the second gate G2 of the driving transistor Tdr are formed, the gate insulating layer 130 can be formed on a side of the gate layer 120 away from the substrate 110. A part opposite to the first gate G1 is the first gate insulating layer 131 of the first switching transistor T1, and a part opposite to the second gate G2 is the second gate insulating layer 132 of the driving transistor Tdr. Then, the semiconductor layer 140 is formed and the semiconductor layer 140 is patterned to form the first active region 141 and the second active region 142. At this time, the first switching transistor T1 and the driving transistor Tdr are bottom-gate transistors. When the gate insulating layer 130 is disposed on a side of the gate layer 120 close to the substrate 110, the semiconductor layer 140 can be first formed for forming the first active region 141 and the second active region 142, then the gate insulating layer 130 is formed on a side of the semiconductor layer 140 away from the substrate 110, and then the gate layer 120 is formed and the gate layer 120 is patterned to form the first gate G1 and the second gate G2. At this time, the first switching transistor T1 and the driving transistor Tdr are top-gate transistors. The first active region 141 is the active layer of the first switching transistor T1 for forming the source-drain regions and the channel region of the first switching transistor T1. The second active region 142 is the active layer of the driving transistor Tdr for forming the source-drain regions and the channel region of the driving transistor Tdr.

[0083] The thickness of the second gate insulating layer 132 is greater than that of the first gate insulating layer 131. The distance between the second gate G2 of the driving transistor Tdr and the second active region 142 is greater than the distance between the first gate G1 of the first switching transistor T1 and the first active region 141. This can make the subthreshold of the driving transistor Tdr greater than that of the first switching transistor T1, and further make the threshold voltage of the driving transistor Tdr greater than that of the first switching transistor T1. At this time, the driving ability of the driving transistor Tdr is greater than that of the first switching transistor T1, ensuring that the driving transistor Tdr can achieve gray-scale expansion and improving the adaptability of the electrical range of the driving transistor Tdr to the pixel circuit 10. At the same time, the switching speed of the first switching transistor T1 is ensured, and the adaptability of the electrical range of the first switching transistor T1 to the pixel circuit 10 is ensured, enabling the pixel circuit 10 to take into account both the switching speed of the first switching transistor T1 and the driving ability of the driving transistor Tdr, thereby improving the display effect of the display panel.

[0084] In some embodiments, the ratio range of the thickness of the second gate insulating layer 132 to the thickness of the first gate insulating layer 131 is 1.5 - 2. For example, the ratio of the thickness of the second gate insulating layer 132 to the thickness of the first gate insulating layer 131 can be 1.6, 1.7, 1.8, 1.9.

[0085] Specifically, by setting the ratio of the thickness of the second gate insulating layer 132 to the thickness of the first gate insulating layer 131 to be greater than or equal to 1.5 and less than or equal to 2, the difference range between the subthreshold of the driving transistor Tdr and the subthreshold of the first switching transistor T1 can be made greater than or equal to 0.1V / decade. Thus, the difference range between the threshold voltage of the driving transistor Tdr and the threshold voltage of the first switching transistor T1 can be 0.3V - 2V, enabling the pixel circuit 10 to adapt to the electrical ranges of both the driving transistor Tdr and the first switching transistor T1 simultaneously, and improving the display effect of the display panel. Exemplarily, by setting the ratio of the thickness of the second gate insulating layer 132 to the thickness of the first gate insulating layer 131, the difference range between the subthreshold of the driving transistor Tdr and the subthreshold of the first switching transistor T1 can be made greater than or equal to 0.2V / decade, and the difference range between the threshold voltage of the driving transistor Tdr and the threshold voltage of the first switching transistor T1 is preferably 0.3V - 0.5V, which can enable the pixel circuit 10 to better adapt to the electrical ranges of both the driving transistor Tdr and the first switching transistor T1 simultaneously, and improve the display effect of the display panel.

[0086] Figure 4 This is a schematic cross-sectional structure diagram of another array substrate provided by an embodiment of the present invention. As Figure 4As shown, the gate layer 120 includes a top gate layer 121 and a bottom gate layer 122, and the gate insulating layer 130 includes a top gate insulating layer GI1 and a bottom gate insulating layer GI2; the bottom gate layer 122 is disposed on one side of the substrate 110, the bottom gate insulating layer GI2 is disposed on the side of the bottom gate layer 122 away from the substrate 110, the semiconductor layer 140 is disposed on the side of the bottom gate insulating layer GI2 away from the substrate 110, the top gate insulating layer GI1 is disposed on the side of the semiconductor layer 140 away from the substrate 110, and the top gate layer 121 is disposed on the side of the top gate insulating layer GI1 away from the substrate 110; the first gate G1 includes a first bottom gate BG1 and a first top gate TG1, and the second gate G2 includes a second bottom gate BG2 and a second top gate TG2; the bottom gate layer 122 includes the first bottom gate BG1 and the second bottom gate BG2, and the top gate layer 121 includes the first top gate TG1 and the second top gate TG2; the first gate insulating layer 131 includes a first top gate insulating layer GI11 and a first bottom gate insulating layer GI21, and the second gate insulating layer 132 includes a second top gate insulating layer GI12 and a second bottom gate insulating layer GI22; the first active region 141 includes a first source region 1411, a first channel region 1412, and a first drain region 1413, and the second active region 142 includes a second source region 1421, a second channel region 1422, and a second drain region 1423; the first bottom gate BG1 is connected to the first source region 1411, and the second top gate TG2 is connected to the second source region 1421; the thickness of the bottom gate insulating layer GI2 is greater than the thickness of the top gate insulating layer GI1.

[0087] Specifically, Figure 4Exemplarily shown in the figure is that the first switching transistor T1 and the driving transistor Tdr can be double-gate transistors. At this time, the first switching transistor T1 and the driving transistor Tdr are four-terminal devices. The first top-gate insulating layer GI11 and the second top-gate insulating layer GI21 are located on the top-gate insulating layer GI1, and the first bottom-gate insulating layer GI21 and the second bottom-gate insulating layer GI22 are located on the bottom-gate insulating layer GI2. The first bottom-gate BG1 is connected to the first source region 1411, that is, the first bottom-gate BG1 of the first switching transistor T1 is connected to the source region. Then, the external terminals of the first switching transistor T1 are the source, the drain, and the first top-gate TG1. At this time, the first top-gate insulating layer GI11 between the first top-gate TG1 and the first channel region 1412 of the first switching transistor T1 is the gate insulating layer of the first switching transistor T1. Then, the thickness of the gate insulating layer of the first switching transistor T1 is the thickness of the top-gate insulating layer GI1. Similarly, the second top-gate TG2 is connected to the second source region 1421, that is, the second top-gate TG2 of the driving transistor Tdr is connected to the source region. Then, the external terminals of the driving transistor Tdr are the source, the drain, and the second bottom-gate BG2. At this time, the second bottom-gate insulating layer GI22 between the second bottom-gate BG2 and the second channel region 1422 of the driving transistor Tdr is the gate insulating layer of the driving transistor Tdr. Then, the thickness of the gate insulating layer of the driving transistor Tdr is the thickness of the bottom-gate insulating layer GI2. By setting the thickness of the bottom-gate insulating layer GI2 to be greater than the thickness of the top-gate insulating layer GI1, the thickness of the gate insulating layer of the driving transistor Tdr can be made greater than the thickness of the gate insulating layer of the first switching transistor T1, so that the sub-threshold of the driving transistor Tdr can be made greater than the sub-threshold of the first switching transistor T1, and further the threshold voltage of the driving transistor Tdr can be made greater than the threshold voltage of the first switching transistor T1. At this time, the driving ability of the driving transistor Tdr is greater than the driving ability of the first switching transistor T1, ensuring that the driving transistor Tdr can achieve gray-scale expansion and improving the adaptability of the electrical range of the driving transistor Tdr to the pixel circuit 10. At the same time, the switching speed of the first switching transistor T1 is ensured, and the adaptability of the electrical range of the first switching transistor T1 to the pixel circuit 10 is ensured, so that the pixel circuit 10 can take into account both the switching speed of the first switching transistor T1 and the driving ability of the driving transistor Tdr, improving the display effect of the display panel.

[0088] It should be noted that the structure of the bottom gate insulating layer GI2 can be a silicon oxide film layer or a stacked structure of a silicon oxide film layer and a silicon nitride film layer. When forming the bottom gate insulating layer GI2, the threshold voltage of the transistor can be further precisely controlled by controlling the film-forming process conditions of the bottom gate insulating layer GI2. Exemplarily, the film-forming process conditions of the bottom gate insulating layer GI2 can include the thickness of the bottom gate insulating layer GI2, the film-forming temperature, and the process parameters during the process. For example, when the process is chemical vapor deposition, the process parameters can include flow rate, power, and spacing, etc. When the process is physical vapor deposition, the process parameters can include the oxygen content. Similarly, when forming the top gate insulating layer GI1, the threshold voltage of the transistor can also be further precisely controlled by controlling the film-forming process conditions of the top gate insulating layer GI1. Exemplarily, the film-forming process conditions of the top gate insulating layer GI1 can include the thickness of the bottom gate insulating layer GI2, the film-forming temperature, and the process parameters during the process. For example, when the process is chemical vapor deposition, the process parameters can include flow rate, power, and spacing, etc. When the manufacturing process of the array substrate includes an annealing process, the conditions of the annealing process include an annealing temperature range of 150 - 450 °C, and the annealing atmosphere can be nitrogen or compressed dry air. When the array substrate includes an interlayer insulating layer 160, the structure of the interlayer insulating layer 160 can be a silicon oxide film layer or a stacked structure of a silicon oxide film layer and a silicon nitride film layer. When forming the interlayer insulating layer 160, the threshold voltage of the transistor can also be further precisely controlled by controlling the film-forming process conditions of the interlayer insulating layer 160. Exemplarily, the film-forming process conditions of the interlayer insulating layer 160 can include the thickness of the interlayer insulating layer 160, the film-forming temperature, and the process parameters during the process. For example, when the process is chemical vapor deposition, the process parameters can include flow rate, power, and spacing, etc.

[0089] Figure 5 FIG. is a schematic cross-sectional structure diagram of another array substrate provided by an embodiment of the present invention. As Figure 5 shown, the first top gate TG1 is connected to the first source region 1411, and the second bottom gate BG2 is connected to the second source region 1421; the thickness of the top gate insulating layer GI1 is greater than the thickness of the bottom gate insulating layer GI2.

[0090] Specifically, Figure 5 and Figure 4The difference lies in that the first top gate TG1 of the first switching transistor T1 is connected to the first source region 1411, that is, the first top gate TG1 of the first switching transistor T1 is connected to the source region. Then, the external terminals of the first switching transistor T1 are the source, the drain, and the first bottom gate BG1. At this time, the first bottom gate insulating layer GI21 between the first bottom gate BG1 and the first channel region 1412 of the first switching transistor T1 is the gate insulating layer of the first switching transistor T1, and the thickness of the gate insulating layer of the first switching transistor T1 is the thickness of the bottom gate insulating layer GI2. Similarly, the second bottom gate BG2 is connected to the second source region 1421, that is, the second bottom gate BG2 of the driving transistor Tdr is connected to the source region. Then, the external terminals of the driving transistor Tdr are the source, the drain, and the second top gate TG2. At this time, the second top gate insulating layer GI12 between the second top gate TG2 and the second channel region 1422 of the driving transistor Tdr is the gate insulating layer of the driving transistor Tdr, and the thickness of the gate insulating layer of the driving transistor Tdr is the thickness of the top gate insulating layer GI1. By setting the thickness of the top gate insulating layer GI1 to be greater than the thickness of the bottom gate insulating layer GI2, it is also possible to make the thickness of the gate insulating layer of the driving transistor Tdr greater than the thickness of the gate insulating layer of the first switching transistor T1. Thus, the sub-threshold of the driving transistor Tdr can be made greater than the sub-threshold of the first switching transistor T1, and further, the threshold voltage of the driving transistor Tdr can be made greater than the threshold voltage of the first switching transistor T1. At this time, the driving ability of the driving transistor Tdr is greater than the driving ability of the first switching transistor T1, ensuring that the driving transistor Tdr can achieve gray-scale expansion and improving the adaptability of the electrical range of the driving transistor Tdr to the pixel circuit 10. At the same time, the switching speed of the first switching transistor T1 is ensured, and the adaptability of the electrical range of the first switching transistor T1 to the pixel circuit 10 is ensured, enabling the pixel circuit 10 to take into account both the switching speed of the first switching transistor T1 and the driving ability of the driving transistor Tdr, and improving the display effect of the display panel.

[0091] Continue to refer to Figure 4 and Figure 5 , the array substrate further includes:

[0092] The source-drain layer 150 is disposed on the side of the top gate layer 121 away from the semiconductor layer 140. The source-drain layer 150 includes a first source 151, a first drain 152, a second source 153, and a second drain 154. The first source 151 is connected to the first source region 1411, the first drain 152 is connected to the first drain region 1413, the second source 153 is connected to the second source region 1421, and the second drain 154 is connected to the second drain region 1423.

[0093] Specifically, the material of the source-drain layer 150 is metal. The first source 151 is connected to the first source region 1411 and serves as the source of the first switching transistor T1. The first drain 152 is connected to the first drain region 1413 and serves as the drain of the first switching transistor T1. The second source 153 is connected to the second source region 1421 and serves as the source of the first switching transistor T1. The second drain 154 is connected to the second drain region 1423 and serves as the drain of the first switching transistor T1.

[0094] Continuing to refer to Figure 4 and Figure 5 , the source-drain layer 150 further includes a first connection structure 155 and a second connection structure 156. The first bottom gate BG1 or the first top gate TG1 is connected to the first source region 1411 through the first connection structure 155, and the second top gate TG2 or the second bottom gate BG2 is connected to the second source region 1421 through the second connection structure 156.

[0095] Specifically, the first connection structure 155 is disposed on the same layer as the first source 151 and the first drain 152, and the first source 151 is connected to the first source region 1411. As Figure 4 shown, when the first bottom gate BG1 is connected to the first source region 1411, the first bottom gate BG1 can be connected to the first source region 1411 through the first connection structure 155. As Figure 5 shown, when the first top gate TG1 is connected to the first source region 1411, the first top gate TG1 can be connected to the first source region 1411 through the first connection structure 155. Thus, the connection reliability between the first bottom gate BG1 or the first top gate TG1 and the first source region 1411 can be ensured. Similarly, the second connection structure 156 is disposed on the same layer as the second source 153 and the second drain 154, and the second source 153 is connected to the second source region 1421. As Figure 4 shown, when the second top gate TG2 is connected to the second source region 1421, the second top gate TG2 can be connected to the second source region 1421 through the second connection structure 156. As Figure 5 shown, when the second bottom gate BG2 is connected to the second source region 1421, the second bottom gate BG2 can be connected to the second source region 1421 through the second connection structure 156. Thus, the connection reliability between the second top gate TG2 or the second bottom gate BG2 and the second source region 1421 can be ensured.

[0096] In addition, a gate lead 157 is further disposed on the source-drain layer 150. The gate lead 157 is connected to the external gate terminal of the transistor and is used to provide a driving signal for the gate of the transistor. Exemplarily, as Figure 4As shown, the external gate terminal of the first switching transistor T1 is the first top gate TG1. At this time, a gate lead 157 is connected to the first top gate TG1 to provide a driving signal for the first top gate TG1 of the first switching transistor T1. The external gate terminal of the driving transistor Tdr is the second bottom gate BG2. At this time, a gate lead 157 is connected to the second bottom gate BG2 to provide a driving signal for the second bottom gate BG2 of the driving transistor Tdr.

[0097] Continue to refer to Figure 4 and Figure 5 , the array substrate further includes:

[0098] An interlayer insulating layer 160 is disposed between the top gate layer 121 and the source-drain layer 150, which can ensure the insulation between the top gate layer 121 and the source-drain layer 150. At the same time, vias are provided on the interlayer insulating layer 160, so that the source and drain on the source-drain layer 150 are respectively connected to the source region and the drain region on the semiconductor layer 140 through different vias.

[0099] In some embodiments, the channel length of the driving transistor Tdr can also be set to be greater than the channel length of the first switching transistor T1, so that the sub-threshold of the driving transistor Tdr is greater than the sub-threshold of the first switching transistor T1, and further the threshold voltage of the driving transistor Tdr is greater than the threshold voltage of the first switching transistor T1. At this time, the driving ability of the driving transistor Tdr is greater than the driving ability of the first switching transistor T1, ensuring that the driving transistor Tdr can achieve gray-scale expansion and improving the adaptability of the electrical range of the driving transistor Tdr to the pixel circuit 10. At the same time, the switching speed of the first switching transistor T1 is ensured, and the electrical range of the first switching transistor T1 is adapted to the pixel circuit 10, so that the pixel circuit 10 can take into account both the switching speed of the first switching transistor T1 and the driving ability of the driving transistor Tdr, improving the display effect of the display panel.

[0100] In some embodiments, the channel length of the driving transistor Tdr is 2-10 times that of the first switching transistor T1. Similarly, the difference range between the sub-threshold of the driving transistor Tdr and that of the first switching transistor T1 can be made greater than or equal to 0.1 V / decade, so that the difference range between the threshold voltage of the driving transistor Tdr and that of the first switching transistor T1 is 0.3 V - 2 V. This enables the pixel circuit 10 to adapt to the electrical ranges of both the driving transistor Tdr and the first switching transistor T1 simultaneously, improving the display effect of the display panel. Exemplarily, by setting the ratio of the channel length of the driving transistor Tdr to that of the first switching transistor T1, the difference range between the sub-threshold of the driving transistor Tdr and that of the first switching transistor T1 can be made greater than or equal to 0.2 V / decade. Preferably, the difference range between the threshold voltage of the driving transistor Tdr and that of the first switching transistor T1 is 0.3 V - 0.5 V, which allows the pixel circuit 10 to better adapt to the electrical ranges of both the driving transistor Tdr and the first switching transistor T1 simultaneously, improving the display effect of the display panel.

[0101] Figure 6 FIG. is a schematic cross-sectional structure diagram of another array substrate provided by an embodiment of the present invention. As Figure 6 shown, the array substrate further includes:

[0102] a substrate 110;

[0103] a gate layer 120 disposed on one side of the substrate 110. The gate layer 120 includes a first gate G1 of the first switching transistor T1 and a second gate G2 of the driving transistor Tdr;

[0104] a gate insulating layer 130 disposed on one side of the gate layer 120. The gate insulating layer 130 includes a first gate insulating layer 131 and a second gate insulating layer 132. The orthographic projection of the first gate G1 on the substrate 110 is located within the orthographic projection of the first gate insulating layer 131 on the substrate 110, and the orthographic projection of the second gate G2 on the substrate 110 is located within the orthographic projection of the second gate insulating layer 132 on the substrate 110;

[0105] The semiconductor layer 140 is disposed on a side of the gate insulating layer 130 away from the gate layer 120. The semiconductor layer 140 includes a first active region 141 and a second active region 142. A positive projection of the first active region 141 on the substrate 110 overlaps with a positive projection of the first gate G1 on the substrate 110. A positive projection of the second active region 142 on the substrate 110 overlaps with a positive projection of the second gate G2 on the substrate 110. The first active region 141 includes a first source region 1411, a first channel region 1412, and a first drain region 1413. The second active region 142 includes a second source region 1421, a second channel region 1422, and a second drain region 1423. The length of the second channel region 1422 is greater than the length of the first channel region 1412.

[0106] Specifically, as Figure 6 shown, the first source region 1411, the first channel region 1412, and the first drain region 1413 are arranged in sequence. The length of the first channel region 1412 is the arrangement direction of the first source region 1411, the first channel region 1412, and the first drain region 1413. The second source region 1421, the second channel region 1422, and the second drain region 1423 are arranged in sequence. The length of the second channel region 1422 is the arrangement direction of the second source region 1421, the second channel region 1422, and the second drain region 1423. By setting the length of the second channel region 1422 to be greater than the length of the first channel region 1412, the threshold voltage of the driving transistor Tdr can be made greater than the threshold voltage of the first switching transistor T1. At this time, the driving ability of the driving transistor Tdr is greater than that of the first switching transistor T1, ensuring that the driving transistor Tdr can achieve gray-scale expansion and improving the adaptability of the electrical range of the driving transistor Tdr to the pixel circuit 10. At the same time, the switching speed of the first switching transistor T1 is ensured, and the adaptability of the electrical range of the first switching transistor T1 to the pixel circuit 10 is ensured, enabling the pixel circuit 10 to take into account both the switching speed of the first switching transistor T1 and the driving ability of the driving transistor Tdr, and improving the display effect of the display panel.

[0107] Continue to refer to Figure 6, the gate layer 120 includes a top gate layer 121 and a bottom gate layer 122, and the gate insulating layer 130 includes a top gate insulating layer GI1 and a bottom gate insulating layer GI2; the bottom gate layer 122 is disposed on one side of the substrate 110, the bottom gate insulating layer GI2 is disposed on the side of the bottom gate layer 122 away from the substrate 110, the semiconductor layer 140 is disposed on the side of the bottom gate insulating layer GI2 away from the substrate 110, the top gate insulating layer GI1 is disposed on the side of the semiconductor layer 140 away from the substrate 110, and the top gate layer 121 is disposed on the side of the top gate insulating layer GI1 away from the substrate 110; the first gate G1 includes a first bottom gate BG1 and a first top gate TG1, and the second gate G2 includes a second bottom gate BG2 and a second top gate TG2; the bottom gate layer 122 includes the first bottom gate BG1 and the second bottom gate BG2, and the top gate layer 121 includes the first top gate TG1 and the second top gate TG2; the first gate insulating layer 131 includes a first top gate insulating layer GI11 and a first bottom gate insulating layer GI21, and the second gate insulating layer 132 includes a second top gate insulating layer GI12 and a second bottom gate insulating layer GI22; the first bottom gate BG1 is connected to the first source region 1411, and the second bottom gate BG2 is connected to the second source region 1421.

[0108] Specifically, Figure 6 it is exemplarily shown in that the first bottom gate BG1 of the first switching transistor T1 is connected to the first source region 1411, and the external terminals of the first switching transistor T1 are the source, the drain, and the first top gate TG1. At this time, the gate insulating layer of the first switching transistor T1 is the first top gate insulating line GI11 between the first top gate TG1 and the first channel region 1412, which is the gate insulating layer of the first switching transistor T1, and the thickness of the gate insulating layer of the first switching transistor T1 is the thickness of the top gate insulating layer GI1. The second bottom gate BG2 is connected to the second source region 1421, and the external terminals of the driving transistor Tdr are the source, the drain, and the second top gate TG2. Then the gate insulating layer of the driving transistor Tdr is the second top gate insulating layer GI12 between the second top gate TG2 and the second channel region 1422, which is the gate insulating layer of the driving transistor Tdr, and the thickness of the gate insulating layer of the driving transistor Tdr is the thickness of the top gate insulating layer GI1. At this time, the thickness of the gate insulating layer of the first switching transistor T1 is the same as the thickness of the gate insulating layer of the driving transistor Tdr, and the first switching transistor T1 and the driving transistor Tdr change the threshold voltage difference between the two by the difference in the channel length.

[0109] Figure 7 It is a schematic cross-sectional structure diagram of another array substrate provided by an embodiment of the present invention. As Figure 7 shown, the first top gate TG1 is connected to the first source region 1411, and the second top gate TG2 is connected to the second source region 1421.

[0110] Specifically, Figure 7 And Figure 6The difference is that the first top gate TG1 is connected to the first source region 1411, and the second top gate TG2 is connected to the second source region 1421. At this time, the gate insulating layers of the first switching transistor T1 and the driving transistor Tdr are both bottom gate insulating layers GI2. The thickness of the gate insulating layer of the first switching transistor T1 is the same as that of the gate insulating layer of the driving transistor Tdr. The first switching transistor T1 and the driving transistor Tdr change the difference in their threshold voltages through the difference in channel lengths.

[0111] Continue to refer to Figure 6 and Figure 7 , the thickness of the bottom gate insulating layer GI2 is equal to the thickness of the top gate insulating layer GI1.

[0112] Specifically, when the channel length of the driving transistor Tdr is greater than the channel length of the first switching transistor T1, such that the threshold voltage of the driving transistor Tdr is greater than the threshold voltage of the first switching transistor T1, the thickness of the bottom gate insulating layer GI2 can be equal to the thickness of the top gate insulating layer GI1, without affecting the difference in the threshold voltages of the driving transistor Tdr and the first switching transistor T1.

[0113] It should be noted that in some embodiments, the thickness of the bottom gate insulating layer GI2 can also be set to be unequal to the thickness of the top gate insulating layer GI1, which is not limited here.

[0114] In some embodiments, when the channel length of the driving transistor Tdr is greater than the channel length of the first switching transistor T1, the gate insulating layers of the first switching transistor T1 and the driving transistor Tdr can also be set to be different gate insulating layers, that is, one is the top gate insulating layer GI1 and the other is the bottom gate insulating wire GI2. At this time, the thickness of the bottom gate insulating layer GI2 can also be set to be equal to the thickness of the top gate insulating layer GI1, which can ensure that the thickness of the gate insulating layer of the first switching transistor T1 is equal to the thickness of the gate insulating layer of the driving transistor Tdr, without affecting the difference in the threshold voltages of the driving transistor Tdr and the first switching transistor T1.

[0115] In some embodiments, the thickness of the gate insulating layer of the driving transistor Tdr can also be set to be greater than the thickness of the gate insulating layer of the first switching transistor T1, and at the same time, the channel length of the driving transistor Tdr is greater than the channel length of the first switching transistor T1. Thus, the difference in the threshold voltages of the driving transistor Tdr and the first switching transistor T1 can be adjusted simultaneously through the thickness of the gate insulating layer and the channel length, increasing the flexibility of adjusting the value of the difference in the threshold voltages of the driving transistor Tdr and the first switching transistor T1.

[0116] Based on the above technical solutions, the first switching transistor is an N-type transistor, and the driving transistor is an N-type transistor, so that the pixel circuit 10 is composed of all N-type transistors, which can reduce the manufacturing cost of the display panel. At the same time, it can make the display panel have good large-area uniformity, which is beneficial to the manufacture of medium-sized and large-sized display panels. At the same time, the threshold voltage of the driving transistor Tdr is greater than the threshold voltage of the first switching transistor T1, which can make the electrical characteristics of both the driving transistor Tdr and the first switching transistor T1 adapt to the pixel circuit 10, improving the yield and display effect of the display panel.

[0117] Figure 8 FIG. 4 is a top view structural schematic diagram of another array substrate provided by an embodiment of the present invention. Figure 9 FIG. 5 is a structural schematic diagram of a gate driving circuit provided by an embodiment of the present invention. Figure 10 FIG. 6 is a cross-sectional structural schematic diagram of another array substrate provided by an embodiment of the present invention. As Figures 8 to 10 shown, the array substrate further includes a gate driving circuit 20. The gate driving circuit 20 includes a second switching transistor T2 and an output transistor TOUT. The second switching transistor T2 is connected to the output transistor TOUT, and the output transistor TOUT is connected to the first switching transistor T1. The second switching transistor T2 is used to control the gate driving signal of the output transistor TOUT, and the gate driving signal is used to control the on state of the first switching transistor T1; the output transistor TOUT includes a third top gate TG3 and a third bottom gate BG3; the third top gate TG3 is connected to the second switching transistor T2, and the third bottom gate BG3 is used to input a first voltage; wherein, the first voltage is adjustable.

[0118] Specifically, the array substrate further includes a non-display area NAA, and the gate driving circuit 20 is disposed in the non-display area NAA. The gate driving circuit 20 may include a cascaded light-emitting control circuit and a cascaded scanning circuit. Referring to Figure 2 , each stage of the light-emitting control circuit is connected to the light-emitting control transistor M5 in a row of pixel circuits 10, and is used to provide a light-emitting control signal for a row of light-emitting control transistors M5, so that the light-emitting control transistor M5 is turned on during the light-emitting stage. The previous-stage scanning circuit is connected to the first initialization transistor M1 and the threshold compensation transistor M4 in the current row of pixel circuits 10, and is used to control the first initialization transistor M1 and the threshold compensation transistor M4 to be turned on in the first stage to realize the compensation of the threshold voltage. The current-stage scanning circuit is connected to the data writing transistor M3 in the current row of pixel circuits 10, and is used to control the data writing transistor M3 to be turned on in the second stage to realize data writing. The next-stage scanning circuit is connected to the second initialization transistor M2 in the current row of pixel circuits 10, and is used to control the second initialization transistor M2 to be turned on in the fourth stage to realize the anode initialization of the light-emitting device D1.

[0119] During the operation of the gate driving circuit 20, the second switching transistor T2 serves as a switching transistor and is connected to the third top gate TG3 of the output transistor TOUT, and can control the gate driving signal of the third top gate TG3 of the output transistor TOUT to control the on-state of the output transistor TOUT. Exemplarily, Figure 9 Exemplarily, it is shown that the scanning circuit in the gate driving circuit 20 includes six second switching transistors T2, two output transistors TOUT, and two capacitors. The six second switching transistors T2 are respectively the first transistor M11, the second transistor M12, the third transistor M13, the fourth transistor M14, the fifth transistor M15, and the sixth transistor M16. The two output transistors TOUT are respectively the first output transistor TOUT1 and the second output transistor TOUT2. The two capacitors are respectively the first storage capacitor C11 and the second storage capacitor C12. During the operation of the gate driving circuit 20, the conduction or cutoff of the six second switching transistors T2 is controlled by the first clock signal SCK1, the second clock signal SCK2, the start signal SIN, the first power signal VGH, and the second power signal VGL, so that the two output transistors TOUT can be conducted respectively to output the second clock signal SCK2 or the second power signal VGL. At this time, the third top gate TG3 of the first output transistor TOU1 can be connected to the second pole of the second transistor M12. The first pole of the second transistor M12 is used to access the first power signal VGH. The gate of the second transistor M12 and the gate of the first transistor M11 are connected to the first clock signal SCK1. The first pole of the first transistor M11 is used to access the start signal SIN. The second pole of the first transistor M11 is connected to the third top gate TG3 of the second output transistor TOUT2 through the sixth transistor M16.

[0120] The third bottom gate BG3 of the output transistor TOUT is used to input a first voltage. The first voltage is adjustable so that the potential of the third bottom gate BG3 of the output transistor TOUT can be independently adjusted. Thus, the potential of the third bottom gate BG3 of the output transistor TOUT can be adjusted by the first voltage, so that the potential of the third bottom gate BG3 is less than 0, thereby controlling the threshold voltage of the output transistor TOUT to be greater than 0, and avoiding the abnormal situation of the gate driving signal output by the gate driving circuit 20 caused by the negative bias of the threshold voltage of the output transistor TOUT. At the same time, on the basis of ensuring the performance of the output transistor TOUT, the process fluctuation range of the output transistor TOUT can be increased, which is beneficial to reducing the manufacturing difficulty and cost of the array substrate. Exemplarily, the first voltage can be input to the third bottom gate BG3 of the first output transistor TOUT1, and / or the first voltage can be input to the third bottom gate BG3 of the second output transistor TOUT2.

[0121] Exemplarily, Figure 11Schematic diagram of the correlation between the threshold voltage of an output transistor and the performance of a gate driving circuit provided by an embodiment of the present invention. Here, the abscissa is the display panel number, and the ordinate is the threshold voltage of the output transistor TOUT. The solid circles are used to represent that the gate driving circuit performance of the display panel is normal, and the dashed circles are used to represent that the gate driving circuit performance of the display panel is abnormal. As Figure 11 shown, when the threshold voltage of the output transistor TOUT is greater than -1V, the discreteness of the output transistor TOUT can be ensured, thereby ensuring the output reliability of the gate driving circuit.

[0122] Continue to refer to Figure 10 , the bottom gate layer 122 of the array substrate includes a third bottom gate BG3; the bottom gate insulating layer GI2 includes a third bottom gate insulating layer GI23, and the third bottom gate insulating layer GI23 covers the third bottom gate BG3; the semiconductor layer 140 includes a third active region 143, and the third active region 143 covers the third bottom gate insulating layer GI23; the top gate insulating layer GI1 includes a third top gate insulating layer GI13, and the third top gate insulating layer GI13 covers the third active region 143; the top gate layer 121 includes a third top gate TG3, and the orthographic projection of the third top gate TG3 on the substrate 110 overlaps with the orthographic projection of the third top gate insulating layer GI13 on the substrate 110.

[0123] Specifically, Figure 10 exemplarily shows that the output transistor TOUT is a double-gate transistor, that is, the output transistor TOUT is a four-terminal device. At this time, the output transistor TOUT can be formed in the same process as the first switching transistor T1 and the driving transistor Tdr in the pixel circuit 10, that is, the output transistor TOUT shares the same film layer with the first switching transistor T1 to form the same film layer structure. By setting the output transistor TOUT as a four-terminal device, independent adjustment of the third bottom gate BG3 can be achieved, so that the threshold voltage of the output transistor TOUT can be adjusted to be greater than 0, avoiding the abnormal situation of the gate driving signal output by the gate driving circuit 20 caused by the negative bias of the threshold voltage of the output transistor TOUT.

[0124] Continue to refer to Figure 10 , the second switching transistor T2 includes a fourth top gate TG4 and a fourth bottom gate BG4. The fourth top gate TG4 is located in the top gate layer 121, the fourth bottom gate BG4 is located in the bottom gate layer 122, and the potentials of the fourth top gate TG4 and the fourth bottom gate BG4 are equal.

[0125] Specifically, Figure 10Exemplarily, the second switching transistor T2 is shown as a double-gate transistor, that is, the second switching transistor T2 is a four-terminal device, such that the structures of the transistors in the pixel circuit 10 and the transistors in the gate driving circuit 20 in the array substrate are the same, which can simplify the manufacturing process of the array substrate. At this time, the second switching transistor T2 can also be formed in the same process as other transistors, such that the same film layer structures of different transistors in the array substrate share the same film layer for formation. When the second switching transistor T2 includes a fourth top gate TG4 and a fourth bottom gate BG4, the potential of the fourth top gate TG4 is equal to the potential of the fourth bottom gate BG4, such that the fourth top gate TG4 and the fourth bottom gate BG4 simultaneously form a current with the active region of the second switching transistor T2, which can increase the current of the second switching transistor T2, such that the current of the second switching transistor T2 is greater than the current of the first switching transistor T1, thereby increasing the driving ability of the second switching transistor T2, improving the output ability of the gate driving circuit 20, being beneficial to improving the display uniformity of the display panel, and improving the display effect of the display panel.

[0126] Continuing to refer to Figure 10 , connecting the fourth top gate TG4 and the fourth bottom gate BG4 can make the potential of the fourth top gate TG4 equal to the potential of the fourth bottom gate BG4, increasing the current of the second switching transistor T2. Exemplarily, when the thickness of the top gate insulating layer GI1 is 150 nm and the thickness of the bottom gate insulating layer GI2 is 300 nm, the current of the second switching transistor T2 is more than 1.5 times greater than the current of the first switching transistor T1, improving the driving ability of the second switching transistor T2, and further improving the output ability of the gate driving current 20.

[0127] In some embodiments, Figure 12 is a schematic diagram showing the correlation between the threshold voltage of a second switching transistor and the performance of a gate driving circuit provided by an embodiment of the present invention. Among them, the abscissa is the number of the display panel, and the ordinate is the threshold voltage of the second switching transistor T2. The solid circles are used to represent that the performance of the gate driving circuit of the display panel is normal, and the dashed circles are used to represent that the performance of the gate driving circuit of the display panel is abnormal. As Figure 12 shown, when the threshold voltage of the second switching transistor T2 is greater than 0.25 V, it can ensure that the turn-off voltage Voff of the second switching transistor T2 is greater than 0, ensuring the normal performance of the gate driving circuit.

[0128] Continuing to refer to Figure 10, the bottom gate insulating layer GI2 includes a fourth bottom gate insulating layer GI24, and the fourth bottom gate insulating layer GI24 covers the fourth bottom gate BG4; the semiconductor layer 140 includes a fourth active region 144, and the fourth active region 144 covers the fourth bottom gate insulating layer GI24; the top gate insulating layer GI1 includes a fourth top gate insulating layer GI14, and the fourth top gate insulating layer GI14 covers the fourth active region 144; the orthographic projection of the fourth top gate TG4 on the substrate 110 overlaps with the orthographic projection of the fourth top gate insulating layer GI14 on the substrate 110; the third active region 143 includes a third source region 1431, a third channel region 1432, and a third drain region 1433; the fourth active region 144 includes a fourth source region 1441, a fourth channel region 1442, and a fourth drain region 1443; the source-drain layer 150 includes a third source 158, a third drain 159, a fourth source 1510, and a fourth drain 1511; the third source 158 is connected to the third source region 1431, the third drain 159 is connected to the third drain region 1433, the fourth source 1510 is connected to the fourth source region 1441, and the fourth drain 1511 is connected to the fourth drain region 1443.

[0129] Specifically, the fourth bottom gate BG4 of the second switching transistor T2 is located in the bottom gate layer 122, the fourth top gate TG4 is located in the top gate layer 121, the fourth bottom gate insulating layer GI24 is located in the bottom gate insulating line GI2, the fourth top gate insulating layer GI14 is located in the top gate insulating layer GI1, the fourth active region 144 is located in the semiconductor layer 140, and the fourth source 1510 and the fourth drain 1511 are located in the source-drain layer 150, such that each film layer of the second switching transistor T2 is located in the same film layer as the same film layer structure of other transistors, which can simplify the structure and manufacturing process flow of the array substrate. The third source region 1431, the third channel region 1432, and the third drain region 1433 are arranged and distributed in sequence. The fourth source region 1441, the fourth channel region 1442, and the fourth drain region 1443 are arranged and distributed in sequence. The third source 158 is connected to the third source region 1431 and serves as the source of the output transistor TOUT. The third drain 159 is connected to the third drain region 1433 and serves as the drain of the output transistor TOUT. The fourth source 1510 is connected to the fourth source region 1441 and serves as the source of the second switching transistor T2. The fourth drain 1511 is connected to the fourth drain region 1443 and serves as the drain of the second switching transistor T2.

[0130] In some embodiments, the source-drain layer further includes a third connection structure, and the fourth top gate is connected to the fourth bottom gate through the third connection structure.

[0131] Specifically, the third connection structure is located in the source-drain layer and can extend to the fourth top gate and the fourth bottom gate through vias, such that the fourth top gate can be connected to the fourth bottom gate through the third connection structure, ensuring the connection reliability between the fourth top gate and the fourth bottom gate.

[0132] An embodiment of the present invention further provides an array substrate. The array substrate includes a gate driving circuit; the gate driving circuit includes a second switching transistor and an output transistor, the second switching transistor is connected to the output transistor, and the output transistor is used to output a gate driving signal; the output transistor includes a third top gate and a third bottom gate; the third top gate is connected to the second switching transistor, and the third bottom gate is used to input a first voltage; wherein, the first voltage is adjustable.

[0133] Specifically, the third top gate is connected to the second switching transistor, so that the second switching transistor can control the conduction state of the output transistor by controlling the potential of the third top gate, thereby enabling the output transistor to output a gate driving signal. The third bottom gate is used to input a first voltage, and the first voltage is adjustable, so that the potential of the third bottom gate of the output transistor can be independently adjusted. Thus, the potential of the third bottom gate can be adjusted by the first voltage, making the potential of the third bottom gate less than 0, thereby controlling the threshold voltage of the output transistor to be greater than 0, and avoiding the abnormal situation of the gate driving signal output by the gate driving circuit caused by the negative bias of the threshold voltage of the output transistor. At the same time, the process fluctuation range of the output transistor can be increased on the basis of ensuring the performance of the output transistor, which is beneficial to reducing the manufacturing difficulty and cost of the array substrate.

[0134] In some embodiments, the array substrate further includes:

[0135] A substrate;

[0136] A bottom gate layer, disposed on one side of the substrate, and the bottom gate layer includes the third bottom gate;

[0137] A bottom gate insulating layer, disposed on the side of the bottom gate layer away from the substrate, and the bottom gate insulating layer includes a third bottom gate insulating layer that covers the third bottom gate;

[0138] A semiconductor layer, disposed on the side of the bottom gate insulating layer away from the substrate, and the semiconductor layer includes a third active region that covers the third bottom gate insulating layer;

[0139] A top gate insulating layer, disposed on the side of the semiconductor layer away from the substrate; the top gate insulating layer includes a third top gate insulating layer that covers the third active region;

[0140] A top gate layer, disposed on the side of the top gate insulating layer away from the substrate, and the top gate layer includes a third top gate, and the orthographic projection of the third top gate on the substrate overlaps with the orthographic projection of the third top gate insulating layer on the substrate.

[0141] In some embodiments, the second switching transistor includes a fourth top gate and a fourth bottom gate, the fourth top gate is located in the top gate layer, the fourth bottom gate is located in the bottom gate layer, and the potentials of the fourth top gate and the fourth bottom gate are equal.

[0142] In some embodiments, the fourth top gate and the fourth bottom gate are connected.

[0143] In some embodiments, the bottom gate insulating layer includes a fourth bottom gate insulating layer that covers the fourth bottom gate; the semiconductor layer includes a fourth active region that covers the fourth bottom gate insulating layer; the top gate insulating layer includes a fourth top gate insulating layer that covers the fourth active region; the orthographic projection of the fourth top gate on the substrate overlaps with the orthographic projection of the fourth top gate insulating layer on the substrate; the third active region includes a third source region, a third channel region, and a third drain region; the fourth active region includes a fourth source region, a fourth channel region, and a fourth drain region;

[0144] The array substrate further includes:

[0145] A source-drain layer disposed on a side of the top gate layer away from the semiconductor layer, the source-drain layer including a third source, a third drain, a fourth source, and a fourth drain; the third source is connected to the third source region, the third drain is connected to the third drain region, the fourth source is connected to the fourth source region, and the fourth drain is connected to the fourth drain region;

[0146] In some embodiments, the source-drain layer further includes a third connection structure, and the fourth top gate is connected to the fourth bottom gate through the third connection structure.

[0147] An embodiment of the present invention further provides a display panel. Figure 13 A schematic structural diagram of a display panel provided by an embodiment of the present invention is shown as Figure 13 shown. The display panel 100 includes the array substrate 101 provided by any embodiment of the present invention. Since the display panel 100 includes the array substrate 101 provided by any embodiment of the present invention, it has the same beneficial effects as the array substrate 101 provided by any embodiment of the present invention, which will not be elaborated here. The display panel 100 can be, for example, any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a smart wearable device, an information inquiry machine in a public place hall, etc.

[0148] Note that the above are only the preferred embodiments of the present invention and the technical principles applied. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described here, and various obvious changes, re-adjustments, and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, it can further include more other equivalent embodiments, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. An array substrate, characterized in that, It includes a pixel circuit, and the pixel circuit includes a first switching transistor and a driving transistor; the first switching transistor is connected to the driving transistor, and the first switching transistor is used to control the gate potential and the first pole potential of the driving transistor, and the driving transistor is used to form a driving current according to the gate potential and the first pole potential; The threshold voltage of the driving transistor is greater than the threshold voltage of the first switching transistor.

2. The array substrate according to claim 1, wherein It further includes: A substrate; A gate layer, disposed on one side of the substrate, and the gate layer includes a first gate of the first switching transistor and a second gate of the driving transistor; A gate insulating layer, disposed on one side of the gate layer, and the gate insulating layer includes a first gate insulating layer and a second gate insulating layer. The orthographic projection of the first gate on the substrate is located within the orthographic projection of the first gate insulating layer on the substrate, and the orthographic projection of the second gate on the substrate is located within the orthographic projection of the second gate insulating layer on the substrate; the thickness of the second gate insulating layer is greater than the thickness of the first gate insulating layer; A semiconductor layer, disposed on the side of the gate insulating layer away from the gate layer, and the semiconductor layer includes a first active region and a second active region. The orthographic projection of the first active region on the substrate overlaps with the orthographic projection of the first gate on the substrate, and the orthographic projection of the second active region on the substrate overlaps with the orthographic projection of the second gate on the substrate; Preferably, the ratio range of the thickness of the second gate insulating layer to the thickness of the first gate insulating layer is 1.5 - 2.

3. The array substrate according to claim 2, wherein The gate layer includes a top gate layer and a bottom gate layer, and the gate insulating layer includes a top gate insulating layer and a bottom gate insulating layer; the bottom gate layer is disposed on one side of the substrate, the bottom gate insulating layer is disposed on the side of the bottom gate layer away from the substrate, the semiconductor layer is disposed on the side of the bottom gate insulating layer away from the substrate, the top gate insulating layer is disposed on the side of the semiconductor layer away from the substrate, and the top gate layer is disposed on the side of the top gate insulating layer away from the substrate; The first gate includes a first bottom gate and a first top gate, and the second gate includes a second bottom gate and a second top gate; the bottom gate layer includes the first bottom gate and the second bottom gate, and the top gate layer includes the first top gate and the second top gate; the first gate insulating layer includes a first top gate insulating layer and a first bottom gate insulating layer, and the second gate insulating layer includes a second top gate insulating layer and a second bottom gate insulating layer; the first active region includes a first source region, a first channel region, and a first drain region, and the second active region includes a second source region, a second channel region, and a second drain region; The first bottom gate is connected to the first source region, and the second top gate is connected to the second source region; the thickness of the bottom gate insulating layer is greater than the thickness of the top gate insulating layer; or, the first top gate is connected to the first source region, and the second bottom gate is connected to the second source region; The thickness of the top gate insulating layer is greater than the thickness of the bottom gate insulating layer; Preferably, the array substrate further includes: A source-drain layer is disposed on a side of the top gate layer away from the semiconductor layer. The source-drain layer includes a first source, a first drain, a second source, and a second drain. The first source is connected to the first source region, the first drain is connected to the first drain region, the second source is connected to the second source region, and the second drain is connected to the second drain region. Preferably, the source-drain layer further includes a first connection structure and a second connection structure. The first bottom gate or the first top gate is connected to the first source region through the first connection structure, and the second top gate or the second bottom gate is connected to the second source region through the second connection structure. Preferably, the array substrate further includes: An interlayer insulating layer disposed between the top gate layer and the source-drain layer.

4. The array substrate according to claim 1, wherein The channel length of the driving transistor is greater than the channel length of the first switching transistor. Preferably, the channel length of the driving transistor is 2-10 times the channel length of the first switching transistor.

5. The array substrate according to claim 4, wherein It further includes: A substrate; A gate layer disposed on one side of the substrate. The gate layer includes a first gate of the first switching transistor and a second gate of the driving transistor. A gate insulating layer disposed on one side of the gate layer. The gate insulating layer includes a first gate insulating layer and a second gate insulating layer. The orthographic projection of the first gate on the substrate is located within the orthographic projection of the first gate insulating layer on the substrate, and the orthographic projection of the second gate on the substrate is located within the orthographic projection of the second gate insulating layer on the substrate. A semiconductor layer disposed on a side of the gate insulating layer away from the gate layer. The semiconductor layer includes a first active region and a second active region. The orthographic projection of the first active region on the substrate overlaps with the orthographic projection of the first gate on the substrate, and the orthographic projection of the second active region on the substrate overlaps with the orthographic projection of the second gate on the substrate. The first active region includes a first source region, a first channel region, and a first drain region. The second active region includes a second source region, a second channel region, and a second drain region. The length of the second channel region is greater than the length of the first channel region. Preferably, the gate layer includes a top gate layer and a bottom gate layer, and the gate insulating layer includes a top gate insulating layer and a bottom gate insulating layer. The bottom gate layer is disposed on one side of the substrate, the bottom gate insulating layer is disposed on a side of the bottom gate layer away from the substrate, the semiconductor layer is disposed on a side of the bottom gate insulating layer away from the substrate, the top gate insulating layer is disposed on a side of the semiconductor layer away from the substrate, and the top gate layer is disposed on a side of the top gate insulating layer away from the substrate. The first gate includes a first bottom gate and a first top gate, and the second gate includes a second bottom gate and a second top gate. The bottom gate layer includes the first bottom gate and the second bottom gate, and the top gate layer includes the first top gate and the second top gate. The first gate insulating layer includes a first top gate insulating layer and a first bottom gate insulating layer, and the second gate insulating layer includes a second top gate insulating layer and a second bottom gate insulating layer. The first bottom gate is connected to the first source region, and the second bottom gate is connected to the second source region; or, the first top gate is connected to the first source region, and the second top gate is connected to the second source region; Preferably, the thickness of the bottom gate insulating layer is equal to the thickness of the top gate insulating layer.

6. The array substrate according to claim 1, characterized in that The first switching transistor is an N-type transistor, and the driving transistor is an N-type transistor.

7. The array substrate according to any one of claims 1-6, characterized in that, It further includes a gate driving circuit. The gate driving circuit includes a second switching transistor and an output transistor. The second switching transistor is connected to the output transistor, and the output transistor is connected to the first switching transistor. The second switching transistor is used to control the gate driving signal of the output transistor, and the gate driving signal is used to control the on-state of the first switching transistor; the output transistor includes a third top gate and a third bottom gate; the third top gate is connected to the second switching transistor, and the third bottom gate is used to input a first voltage; wherein, the first voltage is adjustable; Preferably, the bottom gate layer of the array substrate includes the third bottom gate; The bottom gate insulating layer of the array substrate includes a third bottom gate insulating layer, and the third bottom gate insulating layer covers the third bottom gate; The semiconductor layer of the array substrate includes a third active region, and the third active region covers the third bottom gate insulating layer; The top gate insulating layer of the array substrate includes a third top gate insulating layer, and the third top gate insulating layer covers the third active region; The top gate layer of the array substrate includes a third top gate, and the orthographic projection of the third top gate on the substrate overlaps with the orthographic projection of the third top gate insulating layer on the substrate; Preferably, the second switching transistor includes a fourth top gate and a fourth bottom gate. The fourth top gate is located in the top gate layer, the fourth bottom gate is located in the bottom gate layer, and the potential of the fourth top gate is equal to the potential of the fourth bottom gate; Preferably, the fourth top gate and the fourth bottom gate are connected; Preferably, the bottom gate insulating layer includes a fourth bottom gate insulating layer, and the fourth bottom gate insulating layer covers the fourth bottom gate; the semiconductor layer includes a fourth active region, and the fourth active region covers the fourth bottom gate insulating layer; the top gate insulating layer includes a fourth top gate insulating layer, and the fourth top gate insulating layer covers the fourth active region; the orthographic projection of the fourth top gate on the substrate overlaps with the orthographic projection of the fourth top gate insulating layer on the substrate; the third active region includes a third source region, a third channel region, and a third drain region; the fourth active region includes a fourth source region, a fourth channel region, and a fourth drain region; The source-drain layer of the array substrate includes a third source, a third drain, a fourth source, and a fourth drain; the third source is connected to the third source region, the third drain is connected to the third drain region, the fourth source is connected to the fourth source region, and the fourth drain is connected to the fourth drain region; Preferably, the source-drain layer further includes a third connection structure, and the fourth top gate is connected to the fourth bottom gate through the third connection structure.

8. An array substrate, characterized in that, It includes a gate driving circuit; the gate driving circuit includes a second switching transistor and an output transistor, the second switching transistor is connected to the output transistor, and the output transistor is used to output a gate driving signal; the output transistor includes a third top gate and a third bottom gate; the third top gate is connected to the second switching transistor, and the third bottom gate is used to input a first voltage; wherein, the first voltage is adjustable.

9. The array substrate according to claim 8, wherein It further includes: a substrate; a bottom gate layer disposed on one side of the substrate, and the bottom gate layer includes the third bottom gate; a bottom gate insulating layer disposed on the side of the bottom gate layer away from the substrate, the bottom gate insulating layer includes a third bottom gate insulating layer, and the third bottom gate insulating layer covers the third bottom gate; a semiconductor layer disposed on the side of the bottom gate insulating layer away from the substrate, the semiconductor layer includes a third active region, and the third active region covers the third bottom gate insulating layer; a top gate insulating layer disposed on the side of the semiconductor layer away from the substrate; the top gate insulating layer includes a third top gate insulating layer, and the third top gate insulating layer covers the third active region; a top gate layer disposed on the side of the top gate insulating layer away from the substrate, the top gate layer includes a third top gate, and the orthographic projection of the third top gate on the substrate overlaps with the orthographic projection of the third top gate insulating layer on the substrate; Preferably, the second switching transistor includes a fourth top gate and a fourth bottom gate, the fourth top gate is located in the top gate layer, the fourth bottom gate is located in the bottom gate layer, and the potential of the fourth top gate is equal to the potential of the fourth bottom gate; Preferably, the fourth top gate and the fourth bottom gate are connected; Preferably, the bottom gate insulating layer includes a fourth bottom gate insulating layer, and the fourth bottom gate insulating layer covers the fourth bottom gate; the semiconductor layer includes a fourth active region, and the fourth active region covers the fourth bottom gate insulating layer; the top gate insulating layer includes a fourth top gate insulating layer, and the fourth top gate insulating layer covers the fourth active region; the orthographic projection of the fourth top gate on the substrate overlaps with the orthographic projection of the fourth top gate insulating layer on the substrate; the third active region includes a third source region, a third channel region, and a third drain region; The fourth active region includes a fourth source region, a fourth channel region, and a fourth drain region; The array substrate further includes: a source-drain layer disposed on the side of the top gate layer away from the semiconductor layer, and the source-drain layer includes a third source, a third drain, a fourth source, and a fourth drain; the third source is connected to the third source region, the third drain is connected to the third drain region, the fourth source is connected to the fourth source region, and the fourth drain is connected to the fourth drain region; Preferably, the source-drain layer further includes a third connection structure, and the fourth top gate is connected to the fourth bottom gate through the third connection structure.

10. A display panel, characterized in that, It includes the array substrate according to any one of claims 1-9.

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