A wide bandgap ultra-high voltage and high current semiconductor device structure and its manufacturing method

Abstract

The present invention provides a wide-bandgap ultra-high-voltage, high-current semiconductor device structure and a method for fabricating the same. The device structure comprises: a substrate layer, an epitaxial layer; a channel layer disposed on the epitaxial layer and embedded with a P-type semiconductor layer to form a PN junction; an N-type semiconductor layer disposed within the P-type semiconductor layer; a gate dielectric layer grown on the channel layer; a gate electrode deposited on the gate dielectric layer; and an interlayer dielectric layer grown on the channel layer. A groove is formed and filled with a transparent insulating dielectric to form a current gain window. Under the action of light, light passes through the current gain window and reaches the substrate layer, generating a large number of photogenerated carriers due to the illumination, causing the substrate layer to conduct electricity under the action of an electric field. A first electrode and a second electrode are respectively disposed on either side of the stacked structure of the gate dielectric layer and the interlayer dielectric layer. This structure uses an additional light-control unit to achieve the transition of the gallium oxide device's operating state, solving the problem of high on-resistance caused by the lack of P-type doping in gallium oxide devices.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a wide bandgap ultra-high voltage and high current semiconductor device structure and a manufacturing method thereof. Background Art

[0002] In recent years, power devices have been widely used in numerous fields, ranging from fast charging of mobile phones and new energy vehicles to photovoltaic power generation and high-voltage power grid transmission, greatly facilitating people's daily lives. With the continuous advancement of technology, power devices will continue to play a vital role in the future, further improving people's quality of life.

[0003] In power switching applications, the Baliga's Figure of Merit (BFOM) is widely used to measure the suitability of semiconductor materials for power electronics. This metric is calculated as: BFOM = εμE³, where ε represents the dielectric constant, μ represents the mobility, and E represents the breakdown electric field strength of the semiconductor. Research has shown that the BFOM value is roughly positively correlated with the sixth power of the semiconductor material's bandgap (Eg). Therefore, a larger bandgap means lower power loss and higher conversion efficiency, leading to superior performance in power electronics applications. Among wide-bandgap semiconductor materials, Ga2O3 stands out with its 4.8eV bandgap, 8 MV / cm ideal breakdown electric field strength, and a high BFOM value of 3400. Its BFOM value is approximately four times that of GaN and ten times that of SiC. This demonstrates that Ga2O3 materials have significant research value and broad application prospects in power electronics applications, where higher power density and lower power consumption are urgently needed.

[0004] However, despite Ga2O3's excellent performance in n-type doping, there have been no reports of successful p-type doping. This situation severely limits the application of Ga2O3 in bipolar power devices. Specifically, achieving hole conduction in p-type Ga2O3 faces three major challenges: first, it is difficult to find acceptor impurities with low activation energy; second, theoretical calculations show that the valence band maximum dispersion of Ga2O3 is small, resulting in an extremely large effective mass, making the mobility (μ) of free holes extremely low and showing a local distribution characteristic; finally, theoretical predictions for Ga2O3 indicate that due to local lattice distortion, the energy of local self-capture of free holes in the bulk is extremely high, forming small poles, which undoubtedly hinders the conduction of effective holes.

[0005] Based on this, the present invention provides a new wide bandgap ultra-high voltage and high current semiconductor device structure and a manufacturing method thereof. Summary of the Invention

[0006] Based on the above description, the present invention provides a wide bandgap ultra-high voltage and high current semiconductor device structure and device structure, aiming to solve the technical difficulty of difficult to achieve p-type doping in Ga2O3 materials, thereby breaking through its limitations in bipolar power device applications and further expanding the application scope of Ga2O3 in high-performance power electronic devices.

[0007] The technical solution of the present invention to solve the above technical problems is as follows:

[0008] In a first aspect, the present invention provides a wide bandgap ultra-high voltage and high current semiconductor device structure, comprising:

[0009] substrate layer;

[0010] an epitaxial layer, disposed on the substrate layer;

[0011] A channel layer, which is an N-type Ga2O3 layer or a GaN layer, is provided on the epitaxial layer and has a P-type semiconductor layer embedded therein, wherein the P-type semiconductor layer forms a heterojunction with the channel layer;

[0012] An N-type semiconductor layer is wrapped in the P-type semiconductor layer;

[0013] a gate dielectric layer grown on the channel layer and completely covering a gap between the N-type semiconductor layer and the P-type semiconductor layer;

[0014] a gate electrode deposited on the gate dielectric layer;

[0015] an interlayer dielectric layer grown on the channel layer; a groove is formed by etching downward from the upper surface of the interlayer dielectric layer to the upper surface of the substrate layer; the groove is filled with a transparent insulating medium to form a current gain window; under the action of light, light passes through the current gain window to reach the substrate layer, and the substrate layer generates a large number of photogenerated carriers due to the light, and conducts electricity under the action of the electric field;

[0016] The first electrode and the second electrode are respectively arranged on two sides of the stacked structure of the gate dielectric layer and the interlayer dielectric layer.

[0017] On the basis of the above technical solution, the present invention can also be improved as follows.

[0018] Furthermore, the size of the N-type semiconductor layer along the channel direction is smaller than the size range of the P-type semiconductor, and a gap is provided between the two.

[0019] Furthermore, the resistivity of the substrate layer is greater than , thickness is 300-600μm;

[0020] And / or, the epitaxial layer is an unintentionally doped epitaxial layer, and the doping concentration is less than 1016 cm -3 , thickness is 100-300nm;

[0021] And / or, the channel layer is an intentionally doped high-concentration epitaxial layer with a doping concentration of 1.0x10 18 -1.0x10 19 cm -3 , with a thickness of 100-300nm.

[0022] Furthermore, the P-type semiconductor layer is any one of P-GaN, P-NiO, P-Cu2O, P-doped SiC, P-doped Si and P-doped diamond.

[0023] Furthermore, when the P-type semiconductor layer is P-GaN, the doping concentration of P-GaN is 5.0x10 18 -5.0x10 19 cm -3 .

[0024] Furthermore, both the first electrode and the second electrode are ohmic contact electrodes with a thickness of 10-100 nm.

[0025] Furthermore, the first electrode and the second electrode are respectively an emitter electrode and a collector electrode;

[0026] Or, the first electrode and the second electrode are a source electrode and a drain electrode respectively;

[0027] Or, the first electrode and the second electrode are a cathode and an anode respectively;

[0028] Alternatively, the first electrode and the second electrode are an anode and a cathode, respectively.

[0029] Furthermore, the cross-sectional shape of the current gain window is a bar, a square, a circle or a hexagon.

[0030] Furthermore, the substrate layer and the epitaxial layer are respectively one or any combination of Ga2O3, AlN, BN, SiC, GaN, and diamond.

[0031] In a second aspect, the present invention further provides a method for manufacturing the wide bandgap ultrahigh voltage and high current semiconductor device structure as described in the first aspect, comprising the following steps:

[0032] S1: grow an epitaxial layer on the substrate layer, grow an N-type Ga2O3 layer on the epitaxial layer as a channel layer; embed a P-type semiconductor layer on the channel layer to form a heterojunction with the N-type Ga2O3 layer;

[0033] S2: forming an N-type semiconductor layer opposite to the P-type semiconductor layer in the heterojunction on one side;

[0034] S3: growing a gate dielectric layer on the surface and simultaneously opening a hole in the P-type semiconductor region so that the gate dielectric completely covers the gap between the N-type semiconductor layer and the P-type semiconductor layer;

[0035] S4: depositing a layer of Ti on the surface as an ohmic contact electrode and a gate electrode, and annealing;

[0036] S5: growing a layer of insulating dielectric on the surface as an interlayer dielectric layer, and simultaneously opening a hole at the ohmic contact electrode position to expose the electrode;

[0037] S6: depositing Ti / Al stacked metal on the surface as the first electrode and the second electrode of the device;

[0038] S7: selectively etching the interlayer dielectric layer, the gate dielectric layer, the channel layer, and the epitaxial layer on the surface to obtain a groove structure;

[0039] S8: Filling the groove structure with a transparent insulating medium to obtain a current gain window.

[0040] Compared with the prior art, the technical solution of this application has the following beneficial technical effects:

[0041] The wide bandgap ultra-high voltage and high current semiconductor device structure and its manufacturing method provided by the present invention have the following beneficial effects compared with the prior art:

[0042] First, the wide bandgap ultra-high voltage and high current semiconductor device structure manufactured by the present invention adopts a lateral IGBT device structure combined with a current enhancement window.

[0043] When the device is operating in the forward conduction state, the heterojunction on the collector side is turned on and can provide electrons and holes when the forward voltage is high enough. When the gate electrode voltage exceeds the device threshold voltage, electrons can pass through the emitter through the N-type semiconductor and the channel into the channel layer and the epitaxial layer, and finally into the substrate layer. The substrate layer will generate a large number of photogenerated carriers due to illumination and conduct electricity under the action of the electric field. Eventually, electrons will enter the epitaxial layer and the channel layer from the substrate layer, and finally into the collector, realizing large current transmission.

[0044] When the device is operating in the reverse cutoff state, when the gate voltage causes the channel to be turned off and the light is removed, the current cannot be conducted due to the lack of a conduction path. At this time, the voltage across the collector and emitter will be loaded onto the channel layer and the transparent insulating medium layer. Since there is no net charge in the insulating medium, the electric field distribution in the insulating medium is horizontal. When the insulating medium accounts for a large proportion in cells of the same size, the withstand voltage of the device will also increase. The present invention uses carriers generated by light to solve the problem that the semi-insulating substrate cannot conduct electricity. The generated photogenerated carriers can solve the difficulty in manufacturing high-current devices and solve the problem of high on-resistance of traditional lateral devices. On the one hand, the transparent insulating medium allows light to pass through the surface into the semi-insulating substrate, and on the other hand, it can withstand high voltage during reverse blocking, playing a role in high-voltage resistance.

[0045] Second, when the wide bandgap ultra-high voltage and high current semiconductor device is turned on, the gate voltage needs to reach the threshold voltage and be illuminated to generate enough photogenerated carriers. By controlling the time difference between the two being turned on and triggered, the device can operate in a variety of different modes. For example, when the gate bias and the photon generation trigger circuit are turned on at the same time, the device is forward-conducted. When the gate bias or the photon generation trigger circuit is turned off, the device is cut off. When the device is in a reverse bias state, the photon trigger circuit is turned on, which will generate a large number of carriers inside the semi-insulating substrate. The carriers will produce collision ionization under high electric field strength, thereby generating a large current. At this time, the device is in a high electric field and high voltage state, so it will consume a lot of electric power and generate heat. At this time, it is necessary to control the turn-on time of the photon generation circuit to form a pulse switch, and the current in the device forms a pulse current.

[0046] In summary, the present invention adopts a lateral device structure combined with photogenerated carriers to construct a wide bandgap ultra-high voltage and high current device. The invention adopts a lateral device structure to easily etch the channel layer and the epitaxial layer cleanly and adopts a dielectric filling method to realize the production of high-voltage devices. The mechanism of the high-current device is to use the reserved light channel to generate photogenerated carriers to participate in conduction by irradiating light.

[0047] Therefore, the gallium oxide-based ultra-high voltage and high current device structure proposed in the present invention perfectly solves the problems of low withstand voltage of silicon-based devices and short transmission distance of photons in semiconductor materials. The additional light control unit can easily realize the change of the working state of the gallium oxide device, solving the problem of high on-resistance caused by the lack of P-type doping in gallium oxide devices. At the same time, the ultra-wide bandgap characteristics of gallium oxide are utilized to prepare ultra-high voltage and high current devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 A schematic structural diagram of a wide bandgap ultrahigh voltage and high current semiconductor device structure provided in Example 1 of the present invention;

[0049] Figure 2 and Figure 3 A schematic diagram illustrating the working principle of the wide bandgap ultrahigh voltage and high current semiconductor device structure provided in Example 1 of the present invention;

[0050] Figures 4 to 7 A schematic structural diagram of a wide bandgap ultrahigh voltage and high current semiconductor device of another structural type provided by an embodiment of the present invention;

[0051] Figures 8 to 11 A schematic diagram of the cross-sectional shape of the current gain window of the wide bandgap ultra-high voltage and high current semiconductor device structure provided by an embodiment of the present invention;

[0052] Figure 12 A schematic structural diagram of a wide bandgap ultrahigh voltage and high current semiconductor device structure provided in Example 2 of the present invention;

[0053] Figures 13 to 20 A schematic diagram of a method for manufacturing a wide bandgap ultrahigh voltage and high current semiconductor device structure corresponding to Example 1, provided in Example 3 of the present invention;

[0054] In the accompanying drawings, the components represented by the reference numerals are as follows:

[0055] 1. Substrate layer; 2. Epitaxial layer; 3. Channel layer; 4. P-type semiconductor layer; 5. N-type semiconductor layer; 6. Gate dielectric layer; 7. Gate electrode; 8. Interlayer dielectric layer; 9. Current gain window; 10. First electrode; 11. Second electrode. DETAILED DESCRIPTION

[0056] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0057] Due to the advantages of gallium oxide materials, such as its wide bandgap and high critical breakdown electric field, power devices manufactured using gallium oxide exhibit excellent performance, including high blocking voltage, high operating temperature, and low leakage current. Using a light control unit to control the operating state of gallium oxide high-voltage devices offers lower switching losses, higher device response speed, and greater safety compared to traditional electrical switches. Controlling the operating state transitions and reducing device on-resistance by controlling light intensity and pulse duration offers lower latency, power loss, and greater safety than traditional electrical switches. The heterojunction formed by combining different wide-bandgap semiconductors with gallium oxide combines the advantages of these different wide-bandgap semiconductors. This allows the excellent high-voltage and high-current resistance of gallium oxide materials to be fully utilized, even if p-type gallium oxide doping is unsuccessful, potentially opening up new opportunities for the commercialization of gallium oxide power devices.

[0058] However, in the existing technology, taking gallium oxide as an example, there is currently no example of coupling a wide-bandgap semiconductor switching unit with a light control unit. The existing example is a silicon-based light-controlled device, which has two technical problems. First, silicon material is the voltage-resistant unit of the entire device. Currently developed silicon-based high-voltage devices such as IGBT (insulated gate bipolar transistor), VDMOS (vertical double diffused metal oxide semiconductor) and GTO (thyristor) have almost reached the physical limit of silicon-based materials, and it is very difficult to further improve their voltage resistance. For gallium oxide, its critical breakdown electric field (8MV / cm) is 26 times that of silicon material (0.3MV / cm), which can naturally solve the problem of high-voltage resistance.

[0059] Secondly, the light control units of silicon-based light-control devices all work near the surface of the electrode metal material. Since the silicon material itself is not transparent, when the light control unit starts working, the depth of light entering from the surface of the silicon-based device is very thin and cannot reach the position of the silicon-based device's voltage-resistant layer. At this time, the electron-hole pairs generated by the light are instantly recombined by the existing majority carriers in the neutral zone near the surface, and no positive feedback of the electron-hole pairs will be generated, so it has little effect on the current gain.

[0060] Therefore, the existing technology has certain defects: on the one hand, the voltage resistance of silicon-based devices is not as good as that of wide-bandgap semiconductors with the same parameters, which is not conducive to their use in ultra-high voltage circuits; on the other hand, silicon is an opaque material, and the transmission path of photons in silicon is very short. The electron-hole pairs generated will basically be recombined on the surface, and the current gain is small.

[0061] The embodiments of the present invention are described in further detail below with reference to the accompanying drawings and examples. The following examples are used to illustrate the present invention but are not intended to limit the scope of the present invention.

[0062] Example 1

[0063] like Figure 1 As shown, the wide bandgap ultra-high voltage and high current semiconductor device structure provided in this embodiment integrates the voltage-resistant unit and the light-controlled unit designed with gallium oxide materials to form a gallium oxide-based light-controlled high voltage and high current power device, which is expected to realize the marketization of gallium oxide material applications. It specifically includes: a substrate layer 1, an epitaxial layer 2, a channel layer 3, an N-type semiconductor layer 5, a gate dielectric layer 6, a gate electrode 7, an interlayer dielectric layer 8, a current gain window 9, a first electrode 10 and a second electrode 11.

[0064] The epitaxial layer 2 is disposed on the substrate layer 1 .

[0065] In an optional embodiment, the substrate layer 1 and the epitaxial layer 2 are respectively one or any combination of Ga2O3, AlN, BN, SiC, GaN, and diamond. In this embodiment, the substrate layer 1 and the epitaxial layer 2 are described as gallium oxide material - Ga2O3.

[0066] Specifically preferably, the resistivity of the substrate layer 1 is greater than , thickness is 300-600μm.

[0067] The epitaxial layer 2 is an unintentionally doped epitaxial layer 2, and the doping concentration is less than 10 16 cm -3 , with a thickness of 100-300nm.

[0068] The channel layer 3 is an N-type Ga2O3 layer, which is provided on the epitaxial layer 2 and has a P-type semiconductor layer 4 embedded therein. The P-type semiconductor layer 4 forms a heterojunction with the N-type Ga2O3 layer.

[0069] Specifically, the channel layer 3 is a deliberately doped high-concentration epitaxial layer 2 with a doping concentration of 1.0x10 18 -1.0x10 19 cm -3 , with a thickness of 100-300nm.

[0070] The N-type semiconductor layer 5 is wrapped in the P-type semiconductor layer 4 .

[0071] It should be noted that the size of the N-type semiconductor layer 5 along the channel direction is smaller than the size range of the P-type semiconductor layer 4 , and a gap is provided between the two.

[0072] Specifically, the P-type semiconductor layer 4 is any one of P-GaN, P-NiO, P-Cu2O, P-doped SiC, P-doped Si and P-doped diamond.

[0073] When the P-type semiconductor layer 4 is P-GaN, the doping concentration of P-GaN is 5.0x10 18 -5.0x10 19 cm-3 ; In some examples, its thickness can exceed the channel layer 3 and the epitaxial layer 2 and extend into the substrate layer 1.

[0074] The gate dielectric layer 6 is grown on the channel layer 3 and completely covers the gap between the N-type semiconductor layer 5 and the P-type semiconductor layer 4 .

[0075] The gate electrode 7 is deposited on the gate dielectric layer 6 .

[0076] An interlayer dielectric layer 8 is grown on the channel layer 3; a groove is formed by etching downward from the upper surface of the interlayer dielectric layer 8 to the upper surface of the substrate layer 1, and the groove is filled with a transparent insulating medium to construct a current gain window 9. Under the action of light, light passes through the current gain window 9 to reach the substrate layer 1, and the substrate layer 1 generates a large number of photogenerated carriers due to the light and conducts electricity under the action of the electric field.

[0077] The first electrode 10 and the second electrode 11 are respectively provided on two sides of the stacked structure of the gate dielectric layer 6 and the interlayer dielectric layer 8 .

[0078] In an optional embodiment, the first electrode 10 and the second electrode 11 are both ohmic contact electrodes with a thickness of 10-100 nm.

[0079] In an optional example, the first electrode 10 and the second electrode 11 are respectively an emitter electrode and a collector electrode (eg Figure 1 shown).

[0080] In other optional examples, the first electrode 10 and the second electrode 11 may also be a source and a drain respectively (eg Figure 4 shown).

[0081] In other optional examples, the first electrode 10 and the second electrode 11 are respectively an anode and a cathode (eg Figure 5 and Figure 6 shown).

[0082] That is, the lateral device structure can be various devices, such as IGBT (such as Figure 1 As shown), JFET (as Figure 5 As shown), MOSFET (as Figure 4 As shown), GTO (as Figure 6 As shown), Diode (as Figure 7 shown) etc.

[0083] In an optional embodiment, the cross-sectional shape of the current gain window 9 is a bar (eg Figure 11 As shown), square (as Figure 9 As shown), round (as Figure 8 ) or hexagonal (as Figure 10 As shown), by the same token, it can also be a combination structure of their shapes.

[0084] The wide bandgap ultra-high voltage and high current semiconductor device structure provided in this embodiment adopts a lateral IGBT device structure combined with a current enhancement window.

[0085] Its practical working principle is as follows: Figure 2 As shown in the figure, when the device is working in the forward conduction state, when the forward voltage of the heterojunction on the collector side is high enough, the heterojunction is turned on and can provide electrons and holes. When the gate electrode voltage exceeds the device threshold voltage, electrons can pass through the emitter through the N-type semiconductor and the channel into the channel layer and the epitaxial layer, and finally enter the substrate layer. The substrate layer will generate a large number of photogenerated carriers due to light and conduct electricity under the action of the electric field. Eventually, electrons will enter the epitaxial layer and the channel layer from the substrate layer, and finally enter the collector, realizing large current transmission.

[0086] like Figure 3 As shown, when the device is operating in the reverse cutoff state, when the gate voltage causes the channel to be turned off and the light is removed, the current cannot be conducted due to the lack of a conduction path. At this time, the voltage across the collector and emitter will be loaded onto the channel layer and the transparent insulating dielectric layer. Since there is no net charge in the insulating dielectric, the electric field distribution in the insulating dielectric is horizontal. When the insulating dielectric accounts for a large proportion in cells of the same size, the withstand voltage of the device will also increase. This structure uses carriers generated by light to solve the problem that the semi-insulating substrate cannot conduct electricity. The generated photogenerated carriers can solve the difficulty of manufacturing high-current devices and solve the problem of high on-resistance of traditional lateral devices. On the one hand, the transparent insulating dielectric allows light to pass through the surface into the semi-insulating substrate, and on the other hand, it can withstand high voltage during reverse blocking, playing a role in high-voltage resistance.

[0087] In addition, the wide bandgap ultra-high voltage and high current semiconductor device provided in this embodiment requires the gate voltage to reach the threshold voltage and be illuminated to generate a sufficient number of photogenerated carriers when the device is turned on. By controlling the time difference between the opening and triggering of the two, the device can operate in a variety of different modes, such as when the gate bias and the photon generation trigger circuit are turned on at the same time, the device is forward-conducted. When the gate bias or the photon generation trigger circuit is turned off, the device is cut off. When the device is in a reverse bias state, the photon trigger circuit is turned on, which will cause a large number of carriers to be generated inside the semi-insulating substrate. The carriers will produce collision ionization under high electric field strength, thereby generating a large current. At this time, the device is in a high electric field and high voltage state, and thus will consume a lot of electric power and generate heat. At this time, it is necessary to control the opening time of the photon generation circuit to form a pulse switch, and the current in the device forms a pulse current.

[0088] In summary, the present invention adopts a lateral device structure combined with photogenerated carriers to construct a wide bandgap ultra-high voltage and high current device. The invention adopts a lateral device structure to easily etch the channel layer and the epitaxial layer cleanly and adopts a dielectric filling method to realize the production of high-voltage devices. The mechanism of the high-current device is to use the reserved light channel to generate photogenerated carriers to participate in conduction by irradiating light.

[0089] Example 2

[0090] Based on the above embodiment, the difference of this embodiment is that: Figure 12 As shown, the substrate layer is SiC, the epitaxial layer is unintentionally doped GaN, the channel layer is an N-type GaN layer, and the P-type semiconductor layer and the N-type GaN layer 5 form a heterojunction PN junction; the N-type semiconductor layer 5 is N++GaN, and its thickness exceeds the channel layer and the epitaxial layer, extending into the substrate layer.

[0091] This embodiment also has the beneficial effects brought by embodiment 1, so the beneficial effects of the structure provided by this embodiment will not be described in detail here.

[0092] Example 3

[0093] In order to facilitate understanding of the wide bandgap ultra-high voltage and high current semiconductor device structure provided in Example 1, as shown in FIG. Figures 13 to 20 As shown, this embodiment provides a corresponding manufacturing method:

[0094] Step S1 ( Figure 13 As shown in FIG: an epitaxial layer is grown on the substrate layer, and an N-type Ga2O3 layer is grown on the epitaxial layer as a channel layer; a P-type semiconductor layer is embedded in the channel layer to form a heterojunction with the N-type Ga2O3 layer.

[0095] Specifically, a non-intentionally doped gallium oxide epitaxial layer with a thickness of about 100-300 nm is grown on a semi-insulating Ga2O3 substrate layer, and the resistivity of the semi-insulating substrate is > , thickness is 300-600um; the concentration of unintentionally doped gallium oxide epitaxial layer is less than 10 16 cm -3 A high-concentration channel layer with a thickness of about 100-300 nm is grown on the unintentionally doped gallium oxide epitaxial layer, with a doping concentration of 1.0x10 18 -1.0x10 19 cm -3 A layer of P-GaN or other P-type semiconductor is embedded on the Ga2O3 channel layer to form a heterojunction with the N-Ga2O3 channel layer. The doping concentration of P-GaN is 5.0x10 18 -5.0x10 19 cm -3 , the doping concentration is greater than that of the Ga2O3 channel layer.

[0096] Step S2 ( Figure 14 As shown): An N-type semiconductor layer opposite to the P-type semiconductor layer is formed in the heterojunction on one side.

[0097] Specifically, an N-type semiconductor opposite to P-GaN is formed in the heterojunction on one side. The N-type semiconductor can be homogeneous or heterogeneous with the P-GaN. The N-type semiconductor needs to be wrapped in the P-type semiconductor, and the range of the N-type semiconductor along the channel direction cannot exceed that of the P-type semiconductor.

[0098] Step S3 ( Figure 15 As shown): A gate dielectric layer is grown on the surface, and holes are opened in the P-type semiconductor region. The gate dielectric completely covers the gap between the N-type semiconductor layer and the P-type semiconductor layer.

[0099] Specifically, a 10-100nm layer of Al2O3 is grown on the surface of the existing structure as a gate dielectric, and holes are opened in the previous P-type semiconductor area. The remaining Al2O3 needs to completely cover the gap between the N-type semiconductor and the P-type semiconductor.

[0100] Step S4 ( Figure 16 As shown): A layer of Ti metal is deposited on the surface as an ohmic contact electrode and a gate electrode, and then annealed.

[0101] Specifically, a layer of Ti metal with a thickness of 10-100 nm is deposited on the surface of the structure as an ohmic contact electrode and a gate electrode, and annealed in a N2 atmosphere at 470°C.

[0102] Step S5 ( Figure 17 As shown in the figure): A layer of insulating medium is grown on the surface as an interlayer dielectric layer, and holes are opened at the ohmic contact electrode positions to expose the electrodes.

[0103] Specifically, a layer of insulating medium with a thickness of 100-1000 nm is grown on the surface of the structure as an interlayer dielectric between the gate electrode and the transmitter electrode, and a hole is opened at the previous ohmic contact electrode position to expose the electrode.

[0104] The interlayer dielectric layer may be Al2O3, SiO2, Si3N4 or a stacked dielectric thereof.

[0105] Step S6 ( Figure 18 As shown): Ti / Al stacked metal is deposited on the surface as the first electrode and the second electrode of the device.

[0106] Specifically, a layer of Ti / Al laminated metal with a thickness of 1000-5000 nm is deposited on the surface of the structure as the emitter electrode and collector electrode of the device.

[0107] Step S7 ( Figure 19 As shown): The interlayer dielectric layer, gate dielectric layer, channel layer and epitaxial layer are selectively etched on the surface to obtain a groove structure.

[0108] Specifically, the interlayer dielectric, gate dielectric, channel layer and epitaxial layer are selectively etched on the surface of the structure to block the current conduction channel, and the etching depth must exceed the epitaxial layer.

[0109] S8( Figure 20 As shown): Fill the groove structure with a transparent insulating medium to obtain a current gain window.

[0110] Specifically, the transparent insulating medium is required to have low light absorption and to fill the groove.

[0111] The beneficial effects of this manufacturing method embodiment are the same as those of the wide bandgap ultra-high voltage and high current semiconductor device structure provided in Example 1, and will not be described in detail here.

[0112] In summary, the gallium oxide-based ultra-high voltage, high current device structure proposed in the present invention perfectly solves the problems of low withstand voltage of silicon-based devices and short transmission distance of photons in semiconductor materials. The additional light-control unit can easily realize the change of the working state of the gallium oxide device, solving the problem of high on-resistance caused by the lack of P-type doping in gallium oxide devices. At the same time, the ultra-wide bandgap characteristics of gallium oxide are utilized to prepare ultra-high voltage, high current devices.

[0113] Throughout this specification, reference to terms such as "specific examples" or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and integrate different embodiments or examples, and features of different embodiments or examples, described in this specification, unless otherwise mutually incompatible.

[0114] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A wide bandgap ultra-high voltage and high current semiconductor device structure, characterized in that: include: substrate layer; an epitaxial layer, disposed on the substrate layer; A channel layer, which is an N-type Ga2O3 layer or a GaN layer, is provided on the epitaxial layer and has a P-type semiconductor layer embedded therein, wherein the P-type semiconductor layer forms a PN junction with the channel layer; An N-type semiconductor layer is wrapped in the P-type semiconductor layer; a gate dielectric layer grown on the channel layer and completely covering a gap between the N-type semiconductor layer and the P-type semiconductor layer; a gate electrode deposited on the gate dielectric layer; an interlayer dielectric layer grown on the channel layer; A groove is formed by etching downward from the upper surface of the interlayer dielectric layer to the upper surface of the substrate layer, and the groove is filled with a transparent insulating medium to form a current gain window. Under the action of light, light passes through the current gain window to reach the substrate layer, and the substrate layer generates a large number of photogenerated carriers due to the light, and conducts electricity under the action of the electric field; The first electrode and the second electrode are respectively arranged on two sides of the stacked structure of the gate dielectric layer and the interlayer dielectric layer.

2. The wide bandgap ultra-high voltage and high current semiconductor device structure according to claim 1, characterized in that: The size of the N-type semiconductor layer along the channel direction is smaller than the size range of the P-type semiconductor layer, and a gap is provided between the two.

3. The wide bandgap ultra-high voltage and high current semiconductor device structure according to claim 1, characterized in that: The resistivity of the substrate layer is greater than , thickness is 300-600μm; And / or, the epitaxial layer is an unintentionally doped epitaxial layer, and the doping concentration is less than 10 16 cm -3 , thickness is 100-300nm; And / or, the channel layer is an intentionally doped high-concentration epitaxial layer with a doping concentration of 1.0x10 18 -1.0x10 19 cm -3 , with a thickness of 100-300nm.

4. The wide bandgap ultra-high voltage and high current semiconductor device structure according to claim 1, characterized in that: The P-type semiconductor layer is any one of P-GaN, P-NiO, P-Cu2O, P-doped SiC, P-doped Si and P-doped diamond.

5. The wide bandgap ultra-high voltage and high current semiconductor device structure according to claim 4, characterized in that: When the P-type semiconductor layer is P-GaN, the doping concentration of P-GaN is 5.0x10 18 -5.0x10 19 cm -3 .

6. The wide bandgap ultra-high voltage and high current semiconductor device structure according to claim 1, characterized in that: The first electrode and the second electrode are both ohmic contact electrodes with a thickness of 10-100 nm.

7. The wide bandgap ultra-high voltage and high current semiconductor device structure according to claim 6, characterized in that: The first electrode and the second electrode are respectively an emitter electrode and a collector electrode; Or, the first electrode and the second electrode are a source electrode and a drain electrode respectively; Or, the first electrode and the second electrode are a cathode and an anode respectively; Alternatively, the first electrode and the second electrode are an anode and a cathode, respectively.

8. The wide bandgap ultra-high voltage and high current semiconductor device structure according to claim 1, characterized in that: The cross-sectional shape of the current gain window is a bar, square, circle or hexagon.

9. The wide bandgap ultra-high voltage and high current semiconductor device structure according to claim 1, characterized in that: The substrate layer and the epitaxial layer are respectively one or any combination of Ga2O3, AlN, BN, SiC, GaN, and diamond.

10. A method for manufacturing a wide bandgap ultrahigh voltage and high current semiconductor device structure according to any one of claims 1 to 9, characterized in that: The following steps are involved: S1: grow an epitaxial layer on the substrate layer, grow an N-type Ga2O3 layer on the epitaxial layer as a channel layer; embed a P-type semiconductor layer on the channel layer to form a heterojunction with the N-type Ga2O3 layer; S2: forming an N-type semiconductor layer opposite to the P-type semiconductor layer in the heterojunction on one side; S3: growing a gate dielectric layer on the surface and simultaneously opening a hole in the P-type semiconductor region so that the gate dielectric completely covers the gap between the N-type semiconductor layer and the P-type semiconductor layer; S4: depositing a layer of Ti on the surface as an ohmic contact electrode and a gate electrode, and annealing; S5: growing a layer of insulating dielectric on the surface as an interlayer dielectric layer, and simultaneously opening a hole at the ohmic contact electrode position to expose the electrode; S6: depositing Ti / Al stacked metal on the surface as the first electrode and the second electrode of the device; S7: selectively etching the interlayer dielectric layer, the gate dielectric layer, the channel layer, and the epitaxial layer on the surface to obtain a groove structure; S8: Filling the groove structure with a transparent insulating medium to obtain a current gain window.

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