Photodetector with integrated waveguide core

Abstract

The invention relates to a photodetector with an integrated waveguide core. Structures including a photonic chip of a photodetector and methods of forming such structures are provided. The structure includes a photodetector including a gasket and a semiconductor layer on the gasket. The gasket includes a side edge and a first waveguide core extending from the side edge adjacent to the semiconductor layer. The structure also includes a second waveguide core including a section that abuts the side edge of the shim adjacent to the first waveguide core.

Description

Technical Field

[0001] The present disclosure relates to a photonic chip, and more particularly to a structure of a photonic chip including a photodetector and a method of forming such a structure. Background Art

[0002] Photonic chips are used in many applications and systems, including but not limited to data communication systems and data computing systems. A photonic chip includes a photonic integrated circuit that contains photonic components, such as modulators, polarizers, and optical couplers, for manipulating light received from a light source (such as an optical fiber or a laser). A photodetector can be used in the photonic integrated circuit to convert light (which can be modulated as an optical signal) into an electrical signal. The responsivity of a photodetector is a measure of the photoelectric conversion efficiency. At high optical powers, the performance metrics (such as responsivity) of a photodetector may degrade. The degradation of responsivity may have a negative impact on system-level performance.

[0003] There is a need to improve the structure of a photonic chip including a photodetector and a method of forming such a structure. Summary of the Invention

[0004] In one embodiment of the present invention, there is provided a structure for a photonic chip. The structure includes a photodetector that includes a pad and a semiconductor layer on the pad. The pad includes side edges and a first waveguide core that extends from the side edge adjacent to the semiconductor layer. The structure further includes a second waveguide core that includes a section that abuts the side edge of the pad adjacent to the first waveguide core.

[0005] In one embodiment of the present invention, there is provided a method of forming a structure for a photonic chip. The method includes forming a photodetector that includes a pad and a semiconductor layer on the pad. The pad includes side edges and a first waveguide core that extends from the side edge adjacent to the semiconductor layer. The method further includes forming a second waveguide core that includes a section that abuts the side edge of the pad adjacent to the first waveguide core. Brief Description of the Drawings

[0006] The drawings are incorporated into and constitute a part of this specification, which illustrate various embodiments of the present invention and, together with the general description of the present invention given above and the detailed description of the embodiments given below, are used to explain the embodiments of the present invention. In the drawings, the same reference numerals represent the same features in each view.

[0007] Figure 1 is a top view of a structure at an initial manufacturing stage of a processing method according to an embodiment of the present invention.

[0008] Figure 2is taken along line 2-2 Figure 1 in the cross-sectional view shown in

[0009] Figure 2A is taken along line 2A-2A Figure 1 in the cross-sectional view shown in

[0010] Figure 3 is a top view of the structure at the manufacturing stage of the processing method subsequent to Figure 1 , Figure 2 , Figure 2A shown in

[0011] Figure 4 is taken along line 4-4 Figure 3 in the cross-sectional view shown in

[0012] Figure 4A is taken along line 4A-4A Figure 3 in the cross-sectional view shown in

[0013] Figure 5 is a top view of the structure at the manufacturing stage of the processing method subsequent to Figure 3 , Figure 4 , Figure 4A shown in

[0014] Figure 6 is taken along line 6-6 Figure 5 in the cross-sectional view shown in

[0015] Figure 6A is taken along line 6A-6A Figure 5 in the cross-sectional view shown in

[0016] Figure 7 , Figure 7A is a cross-sectional view of the structure at the manufacturing stage of the processing method subsequent to Figure 5 , Figure 6 , Figure 6A shown in

[0017] Figure 8 , Figure 8A is a cross-sectional view of the structure according to an alternative embodiment of the present invention

[0018] Figure 9 is a top view of the structure according to an alternative embodiment of the present invention

[0019] Figure 10 is taken along line 10-10 Figure 9 in the cross-sectional view shown in

[0020] Figure 10A is taken along line 10A-10A Figure 9 in the cross-sectional view shown in

[0021] Figure 11 is a top view of the structure according to an alternative embodiment of the present invention.

[0022] Figure 12 is a top view of the structure according to an alternative embodiment of the present invention.

[0023] Figure 13 is a top view of the structure according to an alternative embodiment of the present invention.

[0024] Figure 14 is a top view of the structure according to an alternative embodiment of the present invention. Detailed Description

[0025] Referring Figure 1 , Figure 2 , Figure 2A and according to an embodiment of the present invention, the structure 10 includes a waveguide core 12 and a photodetector 14 located on (and above) a dielectric layer 16 and a semiconductor substrate 18. In one embodiment, the dielectric layer 16 may include a dielectric material (such as silicon dioxide), and the semiconductor substrate 18 may include a semiconductor material (such as single crystal silicon). In one embodiment, the dielectric layer 16 may be disposed between the waveguide core 12 and the semiconductor substrate 18, and the dielectric layer 16 may be a buried oxide layer of a silicon-on-insulator substrate, and the dielectric layer 16 may provide a low-index cladding for the waveguide core 12 and the photodetector 14.

[0026] The waveguide core 12 includes a section 20 located near the photodetector 14. The section 20 extends longitudinally along the longitudinal axis 15 and has sidewalls 17 and a sidewall 19 opposite to the sidewall 17. The waveguide core 12 may include slab layers 30 extending outward from each of the sidewalls 17, 19. The slab layers 30 may be formed when the waveguide core 12 is formed, and the thickness of the slab layers 30 may be less than the thickness of the section 20 of the waveguide core 12. The slab layers 30 are connected to the lower part of the section 20 of the waveguide core 12 at each of the sidewalls 17, 19.

[0027] The photodetector 14 includes a pad 24 having side edges 23, a side edge 25 opposite to the side edge 23, a side edge 27, and a side edge 29 opposite to the side edge 27. The side edges 23, 25, 27, 29 may surround the outer periphery of the pad 24, and the side edges 23, 25, 27, 29 may extend to the dielectric layer 16. In one embodiment, the section 20 and the slab layers 30 of the waveguide core 12 may be adjacent to the side edge 23 of the pad 24.

[0028] In one embodiment, the spacer 24 of the waveguide core 12 and the photodetector 14 may include a material having a refractive index greater than that of silica. In one embodiment, the spacer 24 of the waveguide core 12 and the photodetector 14 may include a semiconductor material. In one embodiment, the spacer 24 of the waveguide core 12 and the photodetector 14 may include single-crystalline silicon. The spacer 24 of the waveguide core 12 and the photodetector 14 may be formed by patterning a layer including its constituent materials using lithography and etching processes. In one embodiment, the spacer 24 of the waveguide core 12 and the photodetector 14 may be formed by patterning the semiconductor material (e.g., single-crystalline silicon) of the device layer of a silicon-on-insulator substrate.

[0029] The photodetector 14 further includes a semiconductor layer 26 that provides a light absorption layer disposed inwardly spaced from the outer periphery of the spacer 24 on the spacer 24. The semiconductor layer 26 extends longitudinally on the spacer 24 along the longitudinal axis 36. The semiconductor layer 26 may have sidewalls 34 near the side 23 of the spacer 24, sidewalls 35 near the side 25 of the spacer 24, sidewalls 37 near the side 27 of the spacer 24, and sidewalls 39 near the side 29 of the spacer 24. In one embodiment, the semiconductor layer 26 may be equidistant from the sides 27 and 29. The section 20 of the waveguide core 12 is laterally offset from the longitudinal axis 36 of the semiconductor layer 26 along the side 32. In one embodiment, the section 20 of the waveguide core 12 may be laterally offset between the sidewall 37 of the semiconductor layer 26 and the side 27 of the spacer 24 along the side 23 of the spacer 24.

[0030] The semiconductor layer 26 of the photodetector 14 may include a light absorption material that can generate charge carriers from the photons of the absorbed light through photoelectric conversion. In one embodiment, the semiconductor layer 26 may include an intrinsic semiconductor material. In one embodiment, the semiconductor layer 26 may include intrinsic germanium. In one embodiment, the semiconductor layer 26 may include intrinsic silicon germanium. In an alternative embodiment, the semiconductor layer 26 may include different types of semiconductor materials, such as III-V compound semiconductor materials or intrinsic silicon.

[0031] The semiconductor layer 26 may be formed by an epitaxial growth process. In one embodiment, the semiconductor layer 26 may be epitaxially grown inside and outside the patterned trench 22 in the spacer 24 such that the semiconductor layer 26 includes a lower portion disposed below the top surface 28 of the spacer 24 and an upper portion disposed above the top surface 28 of the spacer 24. A hard mask including a dielectric material may be disposed on the top surface 28 of the spacer 24 and around the trench 22 during the epitaxial growth process and may be removed after the epitaxial growth process.

[0032] Reference Figure 3 、 Figure 4 、 Figure 4A, where like reference numerals represent Figure 1 , Figure 2 , Figure 2A like features in, and in a subsequent manufacturing stage, the structure 10 may include a doped region 40 formed in a portion of the sidewall 37 of the spacer 24 adjacent to the semiconductor layer 26 and a doped region 42 formed in a portion of the sidewall 39 of the spacer 24 adjacent to the semiconductor layer 26. The semiconductor layer 26 is laterally located between the doped region 40 and the doped region 42. The doped regions 40, 42 of different conductivity types may extend completely through the entire thickness of the spacer 24 to the underlying dielectric layer 16. The doped regions 40 and 42 may define the anode and cathode of the photodetector 14, respectively.

[0033] The doped region 40 may be formed by, for example, ion implantation, where the implantation mask has an opening that defines the implantation area of the spacer 24. The implantation mask may include a photoresist applied by a spin coating process, which is pre-baked, exposed to light projected through a photomask, post-exposure baked, and developed with a chemical developer to define an opening in the area of the spacer 24 to be implanted. Implantation conditions such as ion species, dose, and kinetic energy may be selected to adjust the electrical and physical characteristics of the doped region 40. The implantation mask may be stripped after the doped region 40 is formed. In one embodiment, the semiconductor material of the doped region 40 may include a p-type dopant, such as boron, that provides p-type conductivity. In an alternative embodiment, due to the overlap of the opening in the implantation mask with a portion of the semiconductor layer 26, a portion of the semiconductor layer 26 adjacent to the doped region 40 and a lower portion of the spacer 24 may be implanted with the p-type dopant.

[0034] The doped region 42 may be formed by, for example, ion implantation, where the implantation mask has an opening that defines the implantation area of the spacer 24. The implantation mask may include a photoresist applied by a spin coating process, which is pre-baked, exposed to light projected through a photomask, post-exposure baked, and developed with a chemical developer to define an opening in the area of the spacer 24 to be implanted. Implantation conditions such as ion species, dose, and kinetic energy may be selected to adjust the electrical and physical characteristics of the doped region 42. The implantation mask may be stripped after the doped region 42 is formed. In one embodiment, the semiconductor material of the doped region 42 may include an n-type dopant, such as phosphorus or arsenic, that provides n-type conductivity. In an alternative embodiment, due to the overlap of the opening in the implantation mask, a portion of the semiconductor layer 26 adjacent to the doped region 42 and a lower portion of the spacer 24 may be implanted with the n-type dopant. In an alternative embodiment, due to the overlap of the opening in the implantation mask with a portion of the semiconductor layer 26, a portion of the semiconductor layer 26 adjacent to the doped region 42 and a lower portion of the spacer 24 may be implanted with the n-type dopant.

[0035] A portion of the spacer 24 below the semiconductor layer 26 may include an intrinsic semiconductor material (e.g., intrinsic silicon) that is not doped by the ion implantation that forms the doped regions 40, 42. In one embodiment, the intrinsic portion of the spacer 24 may be located below the semiconductor layer 26 and extend from side 23 of the spacer 24 to side 25 of the spacer 24. The doped region 40, the intrinsic semiconductor material of the semiconductor layer 26, and the portion of the spacer 24 below the semiconductor layer 26, and the doped region 42 may define a lateral p-i-n diode structure that enables the photodetector 14 to function.

[0036] A heavily doped region 41 may be formed in a portion of the doped region 40 near side 27 by masked ion implantation. A heavily doped region 43 may be formed by masked ion implantation in a portion of the doped region 42 adjacent to side 29. The heavily doped region 41 may have the same conductivity type as the doped region 40 but a higher dopant concentration. The heavily doped region 43 may have the same conductivity type as the doped region 42 but a higher dopant concentration.

[0037] Reference Figure 5 , Figure 6 , Figure 6A , in which like reference numerals represent Figure 3 , Figure 4 , Figure 4A the same features in

[0038] The trenches 44 and 46 can be disposed at intervals on one side of the semiconductor layer 26, between the side edge 27 of the spacer 24 and the sidewall 37 of the semiconductor layer 26. The trench 48 can be disposed on the opposite side of the semiconductor layer 26, between the side edge 29 of the spacer 24 and the sidewall 39 of the semiconductor layer 26. In one embodiment, the trenches 44, 46, 48 can intersect the side edge 23 of the spacer 24. In one embodiment, the trenches 44, 46 can intersect the side edge 23 of the spacer 24 and be aligned with the portions where the plate layer 30 extends outward from the opposite sidewalls 17, 19 of the section 20 of the waveguide core 12. In one embodiment, the trenches 44, 46, 48 can also terminate at one end adjacent to the side edge 25 of the spacer 24 and the sidewall 35 of the semiconductor layer 26. The spacing between the trench 44 and the trench 46 can decrease as the distance from the side edge 23 increases and the distance from the side edge 25 decreases.

[0039] The portion of the semiconductor material of the spacer 24 between the trenches 44 and 46 defines a waveguide core 50 that is structurally and functionally integrated into the spacer 24. The waveguide core 50 includes sidewalls 53 and a sidewall 55 opposite to the sidewall 53. The sidewall 53 of the waveguide core 50 is disposed near the side edge 27 of the spacer 24, while the sidewall 55 of the waveguide core 50 is disposed near the sidewall 37 of the semiconductor layer 26. The waveguide core 50 has a top surface coplanar with the top surface 28 of the spacer 24.

[0040] The waveguide core 50 provides an optical coupler configured to laterally transmit the light received from the section 20 of the waveguide core 12 to the photodetector 14. The waveguide core 50 is tapered, and the width dimension W1 decreases as the distance from the side edge 23 of the spacer 24 increases. The tapering of the waveguide core 50 facilitates the coupling of light from the waveguide core 50 to the semiconductor layer 26. There is a gap between the sidewall 55 of the waveguide core 50 and the sidewall 37 of the semiconductor layer 26, and the light is laterally transmitted through this gap. In one embodiment, the gap between the sidewall 55 of the waveguide core 50 and the sidewall 37 of the semiconductor layer 26 can be consistent with the position between the side edge 23 and the side edge 25 of the spacer 24. In an alternative embodiment, the gap between the sidewall 55 of the waveguide core 50 and the sidewall 37 of the semiconductor layer 26 can vary with the position between the side edge 23 and the side edge 25 of the spacer 24.

[0041] The waveguide core 50 extends longitudinally along a longitudinal axis 52 that is inclined with respect to the longitudinal axis 36 of the semiconductor layer 26. There is a lateral offset between the longitudinal axis 52 of the waveguide core 50 and the longitudinal axis 36 of the semiconductor layer 26. In one embodiment, the waveguide core 50 can be laterally offset along the side edge 23 of the spacer 24 between the sidewall 37 of the semiconductor layer 26 and the side edge 27 of the spacer 24. The lateral offset of the waveguide core 50 can compensate for the lateral offset of the section 20 of the waveguide core 12 and enable the lateral offset of the section 20 of the waveguide core 12.

[0042] Reference Figure 7 and Figure 7A wherein like reference numerals represent Figure 5 and Figure 6 and Figure 6A like features in

[0043] and in subsequent manufacturing stages, a dielectric layer 60 is formed over the waveguide core 12 and the photodetector 14. In one embodiment, the dielectric layer 60 may comprise a dielectric material (such as silicon dioxide). The dielectric material of the dielectric layer 60 may fill the trenches 44, 46, 48. The dielectric material in the trenches 44, 46 provides a low refractive index cladding for the waveguide core 50. The refractive index contrast between the dielectric material in the trenches 44 and 46 and the waveguide core 50 enables light to be guided through the coupling region adjacent to the semiconductor layer 26 in the waveguide core 50.

[0044] The refractive index contrast between the dielectric material in the trench 48 and the semiconductor material of the spacer 24 enables the trench 48 to be used as a mode confiner, thereby improving the light coupled to the semiconductor layer 26. In this regard, the mode confinement provided by the trench 48 and the dielectric material in the trench 48 can push the electromagnetic field associated with the light guided by the waveguide core 50 towards the semiconductor layer 26. In an alternative embodiment, the trench 48 may be omitted from the structure 10.

[0045] A conformal dielectric layer 62 may be formed that extends across the waveguide core 12 and the photodetector 14 and follows the topography generated by the semiconductor layer 26. In one embodiment, the conformal dielectric layer 62 may comprise a dielectric material (such as silicon nitride). A dielectric layer 64 may be formed over the conformal dielectric layer 62. In one embodiment, the dielectric layer 64 may comprise a dielectric material (such as silicon dioxide) having a refractive index lower than that of the material of the waveguide core 12.

[0046] Contacts 66 may be formed that penetrate completely through the dielectric layers 60, 62, 64 to land on the heavily doped region 41, and contacts 68 may be formed that penetrate completely through the dielectric layers 60, 62, 64 to land on the heavily doped region 43. The heavily doped region 41 electrically couples the contact 66 to the doped region 40 with a reduced contact resistance. The heavily doped region 43 electrically couples the contact 68 to the doped region 42 with a reduced contact resistance. The contacts 66, 68 may comprise a metal (such as tungsten). The doped regions 40, 42 may be biased through the contacts 66, 68, and the contacts 66, 68 may be coupled to interconnects (not shown) in a dielectric layer formed over the dielectric layer 64.

[0047] In use, light (such as a laser) propagates in waveguide core 12 towards photodetector 14 and is transmitted from section 20 of waveguide core 12 to waveguide core 50 at side 23 of spacer 24. Waveguide core 12 and waveguide core 50 can support the propagation of light having transverse-electric polarization, transverse-magnetic polarization, or a combination of both polarizations. Then, waveguide core 50 laterally couples the light guided by waveguide core 50 to semiconductor layer 26 of photodetector 14. In one embodiment, the light received by photodetector 14 can be modulated into an optical signal. Semiconductor layer 26 absorbs the photons of the laterally transmitted light and converts the absorbed photons into charge carriers through photoelectric conversion. The biasing of doped regions 40, 42 causes the charge carriers to be collected and output from photodetector 14 to provide a measurable photocurrent as a function of time.

[0048] The waveguide core 50 integrated into semiconductor layer 26 can be used as a mode-evolution-based optical coupler, thereby improving the responsivity of photodetector 14. The improvement in the responsivity of photodetector 14 (especially at high optical powers) can significantly improve system-level performance.

[0049] Reference Figure 8 、 Figure 8A , according to an alternative embodiment, structure 10 can be modified such that photodetector 14 has a vertical arrangement instead of a lateral arrangement. Specifically, as Figure 8 shown, doped region 40 can extend throughout spacer 24, heavily doped region 41 can be provided in spacer 24 on both sides of semiconductor layer 26, and doped region 42 and heavily doped region 43 can be provided in the upper part of semiconductor layer 26. In an alternative embodiment, as Figure 8A shown, structure 10 can be configured with heavily doped region 41 provided in spacer 24 adjacent to only one side of semiconductor layer 26.

[0050] In an alternative embodiment, semiconductor layer 26 can be entirely provided on (and above) top surface 28 of spacer 24. In an alternative embodiment, photodetector 14 can be configured as an avalanche photodetector, which includes an intrinsic semiconductor material region (which defines a multiplication region) in spacer 24 and additional doped regions (which define charge control regions) in spacer 24.

[0051] Reference Figure 9 、 Figure 10 、 Figure 10AAccording to an alternative embodiment, structure 10 may further include waveguide core 70, which is disposed at a height above waveguide core 50 to define a stacked waveguide structure. Structure 10 may further include waveguide core 72, which is disposed at a height above at least section 20 of waveguide core 12 to define a stacked waveguide structure. In one embodiment, waveguide cores 70, 72 may include a material different from that of waveguide core 12 and waveguide core 50. In one embodiment, waveguide cores 70, 72 may include a dielectric material (such as silicon nitride). In an alternative embodiment, waveguide cores 70, 72 may include a semiconductor material (such as polysilicon).

[0052] In one embodiment, waveguide core 72 may be narrower than waveguide core 12 and located at the center above waveguide core 12 with a dielectric material in between. A section of dielectric layer 62 may be removed from the region between waveguide core 70 and waveguide core 12. Waveguide core 70 may be narrower than waveguide core 50 and located at the center above waveguide core 50 with a dielectric material inserted in between. In one embodiment, the width dimension of waveguide core 70 may be tapered as waveguide core 50 is tapered. For example, waveguide core 70 may be tapered at the same taper angle or a set of taper angles as waveguide core 50.

[0053] Reference Figure 11 According to an alternative embodiment, structure 10 may further include waveguide core 13, which has a section 21 adjacent to photodetector 14. Section 21 may have plates 31 extending outward from its opposite sidewalls. The configurations of waveguide core 13, section 21 of waveguide core 13, and plates 31 may be similar or identical to those of waveguide core 12, section 20 of waveguide core 12, and plates 30, respectively. Section 21 of waveguide core 13 and plates 31 may be adjacent to side 23 of spacer 24. Section 21 of waveguide core 13 may be disposed along side 23 of spacer 24 on the side opposite to section 20 of waveguide core 12 with respect to semiconductor layer 26. In an embodiment, waveguide core 13 may include the same material as waveguide core 12 and spacer 24 of photodetector 14, and plates 31 may include the same material as plates 30.

[0054] Structure 10 may further include a trench 49 that partially penetrates the spacer 24. The trench 49 may be formed by a photolithography and etching process when forming the trenches 44, 46, 48. The trench 49 and the trench 48 are disposed on the same side of the semiconductor layer 26. The trench 48 is disposed between the trench 49 and the sidewall 39 of the semiconductor layer 26, and the trench 49 is disposed between the trench 48 and the side edge 29 of the spacer 24. In one embodiment, the trench 49 may intersect the side edge 23 of the spacer 24. In one embodiment, the trenches 48, 49 may intersect the side edge 23 of the spacer 24 and be aligned with the portion where the plate layer 31 extends outward from the opposite sidewalls of the section 21 of the waveguide core 13. In one embodiment, the trench 49 may also terminate at one end adjacent to the side edge 25 of the spacer 24 and the sidewall 35 of the semiconductor layer 26.

[0055] The portion of the spacer 24 between the trench 48 and the trench 49 defines a waveguide core 51 that is structurally and functionally integrated into the spacer 24. The waveguide core 51 includes sidewalls disposed near the side edge 29 of the spacer 24 and sidewalls disposed near the sidewall 39 of the semiconductor layer 26. The thinned material of the doped region 42 at the bottom of the partially etched trenches 48, 49 retains a portion of the doped region 42 that connects the portion of the spacer 24 located below the semiconductor layer 26 and the heavily doped region 43.

[0056] The waveguide core 51 provides an optical coupler configured to laterally transmit light received from the section 21 of the waveguide core 13 to the photodetector 14. The waveguide core 51 is tapered, and the width dimension W2 decreases as the distance from the side edge 23 of the spacer 24 increases. The tapering of the waveguide core 51 facilitates the transmission of light from the waveguide core 51 to the semiconductor layer 26 of the photodetector 14. There is a gap between the sidewall of the waveguide core 51 and the adjacent sidewall 39 of the semiconductor layer 26, and this gap may be consistent with the position between the side edge 23 and the side edge 25 of the spacer 24, or may vary with the position between the side edge 23 and the side edge 25 of the spacer 24.

[0057] The waveguide core 51 has a lateral offset from the longitudinal axis 36 of the semiconductor layer 26. In one embodiment, the waveguide core 51 may be laterally offset between the sidewall 39 of the semiconductor layer 26 and the side edge 29 of the spacer 24 along the side edge 23 of the spacer 24. The lateral offset of the waveguide core 51 compensates for the lateral offset of the section 21 of the waveguide core 13 and enables the lateral offset of the section 21 of the waveguide core 13. Similar to the waveguide core 50, the waveguide core 51 has a longitudinal axis that is inclined with respect to the longitudinal axis 36 of the semiconductor layer 26.

[0058] In addition to the input provided by section 20 of waveguide core 12 and waveguide core 50, section 21 of waveguide core 13 and waveguide core 51 also provide another input to photodetector 14. The total optical power transmitted to photodetector 14 can be distributed among different inputs, which can further improve the responsivity of photodetector 14 and system-level performance, especially at high optical powers.

[0059] Reference Figure 12 According to an alternative embodiment, section 21 of waveguide core 13 can be adjacent to side 25 of spacer 24 instead of side 23, and trench 49 can be inclined in the opposite direction to form a tapered waveguide core 51, the tapering of which is opposite to that of waveguide core 50 in terms of the change in width dimension. In addition to the input provided by section 20 of waveguide core 12 and waveguide core 50, section 21 of waveguide core 13 and waveguide core 51 also provide another input to photodetector 14, where photodetector 14 is arranged between different inputs.

[0060] Reference Figure 13 According to an alternative embodiment, structure 10 can also include trenches 54, 56 that partially penetrate spacer 24. Trenches 54, 56 can be formed by lithography and etching processes when forming trenches 44, 46, 48. Trenches 54, 56 are provided on the same side of semiconductor layer 26 as trench 48, and trenches 54, 56 are filled with dielectric material of subsequently formed dielectric layer 60. Trenches 48, 54, 56 can be arranged in a row of a one-dimensional array. In one embodiment, trenches 48, 54, 56 can extend parallel to each other. The dielectric-filled trenches 54 and 56 are additional parts of dielectric-filled trench 48, and their function is to further strengthen and enhance mode confinement and further improve the optical coupling with semiconductor layer 26.

[0061] Reference Figure 14 According to an alternative embodiment, trenches 58 arranged in rows and columns of a two-dimensional array can be formed. Trenches 58 can be formed by lithography and etching processes when forming trenches 44, 46. Trenches 58 are provided on the side of semiconductor layer 26 opposite to trenches 44, 46, and are filled with dielectric material of subsequently formed dielectric layer 60. The dielectric material in trenches 58 forms a refractive index contrast with the semiconductor material of spacer 24 and allows the dielectric-filled trenches 58 to provide mode confinement and improve the optical coupling with semiconductor layer 26.

[0062] The above method is used to manufacture integrated circuit chips. The manufacturer may distribute the resulting integrated circuit chips in the form of an original wafer (e.g., a single wafer with multiple unpackaged chips), a bare die, or a packaged form. The chip may be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an intermediate product or a final product. The final product may be any product that includes an integrated circuit chip, such as a computer product with a central processor or a smartphone.

[0063] Terms recited herein that are modified by approximate language, such as "about," "substantially," and "essentially," are not limited to the specified exact value. The approximate language may correspond to the precision of the instrument used to measure the value and, unless otherwise relying on the precision of the instrument, may represent + / - 10% of the recited value.

[0064] Terms recited herein, such as "vertical," "horizontal," etc., are used as examples to establish a reference frame and are not limiting. The term "horizontal" as used herein is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "orthogonal" refer to a direction perpendicular to the horizontal plane as just defined. The term "lateral" refers to a direction in the reference frame within the horizontal plane.

[0065] A feature that is "connected" or "coupled" to another feature may be directly connected or coupled to the other feature, or there may be one or more intermediate features. If there are no intermediate features, the feature may be "directly connected" or "directly coupled" to the other feature. If there is at least one intermediate feature, the feature may be "indirectly connected" or "indirectly coupled" to the other feature. A feature that is "on" or "in contact with" another feature may be directly on or in direct contact with the other feature, or there may be one or more intermediate features. If there are no intermediate features, the feature may be directly "on" or "in direct contact with" the other feature. If there is at least one intermediate feature, the feature may be "not directly" "on" or "not in direct contact with" the other feature. If one feature extends over and covers a portion of another feature, the different features may "overlap."

[0066] The description of the various embodiments of the present invention is for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the embodiments. The terms used herein are selected to best explain the principles of the embodiments, the practical application, or the technological improvements over the known technology in the market, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A structure for a photonic chip, characterized in that The structure includes: A photodetector including a spacer and a semiconductor layer on the spacer, the spacer including a first side and a first waveguide core extending from the first side adjacent to the semiconductor layer; and A second waveguide core including a section adjacent to the first side of the spacer adjacent to the first waveguide core.

2. The structure according to claim 1, characterized in that, The semiconductor layer has a longitudinal axis, and the first waveguide core is laterally offset relative to the longitudinal axis of the semiconductor layer along the first side.

3. The structure according to claim 1, wherein The spacer includes a first trench and a second trench, and the first waveguide core is disposed between the first trench and the second trench.

4. The structure according to claim 3, wherein, The first trench and the second trench partially penetrate the thickness of the spacer.

5. The structure according to claim 3, characterized in that, The first waveguide core includes a semiconductor material having a first refractive index, and the first trench and the second trench are filled with a dielectric material having a second refractive index less than the first refractive index.

6. The structure according to claim 5, wherein The spacer includes the semiconductor material.

7. The structure according to claim 3, characterized in that, The semiconductor layer includes a second sidewall and a first sidewall adjacent to the first waveguide core, the first trench and the second trench are disposed adjacent to the first sidewall, and the spacer includes a third trench disposed adjacent to the second sidewall.

8. The structure according to claim 7, wherein The first waveguide core includes a semiconductor material having a first refractive index, and the first trench, the second trench, and the third trench are filled with a dielectric material having a second refractive index less than the first refractive index.

9. The structure according to claim 7, wherein The spacer includes a fourth trench disposed between the second sidewall and the third trench.

10. The structure according to claim 3, characterized in that, The semiconductor layer includes a second sidewall and a first sidewall adjacent to the first waveguide core, the first trench and the second trench are disposed adjacent to the first sidewall, and the spacer includes a plurality of trenches disposed adjacent to the second sidewall in a two-dimensional array.

11. The structure according to claim 1, wherein, The second waveguide core is aligned with the first waveguide core at the first side of the spacer.

12. The structure according to claim 1, wherein The second waveguide core includes a slab layer.

13. The structure according to claim 1, characterized in that, The semiconductor layer has a longitudinal axis, and the first waveguide core includes a longitudinal axis inclined relative to the longitudinal axis of the semiconductor layer.

14. The structure according to claim 1, wherein The spacer includes a third waveguide core extending from the first side adjacent to the semiconductor layer, and the structure further includes: A fourth waveguide core including a section adjacent to the first side of the spacer adjacent to the third waveguide core.

15. The structure according to claim 14, characterized in that, The semiconductor layer is disposed between the first waveguide core and the third waveguide core, the semiconductor layer has a longitudinal axis, and the third waveguide core includes a longitudinal axis inclined relative to the longitudinal axis of the semiconductor layer.

16. The structure according to claim 1, wherein The spacer includes a second side opposite to the first side and a third waveguide core extending from the second side adjacent to the semiconductor layer, and the structure further includes: A fourth waveguide core including a section adjacent to the second side of the spacer.

17. The structure according to claim 16, wherein, The semiconductor layer is disposed between the first waveguide core and the third waveguide core, the semiconductor layer has a longitudinal axis, and the third waveguide core includes a longitudinal axis inclined relative to the longitudinal axis of the semiconductor layer.

18. The structure according to claim 1, characterized in that, It further includes: A third waveguide core disposed above the first waveguide core, wherein the first waveguide core includes a first material, and the third waveguide core includes a second material different from the first material.

19. The structure according to claim 1, wherein It further includes: A first doped region located in the spacer, the first doped region having a first conductivity type; and A second doped region located in the spacer, the second doped region having a second conductivity type opposite to the first conductivity type, Wherein, the semiconductor layer is disposed on a part of the spacer between the first doped region and the second doped region, and the part of the spacer includes intrinsic semiconductor material.

20. A method of forming a structure for a photonic chip, characterized in that, The method includes: forming a photodetector including a spacer and a semiconductor layer on the spacer, wherein the spacer includes side edges and a first waveguide core that extends from the side edge adjacent to the semiconductor layer; and forming a second waveguide core including a section that abuts the side edge of the spacer adjacent to the first waveguide core.

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