Application of full-photoetching organic field effect transistor based on interdigital structure in manufacturing of power integrated circuit

Abstract

The invention belongs to the technical field of organic electronic devices, and particularly relates to application of a full-photoetching organic field effect transistor based on an interdigital structure in manufacturing of a power integrated circuit. The power integrated circuit manufactured by using the full-photoetching organic field effect transistor of the interdigital structure adopts an upper dielectric layer as a photoetching barrier layer; a photoetching technology is successfully introduced into preparation of an organic circuit by combining a through hole technology, a plurality of organic field effect transistors can be integrated on the same substrate by the preparation technology, effective interconnection of the organic field effect transistors can be realized, and an interdigital channel structure can be used for improving the performance of the device by optimizing an internal carrier transmission path of the device. The circuit conduction current can be obviously improved, and the conduction resistance can be reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of organic electronic devices, and particularly relates to the application of a fully lithographic organic field effect transistor based on an interdigital structure in the fabrication of power integrated circuits. Background Art

[0002] The traditional integrated circuit industry relies on a manufacturing mode with high energy consumption, high emissions, and high costs. The complex production process and the dependence on high-precision equipment are difficult to meet the requirements of green development. For example, traditional power switch transistors are limited by the fixed device polarity, and only one of N-type or P-type can be selected. When constructing an H-bridge circuit, significant structural constraints are faced. There are two technical routes for the current mainstream H-bridge architecture: one is to use a complementary combination of an upper-bridge P-type transistor and a lower-bridge N-type transistor, and the other is to construct based on all N-type transistors. However, both of these two schemes require separate designs for different polarity devices, resulting in limited circuit topology selection, complex process compatibility, and significantly increasing the system integration cost.

[0003] Organic integrated circuits based on copolymer semiconductor materials have broken through the limitations of traditional technologies through new materials, new devices, and new processes. Copolymer materials can be solution-processed, and the manufacturing process is simple and efficient, without the need for high temperatures, greatly reducing energy consumption and costs, while reducing environmental pollution. In addition, organic integrated circuits have the characteristics of flexibility, stretchability, and low power consumption, and are suitable for fields such as flexible electronics, wearable devices, and the Internet of Things. Copolymer organic integrated circuits provide a new solution for the green and sustainable development of the electronics industry with the advantages of environmental friendliness, low cost, high performance, and flexibility, and promote the innovation and diversified applications of integrated circuit technology.

[0004] Copolymer organic field effect transistors (OFETs) have the advantages of low production cost, wide material sources, environmental friendliness, simple process, flexibility, etc., and are widely used in fields such as radio frequency identification tags, biosensors, flexible displays, and photodetectors. As a typical intelligent power integrated circuit, the H-bridge circuit is commonly used in fields such as DC and stepper motor drives, industrial robots, and military equipment. However, the power switch devices (such as MOSFETs, BJTs, IGBTs, etc.) used in traditional H-bridge circuits have problems such as high cost, complex process, cumbersome process, and the need for packaging. Moreover, these devices have fixed polarities and single functions, and cannot achieve multi-functional switching by changing the gate connection method or voltage.

[0005] In the patent document with the publication number CN1151723663B, our research group provided an application of a copolymer organic field-effect transistor in a multimodal power integrated circuit. By using the copolymer organic field-effect transistor to fabricate an organic semiconductor multimodal power integrated circuit, this multimodal control circuit can achieve the conversion of the device's N-type / P-type polarity by changing the gate bias voltage. Only by changing the external gate signal can the switching of the H-bridge, single-stage amplifier, and inverter be realized. Moreover, the manufacturing process of this circuit is simple, with higher integration, low heat dissipation, low cost, environmental friendliness, and no more pollution. The solution disclosed in the above patent document is the preliminary attempt of our research group to apply the organic field-effect transistor as a power device in the power integrated circuit. The accuracy of the source and drain electrodes fabricated is not high, and the manufacturing efficiency is low. Only one finished product of the power integrated circuit can be fabricated at a time. Therefore, when fabricating more complex and precise source and drain patterns, the solution disclosed in the above patent document is basically impossible to achieve. For example, in the interdigitated channel structure, the interdigitated channel is formed by designing the metal electrodes of the source and drain as multiple parallel and intersecting finger-like structures, forming a dense channel network. This layout can significantly increase the effective channel width per unit area, thereby reducing the on-resistance and improving the current-carrying capacity. The interdigitated structure makes the electric field distribute more evenly in the channel region, reducing the phenomenon of local electric field concentration, which helps to improve the breakdown voltage and reliability of the device. Summary of the Invention

[0006] The technical problem to be solved by the present invention is aimed at the deficiencies of the above-mentioned prior art, and provides an application of a fully lithographed organic field-effect transistor based on an interdigitated structure in fabricating a power integrated circuit. The power integrated circuit fabricated by using this fully lithographed organic field-effect transistor based on the interdigitated structure can achieve the goals of low cost, high performance, and environmental friendliness, and provide a new solution for the development of power integrated circuits.

[0007] To solve the above technical problems, the technical solution adopted by the present invention is:

[0008] An application of a fully lithographed organic field-effect transistor based on an interdigitated structure in fabricating a power integrated circuit, that is, the present invention provides a method for fabricating a power integrated circuit of a fully lithographed organic field-effect transistor based on an interdigitated structure. The power integrated circuit includes multiple fully lithographed organic field-effect transistors with an interdigitated structure, and the organic field-effect transistor is a top-gate bottom-contact structure, as Figure 1 shown in the schematic diagram of each layer structure of the organic half-field-effect transistor of the present invention;

[0009] For example, when the power integrated circuit is an H-bridge circuit, the power integrated circuit includes four fully lithographed organic field-effect transistors with an interdigitated structure, as Figure 2 is the layout of the H-bridge circuit constructed based on the organic field-effect transistor, Figure 3 ForFigure 2 Enlarged view of the middle interdigital structure region;

[0010] Combined with, for example Figure 5A , Figure 5B , Figure 5C and Figure 5D The change schematic diagrams of a single organic field effect transistor during the manufacturing process as shown, to elaborate the manufacturing method of the power integrated circuit, the manufacturing method includes the steps:

[0011] As Figure 5A shown, use the room temperature PECVD process to fabricate and generate the lower dielectric layer on the original substrate, the substrate with the lower dielectric layer is the first substrate, preferably, the thickness of the lower dielectric layer is 100 nm; after photolithographing the source-drain metal pattern and the metal lead pattern on the first substrate, it serves as the second substrate, and the source-drain metal pattern is the source-drain electrode pattern of the multiple transistors; the photolithography steps successively include: HDMS pretreatment, spin coating photoresist, pre-baking, exposure, post-baking, flood exposure, development, cleaning and drying; after evaporating the source-drain metal and the metal lead on the second substrate, it serves as the third substrate;

[0012] As Figure 5B shown, the third substrate is subjected to a de-glue treatment, and after de-gluing, it serves as the fourth substrate; an organic semiconductor layer is fabricated on the fourth substrate to serve as the fifth substrate, the fabrication material of the organic semiconductor layer is a copolymer organic material, and preferably any one of organic pentacene, DPPT-TT, P3HT or naphthalimide-based N-type polymer; use the room temperature PECVD process to fabricate and generate the upper dielectric layer on the fifth substrate, that is, on the top of the semiconductor layer, preferably, the thickness range of the upper dielectric layer is 200 nm to 350 nm; the upper dielectric layer can prevent organic solutions such as photoresist and developer from reacting with the organic semiconductor layer and affecting the device performance, and the upper dielectric layer has better anti-leakage ability and can bring better gate control ability to the device;

[0013] As Figure 5C shown, use photolithography technology to photolithograph the via hole structure pattern on the upper dielectric layer, and etch the via hole from the upper dielectric layer, and the via hole reaches the source-drain electrode directly, that is, etch the dielectric layer and the organic semiconductor layer under the via hole structure pattern; evaporate metal in the via hole and complete the metal stripping in the non-via hole area after de-gluing;

[0014] As Figure 5D shown, photolithograph the gate electrode pattern; except that the photolithography mask pattern is different, the steps of photolithographing the gate electrode pattern are the same as those of photolithographing the source-drain metal pattern, and both include HDMS pretreatment, spin coating photoresist, pre-baking, exposure, post-baking, flood exposure, development, cleaning and drying; after evaporating the gate electrode, complete de-gluing;

[0015] Among them, the steps of exposure, post-baking, flood exposure, and development in the photolithography operation are as follows: A photolithography mask is used, the photolithography mode is Hard mode, the exposure duration is 1.5 s to 2 s, and further preferably, the exposure duration is 1.8 s; then it is heated at 110 °C for 2 min to complete post-baking, then flood exposure is completed in Flood-E mode for 5 s, and the silicon wafer substrate is placed in the developer solution and shaken for development for 40 s to 60 s, and further preferably for 45 s;

[0016] The upper dielectric layer and the lower dielectric layer are made of the same material, which is a dielectric with a dielectric constant not less than 3K;

[0017] It should be noted that the degluing refers to removing the photoresist, and the photoresist is a negative photoresist. The negative photoresist becomes less soluble in the exposed area. Under the action of light, the molecules of the photoresist undergo a cross-linking reaction, so that the exposed part of the photoresist is not removed in the developer, and the unexposed part is removed by development. Therefore, the final pattern is consistent with the opaque part on the mask.

[0018] Preferably, the materials for making the upper dielectric layer and the lower dielectric layer are any one of SiO2, Si3N4, Al2O3, phosphosilicate glass, borosilicate glass, or semi-insulating polysilicon, and further preferably SiO2. On the one hand, SiO2 has a relatively high dielectric constant, which improves the isolation performance of the device. On the other hand, it effectively reduces the leakage current of the device and significantly improves the overall electrical performance of the device.

[0019] The degluing is preferably carried out using an NMP solution (N-Methylpyrrolidone); further preferably, the steps of degluing include: heating the NMP solution to 60 °C, then placing the substrate in the NMP solution, and finally putting it into an ultrasonic cleaner for cleaning for 10 min until the metal in the exposed area is completely stripped;

[0020] Preferably, the step of fabricating the lower dielectric layer on the substrate by using the room-temperature PECVD process is as follows: placing the substrate in a room-temperature PECVD instrument, pumping the vacuum degree to below 3 mTorr, then first introducing SiH4 gas for 90 s, and then introducing N2O gas for 110 s, and controlling the thickness of the dielectric layer to be 100 nm to avoid substrate leakage affecting subsequent tests;

[0021] Preferably, the steps of photolithographing source-drain metal patterns and metal lead patterns on the first substrate are as follows: The substrate is ultrasonically treated in acetone, alcohol, and deionized water for 5 minutes respectively, then placed on a heating table and dried at 100°C for 10 minutes, pretreated with HDMS for 800 seconds, and then the silicon wafer substrate is adsorbed onto a spin coater. AZ5214 photoresist is dropped onto the surface and spin-coated. The initial speed of spin coating is 0 rpm, and it is accelerated to 100 rpm at an acceleration of 500 rpm / s. The acceleration and constant speed time in this stage last for a total of 5 seconds; then it is accelerated to 4000 rpm at an acceleration of 1000 rpm / s, and the acceleration and constant speed time in this stage last for a total of 45 seconds; then it is decelerated to 0 rpm at an acceleration of 1000 rpm / s, and the deceleration and stop time in this stage last for a total of 5 seconds. Then it is heated at 95°C for 1 minute and 40 seconds to complete pre-baking. A photolithography mask plate is used. For example, when fabricating an H-bridge circuit, the mask plate is engraved with four transistors. The source electrodes of the upper bridges on both sides are respectively connected to the corresponding drain electrodes of the lower bridges. The drain electrodes of the upper bridges on both sides are connected to form an input terminal, and the source electrodes of the lower bridges on both sides are connected to form a grounding terminal. Then, it is operated according to the steps of exposure, post-baking, flood exposure, and development in the above photolithography operation. Finally, it is cleaned and blown dry with deionized water;

[0022] Preferably, the step of evaporating source-drain metal on the second substrate includes: placing the second substrate in an evaporator and evaporating 5 nm of metal Ni and 40 nm of metal Cu. Preferably, at a speed of evaporate 5 nm of metal Ni, and then at a speed of evaporate 5 nm of metal Cu, then at a speed of evaporate 30 nm of metal Cu, and finally at a speed of evaporate 5 nm of metal Cu. Using a lower rate for the source-drain metal can improve the surface flatness of the metal, reduce the threshold voltage of the device, and improve the performance.

[0023] Preferably, the step of fabricating a semiconductor layer on the fourth substrate includes: ultrasonically treating the fourth substrate in deionized water and alcohol for 3 minutes respectively, then drying it with nitrogen and placing it in an ultraviolet ozone machine for 30 minutes; then adsorbing the substrate onto a spin coater, dropping a 5 mg / ml DPPT-TT / DCB solution onto the surface and spin-coating. The initial speed of spin coating is 0 rpm, and it is accelerated to 500 rpm at an acceleration of 200 rpm / s. The acceleration and constant speed time in this stage last for a total of 10 seconds; then it is accelerated to 1500 rpm at an acceleration of 500 rpm / s, and the acceleration and constant speed time in this stage last for a total of 60 seconds; then it is decelerated to 0 rpm at an acceleration of 500 rpm / s, and the deceleration and stop time in this stage last for a total of 5 seconds. Then it is heated at 80°C for 5 minutes and then annealed at 150°C for 1 hour;

[0024] Preferably, the step of fabricating the upper dielectric layer on the top of the semiconductor layer includes: placing the fifth substrate in a room-temperature PECVD instrument, evacuating the vacuum to below 3 mTorr, then introducing SiH4 gas for 252 s, followed by introducing N2O gas for 312 s, controlling the thickness of the upper dielectric layer to be 300 nm to protect the semiconductor layer from being affected during processes such as photolithography, development, and resist stripping;

[0025] Preferably, the step of lithographically patterning the via hole structure on the upper dielectric layer includes: pre-treating with HDMS for 800 s, then adsorbing the silicon wafer substrate onto a spin coater, dropping AZ5214 photoresist onto the surface for spin coating. The initial speed of spin coating is 0 rpm, accelerating at an acceleration of 500 rpm / s to 100 rpm. The acceleration and constant-speed time in this stage last for a total of 5 s; then accelerating at an acceleration of 1000 rpm / s to 4000 rpm, and the acceleration and constant-speed time in this stage last for a total of 45 s; then decelerating at an acceleration of 1000 rpm / s to 0 rpm, and the deceleration and stop time in this stage last for a total of 5 s. Then heat at 95 °C for 1 min 40 s to complete pre-baking. The mask plate uses a photolithography mask plate with a via hole pattern engraved on it. Then operate according to the steps of exposure, post-baking, flood exposure, and development in the above lithography operation, and clean and dry with deionized water.

[0026] Preferably, the step of etching the inner via hole includes: placing the silicon wafer substrate coated with the inorganic dielectric layer in a grinding machine, and after development, putting the substrate into an etching machine, introducing O2, controlling the etching diameter to be about 5 mm, and the depth to reach 450 nm.

[0027] Preferably, the step of evaporating and filling metal in the via hole includes: placing the substrate after etching the via hole in an electron beam evaporation instrument, controlling the evaporation rate of metal Cu at The evaporated film thickness is 250 nm.

[0028] Preferably, the step of evaporating the gate electrode includes: putting the substrate after lithographically patterning the gate electrode pattern into an evaporator to evaporate 80 nm of metal Cu, wherein, evaporating 5 nm of metal Cu at a speed of After that, evaporating 70 nm of metal Cu at a speed of Finally, evaporating 5 nm of metal Cu at a speed of

[0029] The present invention has the following beneficial effects:

[0030] ​The manufacturing method of the power integrated circuit described in this application uses the upper dielectric layer as a photolithography blocking layer and combines via technology to successfully introduce photolithography technology into the preparation of organic circuits. This preparation technology can integrate multiple organic field-effect transistors on the same substrate, and the organic field-effect transistors can achieve effective interconnection. The interdigital channel structure can significantly increase the conduction current of the circuit and reduce the on-resistance by optimizing the carrier transport path inside the device. At the same time, this structure can effectively reduce the circuit, thereby greatly reducing the circuit power consumption and improving the energy utilization efficiency.

[0031] This application is based on the prior research results of this research group, which applies copolymer organic field-effect transistors to the field of power integrated circuits. A single device can dynamically switch between N-type (electron transport) and P-type (hole transport) bipolar conduction modes. This polarity-reconfigurable characteristic breaks through the physical limitations of traditional power devices, enabling the H-bridge circuit to be constructed using homogeneous devices, simplifying the process flow while achieving free configuration of the topological structure, laying the foundation for the design of high-density power integrated circuits. The copolymer organic field-effect transistor can be dynamically switched between N-type and P-type operating modes through gate voltage regulation. This characteristic not only simplifies the circuit design process but also provides new possibilities for multifunctional integration. Specifically, by flexibly adjusting the gate connection method and bias voltage through a servo control circuit, multiple circuit functions can be achieved with only two transistors, including N-type or P-type inverters, CMOS inverters, and single-stage amplifiers. This circuit reconstruction ability based on gate voltage regulation significantly improves the flexibility and functionality of the integrated circuit, provides a new solution for the design of power electronic systems, and has broad application prospects.

[0032] Therefore, through further development, this application has improved the manufacturing process at the production level of power integrated circuits based on the interdigital channel structure. First, the invention adopts an innovative structural design, unifying the inorganic dielectric layer and the lithography barrier layer into the same inorganic material such as SiO2. This integrated design can effectively encapsulate the semiconductor layer while precisely controlling the thickness of the dielectric layer, thus bringing significant technical advantages: on the one hand, it greatly improves the gate control performance of the device; on the other hand, it effectively reduces the leakage current of the device, significantly improving the overall electrical performance of the device. Secondly, a dielectric layer structure is designed by combining a multi-layer composite lithography mask system with a high-k dielectric material to form a chemical passivation barrier at the nanoscale (50 - 100 nm thickness), which can completely block the penetration of common organic solvents such as developer (e.g., TMAH), NMP solvent (N-methylpyrrolidone), and acetone, reducing the surface roughness of the semiconductor functional layer and also having better gate control performance for the device, greatly improving the on-state characteristics of the device. Thirdly, deep high-aspect-ratio vias are interconnected through self-aligned lithography technology, significantly reducing the device cell area, making it compatible with the 10-μm linewidth lithography process. At least fourteen finished products can be obtained in one process, with better efficiency and precision, supporting 4-inch wafer-level high-density integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Schematic diagram of the structure of the all-lithography organic field-effect transistor with the interdigital structure of the present invention;

[0034] Figure 2 Layout of the H-bridge circuit constructed based on the organic field-effect transistor;

[0035] Figure 3 For Figure 2 Enlarged view of the interdigital structure area in

[0036] Figure 4 Physical object of the H-bridge circuit fabricated based on the organic field-effect transistor prepared in Example 1;

[0037] Figure 5A Schematic diagram of the changes in the first stage during the fabrication process of the organic field-effect transistor of the present invention;

[0038] Figure 5B Schematic diagram of the changes in the second stage during the fabrication process of the organic field-effect transistor of the present invention;

[0039] Figure 5C Schematic diagram of the changes in the third stage during the fabrication process of the organic field-effect transistor of the present invention;

[0040] Figure 5D Schematic diagram of the changes in the fourth stage during the fabrication process of the organic field-effect transistor of the present invention;

[0041] Figure 6 For the signal acquisition result of Test Example 1;

[0042] Figure 7 For the photo of the intermediate product of Comparative Example 1;

[0043] Figure 8A For the photo of the intermediate product of Comparative Example 2;

[0044] Figure 8B For the photo of the finished product of Comparative Example 2;

[0045] Figure 9 For the photo of the intermediate product of Comparative Example 3;

[0046] Figure 10 For the photo of the intermediate product of Comparative Example 4;

[0047] Figure 11 For the state after completing step S4, i.e., gate metal stripping, of Example 1

[0048] Figure 12 For the state after completing step S2, i.e., photolithography and development, of Example 1;

[0049] Figure 13 For the state of the product after all steps of Example 1 are completed;

[0050] Figure 14 For the forward conduction characteristic curve graph of the product fabricated in Example 1 measured at room temperature under different gate voltages. Detailed implementation manners

[0051] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific preferred implementation manners.

[0052] In the description of the present invention, it should be understood that the orientation or positional relationships indicated by terms such as "left side", "right side", "upper part", "lower part", etc. are based on the orientation or positional relationships shown in the accompanying drawings. These are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. The specific dimensions adopted in this embodiment are only for illustrating the technical solution and do not limit the protection scope of the present invention.

[0053] The sources of the kit raw materials used in the following examples and test examples are as follows:

[0054] DPPT-TT: Nanjing Zhiyan Technology Co., Ltd.;

[0055] 1,2-dichlorobenzene (DCB) solution: Sigma-Aldrich Corporation;

[0056] PMMA: Shanghai Hansi Chemical Co., Ltd.;

[0057] The NMP solution was purchased from Shanghai Aladdin Biochemical Technology Co., Ltd.;

[0058] The HDMS pretreatment was carried out using the JS-HDMS90 instrument from Shanghai Juns Experimental Instrument Co., Ltd.;

[0059] Lithography equipment model: MA6;

[0060] The AZ5214 photoresist was purchased from Shaanxi Sidi Technology Co., Ltd.;

[0061] Fabrication of the H-bridge circuit of a fully lithographic organic field-effect transistor based on the interdigital structure in Example 1

[0062] This example provides the manufacturing steps of an H-bridge circuit of a fully lithographic organic field-effect transistor based on the interdigital structure, which are as follows:

[0063] Step S1, through the room-temperature PECVD process, a 100-nm dielectric layer is formed on a 4-inch wafer substrate. The specific growth method is preferably: placing the wafer substrate in a room-temperature PECVD instrument, pumping the vacuum degree to below 3 mTorr, then introducing SiH4 gas for 90 s first, and then introducing N2O gas for 110 s, controlling the thickness of the dielectric layer to be 100 nm, and placing the substrate to prevent leakage from affecting subsequent tests;

[0064] Step S2, lithographing the source-drain metal pattern on the substrate fabricated in step S1: ultrasonically cleaning the substrate in acetone, alcohol, and deionized water for 5 min respectively, then placing it on a heating table and drying it at 100 °C for 10 min, then pretreating it with HDMS for 800 s, then adsorbing the silicon wafer substrate onto a spin coater, dropping the AZ5214 photoresist onto the surface for spin coating. The initial speed of spin coating is 0 rpm, accelerating to 100 rpm at an acceleration of 500 rpm / s. The acceleration and constant speed time in this stage last for 5 s in total; then accelerating to 4000 rpm at an acceleration of 1000 rpm / s. The acceleration and constant speed time in this stage last for 45 s in total; then decelerating to 0 rpm at an acceleration of 1000 rpm / s. The deceleration and stop time in this stage last for 5 s in total. After the photoresist is spin-coated onto the substrate surface, it is then heated at 95 °C for 1 min 40 s to complete pre-baking. The mask plate uses a lithography mask plate, and there are four transistors engraved on the mask plate. The source electrodes of the two upper bridges on both sides are respectively connected to the corresponding drain electrodes of the lower bridges. The drain electrodes of the two upper bridges on both sides are connected to form the input terminal, and the source electrodes of the two lower bridges on both sides are connected to form the ground terminal. The lithography mode is Hard mode, the exposure duration is 1.8 s, then heated at 110 °C for 2 min to complete post-baking, then flood exposure is completed in Flood-E mode for 5 s, the silicon wafer substrate is put into the developer and shaken for development for 45 s, and finally washed and dried with deionized water;

[0065] Step S3, complete source-drain metal evaporation: Place the silicon wafer substrate into an evaporator and evaporate 5 nm of metal Ni and 40 nm of metal Cu. Among them, evaporate 5 nm of metal Ni at a speed, and then evaporate 5 nm of metal Cu at a speed. After that, evaporate 30 nm of metal Cu at a speed, and finally evaporate 5 nm of metal Cu at a speed. Using a lower rate for the source-drain metal can improve the surface flatness of the metal, reduce the threshold voltage of the device, and improve the performance.

[0066] Step S4, complete degluing using NMP solution: First, heat the NMP solution to 60 °C, then place the wafer substrate after evaporation into the NMP solution, and finally put it into an ultrasonic cleaner and clean for 10 min. Pay attention to observing whether the metal in the non-source-drain area is peeled off completely.

[0067] Step S5, fabricate the semiconductor layer: Ultrasonically clean the silicon wafer substrate with deposited source-drain electrodes and leads in deionized water and alcohol for 3 min respectively, then dry it with nitrogen and place it in an ultraviolet ozone machine for 30 min. Then adsorb the silicon wafer substrate onto a spin coater, drop the 5 mg / ml DPPT-TT / DCB solution onto the surface, and spin coat it onto the substrate surface. The initial speed of spin coating is 0 rpm, and it accelerates to 500 rpm at an acceleration of 200 rpm / s. The total acceleration and constant speed time in this stage lasts for 10 s; then it accelerates to 1500 rpm at an acceleration of 500 rpm / s, and the total acceleration and constant speed time in this stage lasts for 60 s; after that, it decelerates to 0 rpm at an acceleration of 500 rpm / s, and the total deceleration and stop time in this stage lasts for 5 s. Then heat it at 80 °C for 5 min, and then anneal it at 150 °C for 1 h;

[0068] Step S6, fabricate the upper dielectric layer: Through the room-temperature PECVD process, generate an upper dielectric layer with a thickness of not less than 200 nm on the top of the semiconductor layer. The specific growth method is as follows: Place the silicon wafer substrate with evaporated source-drain electrodes into a room-temperature PECVD instrument, evacuate the vacuum degree to below 3 mTorr, then first introduce SiH4 gas for 252 s, and then introduce N2O gas for 312 s, and control the thickness of the dielectric layer to be 300 nm to protect the semiconductor layer from being affected during photolithography, development, and degluing processes;

[0069] Step S7, defining the via hole structure pattern on the dielectric layer by lithography: Pretreat with HDMS for 800 s, then adsorb the silicon wafer substrate onto the spin coater, drop AZ5214 photoresist onto the surface, and spin coat it onto the substrate surface. The initial spin speed is 0 rpm, and it is accelerated to 100 rpm at an acceleration of 500 rpm / s. The acceleration and constant speed time in this stage last for 5 s in total; then it is accelerated to 4000 rpm at an acceleration of 1000 rpm / s, and the acceleration and constant speed time in this stage last for 45 s in total; then it is decelerated to 0 rpm at an acceleration of 1000 rpm / s, and the deceleration and stop time in this stage last for 5 s in total. Then it is heated at 95 °C for 1 min 40 s to complete pre-baking. The mask is a lithography mask, and the via hole pattern is engraved on the mask. The lithography mode is Hard mode, and the duration is 1.8 s. Then it is heated at 110 °C for 2 min to complete post-baking. Then it is flood-exposed in Flood-E mode for 5 s. The silicon wafer substrate is put into the developer and shaken for development for 45 s, and then washed and dried with deionized water; Etch the via holes in the dielectric layer. The specific etching method is preferably: Place the silicon wafer substrate coated with the inorganic dielectric layer in the grinding machine. After development, put the substrate into the etching machine, introduce O2, and then control the etching thickness to 450 nm and the diameter to about 5 mm.

[0070] Step S8, place the substrate with the etched via holes in the electron beam evaporation instrument, and control the evaporation rate of metal Cu at The evaporation film thickness is 250 nm.

[0071] Step S9, complete the degluing. Similar to step S3, complete the metal stripping in the non-via hole area.

[0072] Step S10, lithograph the gate electrode pattern: Similar to step S4, complete the HDMS pretreatment, spin coat the photoresist, pre-bake, expose, post-bake, flood-expose, develop and other steps;

[0073] Step S11, deposit the gate electrode: Put it into the evaporation instrument to deposit 80 nm of metal Cu. Among them, deposit 5 nm of metal Cu at a speed of , and then deposit 70 nm of metal Cu at a speed of , and finally deposit 5 nm of metal Cu at a speed of ;

[0074] Step S12, complete the degluing: Similar to step S3 and step S8;

[0075] As Figure 4 shown Figure 1 The physical diagram of the corresponding copolymer organic thin film transistor integrated circuit after completion of production.

[0076] Under the condition of shorter exposure time in Comparative Example 1

[0077] The intermediate product produced in Comparative Example 1 corresponds to Steps S1 to S4 in Example 1. The difference from Example 1 is only that in Step S2, the exposure time is 0.6 s, and the remaining operations and parameters are the same;

[0078] As can be seen from Figure 7 , the photoresist did not react sufficiently, resulting in incomplete pattern transfer, blurred pattern edges, decreased resolution, and poor control of the line width CD.

[0079] Under the condition of a longer exposure time in Comparative Example 2

[0080] Two batches of products were produced in Comparative Example 2. The first batch of intermediate products corresponds to Steps S1 to S3 in Example 1; the second batch of final products corresponds to Steps S1 to S12 in Example 1. The difference between the intermediate products of the two batches in Comparative Example 2 and Example 1 is only that in Step S2, the exposure time is 3 s, and the remaining operations and parameters are the same;

[0081] As can be seen from Figure 8A , the photoresist reacts excessively, which may cause the diffusion of photoacid (for chemically amplified resists), resulting in the proximity effect, that is, the adjacent area is accidentally exposed; as can be seen from Figure 8B , it can be seen that the resolution of the prepared final product is reduced, and small-sized structures may adhere or deform; the internal stress of the photoresist increases, which may affect subsequent etching or deposition processes.

[0082] In Comparative Example 3, the development time is insufficient

[0083] The intermediate product produced in Comparative Example 1 corresponds to Steps S1 to S2 in Example 1. The difference from Example 1 is only that in Step S2, the development time is 30 s, and the remaining operations and parameters are the same;

[0084] As can be seen from Figure 9 , it can be seen that the unreacted photoresist is not completely removed, and the residue may contaminate subsequent processes such as etching or deposition. The pattern edges are not clear, resulting in defects such as short circuits or open circuits in subsequent processes.

[0085] In Comparative Example 4, the development is excessive

[0086] The intermediate product produced in Comparative Example 1 corresponds to Steps S1 to S2 in Example 1. The difference from Example 1 is only that in Step S2, the development time is 1 min 40 s, and the remaining operations and parameters are the same;

[0087] As Figure 10 shown, excessive dissolution may erode the formed pattern structure, resulting in a narrower line width, edge collapse, or structural damage. For negative resists, it may accidentally damage the unexposed area and destroy the pattern integrity.

[0088] Based on the appropriate exposure time and development time in Example 1, the production effects at different stages in Example 1 are as follows. Among them Figure 11 is the state after completing step S4, i.e., gate metal stripping, in Example 1. It shows that the source-drain metal pattern is clear, has a high integrity, and the surface is flat, with a very good display effect; Figure 12 is the effect of the corresponding interdigital channel under an electron microscope after lithography and development in step S2 of Example 1. The channel contour is clear and complete; Figure 13 is the product after all steps of Example 1 are completed. During testing, the overall finished product pattern is clear and the surface is flat.

[0089] Test Example 1

[0090] This embodiment demonstrates the working principle of the copolymer organic semiconductor power integrated circuit: First, the device power supply terminal VDD is connected to a DC power supply for power supply. Thanks to the unique material properties of the organic field-effect transistor, by applying different gate biases (positive bias or negative bias), the device can be flexibly regulated to exhibit N-type or P-type characteristics. In order to avoid dead time during testing, reduce the complexity of testing, and minimize some unnecessary problems, only a signal is applied to two transistors at opposite corners of the H-bridge module circuit during our testing to achieve the circuit conduction function. In a specific experimental setup, a PWM control signal with a frequency of 100 Hz and a duty cycle of 50% is applied to the gates of the two transistors arranged diagonally. As Figure 6 shown, a 1 MΩ resistor is connected in parallel across the load in the experimental circuit, and a dual-channel oscilloscope is configured for signal acquisition to obtain the Vout1 waveform close to the upper transistor and the Vout2 waveform close to the lower transistor respectively. The experimental results show that the device can achieve the expected circuit function and exhibits good working characteristics.

[0091] Test Example 2

[0092] As Figure 14 shown is the forward conduction characteristic curve graph of the product fabricated in Example 1 measured at room temperature under different gate voltages. It can be seen that at a relatively small source-drain voltage, the source-drain current can be as high as hundreds of μA, indicating that the device has a small on-resistance, meeting the expected effect of the device.

Claims

1. Application of a fully lithographed organic field effect transistor based on an interdigital structure in fabricating a power integrated circuit, characterized in that, The power integrated circuit includes a plurality of all-lithographed organic field effect transistors with interdigital structures, and the organic field effect transistor is a top-gate bottom-contact structure; the manufacturing method of the power integrated circuit includes the steps of: using a room-temperature PECVD process to fabricate a lower dielectric layer on the original substrate as the first substrate, and after lithographing the source-drain metal pattern and the metal lead pattern on the first substrate, it serves as the second substrate; The lithography steps sequentially include: HDMS pretreatment, spin-coating photoresist, pre-baking, exposure, post-baking, flood exposure, development, cleaning and drying; after evaporating the source-drain metal and the metal leads on the second substrate, it serves as the third substrate; the third substrate is subjected to a degluing process and after degluing, it serves as the fourth substrate; after fabricating an organic semiconductor layer on the fourth substrate, it serves as the fifth substrate. The material for fabricating the organic semiconductor layer is a copolymer organic material. A upper dielectric layer is fabricated on the top of the semiconductor layer by using a room-temperature PECVD process. The via hole structure pattern is lithographed on the upper dielectric layer by lithography technology. After etching the via holes, metal is evaporated in the via holes, and the metal in the non-via hole area is stripped after degluing; the gate electrode pattern is lithographed. Except that the lithography mask pattern is different, the steps for lithographing the gate electrode pattern are the same as those for lithographing the source-drain metal pattern; Among them, the steps of exposure, post-baking, flood exposure, and development in the lithography operation are: using a lithography mask, the lithography mode is Hard mode, and the exposure duration is 1.5 s to 2 s; then it is heated at 110 °C for 2 min to complete post-baking, then flood exposure is completed in Flood-E mode for 5 s, and the silicon wafer substrate is placed in the developer solution and shaken for development for 40 s to 60 s; the materials for fabricating the upper dielectric layer and the lower dielectric layer are the same and are a dielectric with a dielectric constant not lower than 3K.

2. The application according to claim 1, wherein The material for fabricating the organic semiconductor layer is any one of organic pentacene, DPPT-TT, P3HT, or naphthalimide-based N-type polymer.

3. The application according to claim 1, characterized in that, The exposure duration is 1.8 s and the development time is 45 s.

4. The application according to claim 1, wherein The thickness of the lower dielectric layer is 100 nm; the thickness range of the upper dielectric layer is 200 nm to 350 nm.

5. The application according to claim 1, characterized in that, The materials for fabricating the upper dielectric layer and the lower dielectric layer, that is, the dielectric with a dielectric constant not lower than 3K, are selected from any one of SiO2, Si3N4, Al2O3, phosphosilicate glass, borosilicate glass, or semi-insulating polysilicon.

6. The application according to claim 1, characterized in that, The degluing is carried out using an NMP solution.

7. The application according to claim 1, wherein The steps of photolithographing source-drain metal patterns and metal lead patterns on the first substrate are as follows: The substrate is ultrasonically cleaned in acetone, alcohol, and deionized water for 5 minutes respectively, then placed on a heating table and dried at 100°C for 10 minutes. After that, it is pretreated with HDMS for 800 seconds. Then the silicon wafer substrate is adsorbed onto a spin coater, and AZ5214 photoresist is dropped onto the surface and spin-coated. The initial speed of spin coating is 0 rpm, and it is accelerated to 100 rpm at an acceleration of 500 rpm / s. The total acceleration and constant speed time in this stage lasts for 5 seconds. Then it is accelerated to 4000 rpm at an acceleration of 1000 rpm / s, and the total acceleration and constant speed time in this stage lasts for 45 seconds. After that, it is decelerated to 0 rpm at an acceleration of 1000 rpm / s, and the total deceleration and stop time in this stage lasts for 5 seconds. Then it is heated at 95°C for 1 minute and 40 seconds to complete pre-baking. A photolithography mask plate is used, and then it is operated according to the steps of exposure, post-baking, flood exposure, and development in the above photolithography operation. Finally, it is cleaned and blown dry with deionized water.

8. The application according to claim 1, wherein The steps of evaporating source-drain metal on the second substrate include: putting the second substrate into an evaporator and evaporating 5 nm of metal Ni and 40 nm of metal Cu.

9. The application according to claim 1, wherein The steps of fabricating a semiconductor layer on the fourth substrate include: ultrasonically cleaning the fourth substrate in deionized water and alcohol for 3 minutes respectively, then drying it with nitrogen and putting it into an ultraviolet ozone machine for treatment for 30 minutes. Then the substrate is adsorbed onto a spin coater, and a 5 mg / ml DPPT-TT / DCB solution is dropped onto the surface and spin-coated. The initial speed of spin coating is 0 rpm, and it is accelerated to 500 rpm at an acceleration of 200 rpm / s. The total acceleration and constant speed time in this stage lasts for 10 seconds. Then it is accelerated to 1500 rpm at an acceleration of 500 rpm / s, and the total acceleration and constant speed time in this stage lasts for 60 seconds. After that, it is decelerated to 0 rpm at an acceleration of 500 rpm / s, and the total deceleration and stop time in this stage lasts for 5 seconds. Then it is heated at 80°C for 5 minutes, and then annealed at 150°C for 1 hour.

10. The application according to claim 1, wherein The steps of photolithographing a via hole structure pattern on the upper dielectric layer by photolithography technology include: pretreating with HDMS for 800 seconds, then adsorbing the silicon wafer substrate onto a spin coater, dropping AZ5214 photoresist onto the surface and spin-coating. The initial speed of spin coating is 0 rpm, and it is accelerated to 100 rpm at an acceleration of 500 rpm / s. The total acceleration and constant speed time in this stage lasts for 5 seconds. Then it is accelerated to 4000 rpm at an acceleration of 1000 rpm / s, and the total acceleration and constant speed time in this stage lasts for 45 seconds. After that, it is decelerated to 0 rpm at an acceleration of 1000 rpm / s, and the total deceleration and stop time in this stage lasts for 5 seconds. Then it is heated at 95°C for 1 minute and 40 seconds to complete pre-baking. The mask plate uses a photolithography mask plate with a via hole pattern engraved on it, and then it is operated according to the steps of exposure, post-baking, flood exposure, and development in the above photolithography operation, and then cleaned and blown dry with deionized water.

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