Method of manufacturing a monolithic display

Abstract

A method of manufacturing a monolithic micro LED display component (2), the method comprising: depositing an LED (210) on a top surface (205a) of a substrate (205); depositing a base layer (240) over the LEDs (210), the base layer (240) forming a planar layer that isolates the LEDs (210); processing an organic thin film transistor (260), OTFT, on the base layer (240) by depositing a source (256) and a drain (258) and an active channel comprising an organic semiconductor layer (262); and after processing the OTFT (260), etching a base layer hole (242, 244), the base layer hole (242, 244) including a hole through the base layer (240) to allow a connection between the LED (210) and the OTFT (260).

Description

Technical Field

[0001] The present invention relates to the manufacture of monolithic micro-LED displays. Background Art

[0002] Micro-LED displays are an emerging flat panel display technology that uses an array of micro-LEDs to form individual pixels. Compared to earlier liquid crystal displays (LCDs), micro-LED displays have many advantages. For example, since the LEDs are only powered when the pixel is lit and can be completely turned off at other times, micro-LED displays are much more energy efficient and have better contrast. In addition, micro-LED displays have a faster response time, making them more suitable for augmented reality (AR) and virtual reality (VR) applications, where high pixel density and high frame rate are particularly useful.

[0003] Micro-LED displays are often fabricated by transferring micro-LEDs from a source wafer to a receiver substrate (display backplane). This allows RGB displays to be made from separate source micro-LED wafers for red, green, and blue.

[0004] As an alternative to the above, one method of producing micro-LED displays with very high resolution is to directly process the backplane on top of the micro-LEDs on the source wafer, thereby producing a monolithic display. For example, a sapphire substrate can form the underlying layer of the monolithic display, with micro-LEDs and thin film transistors (TFTs) deposited on top. Holes are formed between the TFTs and the micro-LEDs to allow the TFTs to control the micro-LEDs.

[0005] One challenge with this method is processing the materials in the TFT (such as LTPS) at high temperatures, which can damage other components (e.g., micro-LEDs and connections) that are already part of the backplane. Using organic thin film transistors (OTFTs) has been considered, which can be deposited on top of the micro-LEDs at much lower temperatures than inorganic TFTs. While this can reduce damage to other layers, there may be other difficulties with the deposition of OTFTs.

[0006] For example, during the deposition of the OTFT, organic material can fall into the holes that form the connections of the micro-LEDs. In particular, given that these holes can be deep, subsequent etching may not completely remove this material from the inside of the holes. The remaining material in the holes can cause defects in the resulting device, such as hindering the uniform coating of other layers deposited on top of the holes.

[0007] While micro-LED displays are an important example of a technology that suffers from the above manufacturing challenges, the same issues exist when using other types of optoelectronic devices such as LEDs or photodiodes. In particular, any technology that requires processing of interconnects or other types of circuitry, especially OTFTs, on top of the deposited optoelectronic devices will face similar challenges.

[0008] Accordingly, an object of the present invention is to solve one or more of the problems described above. Summary of the Invention

[0009] According to a first aspect of the present invention, there is provided a method of manufacturing a monolithic micro-LED display component, the method comprising: depositing LEDs on a top surface of a substrate; depositing a base layer on top of the LEDs, the base layer forming a planar layer that isolates the LEDs; processing an organic thin-film transistor, OTFT, on the base layer by depositing a source and a drain and an active channel including an organic semiconductor layer; and after processing the OTFT, etching base layer holes, the base layer holes including holes through the base layer to permit connection between the LEDs and the OTFT.

[0010] Advantageously, by processing the OTFT on a layer that isolates the LEDs, etching away the organic layer can be performed more consistently. As used herein, the term "isolates" preferably means that no holes are formed through the base layer prior to processing the OTFT on the base layer. In other words, during processing of the OTFT on the base layer, the base layer is continuous. As used herein, the term "continuous" preferably means that the base layer is substantially flat and / or does not contain holes, such as pores. For example, conversely if holes are formed through the base layer prior to processing the OTFT, it may be difficult to remove the organic material deposited inside the holes during subsequent processing of the OTFT. Typically, the holes connecting to the LEDs can be deep, which makes it particularly difficult to remove the organic material contained therein. In the presence of unwanted organic material, there may be defects when depositing subsequent layers, such as additional passivation layers that may be deposited over and around the OTFT. For example, the presence of unwanted organic material can cause de-wets in the passivation layer, such as due to insulating residues. In the case where a passivation layer is deposited on the OTFT, one or more passivation layer holes may be etched through the passivation layer. At least one of the passivation layer holes may continue through the base layer to provide the base layer holes.

[0011] Preferably, the method further comprises depositing a top contact layer (e.g., an OTFT contact layer), wherein the top contact layer provides connection between the LEDs and the OTFT through the base layer holes.

[0012] A monolithic micro-LED display component can be a "bottom-emitting" display component, where light from the LED is emitted in a downward direction (e.g., through the substrate). Alternatively, the monolithic LED display component can be a "top-emitting" display component, where light from the LED travels upward (i.e., away from the substrate).

[0013] As used herein, the terms "top", "bottom", "above", and "below" refer to the directions and relative positions depicted in the figures. It will be understood that these terms do not require that any of the embodiments described herein can only operate in a particular orientation. The term "top" indicates the growth direction, i.e., the growth direction relative to the substrate (from which the device may or may not have been removed). In other words, the growth direction is perpendicular to the plane defined by the substrate, the LED, and / or the OTFT. It will be understood that the LED can be any other kind of optoelectronic device, such as a photodiode. Additionally, unless otherwise explicitly stated, terms such as "located", "positioned", and "disposed" are only intended to indicate the relative positions of two components or layers, and do not exclude the presence of other components between the two components or layers.

[0014] The base layer is a dielectric layer that isolates the back-gate layer of the OTFT (below the base layer) from the organic semiconductor layer and the source and gate (above the base layer). Preferably, the chemistry of the base layer is adapted to the organic semiconductor layer to facilitate morphological consistency of the organic semiconductor layer. The base layer can be an organic crosslinked layer, where the chemistry is preferably chosen such that it is resistant to residual ionic contamination that can dope the OTFT under bias stress conditions. The base layer can be an acrylate polymer. The base layer can be selected from those layers described in WO2020 / 002914A1. The base layer is preferably resistant to organic solvents. The base layer can have a thickness of 10 nm to 10 μm, preferably 100 nm to 1 μm.

[0015] The OTFT can be processed at an area of the base layer that at least partially overlaps with the LED. In other words, when viewed along the growth direction (i.e., from the top or bottom of the LED display component), the OTFT overlaps with the LED. In this way, when configured as a "bottom-emitting" display component, the performance of the micro-LED display component is improved. Since the OTFT does not need to be positioned so as not to block light from the LED, the OTFT can cover a larger area of the display component. This can allow the OTFT to provide more current, and / or can allow the use of larger LEDs.

[0016] Alternatively, when the micro-LED display component is configured as a "top-emitting" display component, the LED and the OTFT can be located in non-overlapping areas of the display component such that the OTFT does not block the light from the LED traveling in the upward direction.

[0017] Before depositing the base layer, the method may further include: depositing a planarization layer over the LED; etching a planarization layer hole through the planarization layer; depositing an intermediate contact layer on the planarization layer such that the intermediate contact layer is connected to the LED through the planarization layer hole; the method further includes depositing the base layer over the planarization layer and the intermediate contact layer.

[0018] The step of etching the base layer hole may include etching a hole through the base layer to provide a connection to the intermediate contact layer, the method further including depositing an OTFT contact layer that provides a connection between the OTFT and the intermediate contact layer such that the OTFT is connected to the LED through the intermediate contact layer.

[0019] The method may further include: before etching the base layer hole, depositing a passivation layer over the base layer; etching one or more passivation layer holes through the passivation layer; wherein continuing to etch at least one passivation layer hole provides the base layer hole; and wherein the OTFT contact layer is deposited into the passivation layer hole, thereby connecting the LED to the OTFT through the intermediate contact layer.

[0020] The planarization layer may have a thickness such that a portion of the planarization layer located over the LED has a thickness of at least 0.5 μm. Advantageously, this reduces the risk of LED short - circuiting, such as due to thinning of the planarization layer near the LED corners. Preferably, the thickness of the planarization layer is greater than 1 μm, preferably greater than 2 μm.

[0021] The planarization layer provides a substantially planar surface on which other layers are deposited. The planarization layer may provide a (first or middle) passivation layer. Optionally, a bottom passivation layer may be provided below the middle passivation layer (such as directly on the LED). Typically, since the LED protrudes substantially from the substrate (e.g., about 3 to 4 μm), the planarization layer can be thick. Due to the thickness of the planarization layer, deep holes formed in the planarization layer before depositing the organic material can make it particularly difficult to remove the organic material in later stages. As discussed above, the organic material remaining in the holes can cause manufacturing defects.

[0022] The intermediate contact layer may provide the back - gate layer (i.e., back - gate electrode) of the OTFT.

[0023] Alternatively, the back - gate layer of the OTFT may be provided by a layer separate from the intermediate contact layer.

[0024] The intermediate contact layer may include a first region and a second region. The first region is connected to the cathode of the LED through a first planarization layer hole, and the second region is connected to the anode of the LED through a second planarization layer hole. Preferably, the first region and the second region of the intermediate contact layer are electrically isolated from each other. A third region of the intermediate contact layer (i.e., electrically isolated from the first region and the second region) may provide the back gate layer of the OTFT. This may facilitate providing a micro-LED display component with an isolated back gate. Alternatively, the first region or the second region may provide the back gate layer of the OTFT.

[0025] The intermediate contact layer and / or the back gate layer may provide a reflective layer such that light emitted by the LED in the upward direction is reflected by the reflective layer in the downward direction corresponding to the bottom surface of the LED. Advantageously, for a bottom-emitting display, this improves the efficiency of the micro-LED display component and the display as a whole because all or most of the light is emitted in the downward direction through the bottom side of the micro-LED display component. Alternatively, a reflective layer separate from the back gate layer and / or the intermediate contact layer may be provided.

[0026] Processing the OTFT may include depositing one or more dielectric layers on the organic semiconductor layer. The one or more dielectric layers may include an organic gate insulator and / or an anti-sputtering layer. The organic gate insulator may be deposited on the organic semiconductor layer, and the anti-sputtering layer may be deposited on the organic gate insulator. The anti-sputtering layer may be UV-cured. The anti-sputtering layer is arranged to provide resistance to sputter damage to the organic gate insulator and the organic semiconductor layer during subsequent steps (e.g., forming a front gate electrode).

[0027] Processing the OTFT further includes depositing a front gate metal on the one or more dielectric layers. Processing the OTFT further includes at least partially etching away one or more organic layers above the base layer. As used herein, the term "organic layer" may include layers such as an organic semiconductor layer, an organic gate insulator, and an anti-sputtering layer, although different or additional organic layers may be included. Preferably, the etching includes dry etching. By etching away the organic layers, an OTFT is formed at a specific region above the base layer.

[0028] During at least one and preferably all of the OTFT processing steps described above, the base layer may isolate the LED. In cases where processing the OTFT includes additional steps and / or different steps as described above and herein, the base layer is preferably isolated (i.e., kept continuous without etching holes) until the processing of the OTFT is completed. In other words, during the deposition of the organic layers of the OTFT, the base layer is preferably isolated (kept continuous).

[0029] The method may further include: depositing a passivation layer above the OTFT and the base layer, and etching the passivation layer to form one or more passivation layer holes.

[0030] As used herein, the planarization layer between the LED and the base layer may be referred to as the first (or middle) passivation layer, and the passivation layer deposited over the OTFT may be referred to as the second (or top) passivation layer (or second planarization layer). A bottom passivation layer may be provided under the middle passivation layer (such as directly on the LED). One or more holes through the (second) passivation layer may extend to the source and drain of the OTFT. One or more holes through the (second) passivation layer may extend to the front gate electrode of the OTFT.

[0031] (The second) passivation layer may have a thickness of about 2 μm. The first passivation layer and / or the second passivation layer may be an acrylate-based material, such as the material PL-02-02-01 of SmartKem.

[0032] The base layer holes may be formed by continuing to etch at least one of the passivation layer holes through the base layer.

[0033] In other words, one or more passivation layer holes also extend through the base layer to provide the base layer holes. Preferably, the base layer holes extend to the intermediate contact layer. Preferably, the (second) passivation layer and the base layer are etched continuously and more preferably in the same etching step. Alternatively, etching of the (second) passivation layer and the base layer may be completed in different steps. In this way, a connection may be formed between the LED and the OTFT through the intermediate contact layer.

[0034] The method may further include depositing an OTFT contact layer into one or more of the passivation layer holes. The OTFT contact layer facilitates electrical connection through the holes. For example, the OTFT contact layer may connect the drain of the OTFT to a second region of the intermediate contact layer via the upper surface of the (second) passivation layer. In this way, the drain may be connected to the anode of the LED. Alternatively, the source may be connected to the anode. The OTFT contact layer may provide a connection to the front gate electrode of the OTFT. The OTFT contact layer may provide a connection to the cathode of the LED via the first region of the intermediate contact layer.

[0035] The method may further include growing the LED on a source wafer and then transferring the LED from the source wafer to a substrate using an intermediate substrate. In other words, the LED is deposited on the top surface of the substrate using an intermediate layer. Advantageously, only the required amount of the source wafer is needed to form the LED, and the source wafer may be reused to manufacture other LEDs. The LED may be transferred onto the substrate so as to be aligned with the corresponding quantum dot color conversion material. In this way, LEDs of a certain color may be used to produce pixels (or sub-pixels) of different colors, thus allowing the manufacture of color (e.g., RGB) displays.

[0036] The method may further include separating the substrate from the layer above the substrate.

[0037] The OTFTs can be processed at least in part using solution processing techniques. For example, the organic semiconductor layer can be deposited using solution processing methods. In particular, when wet techniques such as solution processing methods are used, the organic layer is more likely to fall into any holes formed through the underlying layer. Thus, when using solution processing methods, it is particularly advantageous to etch the underlying layer holes after processing the OTFTs.

[0038] Alternatively or additionally, the OTFTs can be processed using vacuum deposition techniques.

[0039] According to another aspect of the present invention, there is provided a monolithic micro-LED display component, comprising: an LED having a top surface and an opposite bottom surface; a planar underlying layer formed above the top surface of the LED; an organic thin film transistor, an OTFT, at least partially processed on the upper surface of the underlying layer; a passivation layer deposited on the OTFT; and an underlying layer hole etched through the underlying layer and the passivation layer to allow an electrical connection between the LED and the OTFT.

[0040] Since the underlying layer hole is etched through the underlying layer and the passivation layer, the hole must be formed after the OTFTs have been processed on the underlying layer. As described above, forming the underlying layer hole after processing the OTFTs prevents organic materials from depositing into existing holes, and the deposition of organic materials into existing holes can cause defects when subsequent layers are deposited on top.

[0041] The integrated circuit can further include a substrate having a top surface and an opposite bottom surface, wherein the LED is formed on the top surface of the substrate.

[0042] The monolithic micro-LED display component can further include an intermediate contact layer formed above the lower surface of the underlying layer and electrically connected to the LED, wherein the underlying layer hole is connected to the intermediate contact layer. The underlying layer and / or the intermediate contact layer can be deposited on a planarization layer formed above the top surface of the LED. The intermediate contact layer can provide a backgate layer for the OTFT.

[0043] As used herein, the term "formed" preferably indicates that the base layer is located above the top surface of the LED. As used herein, the term "processed" preferably indicates that the OTFT is located on the upper surface of the base layer. As used herein, the term "deposited" preferably indicates that the passivation layer is located above the OTFT. The term "etched" preferably indicates that a hole passes through a specific layer, which can be achieved using an etching process. According to another aspect of the present invention, there is provided a monolithic micro-LED display component, comprising: an LED having a top surface and an opposite bottom surface; a planar base layer located above the top surface of the LED; an organic thin-film transistor, OTFT, at least partially located on the upper surface of the base layer; a passivation layer located above the OTFT; and a base layer hole passing through the base layer and the passivation layer to allow an electrical connection between the LED and the OTFT.

[0044] According to another aspect of the present invention, there is provided a monolithic micro-LED display component, comprising: an LED having a top surface and an opposite bottom surface; a planar base layer formed above the top surface of the LED; an organic thin-film transistor, OTFT, processed on at least a portion (e.g., continuous) of the upper surface of the base layer; and a base layer hole etched through the base layer (e.g., through any organic material remaining after processing the OTFT) to allow an electrical connection between the LED and the OTFT. As described above, forming the base layer hole after processing the OTFT prevents organic material from depositing into existing holes, and the deposition of organic material into existing holes can cause defects when subsequent layers are deposited on top.

[0045] According to another aspect of the present invention, there is provided a monolithic micro-LED display component, comprising: an LED having a top surface and an opposite bottom surface; a planarization layer formed above the top surface of the LED; an intermediate contact layer deposited on the planarization layer such that the intermediate contact layer passes through the planarization layer to connect to the LED; a planar base layer formed above the intermediate contact layer; an organic thin-film transistor, OTFT, processed on at least a portion of the upper surface of the base layer; and a base layer hole etched through the base layer to the intermediate contact layer to allow an electrical connection between the LED and the OTFT.

[0046] The intermediate contact layer can provide a back-gate layer for the OTFT. The intermediate contact layer can be connected to the LED via a planarization layer hole etched through the planarization layer.

[0047] Since the problems that occur during the manufacture of existing display components are present regardless of the type of LED used, it will be understood that any of the aspects described above and herein can be applied to other LED display components as well as micro-LED display components. Accordingly, it will be understood that the methods and devices described herein can use LEDs of any size. As used herein, the term "LED" can be used to refer to micro-LEDs and LEDs of other sizes.

[0048] In addition, while the above discussion generally relates to the use of light-emitting optoelectronic devices such as LEDs (i.e., thereby providing an LED display component), it should be understood that the LED can be replaced with a light-detecting optoelectronic device such as a photodiode (i.e., thereby providing a photodetector array). In this manner, a monolithic photodetector array can be provided that can be used to sense incident light rather than emit light. In other words, the direction of light propagation and the operation of the device are effectively reversed to provide a photodetector. When referring to a photodetector array, any of the above-described light propagation directions with respect to the display component can be reversed, although the manufacturing steps and corresponding advantages of the above manufacturing process generally remain the same. For example, the reflective layer not only increases the proportion of light emitted by the display but also increases the proportion of light detected by the photodetector array. In the case of using a photodiode, the OTFT can alternatively be operated to provide a reading of the electrical signal from the photodiode. A GaN or other inorganic diode array can be coupled to the OTFT backplane in a manner similar to the displays described above and herein. Those skilled in the art benefiting from the present disclosure will be aware of any modifications to the display components described above that would be required to alternatively provide a photodetector array.

[0049] According to another aspect of the present invention, there is provided a method of manufacturing a monolithic LED display component, the method comprising: depositing an LED on a top surface of a substrate; depositing a base layer over the LED, the base layer forming a planar layer that isolates the LED; fabricating an organic thin-film transistor, OTFT, on the base layer by depositing a source and a drain and an active channel including an organic semiconductor layer; and after fabricating the OTFT, etching base layer holes, the base layer holes including holes through the base layer to permit connection between the LED and the OTFT.

[0050] According to another aspect of the present invention, there is provided a monolithic LED display component, comprising: an LED having a top surface and an opposite bottom surface; a planar base layer formed above the top surface of the LED; an organic thin film transistor, OTFT, fabricated on at least a portion of the upper surface of the base layer; a passivation layer deposited over the OTFT; and a base layer via etched through the base layer and the passivation layer to permit electrical connection between the LED and the OTFT.

[0051] Those skilled in the art will understand that any device feature described herein may be provided as a method feature and vice versa. It will also be understood that particular combinations of the various features described and defined in any aspect herein may be implemented and / or provided and / or used independently.

[0052] Furthermore, it will be understood that the present invention is described herein by way of example only and that modifications to details may be made within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Reference will now be made to the drawings, in which one or more embodiments will be described by way of example only, in which:

[0054] Figures 1A to 1P A first method of fabricating a monolithic display component is depicted;

[0055] Figure 2A and Figure 2B Depicts defects that may occur during the method of Figures 1A to 1P ;

[0056] Figures 3A to 3J A preferred method of fabricating a monolithic display component according to the present invention is depicted;

[0057] Figure 4 Depicts an embodiment of a monolithic display component that can be formed using the method shown in Figures 3A to 3J ; and

[0058] Figures 5A to 5K A method of fabricating a monolithic display component according to the present invention is depicted. DETAILED DESCRIPTION

[0059] In the following description and drawings, corresponding reference numerals may preferably be used to identify corresponding features to avoid the need to describe in detail the common features for each embodiment.

[0060] A method of fabricating monolithic micro-LED display components 1, 2, 3, 4 will now be described in detail. Generally, the method involves depositing (or growing) at least one LED and at least one organic thin film transistor (OTFT) on a substrate, where holes provide electrical connection between the LED and the OTFT.

[0061] Although the following description will generally describe the display component with reference to a single LED and a single OTFT, it should be understood that the display component may comprise a large array of LEDs, where each LED may have one or more corresponding OTFTs. For example, the LED array may provide an array of pixels. Additionally, each pixel of the display component may include sub-pixels, which may be configured to emit light of a predetermined color, e.g., to provide an RGB display. It will also be understood that for each LED, more than one OTFT may be provided, and other components such as capacitors may be present. For example, each LED may have a corresponding switching TFT and a driving TFT, as further described with reference to Figure 4 as described further below.

[0062] Other components may be combined with the display component so as to provide a display device. For example, a protective layer, a frame, electrical connections, and / or any other suitable components may be combined with the display component.

[0063] As used herein, the term "monolithic" means depositing (or "growing") the OTFT device on a substrate that contains the LED, rather than transferring the LED to a substrate that contains the OTFT device. In this way, the substrate may be referred to as the "source wafer". The deposition of the layers forming the LED component may be achieved in a variety of ways, including chemical vapor deposition (CVD) techniques such as plasma-enhanced chemical vapor deposition (PECVD) or metalorganic chemical vapor deposition (MOCVD), epitaxial techniques such as metalorganic vapor phase epitaxy (MOVPE) or molecular beam epitaxy (MBE), vacuum deposition techniques, solution processing techniques, and / or mass transfer techniques. These techniques allow thin films (or "layers") of materials to be deposited on the substrate so as to form the monolithic micro-LED display component. Throughout the process, portions of the layers may be selectively removed in a process called patterning, which may be achieved by (dry) etching. In this way, regions of each layer may be electrically isolated from one another, and channels (e.g., holes) for forming electrical paths through the layers may be formed.

[0064] Preferably, the display component described herein is configured as a "bottom-emitting" display component, where light from the LED is emitted in the downward direction (i.e., through the substrate). In this configuration, when looking along the growth direction, the OTFT can be located in the area overlapping with the LED, because the OTFT does not need to be positioned to block the light from the LED. This can allow the LED and / or the OTFT to occupy a larger area of the display component, which can allow the OTFT to provide more current. When configured as a bottom-emitting display component, the substrate is preferably at least partially transparent; alternatively or additionally, the substrate can be removed at the end of the manufacturing process. Although the bottom-emitting display component is preferred, the display component can be a top-emitting display component, where the LED and the OTFT are located in non-overlapping areas in the display component so that the OTFT does not block the light from the LED traveling in the upward direction.

[0065] Now, a first method of manufacturing the monolithic micro-LED display component 1 will be described with reference to Figures 1A to 1P Figure.

[0066] In Figure 1A Figure, a substrate 105 is provided, which has a top surface 105a and an opposite bottom surface 105b. The substrate 105 can be a sapphire wafer, although other materials such as zinc oxide, silicon oxide, or silicon carbide can be used. The substrate layer 105 is preferably polished on the bottom surface 105b so as not to affect the quality of the image from the display component 1. The substrate 105 can be polished on the top surface 105a or can be patterned on the top surface 105a, thereby reducing the stress on the layer grown on top of the substrate 105. More specifically, the substrate 105 can be a c-oriented tapered patterned sapphire substrate (CPSS), or can be a conventional unpatterned planar sapphire substrate (USS).

[0067] Subsequently, a cathode layer 112 can be deposited on the top surface 105a of the substrate 105, as Figure 1B shown. The cathode layer 112 can include n-gallium nitride (n-GaN), which can grow on top of the sapphire substrate 105 due to the proper lattice matching between GaN and the sapphire crystal.

[0068] In Figure 1CIn [description], an LED structure 113 is deposited on a cathode layer 112. The LED structure 113 may include a multiple quantum well (MQW) structure, which includes InGaN layers and GaN layers. For example, the LED structure 113 may include a GaN nucleation layer (e.g., 25 nm thick), an undoped GaN layer (e.g., 2.5 μm thick), a highly doped n-type GaN layer (e.g., 2 μm thick), multiple InGan(4.6 nm) / GaN(5.2 nm) MQW pairs (e.g., 13 pairs), a p-type AlGaN electron blocking layer (e.g., 25 nm thick), and a Mg-doped GaN layer (e.g., 100 nm thick). It will be understood that the layers and materials described above are merely exemplary, and other layers and materials may be used.

[0069] Additionally, an anode layer 114 is deposited on top of the LED structure 113. The anode layer 114 may be indium tin oxide (ITO). An electron beam evaporator may be used to deposit the anode layer 114.

[0070] In Figure 1D [description], the LED structure 113 and the anode layer 114 are etched to provide an LED 110 at a specific location on the cathode layer 112. The etching may be dry etching, such as using inductively coupled plasma (ICP) etching technology. Although only one LED 110 is shown in Figure 1D [description], it will be understood that many LEDs may be provided to provide a display component 1 having many pixels, and / or to provide sub-pixels having different colors. Thus, the cathode layer 112 may be shared by many, any optionally all, of the LEDs across the display component 1, which may simplify the manufacture of the display component 1. Alternatively, the cathode layer 112 may be patterned to provide separate cathode layers 122, such as for each pixel of the display component 1.

[0071] In Figure 1E [description], a bottom passivation layer 121 is deposited and patterned on the LED 110 and the cathode layer 112. The bottom passivation layer 121 may include SiO2. The bottom passivation layer 121 may be patterned to provide a first via 121-2 to the cathode layer 112 and a second via 121-4 to the anode layer 114.

[0072] In Figure 1FIn [description], the bottom contact layer 120 is deposited on the bottom passivation layer 121 to provide electrical connection to the LED 110 through the holes 121-2, 121-4 in the bottom passivation layer 121. More specifically, the bottom contact layer 120 has a first bottom contact portion 122 and a second bottom contact portion 124. The first bottom contact portion 122 provides electrical connection to the cathode layer 112 through the first hole 121-2, and the second bottom contact portion 124 provides electrical connection to the anode layer 114 through the second hole 121-4. The bottom contact layer 120 is preferably a metal such as gold.

[0073] In Figure 1G [description], the planarization layer 130 is deposited on the underlying layer to provide a planar surface on which subsequent layers are to be deposited. More specifically, the planarization layer 130 is deposited on the bottom contact layer 120 and the bottom passivation layer 121. This planarization layer 130 can be a passivation layer, which can be referred to as the intermediate passivation layer 130, or the "first" passivation layer 130. Since the LED 110 can protrude from the substrate 105 by about 3 to 4 μm, the planarization layer 130 needs to have a sufficient thickness to prevent short-circuiting of the LED 110, such as due to thinning of the planarization layer 130 near the corners of the LED 110. The planarization layer 130 can have a thickness such that the thickness of the portion of the planarization layer 130 located above the LED 110 is at least 0.5 μm. The thickness of the planarization layer 130 can be greater than 1 μm, preferably greater than 2 μm. The planarization layer 130 can be an acrylate-based material, such as the material PL-02-02-01 of SmartKem.

[0074] In Figure 1H [description], the intermediate (contact) layer 135 is deposited and patterned on the planarization layer 130. As will be discussed later, the intermediate layer 135 can be a back-gate layer that provides the back-gate electrode of the OTFT 160. The intermediate layer 135 can be a metal such as gold or molybdenum-aluminum-molybdenum (MAM).

[0075] In Figure 1IIn [description], the base layer 140 is deposited over the planarization layer 130 and the intermediate layer 135. The base layer 140 creates a planar surface for the subsequent layers and also separates the back gate layer 135 from the other parts of the OTFT 160. The base layer 140 is a dielectric layer, and the chemistry of the base layer 140 is preferably adapted to that of the organic semiconductor layer 162 of the OTFT 160 to facilitate a consistent morphology of the organic semiconductor layer 162. The base layer 140 can be an organic crosslinked layer, and the chemistry is preferably chosen such that it is resistant to residual ionic contamination that can dope the OTFT 160 under bias stress conditions. The base layer 140 can be an acrylate polymer. The base layer 140 can be selected from those layers described in WO2020 / 002914A1. The base layer 140 is preferably resistant to organic solvents. The base layer 140 can have a thickness of 10 nm to 10 μm, preferably 100 nm to 1 μm.

[0076] In Figure 1J [description], holes 142, 144 are etched through the base layer 140 and the planarization layer 130 to allow electrical connection to the LED 110. More specifically, a first planarization hole 142 is etched to allow electrical connection to the first bottom contact portion 122 and thus connection to the cathode layer 112, and a second planarization hole 144 is etched to allow electrical connection to the second bottom contact portion 124 and thus connection to the anode layer 114.

[0077] In Figure 1K [description], the middle contact layer 150 is deposited on the base layer 140. The middle contact layer 150 provides the drain 156 and the source 158 of the OTFT 160. The drain 156 and the source 158 are separated by a distance corresponding to the length of the active channel of the OTFT 160. The middle contact layer 150 also fills the first planarization hole 142 and the second planarization hole 144, thereby providing a first middle contact portion 152 connected to the first bottom contact portion 122 and a second middle contact portion 154 connected to the second bottom contact portion 124. The middle contact layer 150 can be a metal such as gold.

[0078] In Figure 1LIn this case, the OTFT 160 is processed. Processing the OTFT 160 may include depositing one or more organic layers 161. This includes depositing an organic semiconductor layer 162 between the drain 156 and the source 158 to form an active channel. Depositing the OTFT 160 may include depositing one or more dielectric layers on the organic semiconductor layer 162. For example, an organic gate insulator 163 may be deposited on the organic semiconductor layer 162. The choice of the material of the organic gate insulator 163 and its associated dielectric constant determines the carrier density in the active channel and affects device hysteresis. An anti-sputtering layer 164 may be deposited on the organic gate insulator 163. The anti-sputtering layer 164 can be UV cured. The anti-sputtering layer 164 is arranged to provide resistance to sputtering damage to the organic gate insulator 163 and the organic semiconductor layer 162 during subsequent steps. Preferably, the anti-sputtering layer 164 is also selected to enable the deposition of a variety of gate materials.

[0079] In Figure 1M this case, the front gate electrode 167 is deposited on one or more dielectric layers, more specifically, on the anti-sputtering layer 164. In Figure 1N this case, the organic layer 161 is etched to provide the OTFT 160 at specific regions on the base layer 140. The etching can be dry etching. As will be discussed in more detail later, it may be difficult to remove all of the organic material 161 from inside the holes 142, 144, which can lead to defects during subsequent steps.

[0080] In Figure 1O this case, a passivation layer 170 is deposited over the OTFT 160 and the base layer 140. This passivation layer 170 may be referred to as the top passivation layer 170 or the "second" passivation layer 170. The top passivation layer 170 may have a thickness of approximately 2 μm. The top passivation layer 170 may be an acrylate-based material, such as the material PL-02-02-01 from SmartKem.

[0081] One or more holes may be etched through the top passivation layer 170 to allow electrical connections to the OTFT 160 and the LED 110. More specifically, a first passivation layer hole 172 is etched to allow connection to the first middle contact portion 152, a second passivation layer hole 174 is etched to allow connection to the second middle contact portion 154, a third passivation layer hole 176 is etched to allow connection to the drain 156 of the OTFT 160, and a fourth passivation layer hole 177 is etched to allow connection to the front gate electrode 167 of the OTFT 160.

[0082] In Figure 1PIn this case, a top contact layer 180 (or “OTFT contact layer”) is deposited on top of the top passivation layer 170 and within the holes to provide electrical connection through the holes. In this embodiment, the top contact layer 180 provides connection through the first passivation layer holes 172 to the first middle contact portion 152, thereby providing connection to the cathode 112 of the LED 110. The top contact layer 180 also passes through the second passivation layer holes 174 and the third passivation layer holes 176 to connect the drain 156 of the OTFT 160 to the second middle contact portion 154, thereby connecting the drain 156 to the anode 114 of the LED 110. The top contact layer 180 also provides connection through the fourth passivation layer hole 177 to the front gate electrode 167 of the OTFT 160. The top contact layer 180 can be a metal such as gold.

[0083] Optionally, the substrate 105 can be separated from the layers above the substrate 105 (e.g., the cathode layer 112). The substrate 105 can be removed via any suitable etching technique or by using a laser, such as by laser ablation. In this way, when the display component 1 is configured as a downward-emitting display component, the light from the LED 110 does not have to pass through the substrate 105, thereby improving the efficiency of the display.

[0084] The OTFT 160 can be processed at least in part using solution processing techniques. For example, the organic semiconductor layer 162 can be deposited using solution processing. Alternatively or additionally, the OTFT 160 can be processed using vacuum deposition techniques.

[0085] Although the above method can be used to fabricate the monolithic micro-LED display component 1, it may cause the following problems. Figure 2A A close-up view of one of the planarization holes 142, 144 is shown. As previously referenced Figure 1J As described, these holes 142, 144 are etched through the base layer 140 and the planarization layer 130 to allow electrical connection of the LED 110. However, during the subsequent deposition of the organic layer 161 of the OTFT 160 discussed in step 1L, the organic material 161 can enter the planarization holes 142, 144. Although these organic layers 161 are etched away, as referenced Figure 1N As described, due to the depth of the planarization hole 142, it is difficult to remove all of the organic material 161 from inside the holes 142, 144. Therefore, residues are formed, which can cause defects during the subsequent deposition of the top passivation layer 170. More specifically, due to dielectric residues, the material of the top passivation layer 170 can dehydrate out of the holes 142, 144. Figure 2B A top-down view of the display component 1 is shown, where many dehydrates 195 are formed due to the process described above.

[0086] To solve the above problems, a preferred method of manufacturing the monolithic display component 2 will now be described with reference to Figures 3A to 3J and many of the steps and features described correspond to those described with reference to Figures 3A to 3J and Figures 1A to 1J Accordingly, the corresponding features with the corresponding reference numerals are the same so as to avoid the need to describe these common features in detail again. It will be understood that any details discussed above, such as the materials, dimensions, properties, and / or manufacturing processes of the layers, may also be applied to the following preferred method.

[0087] Initially, the method begins as has been described with reference to Figures 1A to 1F Accordingly, Figure 3A shows an arrangement equivalent to Figure 1F In Figure 3B , a planarization layer 230 is deposited over the underlying layer (i.e., over the LED 210), thereby providing a planar surface on which subsequent layers are to be deposited. More specifically, the planarization layer 230 is deposited over the bottom contact layer 220 and the bottom passivation layer 221. This planarization layer 230 may be a passivation layer, which may be referred to as the middle passivation layer 230 or the "first" passivation layer 230.

[0088] As Figure 3B also shows, at least one planarization layer hole may be etched through the planarization layer 230. More specifically, a first planarization layer hole 232 is etched to allow electrical connection to the first bottom contact portion 222, and a second planarization layer hole 234 is etched to allow electrical connection to the second bottom contact portion 224.

[0089] In Figure 3C , an intermediate (contact) layer 235 is deposited and patterned over the planarization layer 230 and in the planarization layer holes 232, 234. More specifically, the intermediate layer 235 may have a first region 235a and a second region 235b, the first region 235a being connected to the cathode 112 of the LED 110 through the first planarization layer hole 232, and the second region 235b being connected to the anode 114 of the LED 110 through the second planarization layer hole 234. The intermediate layer 235 may also be a backgate layer that provides the backgate electrode of the OTFT 260. In this embodiment, the intermediate layer 235 includes a third region 235c that provides the backgate electrode of the OTFT 260. In this way, an isolated backgate micro-LED display component can be manufactured. Alternatively, the first region 235a and / or the second region 235b of the intermediate layer 235 may provide the backgate electrode of the OTFT 260.

[0090] When configured as a bottom-emitting display, the intermediate layer 235 can provide a reflective layer such that light emitted by the LED 210 in the upward direction is reflected by the reflective layer in the downward direction corresponding to the bottom surface of the LED 210. This improves the efficiency of the micro-LED display component 2 and the display as a whole because all or most of the light is emitted in the downward direction through the bottom side of the micro-LED display component 2. Thus, the intermediate layer 235 can provide the back-gate layer of the OTFT 260, and / or can provide a reflective layer. Alternatively, a reflective layer separate from the back-gate layer and / or the intermediate layer 235 can be provided. The reflective layer can be a metal layer and can include Al, Ag, Mo, and / or Au. The reflective layer can also be incorporated into the method described with reference to Figures 1A to 1P The method described.

[0091] In Figure 3D , the base layer 240 is deposited over the planarization layer 230 and the intermediate layer 235. The base layer 240 creates a planar surface for the subsequent layers and also separates the back-gate layer 235c from the other parts of the OTFT 260. Thus, the base layer 240 isolates the LED 210 from the top layers (such as the OTFT 260). Preferably, the term "isolate" means that no holes are formed through the base layer 240 before processing the OTFT 260 on the base layer 240. In other words, the base layer 240 is continuous during the processing of the OTFT 260 on the base layer 240.

[0092] In Figure 3E , the drain 256 and source 258 of the OTFT 260 are deposited on the base layer 240. These electrodes 256, 258 can be referred to as the middle contact layer 250, which is separate from the intermediate contact layer 235 described above.

[0093] In Figure 3F , the OTFT 260 is processed. Processing the OTFT 260 can include depositing an organic layer 261. This includes depositing an organic semiconductor layer 262. Depositing the OTFT 260 can include depositing one or more dielectric layers on the organic semiconductor layer 262. For example, an organic gate insulator 263 can be deposited on the organic semiconductor layer 262, and an anti-sputtering layer 264 can be deposited on the organic gate insulator 263. The anti-sputtering layer 264 can be UV-cured. The anti-sputtering layer 264 is arranged to provide resistance to sputtering damage to the organic gate insulator 263 and the organic semiconductor layer 262 during subsequent steps.

[0094] In Figure 3G , the front gate electrode 267 is deposited on one or more dielectric layers, more specifically on the anti-sputtering layer 264. In Figure 3HIn [description], the organic layer 261 is etched to provide the OTFT 260 at specific regions on the base layer 240. The etching can be dry etching. The etching stops when the organic material 261 above the base layer 240 (but not below the front gate electrode 267) has been removed. Since the base layer 240 is continuous during the deposition of the OTFT 260 and the etching on the base layer 240, the organic layer 261 can be etched more uniformly, thereby reducing the risk of leaving residues during subsequent steps. In particular, during the processing of the OTFT 260, the base layer 240 isolates the LED 210.

[0095] In Figure 3I [description], a passivation layer 270 is deposited over the OTFT 260 and the base layer 240. This passivation layer 270 can be referred to as the top passivation layer 270 or the "second" passivation layer 270.

[0096] Also as Figure 3I shown, holes are etched through the base layer 240 and the top passivation layer 270 to allow electrical connection to the OTFT 260 and the LED 210. In this embodiment, a first passivation layer hole 272 is etched through the top passivation layer 270, where continued etching through the base layer 240 provides a first base layer hole 242 that allows electrical connection to a first region 235a of the intermediate layer 235. In a similar manner, a second passivation layer hole 274 is etched through the top passivation layer 270, where continued etching through the base layer 240 provides a second base layer hole 244 that allows electrical connection to a second region 235b of the intermediate layer 235. A third passivation layer hole 276 is etched through the top passivation layer 270 to allow connection to the drain 256 of the OTFT 260. A fourth passivation layer hole 277 is etched through the top passivation layer 270 to allow connection to the front gate electrode 267 of the OTFT 260. Preferably, the continued etching of the passivation layer holes 272, 274 to provide the base layer holes 242, 244 occurs continuously, and more preferably in the same etching step. Alternatively, the base layer holes 242, 244 can be etched in a step independent of the passivation layer holes 272, 274, 276, 277. For example, before depositing the top passivation layer 270, the base layer holes 242, 244 can be etched through the base layer 240.

[0097] In Figure 3JIn [the figure], a top contact layer 280 (or “OTFT contact layer”) is deposited on the top passivation layer 270 and within the holes to provide electrical connections through the holes. In this embodiment, the top contact layer 280 provides a connection through the first passivation layer holes 272 and the first base layer holes 242 to the first region 235a of the intermediate layer 235, thereby providing a connection to the cathode 212 of the LED 210. The top contact layer 280 also provides a connection from the drain 256 of the OTFT 260 to the second region 235b of the intermediate layer 235, which connection passes through the third passivation layer holes 276, the second passivation layer holes 274, and the second base layer holes 244, thereby connecting the drain 256 to the anode 214 of the LED 210. In this way, the top contact layer 280 provides a connection between the LED 210 and the OTFT 260 through the base layer holes 242, 244, and thus can be referred to as the OTFT base layer 280. The top contact layer 280 also provides a connection through the fourth passivation layer holes 277 to the front gate electrode 267 of the OTFT 260.

[0098] It will be understood that other connections can be formed in addition to those described above. For example, other holes can be formed to provide connections to the back gate layer 235c of the OTFT 260 (such as Figure 4 as shown). Additionally, the back gate layer 235c can be connected to the front gate electrode 267 or the source 258 of the OTFT 260. As discussed in WO2022 / 101644, this can improve voltage stability, reduce power consumption, and improve bias stress stability. Additionally, the holes through the top passivation layer 270 can continue through the base layer 240 and also through the middle passivation layer 230 to connect to the cathode 212 and the anode 214; however, this method can take a very long etching time and requires a thick photoresist for etching protection (typically, about 150% of the entire hole depth). This may limit resolution and may increase manufacturing costs. Therefore, it is preferred to provide connections to the cathode 212 and the anode 214 through the intermediate layer 235.

[0099] Optionally, the substrate 205 can be separated from the layer above the substrate 205 (e.g., the cathode layer 212).

[0100] The OTFT 260 can be at least partially processed using solution processing techniques. For example, the organic semiconductor layer 262 can be deposited using solution processing. In particular, when using wet techniques such as solution processing, the organic layer 261 is more likely to fall inside any holes formed through the base layer 240. Therefore, when using solution processing, it is particularly advantageous to etch the base layer holes 242, 244 after processing the OTFT 260. Alternatively or additionally, the OTFT 260 can be processed using vacuum deposition techniques.

[0101] Figure 4shows a more detailed cross-section of the display component 3, which can be manufactured using the method discussed with reference to Figures 3A to 3J The display component 3 shares many features with the display component 2 formed using the process described above, and corresponding features are identified using corresponding reference numerals.

[0102] The display component 3 includes a driving OTFT 360a and a switching OTFT 360b, and the driving OTFT 360a and the switching OTFT 360b can be processed in a manner similar to that already described. In this embodiment, the driving OTFT 360a has an interdigital structure, where a plurality of active channels are provided to increase the W value of the OTFT 360a so that the OTFT 360a can provide more current. In addition, the display component 3 also includes a V DD terminal 329, and the V DD terminal 329 is connected to the third region 335c of the intermediate layer 335. The third region 335c of the intermediate layer 335 provides a back gate electrode for the driving OTFT 360a and the switching OTFT 360b, although it will be understood that the OTFT 360 can have separate back gates that are electrically isolated from each other and / or can be connected elsewhere. A third base layer hole 349 and a fifth passivation layer hole 379 are provided to allow the use of the top contact layer 380 to form an electrical connection with the V DD terminal 329 and the third region 335c of the intermediate layer 335.

[0103] A V SS terminal 322 is also provided, and the V SS terminal 322 is electrically connected to the cathode layer 312 through the bottom passivation layer 321. The first base layer hole 342 and the first passivation layer hole 372 provide a connection to the first region 335a of the intermediate layer 335 for connection to the cathode layer 312. Alternatively, these holes 342, 372 and the first region 335a of the intermediate layer 335 can be located elsewhere to provide an electrical connection to the cathode layer 312. For example, in the case where the cathode layer 312 is shared by a plurality of LEDs 310 across the display component 3, it may not be necessary to provide an electrical connection to the cathode layer 312 for each LED 310.

[0104] Now a specific embodiment of the mass transfer method for manufacturing the display component 4 will be described with reference to Figures 5A to 5K Many of the steps and features described correspond to those described with reference to Figures 5A to 5K and Figures 1A to 1P and Figures 3A to 3J Therefore, corresponding features are identified using corresponding reference numerals to avoid the need to describe these common features in detail again. It will be understood that any details discussed above, such as those related to the materials, dimensions, properties, and / or manufacturing processes of the layers, can also be applied to the following method.

[0105] In Figure 5A , multiple LEDs 410 are grown on the source wafer 410 in a manner similar to that already described with reference to Figure 1A and Figure 1D . The LEDs 410 can be blue LEDs 410. For clarity, only some of the LEDs 410 have been labeled, and it will be understood that any number of LEDs 410 can be grown on the source wafer 401 to provide the required number of pixels (sub-pixels) in the display component 4. Flip-chip contacts are also formed on each LED 410 to provide connections to the corresponding cathodes 412 and anodes 414. Figure 5A The flip-chip contacts shown differ from the anodes and cathodes described with reference to FIGS. 1 and 3 in that the contacts are all provided on the top surface of the LED 410. In Figure 5B , the LEDs 410 are laser released from the source wafer 401 onto the intermediate film 402. The intermediate film 402 can be referred to as a "transfer substrate" or "intermediate substrate". By using a strong adhesive on the transfer substrate 402 to ensure adhesion of the LEDs 410 during transfer, the transfer yield from the source wafer 401 to the transfer substrate 402 can be optimized.

[0106] In Figure 5C , the plastic substrate 403 is laminated onto the glass substrate 405 using a thermally releasable adhesive 404. Subsequently, as Figure 5D shown, quantum dot (QD) color conversion material 406 is processed on top of the plastic substrate 403. The QD color conversion material 406 is configured to convert light of a specific wavelength (e.g., blue light from the LED) into another color, thereby providing an RGB display. Optionally, a light blocking layer 407 can be processed between the QD color conversion materials 406 to reduce crosstalk between adjacent LEDs 410. Photolithography can be used. In Figure 5E , a planarization film 408 is formed over the QD color conversion material 406 and the light blocking layer 407. The thickness of the planarization film 408 can be 1 to 5 μm. An adhesive film 409 is provided over the planarization film 408.

[0107] In Figure 5F , the LEDs 410 are laser transferred from the intermediate film 402 onto the adhesive film 409 on the planarization film 408. During this step, each LED 410 is aligned with the corresponding QD color conversion material 406. In this way, each LED 410 can provide a sub-pixel, where in the resulting display component 4, multiple sub-pixels (e.g., three RGB sub-pixels) provide a color pixel. Thus, the LEDs 410 are deposited on the top surface of the substrate 405 using the intermediate film 402.

[0108] In Figure 5G , a first (“mid”) passivation layer 430 is deposited over the LEDs 410. Holes 432, 434 are formed through the first passivation layer 430 to permit formation of electrical connections to the flip-chip contact portions of each LED 410. In Figure 5H , an intermediate (contact) layer 435 is deposited and patterned over the first passivation layer 430. As shown, the intermediate layer 435 includes a first region 435a connected to the cathode 412 of the LED 410, and a second region 435b connected to the anode 414 of the LED 410. In Figure 5I , a base layer 440 is deposited over the first passivation layer 430 and the intermediate layer 435. Although not shown in Figure 5H , a third region of the intermediate layer 435 may provide the back gate for each OTFT 460.

[0109] In Figure 5J , a plurality of OTFTs 460 are processed. Although Figure 5J a single OTFT 460 is depicted for each LED 410, it will be understood that more than one OTFT 460 (such as the switching OTFT and the driving OTFT discussed with reference to Figure 4 ) may be provided for each LED 410. A top passivation layer 470 is also deposited. Although not shown in detail in Figure 5J , it should be understood that other elements such as holes and contact layers may also be provided in a manner similar to that already described with reference to Figures 3A to 3J and / or Figure 4 .

[0110] Optionally, in Figure 5K , the glass substrate 405 may be removed from the layers above the glass substrate 405. The glass substrate 405 may be separated from the plastic substrate 403 using a thermal release adhesive 404. By removing the glass substrate 405, a flexible display component 4 may be provided.

[0111] It may be advantageous to use a transfer substrate 402, followed by deposition of the OTFTs 460, to form a monolithic display component 4 because only the desired amount of the LED source wafer 401 is used for light emission. The display component 4 may be considered monolithic in the sense that the OTFTs 460 are grown on the substrate 405 containing the LEDs 410 rather than transferring the LEDs to a substrate containing the OTFTs 460.

[0112] While the foregoing is directed to exemplary embodiments of the present invention, it will be understood that the present invention is described herein purely by way of example and that modifications may be made to the details within the scope of the present invention. Further, those skilled in the art will understand that the present invention may not be limited by the embodiments disclosed herein or to any details not described herein in detail or defined in the claims that are not shown in the drawings. In fact, such superfluous features may be removed from the drawings without affecting the present invention.

[0113] In addition, by considering this specification, other and further embodiments of the present invention will be apparent to those skilled in the art and these embodiments may be designed without departing from the basic scope of the present invention, the basic scope of which is determined by the following claims.

Claims

1. A method of manufacturing a monolithic micro-LED display component, the method comprising: Depositing LEDs on a top surface of a substrate; Depositing a base layer over the LEDs, the base layer forming a planar layer that isolates the LEDs; Fabricating an organic thin-film transistor, OTFT, on the base layer by depositing a source and a drain and an active channel including an organic semiconductor layer; and after fabricating the OTFT, Etching base layer holes, the base layer holes including holes through the base layer to permit connection between the LEDs and the OTFT.

2. The method according to claim 1, wherein the OTFT is fabricated at a region of the base layer that at least partially overlaps with the LEDs.

3. The method according to claim 1 or 2, wherein before depositing the base layer, the method further comprises: Depositing a planarization layer over the LEDs; Etching planarization layer holes through the planarization layer; Depositing an intermediate contact layer on the planarization layer such that the intermediate contact layer connects to the LEDs through the planarization layer holes; the method further comprises depositing the base layer over the planarization layer and the intermediate contact layer.

4. The method according to claim 3, wherein the step of etching the base layer holes comprises etching holes through the base layer to provide connection with the intermediate contact layer, the method further comprising depositing an OTFT contact layer, the OTFT contact layer providing connection between the OTFT and the intermediate contact layer such that the OTFT connects to the LEDs through the intermediate contact layer.

5. The method according to claim 4, further comprising: Depositing a passivation layer over the base layer before etching the base layer holes; Etching one or more passivation layer holes through the passivation layer; Wherein continuing to etch at least one passivation layer hole provides the base layer holes; And Wherein the OTFT contact layer is deposited into the passivation layer holes, thereby connecting the LEDs to the OTFT through the intermediate contact layer.

6. The method according to any one of claims 3 to 5, wherein the planarization layer has a thickness such that a thickness of a portion of the planarization layer located over the LEDs is at least 0.5 μm.

7. The method according to any one of claims 3 to 6, wherein the intermediate contact layer provides a back-gate layer of the OTFT.

8. The method according to any one of claims 3 to 7, wherein the intermediate contact layer includes a first region connected to an anode of the LEDs through a first planarization layer hole and a second region connected to a cathode of the LEDs through a second planarization layer hole.

9. The method according to any one of claims 3 to 8, wherein the intermediate contact layer and / or the back-gate layer provide a reflective layer such that light emitted by the LEDs in an upward direction is reflected by the reflective layer in a downward direction corresponding to a bottom surface of the LEDs.

10. The method according to any of the preceding claims, wherein fabricating the OTFT comprises depositing one or more dielectric layers on the organic semiconductor layer.

11. The method according to claim 10, wherein processing the OTFT further comprises depositing a front gate metal on the one or more dielectric layers.

12. The method according to any one of the preceding claims, wherein processing the OTFT further comprises at least partially etching away one or more organic layers above the base layer.

13. The method according to any one of the preceding claims, further comprising: depositing a passivation layer over the OTFT and the base layer, and etching the passivation layer to form one or more passivation layer holes.

14. The method according to claim 13, wherein the base layer hole is formed by continuing to etch at least one of the passivation layer holes through the base layer.

15. The method according to claim 13 or 14, further comprising depositing an OTFT contact layer into the one or more passivation layer holes.

16. The method according to any one of the preceding claims, further comprising growing the LED on a source wafer and subsequently transferring the LED from the source wafer to a substrate using an intermediate substrate.

17. The method according to any one of the preceding claims, further comprising separating the substrate from the layers above the substrate.

18. The method according to any one of the preceding claims, wherein the OTFT is at least partially processed using solution processing techniques.

19. A monolithic micro-LED display component, comprising: an LED having a top surface and an opposite bottom surface; a planar base layer formed above the top surface of the LED; an organic thin-film transistor, OTFT, at least partially processed above the upper surface of the base layer; a passivation layer deposited on the OTFT; and a base layer hole etched through the base layer and the passivation layer to permit an electrical connection between the LED and the OTFT.

20. The monolithic micro-LED display component according to claim 19, further comprising an intermediate contact layer formed above the lower surface of the base layer and electrically connected to the LED, wherein the base layer hole is connected to the intermediate contact layer.

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