Display device

Abstract

The display device may include: a first sub-pixel, a second sub-pixel, and a third sub-pixel adjacent to each other, the first sub-pixel, the second sub-pixel, and the third sub-pixel each having a storage capacitor; a scan line selectively transmitting a scan signal and a control signal to each of the first sub-pixel, the second sub-pixel, and the third sub-pixel, the scan line extending in the first direction; a data line transmitting a data signal to each of the first to third sub-pixels, the data line extending in a second direction intersecting the first direction; and a first power line electrically connected to each of the first sub-pixel, the second sub-pixel, and the third sub-pixel, and the first power line is supplied with a first driving power voltage. The first power line may be located between the storage capacitor and the data line.

Description

Technical Field

[0001] The present disclosure generally relates to a display device. Background Art

[0002] Recently, with the increasing interest in information display, research and development of display devices have been continuously carried out. Summary of the Invention

[0003] Technical Problem

[0004] Embodiments provide a display device having improved reliability.

[0005] Technical Solution

[0006] According to an aspect of the present disclosure, there is provided a display device including: a first sub-pixel, a second sub-pixel, and a third sub-pixel adjacent to each other, each of the first sub-pixel, the second sub-pixel, and the third sub-pixel having a storage capacitor; a scan line selectively transmitting a scan signal and a control signal to each of the first sub-pixel, the second sub-pixel, and the third sub-pixel, the scan line extending in a first direction; a data line transmitting a data signal to each of the first sub-pixel, the second sub-pixel, and the third sub-pixel, the data line extending in a second direction intersecting the first direction; and a first power line electrically connected to each of the first sub-pixel to the third sub-pixel and supplied with a first driving power voltage, wherein the first power line may be located between the storage capacitor and the data line.

[0007] The display device may further include: a substrate; a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer sequentially disposed on the substrate; a second power line supplied with a second driving power voltage different from the voltage of the first driving power source; and an initialization power line supplied with an initialization power voltage. The first power line may include a first vertical power line and a first horizontal power line, the first vertical power line being configured with a first conductive layer disposed on the substrate, and the first horizontal power line being configured with a second conductive layer disposed on the second insulating layer. In a plan view, the first vertical power line may be located between the storage capacitor of each of the first sub-pixel, the second sub-pixel, and the third sub-pixel and the data line.

[0008] Each of the first sub-pixel, the second sub-pixel, and the third sub-pixel may include: a light-emitting element; a first transistor controlling the current of the light-emitting element; a second transistor connected between the data line and the gate electrode of the first transistor, the second transistor being turned on by the scan signal; a third transistor connected between the initialization power line and the source electrode of the first transistor, the third transistor being turned on by the control signal; and a storage capacitor including a lower electrode and an upper electrode, the lower electrode being electrically connected to the gate electrode of the first transistor and the source electrode of the second transistor, and the upper electrode being electrically connected to the source electrode of the first transistor and the source electrode of the third transistor.

[0009] The first transistor, the second transistor, and the third transistor may be located at one side of the storage capacitor.

[0010] The second power line may include a second vertical power line configured with a first conductive layer and a second horizontal power line configured with a second conductive layer. In a plan view, the storage capacitor may be located between the second vertical power line and the first vertical power line.

[0011] In a plan view, the initialization power line may be located between the first vertical power line and the data line.

[0012] The gate electrodes of the first transistors of each of the first sub-pixel, the second sub-pixel, and the third sub-pixel may be disposed between the storage capacitor and the first vertical power line.

[0013] The lower electrode may be disposed on the substrate, and the upper electrode may be disposed on the first insulating layer to overlap with the lower electrode, and the first insulating layer is interposed between the lower electrode and the upper electrode.

[0014] The upper electrode may be disposed in the same layer as the active patterns of each of the first transistor, the second transistor, and the third transistor.

[0015] The upper electrode may be integrally formed with the source electrode of the first transistor and the source electrode of the third transistor.

[0016] The light-emitting element may include: a first electrode configured with a third conductive layer disposed on a fourth insulating layer; a light-emitting layer disposed on the first electrode; and a second electrode disposed on the light-emitting layer.

[0017] The first electrode may be electrically connected to the source electrode of the first transistor through a contact portion penetrating the second insulating layer to the fourth insulating layer.

[0018] In a plan view, the initialization power line may be located between the second vertical power line and the storage capacitor.

[0019] In a plan view, the initialization power line may be located at one side of the storage capacitor, and the first vertical power line may be located at the other side of the storage capacitor.

[0020] In a plan view, among the first transistor, the second transistor, and the third transistor, the third transistor may be located at one side of the storage capacitor, and the first transistor and the second transistor among the first to third transistors may be located at the other side of the storage capacitor.

[0021] Each of the first sub-pixel, the second sub-pixel, and the third sub-pixel may further include: a packaging layer disposed on the light-emitting element; a color filter layer disposed on the packaging layer; and an outer coating layer disposed on the color filter layer.

[0022] According to another aspect of the present disclosure, a display device is provided, including: a substrate; a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer, stacked on the substrate in sequence; a first sub-pixel, a second sub-pixel, and a third sub-pixel, each including a pixel circuit and a light-emitting element electrically connected to the pixel circuit, the pixel circuit including a storage capacitor disposed on the substrate, and a first transistor, a second transistor, and a third transistor; a scan line disposed on the substrate, the scan line selectively transmitting a scan signal and a control signal to each of the first sub-pixel, the second sub-pixel, and the third sub-pixel; a data line transmitting a data signal to each of the first sub-pixel, the second sub-pixel, and the third sub-pixel; a first power line supplied with a first power voltage; a second power line supplied with a second power voltage different from the first power voltage; and an initialization power line supplied with an initialization power voltage different from the first power voltage and the second power voltage. The gate electrode of the first transistor may be located between the storage capacitor and the first power line.

[0023] The first power line may include a first vertical power line disposed on the substrate and a first horizontal power line disposed on the second insulating layer. The first vertical power line may be located between the storage capacitor and the data line.

[0024] In a plan view, the first transistor, the second transistor, and the third transistor may be located at one side of the storage capacitor.

[0025] In a plan view, the storage capacitor may be located between the initialization power line and the first vertical power line.

[0026] Advantageous Effects

[0027] According to the present disclosure, the first vertical power line is disposed between the storage capacitor and the data line of each sub-pixel, thereby reducing the area of the gate electrode of the first transistor (or driving transistor) of each sub-pixel. Therefore, the area of the storage capacitor can be ensured.

[0028] According to the present disclosure, the capacitance of the storage capacitor of each sub-pixel is increased, thereby improving the reliability of the display device.

[0029] The effects of the present disclosure are not limited to the foregoing, and various other effects are expected herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic plan view showing a display device according to an embodiment of the present disclosure.

[0031] Figure 2 is a schematic view showing Figure 1 a schematic cross-sectional view of the display panel shown in

[0032] Figure 3 is a schematic circuit diagram showing the electrical connection relationships of the components included in each of the pixels shown in Figure 1 .

[0033] Figure 4 and Figure 5 is a schematic plan view showing a pixel according to an embodiment of the present disclosure.

[0034] Figure 6 is a schematic plan view showing only the components included in the first conductive layer in the pixels shown in Figure 5 .

[0035] Figure 7 is a schematic plan view showing only the transistors and the components included in the second conductive layer in the pixels shown in Figure 5 .

[0036] Figure 8 is a schematic cross-sectional view taken along line I-I' shown in Figure 5 .

[0037] Figure 9 and Figure 10 is a schematic cross-sectional view taken along line II-II' shown in Figure 5 .

[0038] Figure 11 shows a pixel according to an embodiment of the present disclosure and is a schematic cross-sectional view corresponding to line I-I' shown in Figure 5 .

[0039] Figure 12 is a schematic plan view showing a pixel according to an embodiment of the present disclosure.

[0040] Figure 13 is a schematic plan view showing only the components included in the first conductive layer in the pixels shown in Figure 12 .

[0041] Figure 14 is a schematic plan view showing only the transistors and the components included in the second conductive layer in the pixels shown in Figure 12 .

[0042] Figure 15 is a schematic cross-sectional view taken along line III-III' shown in Figure 12 . Detailed Description

[0043] The present disclosure can be applied with various changes and different shapes and is thus shown in detail only by way of specific examples. However, the examples are not limited to specific shapes but are applicable to all changes as well as equivalent substances and substitutes. For better understanding, the included drawings are shown in an enlarged manner of the drawings.

[0044] Like reference numerals always denote like elements. In the drawings, for clarity, the thickness of some lines, layers, components, elements or features may be exaggerated. It will be understood that although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, the “first” element discussed below may also be termed “second” element without departing from the teachings of the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form.

[0045] It will also be understood that, as used in this specification, the terms “comprises” and / or “comprising” specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence and / or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Further, the statement that an element such as a layer, region, substrate or plate is “on” or “above” another element not only refers to the case where the element is “directly” on or “right above” the other element, but also refers to the case where yet another element is interposed between the element and the other element. Conversely, the statement that an element such as a layer, region, substrate or plate is “under” or “below” another element not only refers to the case where the element is “directly” under or “right below” another element, but also refers to the case where yet another element is interposed between the element and the other element.

[0046] In this specification, it will be understood that in the case where an element (e.g., a first element) is “(operatively or communicatively) coupled with / to” or “connected to” another element (e.g., a second element), the element can be directly coupled with / to the other element and there may be an intervening element (e.g., a third element) between the element and the other element. Further, in this specification, the terms “connect” or “couple” may inclusively denote a connection or a physical coupling and / or an electrical coupling.

[0047] Hereinafter, exemplary embodiments of the present disclosure and items necessary for those skilled in the art to easily understand the present disclosure will be described in detail with reference to the drawings. In the following description, unless the context clearly indicates otherwise, the singular form in the present disclosure is also intended to include the plural form.

[0048] Figure 1 is a schematic plan view showing a display device DD according to an embodiment of the present disclosure.Figure 2 is a schematic cross-sectional view showing Figure 1 the display panel DP shown in

[0049] In Figure 1 and Figure 2 for ease of description, the structure of the display device DD (e.g., the display panel DP provided in the display device DD) is briefly shown based on the display area DA in which an image is displayed.

[0050] Referring to Figure 1 and Figure 2 for ease of description, the structure of the display device DD (e.g., the display panel DP provided in the display device DD) is briefly shown based on the display area DA in which an image is displayed.

[0051] Referring to Figure 1 and Figure 2 According to embodiments of the present disclosure, the display panel DP (or the display device DD) can be set in various shapes. For example, the display panel DP can be set in a rectangular plate shape having two pairs of sides parallel to each other. However, the present disclosure is not limited thereto. In the case where the display panel DP is set in a rectangular plate shape, any one of the two pairs of sides can be set to be longer than the other pair.

[0052] At least a part of the display panel DP can be flexible and can be folded at the flexible part. However, the present disclosure is not limited thereto.

[0053] The display panel DP can display an image. A self-emitting display panel such as an organic light-emitting display panel (OLED panel) using an organic light-emitting diode as a light-emitting element, a micro LED display panel or a nano LED display panel using a micro LED or a nano LED as a light-emitting element, or a quantum dot organic light-emitting display panel (QD OLED panel) using a quantum dot and an organic light-emitting diode can be used as the display panel DP. In addition, a non-self-emitting display panel such as a liquid crystal display panel (LCD panel), an electrophoretic display panel (EPD panel), or an electro-wetting display panel (EWD panel) can be used as the display panel DP. In the case where the non-self-emitting display panel is used as the display panel DP, the display device DD can include a backlight unit for supplying light to the display panel DP. In an embodiment, the display panel DP can be an organic light-emitting display panel.

[0054] The display panel DP can include a substrate SUB and pixels PXL provided on the substrate SUB.

[0055] The substrate SUB can include a transparent insulating material to enable light to pass through it, but the present disclosure is not limited thereto. The substrate SUB can be a rigid substrate or a flexible substrate.

[0056] The rigid substrate may be, for example, one of a glass substrate, a quartz substrate, a glass-ceramic substrate, and a crystallized glass substrate.

[0057] The flexible substrate may be one of a film substrate and a plastic substrate including a polymer organic material. For example, the flexible substrate may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0058] One region of the substrate SUB may be set as a display region DA in which the pixels PXL are disposed, and other regions of the substrate SUB may be set as non-display regions NDA. For example, the substrate SUB may include a display region DA and a non-display region NDA disposed at the periphery of the display region DA (or adjacent to the display region DA), and the display region DA includes a pixel region PXA in which the corresponding pixels PXL are disposed.

[0059] The non-display region NDA may be positioned adjacent to the display region DA. The non-display region NDA may be disposed at at least one side of the display region DA. For example, the non-display region NDA may surround the perimeter (or edge) of the display region DA. The line portions connected to each pixel PXL and the driver connected to the line portions and driving the pixel PXL may be disposed in the non-display region NDA.

[0060] Each of the pixels PXL may be disposed in the display region DA of the substrate SUB. Each of the pixels PXL may include a light-emitting element that emits white light and / or colored light and a pixel circuit for driving the light-emitting element. The pixel circuit may include at least one transistor electrically connected to the light-emitting element. Each pixel PXL may emit light of one color among red, green, and blue, but the present disclosure is not limited thereto. Each pixel PXL may emit light of one color among cyan, magenta, yellow, and white.

[0061] A plurality of pixels PXL may be arranged in a matrix form along rows extending in a first direction DR1 and columns extending in a second direction DR2 intersecting the first direction DR1. However, the arrangement form of the pixels PXL is not particularly limited, and the pixels PXL may be arranged in various forms. In some embodiments, in the case where a plurality of pixels PXL are provided, the pixels PXL may be provided in different areas (or sizes). For example, in the case where the pixels PXL emit light of different colors, the pixels PXL may be provided in different areas (or sizes) or different shapes with respect to different colors.

[0062] The driver can control the driving of each pixel PXL by providing a predetermined signal and a predetermined voltage to each pixel PXL through a line portion.

[0063] The display panel DP (or each of the pixels PXL) may include a pixel circuit layer PCL, a display element layer DPL, and a packaging layer TFE located on a substrate SUB.

[0064] The pixel circuit layer PCL may be disposed on the substrate SUB and include transistors and signal lines connected to the transistors. For example, the transistors may have a form in which an active pattern (or semiconductor layer), a gate electrode, a source electrode, and a drain electrode are stacked in sequence with an insulating layer interposed therebetween. The semiconductor pattern may include amorphous silicon, polycrystalline silicon, low-temperature polycrystalline silicon, an organic semiconductor, and / or an oxide semiconductor. The gate electrode, the source electrode, and the drain electrode may include one of aluminum (Al), copper (Cu), titanium (Ti), and molybdenum (Mo), but the present disclosure is not limited thereto. For example, the pixel circuit layer PCL may include at least one insulating layer.

[0065] The display element layer DPL may be disposed on the pixel circuit layer PCL. The display element layer DPL may include a light-emitting element that emits light. The light-emitting element may be, for example, an organic light-emitting diode, but the present disclosure is not limited thereto. In some embodiments, the light-emitting element may be an inorganic light-emitting element including an inorganic light-emitting material or a light-emitting element that emits light by changing the wavelength of the emitted light using quantum dots.

[0066] The packaging layer TFE may be selectively disposed on the display element layer DPL. The packaging layer TFE may be a packaging substrate or have a form of a packaging film provided as multiple layers. In the case where the packaging layer TFE has the form of a packaging film, the packaging layer TFE may include an inorganic layer and / or an organic layer. For example, the packaging layer TFE may have a form in which an inorganic layer, an organic layer, and an inorganic layer are stacked in sequence. The packaging layer TFE can prevent external air and moisture from infiltrating into the display element layer DPL and the pixel circuit layer PCL.

[0067] Figure 3 is a schematic circuit diagram showing the electrical connection relationship of components included in each of the pixels PXL shown in Figure 1 For ease of description, the pixel PXL located on the i-th pixel row (or the i-th horizontal line) and the j-th pixel column will be shown in

[0068] (where i and j are natural numbers). Figure 3

[0069] Figures 1 to 3 Referring to Figures 1 to 3 , the pixel PXL may include an emission component EMU that generates light having a luminance corresponding to a data signal. For example, the pixel PXL may further include a pixel circuit PXC for driving the emission component EMU.

[0070] The emission component EMU may include a light-emitting element LD connected between a first power line PL1 supplied with a first driving power voltage VDD and a second power line PL2 supplied with a second driving power voltage VSS. For example, the emission component EMU may include a light-emitting element LD, and the light-emitting element LD includes a first electrode AE connected to the first driving power voltage VDD via a pixel circuit PXC and the first power line PL1 and a second electrode CE connected to the second driving power voltage VSS via the second power line PL2. The first electrode AE may be an anode, and the second electrode CE may be a cathode. The first driving power voltage VDD and the second driving power voltage VSS may have different electric potentials. During the emission period of the pixel PXL, the potential difference between the first driving power voltage VDD and the second driving power voltage VSS may be set to be equal to or higher than the threshold voltage of the light-emitting element LD.

[0071] When the pixel PXL (or sub-pixel) is located in the i-th pixel row and the j-th pixel column in the display area DA, the pixel circuit PXC of the pixel PXL (or sub-pixel) may be electrically connected to the i-th scan line Si and the j-th data line Dj. In addition, the pixel circuit PXC may be electrically connected to the i-th control line CLi and the j-th sensing line SENj.

[0072] The above pixel circuit PXC may include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst.

[0073] The first transistor T1 is a driving transistor for controlling the driving current applied to the light-emitting element LD, and may be electrically connected between the first driving power voltage VDD and the light-emitting element LD. Specifically, the first terminal of the first transistor T1 may be electrically connected to the first driving power voltage VDD through the first power line PL1, the second terminal of the first transistor T1 may be electrically connected to the second node N2, and the gate electrode of the first transistor T1 may be electrically connected to the first node N1. The first transistor T1 may control the amount of driving current applied to the light-emitting element LD from the first driving power supply VDD through the second node N2 according to the voltage applied to the first node N1. In an embodiment, the first terminal of the first transistor T1 may be a drain electrode, and the second terminal of the first transistor T1 may be a source electrode. However, the present disclosure is not limited thereto. In some embodiments, the first terminal may be a source electrode, and the second terminal may be a drain electrode.

[0074] The second transistor T2 is a switching transistor that selects and activates the pixel PXL in response to a scan signal, and can be electrically connected between the data line Dj (e.g., the j-th data line) and the first node N1. The first terminal of the second transistor T2 can be electrically connected to the data line Dj, the second terminal of the second transistor T2 can be electrically connected to the first node N1 (or the gate electrode of the first transistor T1), and the gate electrode of the second transistor T2 can be electrically connected to the scan line Si (or the i-th scan line). The first terminal and the second terminal of the second transistor T2 are different terminals. For example, when the first terminal is the drain electrode, the second terminal can be the source electrode.

[0075] When a scan signal having a gate-on voltage (e.g., a high-level voltage) is supplied from the scan line Si, the second transistor T2 can be turned on to electrically connect the data line Dj and the first node N1 to each other. The first node N1 is a point where the second terminal of the second transistor T2 and the gate electrode of the first transistor T1 are connected to each other, and the second transistor T2 can transfer a data signal to the gate electrode of the first transistor T1.

[0076] The third transistor T3 can electrically connect the first transistor T1 to the sense line SENj (e.g., the j-th sense line) to obtain a sense signal through the sense line SENj, and detect characteristics of the pixel PXL including the threshold voltage of the first transistor T1 and the like by using the sense signal. Information about the characteristics of the pixel PXL can be used to convert image data, thereby compensating for characteristic deviations between pixels PXL. The second terminal of the third transistor T3 can be electrically connected to the second terminal of the first transistor T1, the first terminal of the third transistor T3 can be electrically connected to the sense line SENj, and the gate electrode of the third transistor T3 can be electrically connected to the control line CLi (e.g., the i-th control line). The first terminal can be the drain electrode, and the second terminal can be the source electrode.

[0077] The third transistor T3 is an initialization transistor capable of initializing the second node N2, and can be turned on when a sense control signal is supplied from the control line CLi to transfer the voltage of the initialization power supply to the second node N2. Therefore, the storage capacitor Cst electrically connected to the second node N2 can be initialized.

[0078] The storage capacitor Cst can include a lower electrode LE (or a first storage electrode) and an upper electrode UE (or a second storage electrode). The lower electrode LE can be electrically connected to the first node N1, and the upper electrode UE can be electrically connected to the second node N2. During one frame period, the storage capacitor Cst charges a data voltage corresponding to the data signal supplied to the first node N1. Therefore, the storage capacitor Cst can store a voltage corresponding to the difference between the voltage of the gate electrode of the first transistor T1 and the voltage of the second node N2.

[0079] Although embodiments in which the first transistor T1, the second transistor T2, and the third transistor T3 are all N-type transistors have been disclosed in Figure 3 the present disclosure is not limited thereto. For example, at least one of the first transistor T1, the second transistor T2, and the third transistor T3 may be replaced with a P-type transistor.

[0080] The structure of the pixel circuit PXC can be variously modified and implemented.

[0081] In the following embodiments, for ease of description, the lateral direction on the plane (, the X-axis direction or the horizontal direction) is indicated as the first direction DR1, the longitudinal direction on the plane (, the Y-axis direction or the vertical direction) is indicated as the second direction DR2, and the longitudinal direction on the cross-section is indicated as the third direction DR3.

[0082] Figure 4 and Figure 5 is a schematic plan view showing a pixel PXL according to an embodiment of the present disclosure. Figure 6 is only showing Figure 5 the components included in the first conductive layer C1 in the pixel PXL shown in Figure 7 is only showing Figure 5 the transistors T1, T2, and T3 and the components included in the second conductive layer C2 in the pixel PXL shown in

[0083] In Figure 5 the pixel PXL shown in, additionally shown in Figure 4 the pixel PXL shown in are the first emission area EMA1 of the first sub-pixel SPX1, the second emission area EMA2 of the second sub-pixel SPX2, and the third emission area EMA3 of the third sub-pixel SPX3.

[0084] Referring to Figures 1 to 7 , the pixel PXL according to an embodiment of the present disclosure may be disposed in a pixel area PXA which is an area of a display area DA. The pixel area PXA (or the display area DA) may include a line area LA. For example, the line area LA may be located between two pixels PXL arranged adjacent to each other on the same pixel column. In an embodiment, the line area LA may be an area in which signal lines extending in the first direction DR1 are provided. For example, a first horizontal power line PL1b, a scan line SC, and a second horizontal power line PL2b extending in the first direction DR1 (or the horizontal direction) may be provided in the line area LA, but the present disclosure is not limited thereto.

[0085] A pixel PXL may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. The first sub-pixel SPX1 may include a first pixel circuit PXC1 and a first light-emitting element driven by the first pixel circuit PXC1 (see Figure 8 "LD1" shown therein). The second sub-pixel SPX2 may include a second pixel circuit PXC2 and a second light-emitting element driven by the second pixel circuit PXC2 (see Figure 8 "LD2" shown therein). The third sub-pixel SPX3 may include a third pixel circuit PXC3 and a third light-emitting element driven by the third pixel circuit PXC3 (see Figure 8 "LD3" shown therein). Each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 may be the pixel circuit PXC described with reference to Figure 3 , and each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 may be the light-emitting element LD described with reference to Figure 3 .

[0086] The pixel region PXA may include a first emission region EMA1, a second emission region EMA2, and a third emission region EMA3. In addition, the pixel region PXA may include a non-emission region NEA surrounding the first emission region EMA1, the second emission region EMA2, and the third emission region EMA3. A pixel defining layer (see Figure 8 "PDL" shown therein) defining the first emission region EMA1, the second emission region EMA2, and the third emission region EMA3 may be disposed in the non-emission region NEA.

[0087] The first emission region EMA1 may be a region where light is emitted from the first light-emitting element LD1 of the first sub-pixel SPX1. For example, the first emission region EMA1 may correspond to a region of a first light-emitting layer EML1 in which the first light-emitting element LD1 is disposed.

[0088] The second emission region EMA2 may be a region where light is emitted from the second light-emitting element LD2 of the second sub-pixel SPX2. For example, the second emission region EMA2 may correspond to a region of a second light-emitting layer EML2 in which the second light-emitting element LD2 is disposed.

[0089] The third emission region EMA3 may be a region where light is emitted from the third light-emitting element LD3 of the third sub-pixel SPX3. For example, the third emission region EMA3 may correspond to a region of a third light-emitting layer EML3 in which the third light-emitting element LD3 is disposed.

[0090] Signal lines electrically connected to the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be provided in the pixel region PXA. For example, the scan line SC, data lines D1, D2, and D3, power line PL, initialization power line IPL, etc. may be provided in the pixel region PXA, but the present disclosure is not limited thereto.

[0091] The scan line SC may be located in the line region LA and extend in the first direction DR1. A scan signal and a sensing control signal may be selectively supplied to the scan line SC. The scan line SC may be configured with the second conductive layer C2. The second conductive layer C2 may be formed as a single layer or multiple layers including molybdenum (Mo), copper (Cu), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), indium (In), tin (Sn), and their oxides or alloys.

[0092] The scan line SC may include a first sub-scan line SSL1 extending in the second direction DR2. The first sub-scan line SSL1 may be configured with the second conductive layer C2 and formed integrally with the scan line SC. The first sub-scan line SSL1 may be a region of the scan line SC.

[0093] The first sub-scan line SSL1 may be formed integrally with the second gate electrode GE2 of the second transistor T2 in each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3. For example, a part of the first sub-scan line SSL1 may be the second gate electrode GE2 of the second transistor T2 in each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3.

[0094] For example, the first sub-scan line SSL1 may be formed integrally with the third gate electrode GE3 of the third transistor T3 in each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3. For example, another part of the first sub-scan line SSL1 may be the third gate electrode GE3 of the third transistor T3 in each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3.

[0095] During the driving period of the light-emitting element LD, the scan line SC may supply a scan signal to the second gate electrode GE2 of the second transistor T2 in each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3, and supply a sensing control signal to the third gate electrode GE3 of the third transistor T3 in each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3.

[0096] The data lines D1, D2, and D3 may include a first data line D1, a second data line D2, and a third data line D3 that extend in a second direction DR2 and are arranged in a first direction DR1. Each of the first data line D1, the second data line D2, and the third data line D3 may be supplied with a data signal.

[0097] The first data line D1 may be electrically connected to a second transistor T2 of a first pixel circuit PXC1 (or a first sub-pixel SPX1), the second data line D2 may be electrically connected to a second transistor T2 of a second pixel circuit PXC2 (or a second sub-pixel SPX2), and the third data line D3 may be electrically connected to a second transistor T2 of a third pixel circuit PXC3 (or a third sub-pixel SPX3). Each of the first data line D1, the second data line D2, and the third data line D3 may be configured with a first conductive layer C1. The first conductive layer C1 may include the same material as the second conductive layer C2 described above, or may include a suitable (or selected) material among the materials exemplified as the material constituting the second conductive layer C2. However, the present disclosure is not limited thereto.

[0098] The power line PL may include a first power line PL1 and a second power line PL2.

[0099] The first power line PL1 may be supplied with a voltage of a first driving power voltage VDD. The first power line PL1 may include a first vertical power line PL1a and a first horizontal power line PL1b.

[0100] The first vertical power line PL1a may extend along the second direction DR2 and be disposed between a first storage capacitor Cst1, a second storage capacitor Cst2, and a third storage capacitor Cst3 and the first data line D1, the second data line D2, and the third data line D3 in a plan view. For example, the first vertical power line PL1a may be disposed between the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3 and an initialization power line IPL adjacent to the first data line D1. The first vertical power line PL1a may be configured with the first conductive layer C1. The first vertical power line PL1a may be electrically connected to the first horizontal power line PL1b located in a layer different from that of the first vertical power line PL1a through a corresponding contact hole.

[0101] The first horizontal power line PL1b can be located in the line region LA and extend in the first direction DR1. The first horizontal power line PL1b can be configured with the second conductive layer C2. The first vertical power line PL1a configured with the first conductive layer C1 and the first horizontal power line PL1b configured with the second conductive layer C2 can be electrically connected to each other through corresponding contact holes. The first power line PL1 can have a mesh structure due to the first vertical power line PL1a and the first horizontal power line PL1b being electrically connected to each other.

[0102] The second power line PL2 can be supplied with the voltage of the second driving power voltage VSS. The second power line PL2 can include a second vertical power line PL2a and a second horizontal power line PL2b.

[0103] The second vertical power line PL2a can extend along the second direction DR2 and be located on one side (e.g., the left side) of the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3 in the plan view. The second vertical power line PL2a can be configured with the first conductive layer C1. The second vertical power line PL2a can be electrically connected to an additional conductive pattern ACP located in a layer different from the layer of the second vertical power line PL2a through a corresponding contact hole.

[0104] The additional conductive pattern ACP can be configured with the second conductive layer C2 and extend in the second direction DR2 to overlap with the second vertical power line PL2a. The second vertical power line PL2a can be electrically connected to the additional conductive pattern ACP located in a layer different from the layer of the second vertical power line PL2a through a corresponding contact hole to be implemented as a double-layer structure. The line resistance of the second vertical power line PL2a can be reduced.

[0105] The second horizontal power line PL2b can be located in the line region LA and extend in the first direction DR1. The second horizontal power line PL2b can be configured with the second conductive layer C2. The second vertical power line PL2a configured with the first conductive layer C1 and the second horizontal power line PL2b configured with the second conductive layer C2 can be electrically connected to each other through corresponding contact holes. The second power line PL2 can have a mesh structure due to the second vertical power line PL2a and the second horizontal power line PL2b being electrically connected to each other.

[0106] The initialization power line IPL can extend in the second direction DR2 and be configured with the first conductive layer C1. The initialization power line IPL can be arranged in the plan view between the first vertical power line PL1a and the data lines D1, D2, and D3. The first vertical power line PL1a, the initialization power line IPL, and the data lines D1, D2, and D3 can be arranged to be spaced apart from each other in the first direction DR1. The initialization power line IPL can be a reference Figure 3The described sensing line SENj. The initialization power line IPL can be supplied with an initialization power voltage. The initialization power line IPL can be electrically connected to the third transistor T3 of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 (or the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3).

[0107] The first pixel circuit PXC1 of the first sub-pixel SPX1, the second pixel circuit PXC2 of the second sub-pixel SPX2, and the third pixel circuit PXC3 of the third sub-pixel SPX3 can have substantially similar or identical structures to each other. Hereinafter, the first pixel circuit PXC1 will be mainly described, and the descriptions of the second pixel circuit PXC2 and the third pixel circuit PXC3 will be simplified.

[0108] The first pixel circuit PXC1 can include a first transistor T1, a second transistor T2, a third transistor T3, and a first storage capacitor Cst1.

[0109] The first transistor T1 can include a first gate electrode GE1, a first active pattern ACT1, a first source electrode SE1, and a first drain electrode DE1.

[0110] The first gate electrode GE1 can be electrically connected to the second source electrode SE2 of the second transistor T2 through a corresponding contact hole. The first gate electrode GE1 can be configured with a second conductive layer C2. In an embodiment, the first gate electrode GE1 can be electrically connected to the bottom metal pattern BML through a corresponding contact hole. In an embodiment, the first gate electrode GE1 can be disposed between the first storage capacitor Cst1 and the first vertical power line PL1a.

[0111] The bottom metal pattern BML (or the first bottom metal pattern) can be configured with a first conductive layer C1 and overlap with the first transistor T1. The bottom metal pattern BML can be electrically connected to the first gate electrode GE1 through a corresponding contact hole. Since the bottom metal pattern BML is electrically connected to the first gate electrode GE1, the floating of the bottom metal pattern BML is prevented, and the line resistance of the first gate electrode GE1 can be reduced.

[0112] The first active pattern ACT1, the first source electrode SE1, and the first drain electrode DE1 can be configured with a semiconductor pattern made of polysilicon, amorphous silicon, or an oxide semiconductor, etc. The first active pattern ACT1, the first source electrode SE1, and the first drain electrode DE1 can be formed by an undoped or impurity-doped semiconductor layer. For example, the first source electrode SE1 and the first drain electrode DE1 can be doped with impurities to have conductivity, and the first active pattern ACT1 can be configured with an undoped intrinsic semiconductor layer.

[0113] The first active pattern ACT1 may be located on the bottom of the first gate electrode GE1 configured with the second conductive layer C2, so as to overlap with the first gate electrode GE1. The first active pattern ACT1 may constitute the channel region of the first transistor T1.

[0114] The first source electrode SE1 may be connected to one end of the first active pattern ACT1. The first source electrode SE1 may be doped with impurities in an impurity doping process performed after the formation of the second conductive layer C2 to have conductivity. In an embodiment, the first source electrode SE1 may be integrally formed with the third source electrode SE3 of the third transistor T3 to be connected to the third source electrode SE3.

[0115] The first drain electrode DE1 may be connected to the other end of the first active pattern ACT1. The first drain electrode DE1 may be doped with impurities in an impurity doping process performed after the formation of the second conductive layer C2 to have conductivity. The first drain electrode DE1 may be electrically connected to the first conductive pattern CP1 through a corresponding contact hole.

[0116] The first conductive pattern CP1 is configured with the second conductive layer C2 and overlaps with the first drain electrode DE1 and the first vertical power line PL1a. A part of the first conductive pattern CP1 may be electrically connected to the first drain electrode DE1 through a corresponding contact hole. Another part of the first conductive pattern CP1 may be electrically connected to the first vertical power line PL1a through a contact hole. The first drain electrode DE1 and the first vertical power line PL1a may be electrically connected to each other through the first conductive pattern CP1.

[0117] The second transistor T2 may include a second gate electrode GE2, a second active pattern ACT2, a second source electrode SE2, and a second drain electrode DE2.

[0118] The second gate electrode GE2 may be integrally formed with the first sub-scanning line SSL1 and configured with the second conductive layer C2. The second gate electrode GE2 may overlap with the second active pattern ACT2.

[0119] The second active pattern ACT2, the second source electrode SE2, and the second drain electrode DE2 may be configured with a semiconductor pattern made of polysilicon, amorphous silicon, or an oxide semiconductor, etc. The second source electrode SE2 and the second drain electrode DE2 may be doped with impurities to have conductivity, and the second active pattern ACT2 may be configured with an intrinsic semiconductor layer not doped with impurities.

[0120] The second active pattern ACT2 may be located on the bottom of the second gate electrode GE2, so as to overlap with the second gate electrode GE2. The second active pattern ACT2 may constitute the channel region of the second transistor T2.

[0121] The second source electrode SE2 may be connected to one end of the second active pattern ACT2. The second source electrode SE2 may be doped with impurities in an impurity doping process performed after forming the second conductive layer C2 to have conductivity. The second source electrode SE2 may be electrically connected to the first gate electrode GE1 through a corresponding contact hole.

[0122] The second drain electrode DE2 may be connected to the other end of the second active pattern ACT2. The second drain electrode DE2 may be doped with impurities in an impurity doping process performed after forming the second conductive layer C2 to have conductivity. The second drain electrode DE2 may be electrically connected to the second conductive pattern CP2 through a corresponding contact hole.

[0123] The second conductive pattern CP2 may be configured with the second conductive layer C2 and overlap with the first data line D1 and the second drain electrode DE2. A part of the second conductive pattern CP2 may be electrically connected to the second drain electrode DE2 through a corresponding contact hole. Another part of the second conductive pattern CP2 may be electrically connected to the first data line D1 through a contact hole. The second drain electrode DE2 and the first data line D1 may be electrically connected to each other through the second conductive pattern CP2.

[0124] The third transistor T3 may include a third gate electrode GE3, a third active pattern ACT3, a third source electrode SE3, and a third drain electrode DE3.

[0125] The third gate electrode GE3 may be configured with the second conductive layer C2 and integrally formed with the first sub-scanning line SSL1. The third gate electrode GE3 may overlap with the third active pattern ACT3.

[0126] The third active pattern ACT3, the third source electrode SE3, and the third drain electrode DE3 may be configured with a semiconductor pattern made of polysilicon, amorphous silicon, or an oxide semiconductor, etc. The third source electrode SE3 and the third drain electrode DE3 may be doped with impurities to have conductivity, and the third active pattern ACT3 may be configured with an undoped intrinsic semiconductor layer.

[0127] The third active pattern ACT3 may overlap with the third gate electrode GE3. The third active pattern ACT3 may constitute the channel region of the third transistor T3.

[0128] The third source electrode SE3 may be connected to one end of the third active pattern ACT3. The third source electrode SE3 may be doped with impurities in an impurity doping process performed after forming the second conductive layer C2 to have conductivity. The third source electrode SE3 may be integrally formed with the first source electrode SE1 to be connected to the first source electrode SE1. Since the third source electrode SE3 and the first source electrode SE1 are integrally formed, a separate first connection member for connecting the third source electrode SE3 and the first source electrode SE1 to each other may be omitted.

[0129] The third drain electrode DE3 may be connected to the other end of the third active pattern ACT3. The third drain electrode DE3 may be doped with impurities in an impurity doping process performed after the formation of the second conductive layer C2 to have conductivity. The third drain electrode DE3 may be electrically connected to the third conductive pattern CP3 through a corresponding contact hole.

[0130] The third conductive pattern CP3 may overlap with the initialization power line IPL and the third drain electrode DE3. A part of the third conductive pattern CP3 may be electrically connected to the third drain electrode DE3 through a corresponding contact hole. Another part of the third conductive pattern CP3 may be electrically connected to the initialization power line IPL through a contact hole. The third drain electrode DE3 and the initialization power line IPL may be electrically connected to each other through the third conductive pattern CP3.

[0131] The first storage capacitor Cst1 may include a first lower electrode LE1 and a first upper electrode UE1. The first storage capacitor Cst1 may be the storage capacitor Cst described in the reference Figure 3 description.

[0132] The first lower electrode LE1 may be configured with the first conductive layer C1 and integrally formed with the bottom metal pattern BML. The first lower electrode LE1 (or the bottom metal pattern BML) may be disposed between the second vertical power line PL2a and the first vertical power line PL1a in a plan view. In an embodiment, the first lower electrode LE1 may be electrically connected to the first gate electrode GE1 and the second source electrode SE2 through corresponding contact holes.

[0133] The first upper electrode UE1 may be integrally formed with the first source electrode SE1 and the third source electrode SE3 to be connected to the first source electrode SE1 and the third source electrode SE3. The first upper electrode UE1 may be configured with a semiconductor pattern made of polysilicon, amorphous silicon, or an oxide semiconductor, etc., and have conductivity after doping with impurities. The first upper electrode UE1 may overlap with the first lower electrode LE1 and have a size (or area) similar to or larger than the size (or area) of the first lower electrode LE1. However, the present disclosure is not limited thereto.

[0134] In an embodiment, the first upper electrode UE1 may be arranged not to overlap with the first gate electrode GE1. In a plan view, the first upper electrode UE1 may be disposed between the second vertical power line PL2a and the first vertical power line PL1a.

[0135] The first source electrode SE1, the third source electrode SE3, and the first upper electrode UE1 integrally formed in the first pixel circuit PXC1 having the above configuration may be electrically connected to the (1-1)th electrode AE1 (or the first anode) through a contact portion CNT.

[0136] The (1-1)th electrode AE1 may be configured with the third conductive layer C3. The third conductive layer C3 and the second conductive layer C2 may include the same material. The third conductive layer C3 may include at least one suitable material among the materials exemplified as the material of the second conductive layer C2. However, the present disclosure is not limited thereto. The (1-1)th electrode AE1 may overlap with some components (e.g., the first transistor T1 and the first storage capacitor Cst1 of the first pixel circuit PXC1). For example, the (1-1)th electrode AE1 may overlap with some signal lines electrically connected to the first pixel circuit PXC1. In an embodiment, the (1-1)th electrode AE1 may overlap with the first light-emitting layer EML1 corresponding to the first emission region EMA1. In the case where the first sub-pixel SPX1 is a red pixel, the first light-emitting layer EML1 may emit red light, but the present disclosure is not limited thereto.

[0137] The second pixel circuit PXC2 may include a first transistor T1, a second transistor T2, a third transistor T3, and a second storage capacitor Cst2.

[0138] The first transistor T1 may include a first gate electrode GE1, a first active pattern ACT1, a first source electrode SE1, and a first drain electrode DE1.

[0139] The first gate electrode GE1 may be electrically connected to the second source electrode SE2 of the second transistor T2 through a corresponding contact hole. The first gate electrode GE1 may be configured with the second conductive layer C2 and electrically connected to the bottom metal pattern BML (or the second lower electrode LE2) through a contact hole. In an embodiment, the first gate electrode GE1 may be located between the second storage capacitor Cst2 and the first vertical power line PL1a.

[0140] The bottom metal pattern BML (or the second bottom metal pattern) may be configured with the first conductive layer C1 and overlap with the first transistor T1. In addition, the bottom metal pattern BML may be integrally formed with the second lower electrode LE2 of the second storage capacitor Cst2.

[0141] The first active pattern ACT1 may overlap with the first gate electrode GE1. The first active pattern ACT1 may constitute the channel region of the first transistor T1.

[0142] The first source electrode SE1 may be connected to one end of the first active pattern ACT1. In an embodiment, the first source electrode SE1 may be integrally formed with the third source electrode SE3 of the third transistor T3 to be connected to the third source electrode SE3.

[0143] The first drain electrode DE1 may be connected to the other end of the first active pattern ACT1. The first drain electrode DE1 may be electrically connected to the fourth conductive pattern CP4 through a corresponding contact hole.

[0144] The fourth conductive pattern CP4 can be configured with the second conductive layer C2 and overlap with the first drain electrode DE1 and the first vertical power line PL1a. A part of the fourth conductive pattern CP4 can be electrically connected to the first drain electrode DE1 through a corresponding contact hole. Another part of the fourth conductive pattern CP4 can be electrically connected to the first vertical power line PL1a through a contact hole. The first drain electrode DE1 and the first vertical power line PL1a are electrically connected to each other through the fourth conductive pattern CP4.

[0145] The second transistor T2 can include a second gate electrode GE2, a second active pattern ACT2, a second source electrode SE2, and a second drain electrode DE2.

[0146] The second gate electrode GE2 can be integrally formed with the first sub-scanning line SSL1 and configured with the second conductive layer C2.

[0147] The second active pattern ACT2 can constitute the channel region of the second transistor T2.

[0148] The second source electrode SE2 can be connected to one end of the second active pattern ACT2. The second source electrode SE2 can be electrically connected to the first gate electrode GE1 through a corresponding contact hole.

[0149] The second drain electrode DE2 can be connected to the other end of the second active pattern ACT2. The second drain electrode DE2 can be electrically connected to the fifth conductive pattern CP5 through a corresponding contact hole.

[0150] The fifth conductive pattern CP5 can be configured with the second conductive layer C2 and overlap with the second data line D2 and the second drain electrode DE2. A part of the fifth conductive pattern CP5 can be electrically connected to the second drain electrode DE2 through a corresponding contact hole. Another part of the fifth conductive pattern CP5 can be electrically connected to the second data line D2 through a contact hole. The second drain electrode DE2 and the second data line D2 can be electrically connected to each other through the fifth conductive pattern CP5.

[0151] The third transistor T3 can include a third gate electrode GE3, a third active pattern ACT3, a third source electrode SE3, and a third drain electrode DE3.

[0152] The third gate electrode GE3 can be configured with the second conductive layer C2 and integrally formed with the first sub-scanning line SSL1.

[0153] The third active pattern ACT3 can constitute the channel region of the third transistor T3.

[0154] The third source electrode SE3 may be connected to one end of the third active pattern ACT3. The third source electrode SE3 may be integrally formed with the first source electrode SE1 to be connected to the first source electrode SE1. Since the third source electrode SE3 and the first source electrode SE1 are integrally formed, a separate second connection member for connecting the third source electrode SE3 and the first source electrode SE1 to each other may be omitted.

[0155] The third drain electrode DE3 may be connected to the other end of the third active pattern ACT3. The third drain electrode DE3 may be electrically connected to the sixth conductive pattern CP6 through a corresponding contact hole.

[0156] The sixth conductive pattern CP6 may be configured with the second conductive layer C2 and overlap with the third drain electrode DE3 and the initialization power line IPL. A part of the sixth conductive pattern CP6 may be electrically connected to the third drain electrode DE3 through a corresponding contact hole. Another part of the sixth conductive pattern CP6 may be electrically connected to the initialization power line IPL through a contact hole. The third drain electrode DE3 and the initialization power line IPL may be electrically connected to each other through the sixth conductive pattern CP6.

[0157] The second storage capacitor Cst2 may include a second lower electrode LE2 and a second upper electrode UE2. The second storage capacitor Cst2 may be the storage capacitor Cst described in Figure 3 the reference.

[0158] The second lower electrode LE2 may be configured with the first conductive layer C1 and integrally formed with the bottom metal pattern BML. The second lower electrode LE2 (or the bottom metal pattern BML) may be disposed between the second vertical power line PL2a and the first vertical power line PL1a in a plan view. In an embodiment, the second lower electrode LE2 may be electrically connected to the first gate electrode GE1 and the second source electrode SE2 through corresponding contact holes.

[0159] The second upper electrode UE2 may be integrally formed with the first source electrode SE1 and the third source electrode SE3 to be connected to the first source electrode SE1 and the third source electrode SE3. The second upper electrode UE2 may overlap with the second lower electrode LE2 and have a size (or area) similar to or larger than the size (or area) of the second lower electrode LE2. However, the present disclosure is not limited thereto.

[0160] In an embodiment, the second upper electrode UE2 may be arranged not to overlap with the first gate electrode GE1. In a plan view, the second upper electrode UE2 may be disposed between the second vertical power line PL2a and the first vertical power line PL1a.

[0161] The first source electrode SE1, the third source electrode SE3, and the second upper electrode UE2, which are integrally formed in the second pixel circuit PXC2 having the above configuration, may be electrically connected to the (1-2)th electrode AE2 (or the second anode) through the contact portion CNT.

[0162] The (1-2)th electrode AE2 may be configured with the third conductive layer C3. The (1-2)th electrode AE2 may overlap some components (e.g., the first transistor T1 and the second storage capacitor Cst2 of the second pixel circuit PXC2). For example, the (1-2)th electrode AE2 may overlap some signal lines electrically connected to the second pixel circuit PXC2. In an embodiment, the (1-2)th electrode AE2 may overlap the second light-emitting layer EML2 corresponding to the second emission region EMA2. When the second sub-pixel SPX2 is a green pixel, the second light-emitting layer EML2 may emit green light, but the present disclosure is not limited thereto.

[0163] The third sub-pixel PXC3 may include a first transistor T1, a second transistor T2, a third transistor T3, and a third storage capacitor Cst3.

[0164] The first transistor T1 may include a first gate electrode GE1, a first active pattern ACT1, a first source electrode SE1, and a first drain electrode DE1.

[0165] The first gate electrode GE1 may be electrically connected to the second source electrode SE2 of the second transistor T2 through a corresponding contact hole. The first gate electrode GE1 may be configured with the second conductive layer C2 and electrically connected to the bottom metal pattern BML (or the third lower electrode LE3) through a contact hole. In an embodiment, the first gate electrode GE1 may be disposed between the third storage capacitor Cst3 and the first vertical power line PL1a.

[0166] The bottom metal pattern BML (or the third bottom metal pattern) may be configured with the first conductive layer C1 and overlap the first transistor T1. For example, the bottom metal pattern BML may be integrally formed with the third lower electrode LE3 of the third storage capacitor Cst3.

[0167] The first active pattern ACT1 may overlap the first gate electrode GE1. The first active pattern ACT1 may constitute the channel region of the first transistor T1.

[0168] The first source electrode SE1 may be connected to one end of the first active pattern ACT1. In an embodiment, the first source electrode SE1 may be integrally formed with the third source electrode SE3 of the third transistor T3 to be connected to the third source electrode SE3.

[0169] The first drain electrode DE1 can be connected to the other end of the first active pattern ACT1. The first drain electrode DE1 can be electrically connected to the seventh conductive pattern CP7 through a corresponding contact hole.

[0170] The seventh conductive pattern CP7 can be configured with the second conductive layer C2 and overlap with the first drain electrode DE1 and the first vertical power line PL1a. A part of the seventh conductive pattern CP7 can be electrically connected to the first drain electrode DE1 through a corresponding contact hole. Another part of the seventh conductive pattern CP7 can be electrically connected to the first vertical power line PL1a through a contact hole. The first drain electrode DE1 and the first vertical power line PL1a can be electrically connected to each other through the seventh conductive pattern CP7.

[0171] The second transistor T2 can include a second gate electrode GE2, a second active pattern ACT2, a second source electrode SE2, and a second drain electrode DE2.

[0172] The second gate electrode GE2 can be integrally formed with the first sub-scanning line SSL1 and configured with the second conductive layer C2.

[0173] The second active pattern ACT2 can constitute the channel region of the second transistor T2.

[0174] The second source electrode SE2 can be connected to one end of the second active pattern ACT2. The second source electrode SE2 can be electrically connected to the first gate electrode GE1 through a corresponding contact hole.

[0175] The second drain electrode DE2 can be connected to the other end of the second active pattern ACT2. The second drain electrode DE2 can be electrically connected to the eighth conductive pattern CP8 through a corresponding contact hole.

[0176] The eighth conductive pattern CP8 can be configured with the second conductive layer C2 and overlap with the third data line D3 and the second drain electrode DE2. A part of the eighth conductive pattern CP8 can be electrically connected to the second drain electrode DE2 through a corresponding contact hole. Another part of the eighth conductive pattern CP8 can be electrically connected to the third data line D3 through a contact hole. The second drain electrode DE2 and the third data line D3 can be electrically connected to each other through the eighth conductive pattern CP8.

[0177] The third transistor T3 can include a third gate electrode GE3, a third active pattern ACT3, a third source electrode SE3, and a third drain electrode DE3.

[0178] The third gate electrode GE3 can be configured with the second conductive layer C2 and integrally formed with the first sub-scanning line SSL1.

[0179] The third active pattern ACT3 can constitute the channel region of the third transistor T3.

[0180] The third source electrode SE3 may be connected to one end of the third active pattern ACT3. The third source electrode SE3 may be integrally formed with the first source electrode SE1 to be connected to the first source electrode SE1. Since the third source electrode SE3 and the first source electrode SE1 are integrally formed, a separate third connection member for connecting the third source electrode SE3 and the first source electrode SE1 to each other may be omitted.

[0181] The third drain electrode DE3 may be connected to the other end of the third active pattern ACT3. The third drain electrode DE3 may be electrically connected to the ninth conductive pattern CP9 through a corresponding contact hole.

[0182] The ninth conductive pattern CP9 may be configured with the second conductive layer C2 and overlap with the third drain electrode DE3 and the initialization power line IPL. A part of the ninth conductive pattern CP9 may be electrically connected to the third drain electrode DE3 through a corresponding contact hole. Another part of the ninth conductive pattern CP9 may be electrically connected to the initialization power line IPL through a contact hole. The third drain electrode DE3 and the initialization power line IPL may be electrically connected to each other through the ninth conductive pattern CP9.

[0183] The third storage capacitor Cst3 may include a third lower electrode LE3 and a third upper electrode UE3. The third storage capacitor Cst3 may be the storage capacitor Cst described in Figure 3 the reference.

[0184] The third lower electrode LE3 may be configured with the first conductive layer C1 and integrally formed with the bottom metal pattern BML. The third lower electrode LE3 (or the bottom metal pattern BML) may be disposed between the second vertical power line PL2a and the first vertical power line PL1a in a plan view. In an embodiment, the third lower electrode LE3 may be electrically connected to the first gate electrode GE1 and the second source electrode SE2 through corresponding contact holes.

[0185] The third upper electrode UE3 may be integrally formed with the first source electrode SE1 and the third source electrode SE3 to be connected to the first source electrode SE1 and the third source electrode SE3. The third upper electrode UE3 may overlap with the third lower electrode LE3 and have a size (or area) similar to or larger than that of the third lower electrode LE3.

[0186] In an embodiment, the third upper electrode UE3 may be arranged not to overlap with the first gate electrode GE1. In a plan view, the third upper electrode UE3 may be disposed between the second vertical power line PL2a and the first vertical power line PL1a.

[0187] In the third pixel circuit PXC3 having the above configuration, the first source electrode SE1, the third source electrode SE3, and the third upper electrode UE3 integrally formed therein can be electrically connected to the (1-3)th electrode AE3 (or the third anode) through the contact portion CNT.

[0188] The (1-3)th electrode AE3 can be configured with the third conductive layer C3. The (1-3)th electrode AE3 can overlap some components (e.g., the first transistor T1 and the third storage capacitor Cst3 of the third pixel circuit PXC3). For example, the (1-3)th electrode AE3 can overlap some signal lines electrically connected to the third pixel circuit PXC3. In an embodiment, the (1-3)th electrode AE3 can overlap the third light-emitting layer EML3 corresponding to the third emission region EMA3. In the case where the third sub-pixel SPX3 is a blue pixel, the third light-emitting layer EML3 can emit blue light, but the present disclosure is not limited thereto.

[0189] In the above embodiment, the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3 can be arranged along the second direction DR2 and located on the same line. The first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3 in the pixel region PXA can be located between the second vertical power line PL2a and the first vertical power line PL1a. For example, the second vertical power line PL2a can be located on one side (e.g., the left side) of the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3 in the pixel region PXA, and the first vertical power line PL1a can be located on the other side (e.g., the right side) of the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3 in the pixel region PXA.

[0190] In a case where a first vertical power line PL1a is located on the right side of a first storage capacitor Cst1, a second storage capacitor Cst2, and a third storage capacitor Cst3, a first transistor T1 electrically connected to the first vertical power line PL1a in each of a first pixel circuit PXC1, a second pixel circuit PXC2, and a third pixel circuit PXC3 may be disposed on the right side of the storage capacitor of the corresponding pixel circuit. For example, the first transistor T1 of the first pixel circuit PXC1 may be located between the right side of the first storage capacitor Cst1 and the first vertical power line PL1a, the first transistor T1 of the second pixel circuit PXC2 may be located between the right side of the second storage capacitor Cst2 and the first vertical power line PL1a, and the first transistor T1 of the third pixel circuit PXC3 may be located between the right side of the third storage capacitor Cst3 and the first vertical power line PL1a. A first gate electrode GE1 of the first transistor T1 of the first pixel circuit PXC1 may be located between the right side of the first storage capacitor Cst1 and the first vertical power line PL1a, a first gate electrode GE1 of the first transistor T1 of the second pixel circuit PXC2 may be located between the right side of the second storage capacitor Cst2 and the first vertical power line PL1a, and a first gate electrode GE1 of the first transistor T1 of the third pixel circuit PXC3 may be located between the right side of the third storage capacitor Cst3 and the first vertical power line PL1a.

[0191] For example, in the above-described embodiment, an initialization power line IPL and first data lines D1, D2, and D3 electrically connected to the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 may be located on the right side of the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3, and are arranged to be spaced apart from the first vertical power line PL1a. The second vertical power line PL2a, the first storage capacitor Cst1, the second storage capacitor Cst2, the third storage capacitor Cst3, the first vertical power line PL1a, the initialization power line IPL, the first data line D1, the second data line D2, and the third data line D3 may be sequentially arranged in a pixel region PXA along a first direction DR1.

[0192] When the initialization power line IPL is located on the right side of the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3, the third transistor T3 of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 that is electrically connected to the initialization power line IPL may be located on the right side of the storage capacitor of the corresponding pixel circuit. For example, the third transistor T3 of the first pixel circuit PXC1 may be located between the right side of the first storage capacitor Cst1 and the initialization power line IPL, the third transistor T3 of the second pixel circuit PXC2 may be located between the right side of the second storage capacitor Cst2 and the initialization power line IPL, and the third transistor T3 of the third pixel circuit PXC3 may be located between the right side of the third storage capacitor Cst3 and the initialization power line IPL.

[0193] When the first data line D1 is located on the right side of the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3, the second transistor T2 of the first pixel circuit PXC1 that is electrically connected to the first data line D1 may be arranged on the right side of the first storage capacitor Cst1. When the second data line D2 is located on the right side of the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3, the second transistor T2 of the second pixel circuit PXC2 that is electrically connected to the second data line D2 may be arranged on the right side of the second storage capacitor Cst2. When the third data line D3 is located on the right side of the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3, the second transistor T2 of the third pixel circuit PXC3 that is electrically connected to the third data line D3 may be arranged on the right side of the third storage capacitor Cst3.

[0194] As described above, the first transistor T1, the second transistor T2, and the third transistor T3 of the first pixel circuit PXC1 may be located on the right side of the first storage capacitor Cst1, the first transistor T1, the second transistor T2, and the third transistor T3 of the second pixel circuit PXC2 may be located on the right side of the second storage capacitor Cst2, and the first transistor T1, the second transistor T2, and the third transistor T3 of the third pixel circuit PXC3 may be located on the right side of the third storage capacitor Cst3. In each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3, the electrical connection between the first gate electrode GE1 and the second source electrode SE2 (or the corresponding data line) may be made on the right side of the storage capacitor of the corresponding sub-pixel. Therefore, the influence of the electrical connection between the first gate electrode GE1 and the second source electrode SE2 on each of the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3 can be reduced or prevented. In each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3, the area (or size) of the first gate electrode GE1 of the first transistor T1 can be reduced, and the area of the storage capacitor of the corresponding sub-pixel can be ensured by the reduced area (or size) of the first gate electrode GE1. For example, in the first sub-pixel SPX1, the area of the first gate electrode GE1 of the first transistor T1 is reduced, and the areas of the first lower electrode LE1 and the first upper electrode UE1 are increased by the reduced area of the first gate electrode GE1, so that the overlapping area of the first lower electrode LE1 and the first upper electrode UE1 is further ensured, thereby increasing the capacitance of the first storage capacitor Cst1. In the second sub-pixel SPX2, the area of the first gate electrode GE1 of the first transistor T1 is reduced, and the areas of the second lower electrode LE2 and the second upper electrode UE2 are increased by the reduced area of the first gate electrode GE1, so that the overlapping area of the second lower electrode LE2 and the second upper electrode UE2 is further ensured, thereby increasing the capacitance of the second storage capacitor Cst2. In the third sub-pixel SPX3, the area of the first gate electrode GE1 of the first transistor T1 is reduced, and the areas of the third lower electrode LE3 and the third upper electrode UE3 are increased by the reduced area of the first gate electrode GE1, so that the overlapping area of the third lower electrode LE3 and the third upper electrode UE3 is further ensured, thereby increasing the capacitance of the third storage capacitor Cst3.

[0195] According to the above-described embodiment, the capacitance of each of the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3 is increased, thereby improving the reliability of the pixel PXL (or the display device DD).

[0196] According to the above-described embodiment, since the first source electrode SE1 of the first transistor T1 and the third source electrode SE3 of the third transistor T3 are integrally formed in each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3, connection members (e.g., contact holes, conductive patterns, etc.) for electrically connecting the first source electrode SE1 and the third source electrode SE3 can be omitted. Accordingly, the area of the first storage capacitor Cst1 in the first pixel circuit PXC1 is further ensured, thereby increasing the capacitance of the first storage capacitor Cst1. The area of the second storage capacitor Cst2 in the second pixel circuit PXC2 is further ensured, thereby increasing the capacitance of the second storage capacitor Cst2. Also, the area of the third storage capacitor Cst3 in the third pixel circuit PXC3 is further ensured, thereby increasing the capacitance of the third storage capacitor Cst3.

[0197] According to the above-described embodiment, when the first vertical power line PL1a is disposed on the right side of the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3, the first transistor T1, the second transistor T2, and the third transistor T3 in each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 can be located on the right side of the storage capacitor of the corresponding pixel circuit. The first transistor T1, the second transistor T2, and the third transistor T3 are easily formed on the right side of each of the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3, such that design constraints based on the positions of the first transistor T1, the second transistor T2, and the third transistor T3 can be reduced.

[0198] Hereinafter, reference will be made to Figures 8 to 10 mainly describe the stacked structure (or cross-sectional structure) of the pixel PXL according to the above-described embodiment.

[0199] Figure 8 is a schematic cross-sectional view taken along the line I-I' shown in Figure 5 . Figure 9 and Figure 10 is a schematic cross-sectional view taken along the line II-II' shown in Figure 5 .

[0200] Figure 10 shows Figure 9 a modification example of the position and the like of the second insulating layer INS2 in the embodiment shown in.

[0201] In Figures 8 to 10 , the stacked structure of the pixel PXL is simplified and shown, such that each electrode is shown as an electrode having a signal layer, and each insulating layer is shown as an insulating layer provided as a single layer, but the present disclosure is not limited thereto.

[0202] Regarding Figures 8 to 10 For the embodiments shown, parts that are different from the above embodiments will be mainly described to avoid redundancy.

[0203] Referring to Figures 1 to 10 , according to an embodiment of the present disclosure, a pixel PXL may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3 that are adjacent to each other.

[0204] The first sub-pixel SPX1 may include a first emission area EMA1 and a non-emission area NEA surrounding the first emission area EMA1. The second sub-pixel SPX2 may include a second emission area EMA2 and a non-emission area NEA surrounding the second emission area EMA2. The third sub-pixel SPX3 may include a third emission area EMA3 and a non-emission area NEA surrounding the third emission area EMA3.

[0205] Each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, and a packaging layer TFE.

[0206] The substrate SUB may include a transparent insulating material to allow light to transmit through it. The substrate SUB may be a rigid substrate or a flexible substrate.

[0207] Circuit elements (e.g., a first transistor T1, a second transistor T2, and a third transistor T3) and signal lines electrically connected to the circuit elements may be disposed in the pixel circuit layer PCL. A light-emitting element (see "LD" shown in Figure 3 ) electrically connected to the circuit elements of each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be disposed in the display element layer DPL.

[0208] At least one insulating layer may be disposed on the substrate SUB. For example, a first insulating layer INS1, a second insulating layer INS2, a third insulating layer INS3, and a fourth insulating layer INS4 stacked in sequence along a third direction DR3 may be disposed on the substrate SUB. For example, at least one conductive layer may be disposed on the substrate SUB. For example, the conductive layer may include a first conductive layer C1 disposed between the substrate SUB and the first insulating layer INS1, a second conductive layer C2 disposed on the second insulating layer INS2, and a third conductive layer C3 disposed on the fourth insulating layer INS4.

[0209] The first conductive layer C1 may include a first vertical power line PL1a, a second vertical power line PL2a, an initialization power line IPL, a first data line D1, a second data line D2, and a third data line D3, a bottom metal pattern BML, and a first lower electrode LE1, a second lower electrode LE2, and a third lower electrode LE3. The second conductive layer C2 may include a first horizontal power line PL1b, a second horizontal power line PL2b, an additional conductive pattern ACP, a first conductive pattern CP1 to a ninth conductive pattern CP9, a first gate electrode GE1, a second gate electrode GE2, and a third gate electrode GE3, a scan line SC, and a first sub-scan line SSL1. The third conductive layer C3 may include a (1-1) electrode AE1, a (1-2) electrode AE2, and a (1-3) electrode AE3.

[0210] The pixel circuit layer PCL may be disposed on the substrate SUB. The above-mentioned first insulating layer INS1, second insulating layer INS2, third insulating layer INS3, and fourth insulating layer INS4 may be disposed in the pixel circuit layer PCL.

[0211] The first insulating layer INS1 (or buffer layer) may be entirely disposed on the substrate SUB. The first insulating layer INS1 may prevent impurities from diffusing into the first transistor T1, the second transistor T2, and the third transistor T3. The first insulating layer INS1 may be an inorganic insulating layer including an inorganic material. The first insulating layer INS1 may include at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), and silicon oxynitride (SiO x N y ), or at least one of metal oxides such as aluminum oxide (AlO x ). The first insulating layer INS1 may be provided as a single layer, but may be provided as a multi-layer including at least two layers. In the case where the first insulating layer INS1 is provided as a multi-layer, the layers may be formed of the same material or different materials. The first insulating layer INS1 may be omitted depending on the material of the substrate SUB, process conditions, etc.

[0212] The second insulating layer INS2 (or gate insulating layer) may be entirely disposed on the first insulating layer INS1. The second insulating layer INS2 may include the same material as the above-mentioned first insulating layer INS1, or include a suitable (or selected) material among the material examples constituting the first insulating layer INS1. For example, the second insulating layer INS2 may include an inorganic insulating layer containing an inorganic material. In an embodiment, the second insulating layer INS2 may be as Figure 10The part shown is partially disposed on the first insulating layer INS1. For example, the second insulating layer INS2 can be etched together with the base material of the second conductive layer C2 during the manufacturing process of the second conductive layer C2 to be disposed only on the bottom of the second conductive layer C2. The second insulating layer INS2 can have the same width as the second conductive layer C2 located on top of it, but the present disclosure is not limited thereto.

[0213] The third insulating layer INS3 (or interlayer insulating layer) can be completely disposed and / or formed on the second insulating layer INS2. The third insulating layer INS3 can include the same material as the first insulating layer INS1, or include a suitable (or selected) material among the materials exemplified as the material constituting the first insulating layer INS1. For example, the third insulating layer INS3 can be an inorganic insulating layer including an inorganic material.

[0214] The fourth insulating layer INS4 (or via layer) can be completely disposed and / or formed on the third insulating layer INS3. The fourth insulating layer INS4 can be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. The inorganic insulating layer can include, for example, at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and aluminum oxide (AlO x ). The organic insulating layer can include, for example, at least one of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin. In an embodiment, the fourth insulating layer INS4 can be an organic insulating layer including an organic material.

[0215] Each of the second insulating layer INS2, the third insulating layer INS3, and the fourth insulating layer INS4 described above can be partially opened to include a contact portion CNT (or contact hole). The contact portion CNT can be a connection point for electrically connecting the light-emitting elements LD of each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 to each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3.

[0216] The pixel circuit layer PCL of each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may include a first transistor T1, a second transistor T2, and a third transistor T3 disposed on the first insulating layer INS1, and a storage capacitor. For example, the pixel circuit layer PCL of the first sub-pixel SPX1 may include a first transistor T1, a second transistor T2, and a third transistor T3 disposed on the first insulating layer INS1, and a first storage capacitor Cst1. The pixel circuit layer PCL of the second sub-pixel SPX2 may include a first transistor T1, a second transistor T2, and a third transistor T3 disposed on the first insulating layer INS1, and a second storage capacitor Cst2. The pixel circuit layer PCL of the third sub-pixel SPX3 may include a first transistor T1, a second transistor T2, and a third transistor T3 disposed on the first insulating layer INS1, and a third storage capacitor Cst3.

[0217] The first transistor T1 may include a first active pattern ACT1, a first source electrode SE1, and a first drain electrode DE1 disposed on the first insulating layer INS1, and a first gate electrode GE1 disposed on the second insulating layer INS2. A bottom metal pattern BML may be disposed on the bottom of the first transistor T1. The bottom metal pattern BML may be configured with a first conductive layer C1 located between the substrate SUB and the first insulating layer INS1, and integrally formed with a corresponding one of the first lower electrode LE1, the second lower electrode LE2, and the third lower electrode LE3.

[0218] The second transistor T2 may include a second active pattern ACT2, a second source electrode SE2, and a second drain electrode DE2 disposed on the first insulating layer INS1, and a second gate electrode GE2 disposed on the second insulating layer INS2.

[0219] The third transistor T3 may include a third active pattern ACT3, a third source electrode SE3, and a third drain electrode DE3 disposed on the first insulating layer INS1, and a third gate electrode GE3 disposed on the second insulating layer INS2.

[0220] The first storage capacitor Cst1 may include a first lower electrode LE1 disposed between a substrate SUB and a first insulating layer INS1, and a first upper electrode UE1 overlapping the first lower electrode LE1 with the first insulating layer INS1 interposed therebetween. The first lower electrode LE1 may be configured of a first conductive layer C1, and the first upper electrode UE1 may be configured of a semiconductor pattern disposed between the first insulating layer INS1 and a second insulating layer INS2 and doped with impurities to have conductivity. In the first sub-pixel SPX1, the first lower electrode LE1 may be integrally formed with a bottom metal pattern BML, and the first upper electrode UE1 may be integrally formed with a first source electrode SE1 and a third source electrode SE3. The first upper electrode UE1 may be electrically connected to partial components, such as a (1-1) electrode AE1 of a display element layer DPL, through a corresponding contact portion CNT.

[0221] The second storage capacitor Cst2 may include a second lower electrode LE2 disposed between a substrate SUB and a first insulating layer INS1, and a second upper electrode UE2 overlapping the second lower electrode LE2 with the first insulating layer INS1 interposed therebetween. The second lower electrode LE2 may be configured of a first conductive layer C1, and the second upper electrode UE2 may be configured of a semiconductor pattern disposed between the first insulating layer INS1 and a second insulating layer INS2 and doped with impurities to have conductivity. In the second sub-pixel SPX2, the second lower electrode LE2 may be integrally formed with a bottom metal pattern BML, and the second upper electrode UE2 may be integrally formed with a first source electrode SE1 and a third source electrode SE3. The second upper electrode UE2 may be electrically connected to partial components, such as a (1-2) electrode AE2 of a display element layer DPL, through a corresponding contact portion CNT.

[0222] The third storage capacitor Cst3 may include a third lower electrode LE3 disposed between a substrate SUB and a first insulating layer INS1, and a third upper electrode UE3 overlapping the third lower electrode LE3 with the first insulating layer INS1 interposed therebetween. The third lower electrode LE3 may be configured of a first conductive layer C1, and the third upper electrode UE3 may be configured of a semiconductor pattern disposed between the first insulating layer INS1 and a second insulating layer INS2 and doped with impurities to have conductivity. In the third sub-pixel SPX3, the third lower electrode LE3 may be integrally formed with a bottom metal pattern BML, and the third upper electrode UE3 may be integrally formed with a first source electrode SE1 and a third source electrode SE3. The third upper electrode UE3 may be electrically connected to partial components, such as a (1-3) electrode AE3 of a display element layer DPL, through a corresponding contact portion CNT.

[0223] The third insulating layer INS3 and the fourth insulating layer INS4 can be continuously provided and / or formed over the aforementioned first transistor T1, second transistor T2, and third transistor T3, as well as the first storage capacitor Cst1, second storage capacitor Cst2, and third storage capacitor Cst3.

[0224] The display element layer DPL can be provided and / or formed over the fourth insulating layer INS4.

[0225] The display element layer DPL can include a first light-emitting element LD1, a second light-emitting element LD2, a third light-emitting element LD3, and a pixel defining layer PDL. The first light-emitting element LD1 can be provided in the display element layer DPL of the first sub-pixel SPX1 and electrically connected to the first pixel circuit PXC1. The second light-emitting element LD2 can be provided in the display element layer DPL of the second sub-pixel SPX2 and electrically connected to the second pixel circuit PXC2. The third light-emitting element LD3 can be provided in the display element layer DPL of the third sub-pixel SPX3 and electrically connected to the third pixel circuit PXC3. Each of the first light-emitting element LD1, second light-emitting element LD2, and third light-emitting element LD3 can be the light-emitting element LD described in Figure 3 reference.

[0226] The first light-emitting element LD1 can include a (1-1)th electrode AE1, a first light-emitting layer EML1, and a second electrode CE. The second light-emitting element LD2 can include a (1-2)th electrode AE2, a second light-emitting layer EML2, and a second electrode CE. The third light-emitting element LD3 can include a (1-3)th electrode AE3, a third light-emitting layer EML3, and a second electrode CE.

[0227] The (1-1)th electrode AE1, (1-2)th electrode AE2, and (1-3)th electrode AE3 can be configured with a third conductive layer C3 provided and / or formed over the fourth insulating layer INS4 of the corresponding sub-pixel. The (1-1)th electrode AE1, (1-2)th electrode AE2, and (1-3)th electrode AE3 can be provided spaced apart from each other over the fourth insulating layer INS4. The (1-1)th electrode AE1 can be the anode of the first light-emitting element LD1, the (1-2)th electrode AE2 can be the anode of the second light-emitting element LD2, and the (1-3)th electrode AE3 can be the anode of the third light-emitting element LD3.

[0228] The (1-1) electrode AE1 can be electrically connected to the first upper electrode UE1 of the first storage capacitor Cst1 through a corresponding contact portion CNT. The (1-2) electrode AE2 can be electrically connected to the second upper electrode UE2 of the second storage capacitor Cst2 through a corresponding contact portion CNT. The (1-3) electrode AE3 can be electrically connected to the third upper electrode UE3 of the third storage capacitor Cst3 through a corresponding contact portion CNT.

[0229] Each of the (1-1) electrode AE1, the (1-2) electrode AE2, and the (1-3) electrode AE3 can be configured with a conductive material (or substance). The conductive material can include an opaque metal. The opaque metal can include, for example, metals such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and their alloys. However, the material of each of the (1-1) electrode AE1, the (1-2) electrode AE2, and the (1-3) electrode AE3 is not limited to the above embodiments. In some embodiments, the (1-1) electrode AE1, the (1-2) electrode AE2, and the (1-3) electrode AE3 can include a transparent conductive material (or substance). The transparent conductive material (or substance) can include conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), or indium tin zinc oxide (ITZO), conductive polymers such as poly(3,4-ethylenedioxythiophene) (PEDOT), etc. In the case where the (1-1) electrode AE1, the (1-2) electrode AE2, and the (1-3) electrode AE3 include a transparent conductive material (or substance), a separate conductive layer formed of an opaque metal can be added to reflect the light emitted from the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 in the image display direction of the display device DD (or the upper direction of the encapsulation layer TFE).

[0230] The (1-1) electrode AE1 can be at least located in the first emission region EMA1, the (1-2) electrode AE2 can be at least located in the second emission region EMA2, and the (1-3) electrode AE3 can be at least located in the third emission region EMA3.

[0231] The pixel defining layer PDL can be disposed on the pixel circuit layer PCL in the non-emission area NEA and define (or separate) the first emission area EMA1, the second emission area EMA2, and the third emission area EMA3. The pixel defining layer PDL can include an organic insulating layer made of an organic material. The organic material can include acrylic resins, epoxy resins, phenolic resins, polyamide resins, polyimide resins, and the like. In some embodiments, the pixel defining layer PDL can include a light absorbing material or have a light absorbent coated thereon to absorb light introduced from the outside. For example, the pixel defining layer PDL can include a carbon-based black pigment. However, the present disclosure is not limited thereto.

[0232] The pixel defining layer PDL can be partially open to include an opening OP that exposes an area of each of the (1-1) electrode AE1, the (1-2) electrode AE2, and the (1-3) electrode AE3, and protrude from the fourth insulating layer INS4 in the third direction DR3 along the periphery of each of the first emission area EMA1, the second emission area EMA2, and the third emission area EMA3.

[0233] The first light emitting layer EML1 can be disposed on the (1-1) electrode AE1 exposed by the opening OP of the pixel defining layer PDL, the second light emitting layer EML2 can be disposed on the (1-2) electrode AE2 exposed by another opening OP of the pixel defining layer PDL, and the third light emitting layer EML3 can be disposed on the (1-3) electrode AE3 exposed by yet another opening OP of the pixel defining layer PDL.

[0234] The first light emitting layer EML1 can be located only on the (1-1) electrode AE1 within the opening OP of the pixel defining layer PDL, the second light emitting layer EML2 can be located only on the (1-2) electrode AE2 within another opening OP of the pixel defining layer PDL, and the third light emitting layer EML3 can be located only on the (1-3) electrode AE3 within yet another opening OP of the pixel defining layer PDL. Each of the first light emitting layer EML1, the second light emitting layer EML2, and the third light emitting layer EML3 can be supplied to a desired area of the corresponding sub-pixel (e.g., supplied onto an area of the first electrode (see "AE" shown in Figure 3 ), which is exposed by the opening OP of the pixel defining layer PDL), but the present disclosure is not limited thereto.

[0235] Each of the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 may have a multi-layer thin film structure including a light-generating layer that generates light. For example, the first light-emitting layer EML1 may include a light-generating layer that generates and emits red light, the second light-emitting layer EML2 may include a light-generating layer that generates and emits green light, and the third light-emitting layer EML3 may include a light-generating layer that generates and emits blue light. However, the present disclosure is not limited thereto. In some embodiments, each of the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 may include a light-generating layer that generates and emits white light. A color conversion layer or the like for converting white light (or light of a first color) into light of a specific color (or light of a second color) may be provided.

[0236] The second electrode CE may be provided and / or formed over the first light-emitting layer EML1, the second light-emitting layer EML2, the third light-emitting layer EML3, and the pixel defining layer PDL.

[0237] The second electrode CE may be a common layer commonly provided in the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. The second electrode CE may be provided in a plate shape over the entire area of the display area DA, but the present disclosure is not limited thereto.

[0238] The second electrode CE may be a thin metal layer having a thickness such that light emitted from each of the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 can pass through it. The second electrode CE may be formed of a metal material to have a relatively thin thickness or formed of a transparent conductive material. For example, the second electrode CE may be configured with various transparent conductive materials. The second electrode CE may include at least one of various transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, and gallium tin oxide, and is formed to be substantially transparent or semi-transparent to satisfy a predetermined transmittance. Thus, light emitted from each of the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 located at the bottom of the second electrode CE can be emitted upward from the encapsulation layer TFE while passing through the second electrode CE.

[0239] For example, the second electrode CE may be electrically connected to the second power line PL2.

[0240] The encapsulation layer TFE may be completely provided and / or formed over the second electrode CE.

[0241] The encapsulation layer TFE may include a first capping layer ENC1, a second capping layer ENC2, and a third capping layer ENC3 that are sequentially located on the second electrode CE. The first capping layer ENC1 may be formed on the display element layer DPL (or the second electrode CE) and located in at least a part of the non-display area NDA and the entire display area DA. The second capping layer ENC2 may be formed on the first capping layer ENC1 and located in at least a part of the non-display area NDA and the entire display area DA. The third capping layer ENC3 may be formed on the second capping layer ENC2 and located in at least a part of the non-display area NDA and the entire display area DA. In some embodiments, the third capping layer ENC3 may be located in the entire display area DA and the entirety of the non-display area NDA.

[0242] Each of the first capping layer ENC1 and the third capping layer ENC3 may be configured to include an inorganic layer of an inorganic material, and the second capping layer ENC2 may be configured to include an organic layer of an organic material. The inorganic layer may include, for example, silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), etc. The organic layer may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, or benzocyclobutene (BCB).

[0243] In some embodiments, a color filter layer and / or a color conversion layer for releasing the light emitted from the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 as light having excellent color reproducibility may be selectively provided and / or formed on the encapsulation layer TFE.

[0244] Figure 11 Shows a pixel PXL according to an embodiment of the present disclosure and is a schematic cross-sectional view corresponding to the line I-I' shown in Figure 5 .

[0245] Regarding Figure 11 the embodiment shown in, parts that are different from parts of the above embodiment will be mainly described to avoid redundancy.

[0246] Referring to Figures 1 to 5 and Figure 11 , a pixel PXL according to an embodiment of the present disclosure may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, an encapsulation layer TFE, a color filter layer CFL, and an outer coating OC.

[0247] The color filter layer CFL can be formed on top of the encapsulation layer TFE through a continuous process. The color filter layer CFL can include a color filter CF and a light blocking pattern BM. The color filter CF can include a first color filter CF1, a second color filter CF2, and a third color filter CF3.

[0248] The first color filter CF1 can be disposed on one surface of the third encapsulation layer ENC3 of the encapsulation layer TFE to correspond to the first light emitting layer EML1. The second color filter CF2 can be disposed on one surface of the third encapsulation layer ENC3 of the encapsulation layer TFE to correspond to the second light emitting layer EML2. The third color filter CF3 can be disposed on one surface of the third encapsulation layer ENC3 of the encapsulation layer TFE to correspond to the third light emitting layer EML3.

[0249] The light blocking pattern BM can be positioned adjacent to the first color filter CF1, the second color filter CF2, and the third color filter CF3 on one surface of the third encapsulation layer ENC3 of the encapsulation layer TFE. For example, the light blocking pattern BM can be disposed on one surface of the third encapsulation layer ENC3 in the non-emitting area NEA to correspond to the pixel defining layer PDL. The light blocking pattern BM can include a light blocking material. For example, the light blocking pattern BM can be a black matrix, but the present disclosure is not limited thereto. In some embodiments, the light blocking pattern BM can include at least one light blocking material and / or at least one reflective material to allow the light emitted from each of the first light emitting layer EML1, the second light emitting layer EML2, and the third light emitting layer EML3 to further advance in the image display direction of the display device DD, thereby improving the light emission efficiency. The light blocking pattern BM can prevent color mixing of the light emitted from the first light emitting layer EML1, the second light emitting layer EML2, and the third light emitting layer EML3.

[0250] Each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 can include a colorant such as a dye or a pigment that absorbs wavelengths other than the corresponding color wavelengths. The first color filter CF1 can be a red color filter, the second color filter CF2 can be a green color filter, and the third color filter CF3 can be a blue color filter. Although the case where adjacent color filters CF are shown spaced apart from each other and the light blocking pattern BM is interposed therebetween in the drawings, the adjacent color filters CF can at least partially overlap each other on the light blocking pattern BM. In some embodiments, the first color filter CF1, the second color filter CF2, and the third color filter CF3 can be used as light blocking members that are arranged to overlap each other in the non-emitting area NEA to block light interference between adjacent sub-pixels. The light blocking pattern BM can be omitted.

[0251] An outer coating OC can be disposed on top of the above-described color filter layer CFL.

[0252] An outer coating OC may be provided over the color filter layer CFL to cover a lower member including the color filter layer CFL. The outer coating OC may prevent external moisture, external air, etc. from infiltrating into the color filter layer CFL and damaging or contaminating the color filter layer CFL. For example, the outer coating OC may prevent the colorant of the color filter layer CFL from diffusing into another component. The outer coating OC may include an inorganic insulating layer containing an inorganic material, but the present disclosure is not limited thereto.

[0253] Figure 12 is a schematic plan view showing a pixel PXL according to an embodiment of the present disclosure. Figure 13 only shows Figure 12 a schematic plan view of components included in the first conductive layer C1 in the pixel PXL shown in Figure 14 only shows Figure 12 a schematic plan view of the transistors T1, T2, and T3 in the pixel PXL shown in Figure 15 is a schematic cross-sectional view taken along the line III-III' shown in Figure 12

[0254] Figure 12 The embodiment shown in Figure 4 shows a modified example regarding the position of the initialization power line IPL and the like shown in

[0255] Regarding Figures 12 to 15 the embodiment shown in

[0256] Reference Figures 1 to 3 and Figures 12 to 15 According to an embodiment of the present disclosure, a pixel PXL may include a first sub-pixel SPX1 including a first pixel circuit PXC1, a second sub-pixel SPX2 including a second pixel circuit PXC2, and a third sub-pixel SPX3 including a third pixel circuit PXC3. Each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 may include a first transistor T1, a second transistor T2, and a third transistor T3, and a storage capacitor Cst.

[0257] Signal lines electrically connected to the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 may be provided in a pixel region PXA in which the pixel PXL is provided. For example, a scan line SC, a first data line D1, a second data line D2, a third data line D3, a power line PL, and an initialization power line IPL may be provided in the pixel region PXA.

[0258] ​The scan line SC may be configured with the second conductive layer C2. The scan line SC extends along the first direction DR1 and is disposed on the second insulating layer INS2. The scan line SC may include a first sub-scan line SSL1 and a second sub-scan line SSL2 that extend in the second direction DR2. The first sub-scan line SSL1 may be integrally formed with the second gate electrode GE2 of the second transistor T2 of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3. The second sub-scan line SSL2 may be integrally formed with the third gate electrode GE3 of the third transistor T3 of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3.

[0259] The first data line D1 may be electrically connected to the second transistor T2 of the first pixel circuit PXC1, the second data line D2 may be electrically connected to the second transistor T2 of the second pixel circuit PXC2, and the third data line D3 may be electrically connected to the second transistor T2 of the third pixel circuit PXC3.

[0260] The power line PL may include a first power line PL1 and a second power line PL2. The first power line PL1 may include a first vertical power line PL1a and a first horizontal power line PL1b that are disposed in different layers and are electrically connected to each other through corresponding contact holes. The second power line PL2 may include a second vertical power line PL2a and a second horizontal power line PL2b that are disposed in different layers and are electrically connected to each other through corresponding contact holes. In an embodiment, the first vertical power line PL1a may be disposed between the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3 and the first data line D1.

[0261] The initialization power line IPL may be disposed in a plan view between the second vertical power line PL2a and the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3. The second vertical power line PL2a may be located at one side (e.g., the left side) of the initialization power line IPL, and each of the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3 may be located at the other side (e.g., the right side) of the initialization power line IPL.

[0262] In an embodiment, the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3 may be arranged along the second direction DR2 and located on the same line. The first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3 may be located between the initialization power line IPL and the first vertical power line PL1a. The initialization power line IPL may be located at one side (e.g., the left side) of the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3, and the first vertical power line PL1a may be located at the other side (e.g., the right side) of the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3.

[0263] When the first vertical power line PL1a is located at the right side of the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3, the first transistor T1 electrically connected to the first vertical power line PL1a in each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 may be arranged at the right side of the storage capacitor of the corresponding pixel circuit. In an embodiment, the first data line D1, the second data line D2, and the third data line D3 may be located at one side (e.g., the right side) of the first vertical power line PL1a and spaced apart from the first vertical power line PL1a along the first direction DR1. When each of the first data line D1, the second data line D2, and the third data line D3 is located at the right side of the first vertical power line PL1a, the second transistor T2 electrically connected to the first data line D1 in the first pixel circuit PXC1, the second transistor T2 electrically connected to the second data line D2 in the second pixel circuit PXC2, and the second transistor T2 electrically connected to the third data line D3 in the third pixel circuit PXC3 may be arranged at the right side of the storage capacitor of the corresponding pixel circuit.

[0264] When the initialization power line IPL is located at the left side of the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3, the third transistor T3 electrically connected to the initialization power line IPL in each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 may be arranged at the left side of the storage capacitor of the corresponding pixel circuit.

[0265] As described above, with respect to each of the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3, the first transistor T1 and the second transistor T2 may be disposed on their right sides, and the third transistor T3 may be disposed on their left sides. The direct influence of the electrical connection between the first gate electrode GE1 of the first transistor T1 and the second source electrode SE2 of the second transistor T2 on each of the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3 can be reduced or prevented. Accordingly, the area (or size) of the first gate electrode GE1 of the first transistor T1 in each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 (or the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3) can be reduced, and the area of the storage capacitor of the corresponding sub-pixel is further ensured by the reduced area (or size) of the first gate electrode GE1, thereby increasing the capacitance of the storage capacitor.

[0266] Exemplary embodiments have been disclosed herein, and although specific terms are employed, they are used in a generic and descriptive sense and are to be construed as such and not for purposes of limitation. In some instances, as will be apparent to those of ordinary skill in the art as of the filing of the present application, unless otherwise expressly stated, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments.

[0267] Accordingly, it will be understood by those of skill in the art that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure as set forth in the following claims.

Claims

1. A display device, comprising: A first sub-pixel, a second sub-pixel, and a third sub-pixel adjacent to each other, wherein the first sub-pixel, the second sub-pixel, and the third sub-pixel each have a storage capacitor; A scan line selectively transmitting a scan signal and a control signal to each of the first sub-pixel to the third sub-pixel, the scan line extending in a first direction; A data line transmitting a data signal to each of the first sub-pixel to the third sub-pixel, the data line extending in a second direction intersecting the first direction; And A first power line electrically connected to each of the first sub-pixel, the second sub-pixel, and the third sub-pixel, and the first power line is supplied with a first driving power voltage, Wherein the first power line is located between the storage capacitor and the data line.

2. The display device according to claim 1, further comprising: A substrate; A first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer sequentially disposed on the substrate; A second power line supplied with a second driving power voltage different from the first driving power voltage; And An initialization power line supplied with an initialization power voltage, Wherein the first power line includes a first vertical power line and a first horizontal power line, the first vertical power line is configured with a first conductive layer disposed on the substrate, the first horizontal power line is configured with a second conductive layer disposed on the second insulating layer, and Wherein, in a plan view, the first vertical power line is located between the storage capacitor of each of the first sub-pixel, the second sub-pixel, and the third sub-pixel and the data line.

3. The display device according to claim 2, wherein, Each of the first sub-pixel, the second sub-pixel, and the third sub-pixel includes: A light-emitting element; A first transistor controlling the current of the light-emitting element; A second transistor connected between the data line and the gate electrode of the first transistor, the second transistor being turned on by the scan signal; A third transistor connected between the initialization power line and the source electrode of the first transistor, the third transistor being turned on by the control signal; and The storage capacitor includes a lower electrode and an upper electrode, the lower electrode is electrically connected to the gate electrode of the first transistor and the source electrode of the second transistor, and the upper electrode is electrically connected to the source electrode of the first transistor and the source electrode of the third transistor.

4. The display device according to claim 3, wherein, The first transistor, the second transistor, and the third transistor are located at one side of the storage capacitor.

5. The display device according to claim 3, wherein, The second power line includes a second vertical power line configured with the first conductive layer and a second horizontal power line configured with the second conductive layer, and Wherein, in a plan view, the storage capacitor is located between the second vertical power line and the first vertical power line.

6. The display device according to claim 5, wherein, In a plan view, the initialization power line is located between the first vertical power line and the data line.

7. The display device according to claim 6, wherein, The gate electrode of the first transistor of each of the first sub-pixel, the second sub-pixel, and the third sub-pixel is disposed between the storage capacitor and the first vertical power line.

8. The display device according to claim 3, wherein, The lower electrode is disposed on the substrate, and the upper electrode is disposed on the first insulating layer so as to overlap the lower electrode, and the first insulating layer is interposed between the lower electrode and the upper electrode.

9. The display device according to claim 8, wherein, The upper electrode and the active pattern of each of the first transistor, the second transistor, and the third transistor are disposed in the same layer.

10. The display device according to claim 9, wherein, The upper electrode is integrally formed with the source electrode of the first transistor and the source electrode of the third transistor.

11. The display device according to claim 3, wherein, The light-emitting element includes: a first electrode configured with a third conductive layer disposed on the fourth insulating layer; a light-emitting layer disposed on the first electrode; and a second electrode disposed on the light-emitting layer.

12. The display device according to claim 11, wherein, The first electrode is electrically connected to the source electrode of the first transistor through a contact portion that penetrates the second insulating layer to the fourth insulating layer.

13. The display device according to claim 5, wherein, In a plan view, the initialization power line is located between the second vertical power line and the storage capacitor.

14. The display device according to claim 13, wherein, In a plan view, the initialization power line is located at one side of the storage capacitor, and the first vertical power line is located at the other side of the storage capacitor.

15. The display device according to claim 14, wherein, In a plan view, among the first transistor, the second transistor, and the third transistor, the third transistor is located at one side of the storage capacitor, and the first transistor and the second transistor among the first to third transistors are located at the other side of the storage capacitor.

16. The display device according to claim 3, wherein, Each of the first sub-pixel, the second sub-pixel, and the third sub-pixel further includes: a packaging layer disposed on the light-emitting element; a color filter layer disposed on the packaging layer; and an outer coating layer disposed on the color filter layer.

17. A display device, comprising: a substrate; a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer, sequentially stacked on the substrate; a first sub-pixel, a second sub-pixel, and a third sub-pixel, each including a pixel circuit and a light-emitting element electrically connected to the pixel circuit, the pixel circuit including a storage capacitor disposed on the substrate and a first transistor, a second transistor, and a third transistor; a scan line disposed on the substrate, the scan line selectively transmitting a scan signal and a control signal to each of the first sub-pixel, the second sub-pixel, and the third sub-pixel; a data line transmitting a data signal to each of the first to third sub-pixels; a first power line supplied with a first power voltage; a second power line supplied with a second power voltage different from the first power voltage; and an initialization power line supplied with an initialization power voltage different from the first power voltage and the second power voltage, wherein a gate electrode of the first transistor is located between the storage capacitor and the first power line.

18. The display device according to claim 17, wherein the first power line includes a first vertical power line disposed on the substrate and a first horizontal power line disposed on the second insulating layer, and the first vertical power line is located between the storage capacitor and the data line.

19. The display device according to claim 18, wherein, In a plan view, the first transistor, the second transistor, and the third transistor are located at one side of the storage capacitor.

20. The display device according to claim 18, wherein, In a plan view, the storage capacitor is located between the initialization power line and the first vertical power line.

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