Flash memory device supporting pseudo operation suspension and resumption and control method

Abstract

The present invention provides a flash memory device and control method that supports pseudo-operation pause and resume. The device includes a pseudo-operation pause and resume control module, a flash array basic operation module, and a flash array with customizable capacity. The pseudo-operation pause and resume control module is responsible for receiving and processing operation commands sent by a host computer and sending the processed commands to the flash array basic operation module. The flash array basic operation module is responsible for processing received read, program, and erase operation commands, ensuring that the flash memory correctly executes read, program, and erase operations through the scheduling control of multiple eFLASH IPs. The customizable flash array is used to execute each command operation. The present invention implements program / erase pause and resume operations for the flash memory, ensures correct response to program pause and erase pause commands, and improves the efficiency and reliability of the memory.

Description

Technical Field

[0001] The present invention relates to the technical field of flash memory, and in particular to a flash memory device supporting pseudo-operation suspension and resumption and a control method thereof. Background Art

[0002] Flash memory, an electrically erasable and programmable memory, has penetrated deeply into key sectors such as embedded systems, aerospace, and consumer electronics thanks to its remarkable properties, including non-volatility, high-speed read / write speeds, strong shock resistance, low power consumption, and compact size. As one of the core technologies of modern storage, flash memory not only carries the heavy responsibility of data storage but also plays an indispensable role in driving the advancement of information technology. Flash memory includes NOR flash memory and NAND flash memory. The basic storage unit of NOR flash memory is the bit, allowing users to randomly access any bit of information. The basic storage unit of NAND flash memory is the page, allowing erase operations at the block level (sector) and programming and reading operations at the page level (page).

[0003] Flash memory's basic operations fall into three categories: reading, programming (writing), and erasing. Reading is quick and straightforward, while programming and erasing are relatively time-consuming. The ability to pause and resume flash memory operations is particularly important if the user needs to temporarily attend to other tasks during programming or erasing. However, current technologies that support this functionality rely on design optimizations of the flash memory's underlying hardware storage circuitry. This approach is not only costly but also limited in flexibility. Once an operation is paused, the initial operation is interrupted, significantly reducing the flash memory's operating efficiency. Consequently, flash memory currently faces unprecedented challenges: on the one hand, requirements for storage density, read speed, and erase / write speed are increasing; on the other hand, flexibility has become a key performance metric for flash memory.

[0004] To meet these requirements, developers have attempted to implement customizable flash memory capacity by splicing multiple eFLASH IPs together. However, this approach is not perfect. Most fab eFLASH IPs do not support operation pauses. Once an operation (such as erase or program) begins, it must wait until the current operation completes before accepting a new command. This limitation can lead to delayed or even lost commands and prevents users from pausing the current operation to perform other tasks, thus reducing the memory's reliability and flexibility. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the present invention provides a flash memory device and a control method that supports pseudo-operation suspension and resumption, which are specifically implemented through the following technical solutions:

[0006] On the one hand, a flash memory device supporting pseudo operation suspension and resumption is provided, the device comprising three modules: a pseudo operation suspension and resumption control module, a flash array basic operation module, and a flash array with customizable capacity;

[0007] The pseudo operation pause and resume control module is responsible for receiving and processing the read, program, erase, and program / erase pause and resume operation commands sent by the host computer, and sending the processed commands to the Flash array basic operation module;

[0008] The Flash array basic operation module is responsible for processing received read, program, and erase operation commands, and controlling the customizable Flash array through the scheduling of multiple eFLASH IPs to ensure that the flash memory correctly executes read, program, and erase operations;

[0009] The capacity can be customized Flash array, used to execute various command operations; the module adopts multiple eFLASH IP splicing expansion, and the eFLASH IPs respectively correspond to the sectors of the flash memory to realize the structured division of the hardware circuit.

[0010] Furthermore, the interface signals of the flash memory device include chip select (ce_n), output enable (oe_n), operation command (command), address line (addr), data line (data), and idle / busy (ryby). The idle / busy (ryby) signal indicates whether the flash memory is in an idle or busy state. When the flash memory is not performing any operation, the signal is idle; otherwise, the signal is busy. Generally, a flash memory can only receive new program or erase commands when it is in the idle state.

[0011] Furthermore, the pseudo-operation suspension and resumption control module further includes a command arbitration unit for processing new commands received during the pseudo-operation suspension period by arbitrating the priority levels of the initial operation and the new command.

[0012] Furthermore, the pseudo-operation pause and resume control module further includes:

[0013] When a program / erase suspend or resume operation command is received, the pseudo operation suspend and resume control module enters or exits a pseudo program / erase suspend state;

[0014] When a read, program, or erase operation command is received, it is necessary to determine whether the pseudo operation pause and resume control module is in a pseudo program / erase pause state, wherein:

[0015] If it is in the pseudo program / erase pause state, after the pseudo operation pause and resume control module internal control logic and command arbitration, it is determined whether to transmit the command to the Flash array basic operation module;

[0016] If the module is not in the pseudo program / erase pause state, the received command is directly transmitted to the Flash array basic operation module.

[0017] Furthermore, in the Flash array basic operation module, the Flash array basic operation module implements read, program, and erase operations by controlling multiple eFLASH IPs, specifically:

[0018] The read operation is divided into two types: a read data operation and a read status operation. When the customizable Flash array is performing a program / erase operation, the read operation is a read status operation, and the state of the flash memory is read out. Otherwise, the read operation is a read data operation, and the data of the flash memory address is read out.

[0019] The program / erase operation uses an operation register and a data memory to store the operation information of multiple eFLASH IPs, wherein: the operation register is divided into a program operation register and an erase operation register, which are used to store sector / eFLASH IP information for program and erase operations respectively; the data memory is used to store data for program operations.

[0020] Furthermore, in the capacity-customizable Flash array, the capacity-customizable Flash array is based on the splicing expansion of multiple eFLASH IPs, and the hardware circuit of the flash memory is divided. One or more eFLASH IPs correspond to one or more sectors (SA) of the memory, respectively, to realize a structured flash memory storage array.

[0021] On the other hand, the present invention also provides a method for controlling a flash memory device that supports suspending and resuming pseudo operations, the method comprising the following steps:

[0022] Step 1: The pseudo operation suspend and resume module receives a new command from the host computer in the pseudo program / erase suspend state and determines whether the initial program / erase operation of the customizable Flash array executed by the eFLASH IP in the program / erase suspend state has completely completed. Based on the status, the module transmits the new command to the Flash array basic operation module.

[0023] Step 2: The Flash array basic operation module receives the new command issued by the pseudo operation suspend and resume module, generates a control signal and timing for the eFLASH IP to execute the new command operation, and transmits the control signal to the capacity customizable Flash array according to the timing;

[0024] Step 3: The capacity-customizable Flash array receives the control signal and executes the new command operation of the flash memory.

[0025] Furthermore, in step 1, the new command includes a read operation command, a program operation command, and an erase operation command, wherein:

[0026] The read operation command is controlled by the chip select signal (ce_n) and output enable signal (oe_n) sent by the host computer. If both signals are valid at low levels, then when both ce_n and oe_n are low, the flash memory recognizes it as a read command and performs the read operation;

[0027] The program operation command and the erase operation command are sent by the host computer as corresponding operation instructions, wherein: the erase operation command includes a sector erase command and a whole chip erase command.

[0028] Furthermore, in step 1, the process of determining whether the initial program / erase operation of the customizable capacity Flash array by the program / erase-suspended eFLASHIP is completely completed and transmitting a new command to the Flash array basic operation module based on the status may further include:

[0029] Step 101: If the status is "Ended", it means that the capacity customizable Flash array is completely idle, and the new command is directly transmitted to the Flash array basic operation module;

[0030] Step 102: If the status is not ended, start the corresponding command arbitration mechanism and determine the priority of the initial operation and the new command through the command arbitration mechanism, process the new command, and transmit the processed new command to the Flash array basic operation module.

[0031] Furthermore, in step 102, the command arbitration mechanism includes two types: a command arbitration mechanism during a pseudo program suspension period and a command arbitration mechanism during a pseudo erase suspension period.

[0032] Furthermore, in step 102, the corresponding command arbitration mechanism is started and the priority of the initial operation and the new command is determined by the command arbitration mechanism, the new command is processed, and the processed new command is transmitted to the Flash array basic operation module, which also includes:

[0033] Step 1021: If the capacity customizable Flash array receives a new command during the initial programming operation, the command arbitration mechanism during the pseudo-programming suspension period is initiated;

[0034] Step 1022: If the capacity customizable Flash array receives a new command during the initial erase operation, the command arbitration mechanism during the pseudo erase period is started.

[0035] Furthermore, in step 1021, if the capacity customizable Flash array receives a new command during the initial programming operation, the command arbitration mechanism during the pseudo program suspension period is initiated, which further includes:

[0036] Step 1021-1: If the new command is a read operation command, the read type is determined based on the working status of the sector where the read address is located and the corresponding operation is performed, where:

[0037] If the working status of the sector where the read address is located is idle, the read type is read data;

[0038] If the working status of the sector where the read address is located is busy, the read type is read status;

[0039] Step 1021-2: If the new command is a program operation command or an erase operation command, determine whether the sector where the operation address corresponding to the new command is located is idle, wherein:

[0040] If it is idle, it means that the new command and the initial command do not conflict with each other and have the same priority. The new command can be immediately sent to the Flash array basic operation module to execute the new command operation;

[0041] If it is busy, it means that the new command operation address is in the pseudo program pause sector. At this time, it is necessary to determine whether the new command type is a program operation command or an erase operation command, including:

[0042] If it is a program operation command, for the initial program operation, the program command in the pseudo program pause sector is defined as an operation command with a lower priority. After the initial program operation is completed, the program command is sent to the Flash array basic operation module, and the flash memory executes the new program command.

[0043] If it is an erase operation command, the erase command of the pseudo program pause sector is defined as an operation command with a higher priority, and the erase command is sent to the Flash array basic operation module. The flash memory can directly terminate the initial programming operation and immediately perform the erase operation.

[0044] Furthermore, in step 1022, if the capacity-customizable Flash array receives a new command during the initial erase operation, the command arbitration mechanism during the pseudo erase period is initiated, which further includes:

[0045] Step 1022-1: If the new command is a read operation command, the read type is determined based on the working status of the sector where the read address is located and the corresponding operation is performed, where:

[0046] If the working status of the sector where the read address is located is idle, the read type is read data;

[0047] If the working status of the sector where the read address is located is busy, the read type is read status;

[0048] Step 1022-2: For a program operation command or an erase operation command, it is necessary to determine whether the sector where the operation address corresponding to the new command is located is idle, wherein:

[0049] If it is idle, it means that the new command and the initial command do not conflict with each other and have the same priority. The new command can be immediately sent to the Flash array basic operation module to execute the new command operation;

[0050] If it is busy, it means that the new command operation address is in the pseudo erase suspended sector and the next arbitration is required, including:

[0051] If it is a programming operation command, for the initial erase operation, the programming command in the pseudo erase pause sector is defined as an operation command with a lower priority. After the initial erase operation is completed, the programming command is sent to the Flash array basic operation module, and the flash memory executes the new programming command;

[0052] If it is a sector erase command, the same sector erase command is defined as a redundant command and discarded directly;

[0053] If it is a whole chip erase command, the whole chip erase command is defined as an operation of the same priority, and the whole chip erase command is sent to the Flash array basic operation module, and the flash memory can immediately execute the whole chip erase operation.

[0054] Furthermore, in step 3, when the capacity-customizable Flash array receives a control signal and executes a new command operation of the flash memory, the idle / busy flag signal ryby of the flash memory enters a busy flag state.

[0055] Furthermore, the control method of the flash memory device supporting pseudo operation suspension and resumption further includes:

[0056] When the capacity-customizable Flash array is in the pseudo program / erase pause state, the host computer sends a program / erase resume command (resume) to the pseudo operation pause and resume control module again to end the operation pause. If the pseudo operation pause and resume control module receives the command, the new command operation has not yet ended, then the command is ignored. Otherwise, it is determined whether the initial program / erase operation has been completed during the pseudo program / erase pause period, wherein:

[0057] If completed, the idle / busy flag signal (ryby) of the flash memory returns to idle;

[0058] If not completed, the capacity customizable Flash array continues to perform the initial operation, and the idle / busy flag signal (ryby) of the flash memory re-enters the busy state, and returns to the idle state after the initial program / erase operation is completed.

[0059] Compared with the prior art, the present invention has the following advantages:

[0060] 1. The flash memory device provided by the present invention realizes the pause and resume functions of flash memory operations while meeting the designed memory capacity. Different operations can be performed simultaneously through different eFLASH IPs, thereby greatly improving the working efficiency of the flash memory.

[0061] 2. The flash memory device control method provided by the present invention correctly responds to program and erase suspend commands through pseudo-operation suspend and resume control. Furthermore, during the operation suspend period, a command arbitration mechanism is used to select and process commands of different priorities, thereby improving the efficiency and reliability of the memory.

[0062] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0064] Figure 1 The figure is a block diagram of a flash memory device that supports pseudo-operation suspend and resume.

[0065] Figure 2 This is a block diagram of the flash memory storage array and its basic operating modules.

[0066] Figure 3 The present invention is a flow chart of a flash memory control method that supports spurious operation suspension and resumption.

[0067] Figure 4 is a flowchart for programming suspension and resumption.

[0068] Figure 5 is a flowchart of pseudo erase suspend and resume. DETAILED DESCRIPTION

[0069] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0070] In an exemplary embodiment, see Figure 1 , provides a flash memory device that supports pseudo operation suspend and resume, Figure 1 This is a block diagram of a flash memory device that supports pseudo-operation suspension and resumption. The flash memory device comprises three modules: a pseudo-operation suspension and resumption control module, a flash array basic operation module, and a flash array with customizable capacity.

[0071] The pseudo operation pause and resume control module is responsible for receiving and processing the read, program, erase, and program / erase pause and resume operation commands sent by the host computer, and sending the processed commands to the Flash array basic operation module;

[0072] Furthermore, the pseudo-operation pause and resume control module further includes:

[0073] When a program / erase suspend or resume operation command is received, the pseudo operation suspend and resume control module enters or exits a pseudo program / erase suspend state;

[0074] When a read, program, or erase operation command is received, it is necessary to determine whether the pseudo operation pause and resume control module is in a pseudo program / erase pause state, wherein:

[0075] If it is in the pseudo program / erase pause state, after the pseudo operation pause and resume control module internal control logic and command arbitration, it is determined whether to transmit the command to the Flash array basic operation module;

[0076] If the module is not in the pseudo program / erase pause state, the received command is directly transmitted to the Flash array basic operation module.

[0077] Furthermore, the pseudo-operation suspension and resumption control module further includes a command arbitration unit for processing new commands received during the suspension period by arbitrating the priority levels of the initial operation and the new command.

[0078] The Flash array basic operation module is responsible for processing received read, program, and erase operation commands, and controlling the customizable Flash array through the scheduling of multiple eFLASH IPs to ensure that the flash memory correctly executes read, program, erase, and other operations;

[0079] The capacity can be customized Flash array, used to execute various command operations; the module adopts multiple eFLASH IP splicing expansion, and the eFLASH IPs respectively correspond to the sectors of the flash memory to realize the structured division of the hardware circuit.

[0080] Furthermore, the flash memory device further includes interface signals, including chip select (ce_n), output enable (oe_n), operation command (command), address line (addr), data line (data), and idle / busy (ryby). The idle / busy (ryby) signal indicates whether the flash memory is in an idle or busy state. When the flash memory is not performing any operation, the signal is idle; otherwise, the signal is busy. Generally, the flash memory can only receive new program or erase commands when it is in the idle state.

[0081] In one embodiment, see Figure 2 , Figure 2 This is a block diagram of the Flash array and its basic operating modules. Different application scenarios have different requirements for the bit width and capacity of the Flash memory. Developing a new Flash memory is not only difficult but also requires a lot of manpower. Therefore, in this embodiment, the factory's eFLASH IP is used to implement a Flash memory with customizable capacity. Specifically:

[0082] In a customizable capacity Flash array, the hardware circuit of the Flash memory is divided based on the splicing and expansion of multiple eFLASH IPs. One or more eFLASH IPs correspond to one or more sectors (SA) of the Flash memory, realizing a structured Flash storage array.

[0083] In the Flash array basic operation module, basic operations such as reading, programming, and erasing are implemented by controlling multiple eFLASH IPs.

[0084] The read operation is divided into two types: a read data operation and a read status operation. When the customizable Flash array is performing a program / erase operation, the read operation is a read status operation, and the state of the flash memory is read out. Otherwise, the read operation is a read data operation, and the data of the flash memory address is read out.

[0085] The programming operation uses an operation register and a data memory to store the operation information of multiple eFLASH IPs; wherein the operation register is divided into a programming operation register and an erase operation register, which are used to store the sector / eFLASH IP information for programming and erase operations, respectively; the data memory is used to store data for programming operations. In this embodiment, taking a single eFLASH IP under a certain process that supports a maximum storage of 64KB of data at an 8-bit bit width, that is, a data width of 16, as an example, the operations in the basic operation module of the Flash array are further explained: in order to realize a 2M capacity flash memory (containing 32 sectors (SA), each sector is 64KB), 32 eFLASH IPs can be spliced, and each eFLASH_IP corresponds to a storage sector; these 32 IPs are numbered from 0 to 31, Flash_0 to Flash31, corresponding to SA0 to SA31 of the chip respectively; the upper five bits of the input address are used to identify the eFLASH corresponding to the sector where the address is located. The IP number is enabled according to the received operation command, and the control signal of the corresponding IP is stored in the program operation register PROGRAM_ID[31:0] and the erase operation register ERASE_ID[31:0] respectively; PROGRAM_ID[i]=1 indicates that the program operation is performed on the i-th IP; ERASE_ID[i]=1 indicates that the erase operation is performed on the i-th IP; if a program command is received, the programming data is stored in the data register PROGRAM_DATA at the same time; the 16th bit of the input address is used as the input address of the execution operation IP, thereby controlling the eFLASH IP to complete the operation.

[0086] Through the above method, while meeting the capacity of the flash memory to be designed, it is possible to suspend and resume the operation of the flash memory. That is, different operations are performed simultaneously by different eFLASH IPs to realize the suspension and resumption of the flash memory operation, thereby greatly improving the working efficiency of the flash memory.

[0087] In one embodiment, continuing with the above technical solution, a Flash array with customizable capacity is implemented by splicing and expanding multiple eFLASH IPs, and the Flash array basic operation module controls the multiple eFLASH IPs to perform normal read, program, and erase operations. If an operation pause command is received from a host computer during the process of the Flash array basic operation module controlling the multiple eFLASH IPs to perform program and erase operations, the pseudo operation pause and resume control module will enter a pseudo program / erase pause state.

[0088] When the pseudo-operation suspend and resume control module is in the pseudo-program / erase suspend state, the flash memory's idle / busy flag (ryby) returns to idle, meaning it can receive and process new commands. However, the eFLASH IP, which is currently in the program / erase suspend state for the customizable Flash array, will continue executing the initial program / erase operation. Therefore, when the pseudo-operation suspend and resume control module receives a new read, program, or erase command in the pseudo-program / erase suspend state, it uses the command arbitration mechanism to determine the priority between the initial operation and the new command and then processes the new command.

[0089] For this process, see Figure 3 , provides a flash memory control method that supports pseudo operation suspension and resumption, Figure 3 The present invention is a flow chart of a flash memory control method supporting pseudo operation suspension and resumption, the method comprising:

[0090] Step S1: The pseudo operation suspension and resumption module receives a new command from the host computer in the pseudo program / erase suspension state, and determines whether the initial program / erase operation of the customizable capacity Flash array executed by the eFLASH IP in the program / erase suspension state has completely ended. Based on the status, the new command is transmitted to the Flash array basic operation module.

[0091] Furthermore, the new commands include a read operation command, a program operation command, and an erase operation command, wherein:

[0092] The read operation command is controlled by the chip select signal (ce_n) and output enable signal (oe_n) sent by the host computer. If both signals are valid at low levels, then when both ce_n and oe_n are low, the flash memory recognizes it as a read command and performs the read operation;

[0093] The program operation command and the erase operation command are sent by the host computer as corresponding operation instructions, wherein: the erase operation command includes a sector erase command and a whole chip erase command.

[0094] Furthermore, the step of determining whether the initial program / erase operation of the customizable capacity Flash array executed by the program / erase-suspended eFLASH IP is completely completed and transmitting a new command to the Flash array basic operation module based on the status further includes the following steps:

[0095] Step S101: If the status is "Ended", it means that the capacity customizable Flash array is completely idle, and the new command is directly transmitted to the Flash array basic operation module;

[0096] Step S102: If the status is not ended, start the corresponding command arbitration mechanism and determine the priority of the initial operation and the new command through the command arbitration mechanism, process the new command, and transmit the processed new command to the Flash array basic operation module.

[0097] Furthermore, the command arbitration mechanism includes two types: a command arbitration mechanism during a pseudo program suspension period and a command arbitration mechanism during a pseudo erase suspension period.

[0098] Further, in step S102, please refer to Figure 4 and Figure 5 In the red dotted box, Figure 4 is a flowchart of pseudo programming suspension and resumption, Figure 5 This is a flowchart of pseudo erase suspension and resumption; the corresponding command arbitration mechanism is started and the priority of the initial operation and the new command is determined by the command arbitration mechanism, the new command is processed, and the processed new command is transmitted to the Flash array basic operation module, which specifically includes the following steps:

[0099] Step A: If the capacity customizable Flash array receives a new command during the initial programming operation, the command arbitration mechanism during the pseudo programming suspension period is started; see Figure 4 , its specific operations include:

[0100] Step A-1: ​​If the new command is a read operation command, the read type is determined and the corresponding operation is performed according to the working status of the sector where the read address is located, where:

[0101] If the working status of the sector where the read address is located is idle, the read type is read data;

[0102] If the working status of the sector where the read address is located is busy, the read type is read status;

[0103] Step A-2: If the new command is a program operation command or an erase operation command, determine whether the sector where the operation address corresponding to the new command is located is idle, wherein:

[0104] If it is idle, it means that the new command and the initial command do not conflict with each other and have the same priority. The new command can be immediately sent to the Flash array basic operation module to execute the new command operation;

[0105] If it is busy, it means that the new command operation address is in the pseudo program pause sector. At this time, it is necessary to determine whether the new command type is a program operation command or an erase operation command, including:

[0106] If it is a program operation command, for the initial program operation, the program command in the pseudo program pause sector is defined as an operation command with a lower priority. After the initial program operation is completed, the program command is sent to the Flash array basic operation module, and the flash memory executes the new program command.

[0107] If it is an erase operation command, the erase command of the pseudo program pause sector is defined as an operation command with a higher priority, and the erase command is sent to the Flash array basic operation module. The flash memory can directly terminate the initial programming operation and immediately perform the erase operation.

[0108] Step B: If the capacity-customizable Flash array receives a new command during the initial erase operation, the command arbitration mechanism during the pseudo erase is started; see Figure 5 , its specific operations include:

[0109] Step B-1: If the new command is a read operation command, the read type is determined and the corresponding operation is performed according to the working status of the sector where the read address is located, where:

[0110] If the working status of the sector where the read address is located is idle, the read type is read data;

[0111] If the working status of the sector where the read address is located is busy, the read type is read status.

[0112] Step B-2: For a program operation command or an erase operation command, it is necessary to determine whether the sector where the operation address corresponding to the new command is located is idle, wherein:

[0113] If it is idle, it means that the new command and the initial command do not conflict with each other and have the same priority. The new command can be immediately sent to the Flash array basic operation module to execute the new command operation;

[0114] If it is busy, it means that the new command operation address is in the pseudo erase suspended sector and the next arbitration is required, including:

[0115] If it is a programming operation command, for the initial erase operation, the programming command in the pseudo erase pause sector is defined as an operation command with a lower priority. After the initial erase operation is completed, the programming command is sent to the Flash array basic operation module, and the flash memory executes the new programming command;

[0116] If it is a sector erase command, the same sector erase command is defined as a redundant command and discarded directly;

[0117] If it is a whole chip erase command, the whole chip erase command is defined as an operation of the same priority, and the whole chip erase command is sent to the Flash array basic operation module, and the flash memory can immediately execute the whole chip erase operation.

[0118] Step S2: The Flash array basic operation module receives the new command issued by the pseudo operation suspend and resume module, generates a control signal and timing for the eFLASH IP to execute the new command operation, and transmits the control signal to the capacity customizable Flash array according to the timing;

[0119] Step S3: The capacity-customizable Flash array receives the control signal and executes a new command operation of the flash memory.

[0120] Furthermore, in step S3, when the capacity-customizable Flash array receives a control signal and executes a new command operation of the flash memory, the idle / busy flag signal ryby of the flash memory enters a busy flag state.

[0121] In one embodiment, when the capacity-customizable Flash array is in a pseudo program / erase pause state, the host computer again sends a program / erase resume command (resume) to the pseudo operation pause and resume control module to end the operation pause. At this time, if the pseudo operation pause and resume control module receives the command but the new command operation has not yet ended, the command is ignored. Otherwise, it is necessary to determine whether the initial program / erase operation has been completed during the pseudo program / erase pause period, wherein:

[0122] If completed, the idle / busy flag signal (ryby) of the flash memory returns to idle;

[0123] If not completed, the capacity customizable Flash array continues to perform the initial operation, and the idle / busy flag signal (ryby) of the flash memory re-enters the busy state, and returns to the idle state after the initial program / erase operation is completed.

[0124] Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A flash memory device supporting pseudo-operation suspension and resumption, characterized in that: It consists of three modules: pseudo-operation pause and resume control module, Flash array basic operation module, and capacity-customizable Flash array. The pseudo operation pause and resume control module is responsible for receiving and processing the read, program, erase, and program / erase pause and resume operation commands sent by the host computer, and sending the processed commands to the Flash array basic operation module; The Flash array basic operation module is responsible for processing the received read, program and erase operation commands, and controlling the capacity-customizable Flash array through the scheduling of multiple eFLASH IPs to ensure that the flash memory correctly executes the read, program and erase operations; the Flash array basic operation module implements the read, program and erase operations by controlling multiple eFLASH IPs, wherein: The read operation is divided into two types: a read data operation and a read status operation. Specifically, when the customizable Flash array performs a program / erase operation, the read operation is a read status operation, and the state of the flash memory is read out; otherwise, the read operation is a read data operation, and the data of the flash memory address is read out; The program / erase operation uses an operation register and a data memory to store operation information of multiple eFLASH IPs, wherein the operation register is divided into a program operation register and an erase operation register, respectively used to store sector / eFLASH IP information for program and erase operations; the data memory is used to store data for program operations; The capacity of the customizable Flash array is used to execute various command operations.

2. The flash memory device supporting pseudo-operation suspension and resumption according to claim 1, wherein: The flash memory device also has interface signals, including chip select ce_n, output enable oe_n, operation command command, address line addr, data line data, and idle / busy ryby, wherein: The idle / busy signal is used to indicate whether the flash memory is in an idle or busy state. When the flash memory is not performing any operation, the signal is idle; otherwise, the signal is busy.

3. The flash memory device supporting pseudo operation suspension and resumption according to claim 1, wherein: The pseudo operation suspension and resumption control module further includes a command arbitration unit for processing new commands received during the pseudo operation suspension period by arbitrating the priority levels of the initial operation and the new command.

4. The flash memory device supporting pseudo operation suspension and resumption according to claim 3, wherein: When the pseudo operation suspension and resumption control module receives a program / erase suspension or resumption operation command, the pseudo operation suspension and resumption control module enters or exits a program / erase suspension state; When the pseudo operation suspension and resumption control module receives a read, program, sector erase, or full-chip erase operation command, it is necessary to determine whether the pseudo operation suspension and resumption control module is in a program / erase suspension state, wherein: If the pseudo operation pause and resume control module is in a program / erase pause state, it determines whether to transmit the command to the Flash array basic operation module after the internal control logic and command arbitration of the pseudo operation pause and resume control module; If the pseudo operation suspension and resumption control module is not in the program / erase suspension state, the received command is directly transmitted to the Flash array basic operation module.

5. The flash memory device supporting pseudo operation suspension and resumption according to claim 1, wherein: The capacity-customizable Flash array is based on the splicing and expansion of multiple eFLASH IPs, and the hardware circuit of the flash memory is divided. One or more eFLASH IPs correspond to one or more sectors SA of the memory, thereby realizing a structured flash memory storage array.

6. A control method for a flash memory device supporting pseudo operation suspension and resumption based on any one of claims 1 to 5, characterized in that: include: The pseudo operation suspension and resumption module receives a new command from the host computer in the pseudo program / erase suspension state, and determines whether the initial program / erase operation of the customizable Flash array by the eFLASH IP in the program / erase suspension state has been completely completed. Based on the status, the module transmits the new command to the Flash array basic operation module. The Flash array basic operation module receives the new command issued by the pseudo operation suspension and resumption module, generates a control signal and timing for eFLASHIP to execute the new command operation, and transmits the control signal to the capacity customizable Flash array according to the timing; The capacity-customizable Flash array receives a control signal and executes a new command operation of the flash memory.

7. The method for controlling a flash memory device supporting suspend and resume of pseudo operations according to claim 6, wherein: The new commands include a read operation command, a program operation command, and an erase operation command, wherein: The read operation command is controlled by the chip select signal ce_n and the output enable signal oe_n sent by the host computer. If both signals are valid at low levels, then when both ce_n and oe_n are at low levels, the flash memory recognizes it as a read command and performs a read operation; The program operation command and the erase operation command are sent by the host computer as corresponding operation instructions, wherein: the erase operation command includes a sector erase command and a whole chip erase command.

8. The control method of a flash memory device supporting suspend and resume of pseudo operations according to claim 7, wherein: The determination of whether the initial program / erase operation of the customizable capacity Flash array by the eFLASH IP in program / erase suspension is completely completed is performed, and based on the status, a new command is transmitted to the Flash array basic operation module, wherein: If the status is "Ended", it means that the capacity customizable Flash array is completely idle, and the new command is directly transmitted to the Flash array basic operation module; If the status is not ended, the corresponding command arbitration mechanism is started and the priority of the initial operation and the new command is determined by the command arbitration mechanism, the new command is processed, and the processed new command is transmitted to the Flash array basic operation module.

9. The method for controlling a flash memory device supporting suspend and resume of pseudo operations according to claim 8, wherein: The command arbitration mechanism includes two types: a command arbitration mechanism during a pseudo program suspension period and a command arbitration mechanism during a pseudo erase suspension period.

10. The control method of a flash memory device supporting suspend and resume of pseudo operations according to claim 9, characterized in that: The method includes starting the corresponding command arbitration mechanism, determining the priority of the initial operation and the new command through the command arbitration mechanism, processing the new command, and transmitting the processed new command to the Flash array basic operation module, including: When the capacity-customizable Flash array receives a new command during the initial programming operation, the command arbitration mechanism during the pseudo-programming suspension period is initiated; When the capacity-customizable Flash array receives a new command during the initial erase operation, the command arbitration mechanism during the pseudo erase period is started.

11. The method for controlling a flash memory device supporting suspend and resume of pseudo operations according to claim 10, wherein: The command arbitration mechanism during the start-up pseudo-program suspension period includes: If the new command is a read operation command, the read type is determined and the corresponding operation is performed based on the working status of the sector where the read address is located. If the working status of the sector where the read address is located is idle, the read type is read data; If the working status of the sector where the read address is located is busy, the read type is read status; If the new command is a program operation command or an erase operation command, it is determined whether the sector where the operation address corresponding to the new command is located is idle, wherein: If the sector where the operation address corresponding to the new command is located is idle, it means that the new command and the initial command do not conflict with each other and have the same priority. The new command can be immediately sent to the Flash array basic operation module to execute the new command operation. If the sector where the operation address corresponding to the new command is located is busy, it means that the new command operation address is located in the pseudo-programming suspended sector. At this time, it is necessary to determine whether the new command type is a program operation command or an erase operation command, including: If the new command type is a program operation command, then for the initial program operation, the program command in the pseudo program-suspend sector is defined as an operation command with a lower priority. After the initial program operation is completed, the program command is sent to the Flash array basic operation module, and the flash memory executes the new program command. If the new command type is an erase operation command, the erase command of the pseudo program suspended sector is defined as an operation command with a higher priority, and the erase command is sent to the Flash array basic operation module. The Flash memory can directly terminate the initial programming operation and immediately execute the erase operation.

12. The method for controlling a flash memory device supporting suspend and resume of pseudo operations according to claim 10, wherein: The command arbitration mechanism during the start-up of the pseudo erase comprises: If the new command is a read operation command, the read type is determined and the corresponding operation is performed based on the working status of the sector where the read address is located. If the working status of the sector where the read address is located is idle, the read type is read data; If the working status of the sector where the read address is located is busy, the read type is read status; For a program operation command or an erase operation command, it is necessary to determine whether the sector where the operation address corresponding to the new command is located is idle, where: If the sector where the operation address corresponding to the new command is located is idle, it means that the new command and the initial command do not conflict with each other and have the same priority. The new command can be immediately sent to the Flash array basic operation module to execute the new command operation. If the sector where the operation address corresponding to the new command is located is busy, it means that the operation address of the new command is located in the pseudo erase pause sector. The new command needs to be arbitrated in the next step, including: If the new command is a programming operation command, then for the initial erase operation, the programming command in the pseudo erase pause sector is defined as an operation command with a lower priority. After the initial erase operation is completed, the programming command is sent to the Flash array basic operation module, and the flash memory executes the new programming command. If the new command is a sector erase command, the same sector erase command is defined as a redundant command and discarded directly; If the new command is a full-chip erase command, the full-chip erase command is defined as an operation of the same priority level, and the full-chip erase command is sent to the Flash array basic operation module. The flash memory can immediately execute the full-chip erase operation.

13. The method for controlling a flash memory device supporting suspend and resume of pseudo operations according to claim 6, wherein: When the capacity-customizable Flash array receives a control signal and executes a new command operation of the flash memory, the idle / busy flag signal ryby of the flash memory enters a busy flag state.

14. The control method of a flash memory device supporting suspend and resume of pseudo operations according to any one of claims 6 to 13, characterized in that: Also includes: When the capacity customizable Flash array is in the pseudo program / erase pause state, the host computer sends a program / erase resume command to the pseudo operation pause and resume control module again to end the operation pause. If the pseudo operation pause and resume control module receives the command and the new command operation has not ended, the command is ignored. Otherwise, it is determined whether the initial program / erase operation has been completed during the program / erase suspend period, wherein: The initial program / erase operation is completed during the program / erase suspension period, and the idle / busy flag signal ryby of the flash memory returns to idle; If the initial program / erase operation is not completed during the program / erase suspension period, the capacity customizable Flash array continues to perform the initial operation, and the idle / busy flag signal ryby of the flash memory re-enters busy and returns to idle after the initial program / erase operation is completed.

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