GPU and parallel IO collaborative optimization method based on heterogeneous computing

Abstract

The present invention discloses a method for collaborative optimization of GPU and parallel IO based on pattern heterogeneous computing, specifically relating to the field of heterogeneous computing optimization, including real-time monitoring of pattern characteristics during the execution of target computing tasks through an instruction analyzer, synchronously collecting dynamic parameters of the heterogeneous computing environment to generate a multi-dimensional resource situation matrix; based on the pattern and resource situation matrix, performing collaborative optimization operations of the binding device dimension and the scheduling time dimension; constructing a three-level adaptive transmission mechanism and periodically implementing feedback optimization according to its execution status. The method for collaborative optimization of GPU and parallel IO based on pattern heterogeneous computing improves the data prefetch hit rate by dynamically perceiving the matching relationship between heterogeneous computing patterns and I / O access patterns; reduces end-to-end latency and reduces task contention conflicts through a dynamic matching strategy between device capability profiles and task types; and improves heterogeneous storage bandwidth peak utilization and I / O throughput by differentially utilizing multi-level storage hierarchy characteristics.

Description

Technical Field

[0001] The present invention relates to the technical field of heterogeneous computing optimization, and more specifically, to a GPU and parallel IO collaborative optimization method based on heterogeneous computing patterns. Background Art

[0002] With the explosive growth in demand for high-performance computing and big data processing, heterogeneous computing architecture has become a key technical direction for improving computing power and energy efficiency. Especially in scientific computing and industrial applications, traditional heterogeneous computing architecture uses the CPU as the control core and the GPU as the coprocessor, and implements task allocation through a master-slave programming model. It has played a key role in accelerating compute-intensive tasks. However, traditional heterogeneous systems often focus only on computing acceleration and ignore the coordinated optimization between parallel I / O and computing tasks, resulting in increasingly prominent storage walls and I / O bottlenecks.

[0003] At present, existing technologies have proposed dynamic load balancing and asynchronous data transmission optimization methods. By introducing a hierarchical task scheduling mechanism, MPI distributed communication is adopted between nodes, CPU multi-threading and GPU stream processor collaboration are realized within the node, and double buffering technology is used to overlap calculation and data transmission, the task allocation granularity is refined to the thread level, and the CPU / GPU task ratio is dynamically adjusted through runtime performance prediction.

[0004] However, in actual use, it still has some shortcomings, such as the lack of matching between heterogeneous computing modes and I / O access modes, which leads to decreased storage locality and lower data prefetch hit rate; the data dependencies caused by dynamic task migration are difficult to effectively synchronize through existing communication protocols, and task contention leads to a surge in end-to-end latency; the access characteristics of multi-level storage hierarchies are not utilized in a differentiated manner, and the peak utilization rate of heterogeneous storage bandwidth is low. Summary of the Invention

[0005] In order to overcome the above-mentioned defects of the prior art, the present invention provides a GPU and parallel IO collaborative optimization method based on pattern heterogeneous computing, and solves the problems raised in the above-mentioned background technology through the following scheme.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] A GPU and parallel IO collaborative optimization method based on heterogeneous computing includes:

[0008] S1: During the execution of the target computing task, the instruction analyzer monitors and obtains the pattern characteristics of the target computing task in real time;

[0009] S2: collecting dynamic parameters of the heterogeneous computing environment where the target computing task is located in real time to generate a multi-dimensional resource situation matrix;

[0010] S3: Based on the pattern characteristics and the multi-dimensional resource situation matrix, performing a collaborative optimization operation, the collaborative optimization operation including binding a device dimension and a scheduling time dimension;

[0011] S4: Based on the execution status of the collaborative optimization operation, a three-level adaptive transmission mechanism is constructed:

[0012] S5: Based on the execution status of the three-level adaptive transmission mechanism, periodically perform feedback optimization operations.

[0013] Preferably, the S1 pattern features include a computational density coefficient, data locality strength, and a communication dependency graph, wherein the computational density coefficient is a quantitative indicator used to reflect the relative relationship between computational intensity and memory access intensity; the data locality strength is used to measure the degree of concentration of data access during the execution of a computing task; and the communication dependency graph is used to describe the data transfer relationship and load conditions between different computing tasks in a heterogeneous computing environment.

[0014] Preferably, the step of obtaining the pattern feature by the instruction analyzer in S1 includes:

[0015] The sliding window weighted average algorithm is used to calculate the density coefficient Calculation is performed, specifically expressed as:

[0016] ,

[0017] in, and Respectively expressed as The number of floating-point operation instructions and memory access instructions counted within a time window; Indicated as assigned to The weight of the time window, It is expressed as the number of time windows. Exponential decay is used to control the influence of data in each time window, which is specifically expressed as:

[0018] ,

[0019] in, Expressed as a pre-configured attenuation coefficient;

[0020] Based on the memory access address sequence obtained in a sampling period, the discrete degree between addresses is calculated to represent the spatial locality metric , specifically expressed as:

[0021] ,

[0022] in, It is expressed as the total number of memory access operations within the sampling period. Represents the index of the memory access operation, Expressed as The target address of the memory access operation; It is expressed as calculating the Hamming distance between two consecutive memory access addresses; The address width expressed as the computational spatial locality;

[0023] Count the distribution of reuse distances of memory access addresses and calculate the entropy value to represent the temporal locality metric , specifically expressed as:

[0024] ,

[0025] in, It is represented by the preset maximum reuse distance threshold, is represented as an index of reuse distance, The reuse distance is expressed as The proportion of memory access operations in the sampling period is taken as the reuse distance The ratio of the number of memory accesses to the total number of memory access operations during the sampling period.

[0026] Preferably, the multi-dimensional resource situation matrix S2 includes a device dimension, a resource type dimension and a time dimension, wherein the resource type dimension is used to identify specific dynamic parameters.

[0027] Preferably, the method for implementing the binding device dimensions in the collaborative optimization operation in S3 includes:

[0028] Determine the task type of the target computing task based on the pattern characteristics;

[0029] Generate a device capability profile based on the dynamic parameters of the heterogeneous computing environment in the multi-dimensional resource status matrix. The device capability profile includes the real-time computing power score of the GPU, the I / O throughput score of the storage node, and the transmission quality score of the communication path between nodes.

[0030] Based on the matching strategy between task type and device capability profile, device dimension binding decisions are dynamically executed.

[0031] Preferably, the method for implementing the scheduling time dimension in the collaborative optimization operation in S3 includes:

[0032] 1-3 clock cycles before the GPU kernel function starts, the prefetch strategy is triggered by the CUDA stream event to load the next calculation window data;

[0033] Through the hardware and software coordination mechanism, strict timing matching between the execution of computing kernel functions and data transmission is achieved, and the computing cycle and DMA transmission cycle are monitored in real time;

[0034] If the calculation cycle is smaller than the DMA transfer cycle, enable GPU dynamic frequency scaling to increase the SM clock frequency to the theoretical peak value;

[0035] If the calculation cycle is longer than the DMA transfer cycle, increase the DMA queue depth.

[0036] Preferably, the S4, three-level adaptive transmission mechanism includes register-level transmission optimization, storage-level transmission optimization and network-level transmission optimization, wherein the register-level transmission optimization is for the target computing task whose task type is computationally intensive and whose GPU real-time computing power score in the device capability portrait is greater than the GPU real-time computing power score threshold, the storage-level transmission optimization is for the high I / O throughput demand type and whose I / O throughput capability score of the target storage node is greater than the I / O throughput capability score threshold, and the network-level transmission optimization is for the communication intensive type and whose transmission quality score between nodes involved is greater than the transmission quality score threshold.

[0037] Preferably, in S4, the priority of the three-level adaptive transmission mechanism is register-level transmission optimization level > storage-level transmission optimization > network-level transmission optimization. When the target computing task meets the trigger conditions of multiple levels at the same time, the optimization strategy with the highest priority will be executed first.

[0038] Technical effects and advantages of the present invention:

[0039] 1. The present invention monitors the computing task mode in real time and dynamically perceives the matching relationship between heterogeneous computing modes and I / O access modes, thereby solving the problem of missing matching between heterogeneous computing modes and I / O access modes and improving the data prefetch hit rate.

[0040] 2. This invention uses a dynamic matching strategy between device capability profiles and task types, combined with a phase alignment mechanism between CUDA streams and the DMA engine, to effectively solve the data dependency synchronization problem in dynamic task migration, reduce end-to-end latency, and mitigate task contention conflicts.

[0041] 3. The present invention improves the peak utilization of heterogeneous storage bandwidth by differentially utilizing the multi-level storage hierarchy characteristics, solves the defect that the traditional multi-level storage hierarchy access characteristics are not fully utilized, and improves the I / O throughput of storage-intensive tasks. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 This is a flowchart of the steps of a GPU and parallel IO collaborative optimization method based on heterogeneous computing provided in an embodiment of the present application.

[0043] Figure 2 This is a flowchart of the steps for binding device dimensions in the GPU and parallel IO collaborative optimization method based on heterogeneous computing provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0045] The terms used in the following embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in the specification of the present application, the singular expressions "one", "a kind of", "said", "above", "the" and "this" are intended to also include plural expressions, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used in the present application refers to and includes any or all possible combinations of one or more listed items. In the description of the embodiments of the present application, unless otherwise stated, the meaning of "multiple" is two or more.

[0046] As attached Figure 1 The GPU and parallel IO collaborative optimization method based on pattern heterogeneous computing shown in the figure includes real-time monitoring of pattern characteristics during the execution of target computing tasks through an instruction analyzer, synchronously collecting dynamic parameters of the heterogeneous computing environment to generate a multi-dimensional resource situation matrix; based on the pattern and resource situation matrix, performing collaborative optimization operations in the binding device dimension and the scheduling time dimension; constructing a three-level adaptive transmission mechanism and periodically implementing feedback optimization according to its execution status.

[0047] In a specific embodiment, the GPU and parallel IO collaborative optimization method based on heterogeneous computing can be applied to a heterogeneous computing environment including one or more host CPUs, one or more graphics processing units (GPUs), and a parallel storage system. The specific steps of the GPU and parallel IO collaborative optimization method based on heterogeneous computing are as follows:

[0048] S1: During the execution of the target computing task, the instruction analyzer monitors and obtains the pattern characteristics of the target computing task in real time;

[0049] S2: collecting dynamic parameters of the heterogeneous computing environment where the target computing task is located in real time to generate a multi-dimensional resource situation matrix;

[0050] S3: Based on the pattern characteristics and the multi-dimensional resource situation matrix, performing a collaborative optimization operation, the collaborative optimization operation including binding a device dimension and a scheduling time dimension;

[0051] S4: Based on the execution status of the collaborative optimization operation, a three-level adaptive transmission mechanism is constructed:

[0052] S5: Based on the execution status of the three-level adaptive transmission mechanism, periodically perform feedback optimization operations.

[0053] Specifically, in S1, the pattern features include computing density coefficient, data locality strength, and communication dependency graph, where the computing density coefficient is a quantitative indicator used to reflect the relative relationship between computing intensity and memory access intensity; data locality strength is used to measure the degree of concentration of data access during the execution of computing tasks, and in this embodiment includes spatial locality measurement and temporal locality measurement; the communication dependency graph is used to describe the data transfer relationship and load conditions between different computing tasks in a heterogeneous computing environment.

[0054] It should be noted that the calculation density coefficient uses an instruction analysis tool to capture the instruction stream of the target computing task executed on the GPU in real time. The instruction analysis tool includes but is not limited to dynamic binary instrumentation, the use of hardware performance counter interface or specific hardware tracking unit, etc., to count the number of floating-point operation instructions and memory access instructions within a preset time window, where the number of floating-point operation instructions includes but is not limited to single-precision, double-precision, half-precision and other arithmetic and logical instructions; the number of memory access instructions includes but is not limited to global memory load and store instructions, shared memory access instructions, etc.

[0055] In this embodiment, in order to smooth the instantaneous fluctuation and reflect the recent trend, a sliding window weighted average algorithm is used to calculate the density coefficient. Calculation is performed, specifically expressed as:

[0056] ,

[0057] in, and Respectively expressed as The number of floating-point operation instructions and memory access instructions counted within a time window; Indicated as assigned to The weight of the time window, It is expressed as the number of time windows. Furthermore, exponential decay is used to control the influence of data in each time window, which is specifically expressed as:

[0058] ,

[0059] in, It represents a pre-configured attenuation coefficient, which is set to 0.1 in this embodiment.

[0060] It should be noted that the spatial locality metric in data locality strength is used to measure the proximity of consecutive memory access operations in the address space; the temporal locality metric is used to measure the frequency of repeated access to the same data.

[0061] This embodiment is based on the memory access address sequence obtained within a sampling period, and the discrete degree between the addresses is calculated to represent the spatial locality metric. , specifically expressed as:

[0062] ,

[0063] in, It is expressed as the total number of memory access operations within the sampling period. Represents the index of the memory access operation, Expressed as The target address of the memory access operation; It is expressed as calculating the Hamming distance between two consecutive memory access addresses; Represents the address width for computing spatial locality; further, The closer the value is to 1, the better the spatial locality. The Hamming distance is a measure of the difference between two strings, defined as the number of different bits at each position in the two strings.

[0064] This embodiment calculates the distribution of the reuse distance of the memory access address, where the reuse distance is the number of accesses to other different addresses between two consecutive accesses to the address, and calculates the entropy value to represent the temporal locality metric. , specifically expressed as:

[0065] ,

[0066] in, It is represented by the preset maximum reuse distance threshold, is represented as an index of reuse distance, The reuse distance is expressed as The proportion of memory access operations in the sampling period is taken as the reuse distance The ratio of the number of accesses to the total number of memory access operations during the sampling period; further, A smaller value indicates a more concentrated and predictable address reuse pattern, that is, better temporal locality.

[0067] The steps for obtaining the communication dependency graph in this embodiment are as follows:

[0068] S101: By intercepting, monitoring, and utilizing a standard inter-process communication interface, communication event data is periodically recorded. The communication event data includes communication endpoints, data characteristics, and time information. The communication endpoints are logical identifiers of the source and target devices. The data characteristics include the amount of data transmitted per communication, the frequency of communication, and the direction of transmission. The time information includes the timestamps of the start and end of the communication.

[0069] S102: Based on the number of captured communication events, a weighted directed graph is constructed within a preset time window to represent the communication topology and load intensity, i.e., a communication dependency graph; wherein each vertex of the weighted directed graph represents a computing entity participating in the communication, and by adding a directed edge from vertex i to vertex j in the weighted directed graph, it indicates that data transmission from entity i to entity j is observed within the time window; the weights of the edges of the weighted directed graph are used to quantify the communication load between devices i to j.

[0070] Specifically, in S2, the dynamic parameters of the heterogeneous computing environment where the target computing task is located are collected. The dynamic parameters are key performance indicators that reflect the real-time working status and load level of each computing, storage, and communication unit when the system is running. Furthermore, the dynamic parameters include computing resource parameters, storage resource parameters, and I / O resource parameters. Among them, the computing resource parameters include but are not limited to CPU utilization, SM occupancy, GPU register file pressure value, GPU shared memory Bank conflict rate, and GPU thread bundle scheduling efficiency. Storage resource parameters include GPU video memory access latency and bandwidth utilization, host DRAM memory bandwidth utilization and page hit rate, and NVM read / write bandwidth and IO queue depth. Communication / network resource parameters include PCIe link effective bandwidth, RDMA end-to-end latency, network interface bandwidth utilization, number of network hops between nodes, network switch port congestion rate, TCP / UDP packet loss rate, and network interface IO queue status.

[0071] This embodiment performs data collection periodically during operation, and the preset collection period is set to 10ms.

[0072] Furthermore, a multi-dimensional resource situation matrix is constructed based on the collected dynamic parameters of the heterogeneous computing environment. The multi-dimensional resource situation matrix is used to integrate, quantify and track the real-time status of each device in the heterogeneous computing environment in different resource dimensions and its changing trends over time; the multi-dimensional resource situation matrix includes device dimension, resource type dimension and time dimension, among which the device dimension is used to identify each physical device involved in the calculation and is represented by the device number; the resource type dimension is used to identify specific dynamic parameters and is distinguished by predefined subclass codes; the time dimension is used to track historical status, represented by the time window sequence number and adopts a rolling update mechanism.

[0073] It should be noted that the generation process of the multidimensional resource situation matrix includes: collecting the original dynamic parameter values of each device according to a pre-set collection cycle; data cleaning and preprocessing, smoothing outliers caused by instantaneous noise, and unifying data units; applying the normalization formula to each preprocessed parameter value to calculate a score in the [0, 1] interval; filling the calculated normalized score value into the corresponding position in the multidimensional resource situation matrix, and rolling updating the time window, discarding the oldest data, to complete the update of the multidimensional resource situation matrix.

[0074] Specifically, in S3, based on the pattern features obtained in S1 and the multi-dimensional resource situation matrix obtained in S2, collaborative optimization operations are performed respectively. The collaborative optimization operations include binding device dimensions and scheduling time dimensions.

[0075] Furthermore, the implementation method of binding device dimensions in the collaborative optimization operation includes: judging the task type of the target computing task based on pattern characteristics; it should be noted that if the computing density coefficient is greater than a preset computing density coefficient threshold, the target computing task is judged to be a computing-intensive task; if the data locality strength is less than the preset data locality strength threshold and the communication dependency graph shows that the number of data transmissions between the task and the storage node is greater than the transmission threshold, the target computing task is judged to be a high I / O throughput demand task; if there is a cross-node communication path in the communication dependency graph, the target computing task is judged to be communication-intensive; based on the dynamic parameters corresponding to the heterogeneous computing environment in the multi-dimensional resource situation matrix, a device capability profile is generated, the device capability profile including the real-time computing power score of the GPU, the I / O throughput capability score of the storage node, and the transmission quality score of the communication path between nodes;

[0076] In this embodiment, the device capability profile is generated by weighted aggregation and dynamic calibration algorithm, wherein the real-time computing power score of the GPU is calculated. , specifically expressed as:

[0077] ,

[0078] in, 、 、 、 They are respectively expressed as the weight coefficients for calculating the real-time computing power score of the GPU, Expressed as SM occupancy, Expressed as the theoretical maximum occupancy of SM, Expressed as GPU register file pressure value, Represents the upper limit of register file capacity, Expressed as GPU warp scheduling efficiency, Expressed as the bandwidth utilization of GPU memory, Expressed as the theoretical peak bandwidth of video memory; further, when >90%, automatically reduce Weight to avoid overloaded equipment from being selected; when When <30%, increase Weight,prioritize bandwidth-sensitive tasks;

[0079] Calculate the I / O throughput score of the storage node, specifically expressed as:

[0080] ,

[0081] in, 、 、 They represent the weight coefficients for calculating the I / O throughput score of the storage node, Expressed as the read bandwidth of NVM, Expressed as the write bandwidth of NVM, Expressed as the nominal bandwidth of the NVM device, Expressed as IO queue depth, Expressed as the maximum supported queue depth, Expressed as the effective bandwidth of the PCIe link, Expressed as the theoretical bandwidth of the PCIe link; further, when >80% When triggered Weight decay to avoid queue overflow; when >90%, then The weight is reduced to 0 to avoid link congestion;

[0082] Calculate the transmission quality score of the communication path between nodes, which is specifically expressed as:

[0083] ,

[0084] in, 、 、 They are respectively represented as weight coefficients for calculating the transmission quality score of the communication path between nodes, Expressed as RDMA end-to-end latency, Expressed as the network switch port congestion rate, Expressed as TCP packet loss rate;

[0085] Based on the matching strategy between task type and device capability profile, device dimension binding decisions are dynamically executed:

[0086] It should be noted that the device dimension binding decision is the matching strategy corresponding to the target computing task. The matching strategy includes but is not limited to the matching strategy for computing-intensive tasks, the matching strategy for tasks with high I / O throughput requirements, and the matching strategy for communication-intensive tasks.

[0087] In this embodiment, the matching strategy for computationally intensive tasks is to select the GPU device with the highest real-time computing power score of the GPU, and give priority to binding it to the computing unit with an SM occupancy rate lower than 80% and a register pressure value less than 70% to avoid resource contention; the matching strategy for tasks with high I / O throughput requirements is to map the tasks to the storage node with the highest I / O throughput capability score, and give priority to storage devices with an NVMe queue depth less than 80% and a PCIe bandwidth utilization rate less than 75%; the matching strategy for communication-intensive tasks is to build a directly connected subnet based on the minimum communication overhead according to the topological relationship of the communication dependency graph, and give priority to the communication path with the highest transmission quality score.

[0088] Furthermore, the implementation method of the scheduling time dimension in the collaborative optimization operation includes: generating a prefetch strategy for the target computing task based on the device dimension binding decision and the task type of the target computing task, triggering the prefetch strategy through a CUDA stream event 1-3 clock cycles before the GPU kernel function is started, and loading the next computing window data into the L2 cache;

[0089] Furthermore, when the target computation task has a high data locality Access latency between storage tiers and storage resource class parameters , calculate the prefetch window length , specifically expressed as:

[0090] ,

[0091] in, is the task adjustment factor; in this embodiment, the adjustment factor for computing-intensive tasks is 0.8, the adjustment factor for communication-intensive tasks is 0.5, and the adjustment factor for I / O-intensive tasks is 0.3;

[0092] Through the hardware and software collaboration mechanism, strict timing matching between the execution of computing kernel functions and data transmission is achieved; the PTP protocol of InfiniBand NIC is used to calibrate the clock reference of GPU and NIC, with the error controlled within ±50ns, and a synchronization barrier is inserted in the CUDA stream to force the kernel function to wait for the DMA transfer completion signal; the computing cycle and DMA transfer cycle are monitored in real time. If the computing cycle is less than the DMA transfer cycle, GPU dynamic frequency scaling is enabled to increase the SM clock frequency to the theoretical peak; if the computing cycle is greater than the DMA transfer cycle, the DMA queue depth is increased.

[0093] Specifically, in S4, the execution states of the collaborative optimization operations are dynamically associated to build a three-level adaptive transmission mechanism;

[0094] It should be noted that the three-level adaptive transmission mechanism is based on the data transmission bottlenecks of multiple resource levels in a heterogeneous computing environment. The resource levels include registers, storage, and networks, and dynamically selects the optimal transmission strategy. The three-level adaptive transmission mechanism includes register-level transmission optimization, storage-level transmission optimization, and network-level transmission optimization. Among them, the register-level transmission optimization is for the target computing task type that is compute-intensive and the GPU real-time computing power score in the device capability profile is greater than the GPU real-time computing power score threshold. The storage-level transmission optimization is for high I / O throughput requirements and the I / O throughput capability score of the target storage node is greater than the I / O throughput capability score threshold. The network-level transmission optimization is for communication-intensive tasks and the transmission quality score between nodes involved is greater than the transmission quality score threshold. When the target computing task meets the trigger conditions of multiple levels at the same time, the optimization strategy with the highest priority will be executed first. The priority of the three-level adaptive transmission mechanism is register-level transmission optimization > storage-level transmission optimization > network-level transmission optimization.

[0095] In this embodiment, register-level transfer optimization is triggered when the target computing task is compute-intensive and the GPU real-time computing power score is greater than the GPU real-time computing power score threshold. In this embodiment, the GPU real-time computing power score threshold is set to 0.8. The GPU thread warps are logically divided into odd and even groups, which are mapped to different physical areas of the register file. PTX instructions are used to explicitly control data prefetching to achieve overlap between computation and data loading. Based on the prefetch window length of the computing core, a 4 to 8 times loop unrolling instruction sequence is inserted into the GPU kernel function. Synchronization primitives are used to coordinate the computation and data transfer pipelines between the odd and even warp groups to maximize instruction-level parallelism. At the same time, the register file pressure value is monitored in real time and register resources are allocated on demand based on the register file pressure value. When the register file pressure value exceeds 70%, the register overflow detection mechanism is triggered to temporarily store some less active variables in shared memory to alleviate register pressure.

[0096] In this embodiment, storage-level transfer optimization is triggered when the target computing task type is high I / O throughput demand and the I / O throughput capability score of the target storage node is greater than the I / O throughput capability score threshold. In this embodiment, the I / O throughput capability score threshold is set to 0.7. The NVMe-driven libcufile library is used to establish a direct memory access channel from the SSD to the GPU video memory. Data transfer is performed in 16KB aligned data blocks, completely bypassing the host CPU and memory, eliminating unnecessary copy overhead. The data transfer block size is dynamically adjusted based on the NVMe queue depth and PCIe bandwidth in the real-time STS indicator. In particular, when the IO queue depth is greater than 80% of the maximum supported queue depth, the random access optimized block mode is switched to adapt to high-concurrency random read and write scenarios. GPU atomic operations are used to accurately track the completion status of each DMA transfer block, ensuring that the computing kernel function starts execution only after all required data has been completely transferred to the GPU video memory, ensuring data consistency.

[0097] In this embodiment, network-level transmission optimization is triggered when the target computing task is communication-intensive and the transmission quality score between the involved nodes exceeds the transmission quality score threshold. In this embodiment, the transmission quality score threshold is set to 0.6. When the topological hop count of the communication path is ≥3, the UCX protocol is preferentially used, and the communication path is dynamically calculated and compressed in combination with a hierarchical routing algorithm to reduce network latency and congestion. When communication occurs within a node, the zero-copy mode of MPI_Isend / IRecv is preferentially enabled, and GPURDMA technology is used to directly access the peer GPU memory to avoid data transfer between host memories. The congestion rate of the network switch port on the critical path is monitored in real time. If the network switch port congestion rate is greater than 30%, the TCP transmission window size is dynamically adjusted to ensure the service quality of critical data transmission. For high-reliability critical communication paths with a transmission quality score greater than 0.9, a dual-path redundant transmission mechanism is enabled. The receiving end verifies the integrity of the data packet through hashing and other methods, and selects the valid data packet that arrives first to improve communication robustness.

[0098] Specifically, in S5, the execution states of the three-level adaptive transmission mechanism are dynamically associated, and a feedback optimization operation is performed at a preset period. The feedback optimization operation is a closed-loop optimization of S1-S4.

[0099] In this embodiment, the conditions for triggering the feedback optimization operation are to map the performance indicators of the three-level adaptive transmission mechanism to the pattern characteristics of S1, and dynamically adjust the feature extraction rules of the computational density coefficient and the data locality strength; according to the exceeding of the PCIe bandwidth utilization rate of the storage-level transmission optimization transmission, trigger the real-time update of the multi-dimensional resource situation matrix in S2, including the retraining of the NVMe queue depth threshold and the GPU computing power score; when the cross-node delay fluctuation of the network-level transmission optimization exceeds 20%, S3 re-optimizes the device dimension binding decision and prefetch window length; if the Warp double buffering strategy of the register-level transmission optimization fails to achieve the expected optimization effect for 5 consecutive times, the degradation evaluation of the three-level adaptive transmission mechanism of S4 is automatically triggered, and the trigger condition threshold is adjusted.

[0100] Secondly: The drawings of the embodiments disclosed in the present invention only involve structures related to the embodiments disclosed in the present invention. Other structures may refer to conventional designs. The same embodiment and different embodiments of the present invention may be combined with each other without conflict.

[0101] Finally: The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A GPU and parallel IO collaborative optimization method based on heterogeneous computing is characterized by: include: S1: During the execution of the target computing task, the instruction analyzer monitors and obtains the pattern characteristics of the target computing task in real time; The step of obtaining the pattern feature through the instruction analyzer includes: The sliding window weighted average algorithm is used to calculate the density coefficient Calculation is performed, specifically expressed as: in, and Respectively expressed as The number of floating-point operation instructions and memory access instructions counted within a time window; Indicated as assigned to The weight of the time window, Expressed as the number of time windows; Exponential decay is used to control the influence of data in each time window, which is specifically expressed as: in, Expressed as a pre-configured attenuation coefficient; Based on the memory access address sequence obtained in a sampling period, the discrete degree between addresses is calculated to represent the spatial locality metric , specifically expressed as: in, It is expressed as the total number of memory access operations within the sampling period. Represents the index of the memory access operation, Expressed as The target address of the memory access operation; Expressed as calculating the Hamming distance between two consecutive memory access addresses, The address width expressed as the computational spatial locality; Count the distribution of reuse distances of memory access addresses and calculate the entropy value to represent the temporal locality metric , specifically expressed as: in, It is represented by the preset maximum reuse distance threshold, Represented as an index of reuse distance, The reuse distance is expressed as The proportion of memory access operations in the sampling period is taken as the reuse distance The ratio of the number of accesses to the total number of memory access operations during the sampling period; S2: collecting dynamic parameters of the heterogeneous computing environment where the target computing task is located in real time to generate a multi-dimensional resource situation matrix; S3: Based on the pattern characteristics and the multi-dimensional resource situation matrix, performing a collaborative optimization operation, the collaborative optimization operation including binding a device dimension and a scheduling time dimension; S4: Building a three-level adaptive transmission mechanism based on the execution status of the collaborative optimization operation; The three-level adaptive transmission mechanism includes register-level transmission optimization, storage-level transmission optimization, and network-level transmission optimization. The register-level transmission optimization is targeted at target computing tasks that are computationally intensive and whose GPU real-time computing power score in the device capability profile is greater than the GPU real-time computing power score threshold. The storage-level transmission optimization is targeted at high I / O throughput requirements and whose I / O throughput capability score of the target storage node is greater than the I / O throughput capability score threshold. The network-level transmission optimization is targeted at communication-intensive tasks and whose transmission quality score between nodes is greater than the transmission quality score threshold. S5: Based on the execution status of the three-level adaptive transmission mechanism, periodically perform feedback optimization operations.

2. The GPU and parallel IO collaborative optimization method based on heterogeneous computing according to claim 1 is characterized in that: The S1, pattern features include computational density coefficient, data locality strength and communication dependency graph, wherein the computational density coefficient is a quantitative indicator used to reflect the relative relationship between computational intensity and memory access intensity; Data locality strength is used to measure the degree to which computing tasks access data in a centralized manner during execution; The communication dependency graph is used to describe the data transfer relationship and load conditions between different computing tasks in a heterogeneous computing environment.

3. The GPU and parallel IO collaborative optimization method based on heterogeneous computing according to claim 1, characterized in that: Said S2, multi-dimensional resource situation matrix includes device dimension, resource type dimension and time dimension, wherein the resource type dimension is used to identify specific dynamic parameters.

4. The GPU and parallel IO collaborative optimization method based on heterogeneous computing according to claim 1, characterized in that: The method for implementing the binding device dimension in the collaborative optimization operation in S3 includes: Determine the task type of the target computing task based on the pattern characteristics; Generate a device capability profile based on the dynamic parameters of the heterogeneous computing environment in the multi-dimensional resource status matrix. The device capability profile includes the real-time computing power score of the GPU, the I / O throughput score of the storage node, and the transmission quality score of the communication path between nodes. Based on the matching strategy between task type and device capability profile, device dimension binding decisions are dynamically executed.

5. The GPU and parallel IO collaborative optimization method based on heterogeneous computing according to claim 1, characterized in that: The method for implementing the scheduling time dimension in the collaborative optimization operation in S3 includes: 1-3 clock cycles before the GPU kernel function starts, the prefetch strategy is triggered by the CUDA stream event to load the next calculation window data; Through the hardware and software coordination mechanism, strict timing matching between the execution of computing kernel functions and data transmission is achieved, and the computing cycle and DMA transmission cycle are monitored in real time; If the calculation cycle is smaller than the DMA transfer cycle, enable GPU dynamic frequency scaling to increase the SM clock frequency to the theoretical peak value; If the calculation cycle is longer than the DMA transfer cycle, increase the DMA queue depth.

6. The GPU and parallel IO collaborative optimization method based on heterogeneous computing according to claim 1, characterized in that: In S4, the priority of the three-level adaptive transmission mechanism is register-level transmission optimization > storage-level transmission optimization > network-level transmission optimization. When the target computing task meets the trigger conditions of multiple levels at the same time, the optimization strategy with the highest priority will be executed first.

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