Multi-core simulation method, system and equipment and storage medium

Abstract

The invention provides a multi-chip simulation method, system and device and a storage medium, a chip in multi-chip simulation comprises a CPU and a plurality of CGRA assemblies, each CGRA assembly comprises a CGRA front-end interface and a rear-end CGRA simulator, the rear-end CGRA simulator based on SystemC is packaged into a dynamic link library capable of being recognized by SST, the CGRA front-end interface is used as connection to interact with SST during operation, and the SST is used as a dynamic link library capable of being recognized by SST. And the compatibility problem of the SystemC and the SST framework is solved. In an SST simulation framework, a communication link of a CPU and a CGRA assembly is established, an application program is operated, a CGRA task needing to be executed and a data packet needed for operating the CGRA task are determined, the data packet is transmitted to the corresponding CGRA assembly through the communication link, the data packet is received through a CGRA front-end interface of the CGRA assembly, a rear-end CGRA simulator is driven to perform task operation, and multi-core simulation is achieved.

Description

Technical Field

[0001] This specification relates to the field of computer technology, and particularly to a multi-die simulation method, system, device, and storage medium. Background Art

[0002] With the continuous evolution of information technology, the importance of reconfigurable computing hardware in contemporary computing architectures has become increasingly prominent. This kind of hardware can dynamically adjust its own configuration according to the tasks assigned by the main processor and execute various complex computing tasks. Among them, the coarse-grained reconfigurable array (CGRA), as a coarse-grained reconfigurable computing chip, balances flexibility and resource consumption and has more advantages in scenarios that require efficient processing of multiple computing tasks.

[0003] In the field of simulation technology for multi-CGRA dies, existing tools still have significant technical bottlenecks. Specifically, although existing simulation tools can effectively simulate the operating characteristics of a single CGRA die, there are still functional deficiencies when building a simulation model of a complex system that includes multiple dies. It is worth noting that the current mainstream CGRA simulators are generally developed using the SystemC hardware modeling language, and this technology selection results in insufficient compatibility with the general C / C++ software framework, thus forming a technical obstacle to the realization of multi-die system-level integration. This limitation makes it difficult to accurately quantify and evaluate the global performance indicators and resource utilization efficiency of the multi-CGRA die architecture through simulation means when developing large-scale parallel computing systems. Summary of the Invention

[0004] To overcome the problems existing in the related art, this specification provides a multi-die simulation method, system, device, and storage medium.

[0005] According to the first aspect of the embodiments of this specification, a method is provided. The method is used to test an application program through a simulator. The die includes a CPU and multiple CGRA components. The CGRA components include a CGRA front-end interface and a back-end CGRA simulator; a communication connection between the CPU and the CGRA components is established through a preset structural simulation toolkit. The method includes: The CPU sends a data packet to the CGRA component running the CGRA task through the communication connection. The data packet is the CGRA task obtained by running the application program at the CPU end and the data packet required to run the CGRA task. The CGRA front-end interface of the CGRA component receives the data packet, and after sending the information in the data packet to the back-end CGRA simulator for calculation and obtaining the operation result, returns the operation result to the CPU through the communication connection for the CPU to continue running the application program.

[0006] A multi-die simulation method provided in this specification, establishing a communication connection between the CPU and the CGRA component through a structural simulation toolkit, includes: Configuring the CPU and the CGRA component through the structural simulation toolkit, and instantiating the CPU and the CGRA component according to the configuration; Establishing a communication link between the CPU and the CGRA component according to the configuration information; Wherein, the configuration includes configuring unique addresses and numbers for each of the CPU and the CGRA component.

[0007] A multi-die simulation method provided in this specification, the CPU sending a data packet to the CGRA component running a CGRA task through the communication connection, includes: The CPU runs the application program, determines the CGRA task and the target CGRA component for executing the CGRA task; Packing the CGRA task and the information required for running the CGRA task into a data packet; Sending the data packet to the target CGRA component through the target communication link between the CPU and the target CGRA component.

[0008] A multi-die simulation method provided in this specification, the target communication link is established according to the address and number information of the target CGRA component and the CPU.

[0009] A multi-die simulation method provided in this specification, the CGRA simulator includes reconfigurable computing logic; The CGRA front-end interface of the CGRA component receives the data packet, and sends the information in the data packet to the back-end CGRA simulator for operation and obtains an operation result, including: The back-end CGRA simulator performs task calculations based on the reconfigurable computing logic and the information sent by the CGRA front-end interface, obtains an operation result, and returns the operation result to the CGRA front-end interface.

[0010] A multi-die simulation method provided in this specification, the back-end CGRA simulator further includes a clock control function; During the operation of the back-end CGRA simulator of the CGRA component, the method further includes: The back-end CGRA simulator in the CGRA component performs task calculations according to the clock of the triggered back-end CGRA simulator and executes an operation for one clock cycle; Among them, the triggering of the clock is achieved by the structural simulation tool calling the clock control function through the CGRA front-end interface.

[0011] According to a multi-die simulation method provided in this specification, the method further includes: The structural simulation tool periodically calls the clock control function according to the clock cycle of the back-end CGRA simulator to trigger the clock of the back-end CGRA simulator; Among them, the clock cycle of the back-end CGRA simulator is determined according to the configuration of the CGRA component to which it belongs, and the configuration includes frequency parameters.

[0012] According to a multi-die simulation method provided in this specification, the step of returning the operation result to the CPU through the communication connection for the CPU to continue running the application program includes: After the CGRA component finishes running, update the running state to the completed state and send an event notification of task completion to the CPU; When the CPU obtains the event notification and determines that the CGRA component is in the completed state, the CPU obtains the operation result.

[0013] According to a second aspect of the embodiments of this specification, a system is provided, including: It includes the multi-die simulation method as described in any one of the above and multiple dies. Each die includes a CPU and multiple CGRA components. The CGRA component includes a CGRA front-end interface and a back-end CGRA simulator; a communication connection between the CPU and the CGRA component is established through a preset structural simulation tool kit.

[0014] According to a third aspect of the embodiments of this specification, a device is provided, including: It includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, it implements the multi-die simulation method as described in any one of the above.

[0015] According to a fourth aspect of the embodiments of this specification, a computer-readable storage medium is provided, including: When the computer program is executed by a processor, it implements the multi-die simulation method as described in any one of the above.

[0016] The technical solutions provided by the embodiments of this specification may include the following beneficial effects: In the embodiments of this specification, the multi-dielet simulation dielet includes a CPU and multiple CGRA components. The CGRA component includes a CGRA front-end interface and a back-end CGRA simulator. The back-end CGRA simulator based on SystemC is encapsulated as a dynamic link library recognizable by SST. At runtime, the CGRA front-end interface serves as a connection to interact with SST, solving the compatibility problem between SystemC and the SST framework. In the SST simulation framework, an application program is run and the CGRA tasks to be executed and the data packets required to run the CGRA tasks are determined. Through the communication connection between the CPU and the CGRA components, the data packets are transmitted to the corresponding CGRA components, received through its CGRA front-end interface, and the back-end CGRA simulator is driven to run the tasks, realizing the simulation of multi-dielets.

[0017] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit this specification. Description of the Drawings

[0018] The drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with this specification, and are used together with the specification to explain the principles of this specification.

[0019] Figure 1 It is a structural diagram of a CGRA component shown according to an exemplary embodiment of this specification.

[0020] Figure 2 It is a structural diagram of an SST simulation framework shown according to an exemplary embodiment of this specification.

[0021] Figure 3 It is a schematic diagram of running an application program for simulation shown according to an exemplary embodiment of this specification.

[0022] Figure 4 It is a flowchart of a method shown according to an exemplary embodiment of this specification.

[0023] Figure 5 It is a schematic diagram of the communication method between a CGRA component and the SST framework shown according to an exemplary embodiment of this specification.

[0024] Figure 6 It is a schematic diagram of the control and management of a CGRA simulator component by a CPU shown according to an exemplary embodiment of this specification.

[0025] Figure 7 It is a block diagram of a device shown according to an exemplary embodiment of this specification.

[0026] Figure 8 It is a schematic diagram of a device shown according to an exemplary embodiment of this specification. Detailed implementation manners

[0027] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with this specification. On the contrary, they are merely examples of devices and methods consistent with some aspects of this specification as detailed in the appended claims.

[0028] The terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit this specification. The singular forms "a", "the", and "said" used in this specification and the appended claims are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0029] It should be understood that although the terms first, second, third, etc. may be used in this specification to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this specification, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "when" or "while" or "in response to determining".

[0030] This specification provides a multi-die simulation method, device, and computer-readable storage medium. The embodiments of this specification will be described in detail below with reference to the drawings. Without conflict, the features in the following embodiments and implementation manners may be combined with each other.

[0031] Existing CGRA (Coarse-Grained Reconfigurable Array) simulators are usually designed for single die, and their kernels only support the initialization and operation of a single CGRA model, and cannot dynamically generate multiple CGRA instances by configuring parameters. At the same time, they lack global interconnection topology management and task scheduling logic. Therefore, in the field of simulation technology for multi-CGRA die systems, how to simulate multiple CGRA die systems is a difficult problem.

[0032] Typically, SST (Structural Simulation Toolkit) is a framework for computer architecture simulation that can instantiate, interconnect, and clock hardware components and support co-simulation of multiple components. However, most current CGRA simulators are developed using the hardware modeling language SystemC. The hardware modeling features of SystemC create a technology stack gap with general C++ frameworks (such as SST) in terms of language features, compilation models, memory models, execution environments, and interface specifications. For example, the compiled binary files depend on specific versions of the SystemC library, which may conflict with the compilation environment of general C++ frameworks. The lack of compatibility between the two means that the multi-component management capabilities of the framework cannot be utilized, resulting in a lack of underlying support for multi-die interconnection and thus posing a technical obstacle to the implementation of multi-die system-level integration. Therefore, a technical solution that can solve the compatibility problem between SystemC and C / C++ is needed to simulate CGRA dies by providing functional control and management of CGRA components through the SST framework.

[0033] To solve the above technical problems, this specification provides a multi-die simulation method.

[0034] The aim is to design CGRA components compatible with the SST framework and run them on SST to achieve the simulation of multiple CGRA dies.

[0035] It should be noted that by integrating multiple dedicated dies (such as CPUs, CGRAs), a flexible and high-performance computing system can be constructed, reducing the complexity and cost of chip design.

[0036] As Figure 1 shown, Figure 1 is a structural diagram of a CGRA component shown in this specification according to an exemplary embodiment.

[0037] The CGRA component includes a CGRA front-end interface and a back-end CGRA simulator developed based on SystemC. The back-end CGRA simulator based on SystemC is encapsulated as a dynamic link library recognizable by SST, and a reconfigurable computing function configuration file is executed to simulate the functions provided by a real CGRA. At runtime, the CGRA front-end interface serves as a connection to interact with SST through a standardized C++ interface, receiving external clocks and data and driving the back-end CGRA simulator to run tasks. That is, the SST framework communicates with the SystemC simulator through the front-end interface of the CGRA component, and achieves seamless integration of the SystemC simulator and SST (SST is created based on C / C++) through the component interface, solving the compatibility problem between SystemC and C / C++.

[0038] Further, as Figure 2 shown, Figure 2 FIG. Figure 2 is a structural diagram of an SST simulation framework shown in this specification according to an exemplary embodiment. The SST simulation framework integrates a CPU simulator component and a CGRA simulator component. In terms of the simulation of multiple CGRA die, the simulation framework includes a CPU component and n CGRA components, and the CPU simulator component and the CGRA component are connected through the SST framework.

[0039] In the SST framework, the CPU can control and manage the CGRA component through the functions provided by the SST framework and communicate with the CGRA. As Figure 3 shown, Figure 3 FIG. Figure 3 is a schematic diagram of running an application for simulation shown in this specification according to an exemplary embodiment.

[0040] When running an application, the CPU component will transfer the task configuration and data of the CGRA in the application to the CGRA component through the SST framework. After receiving the task, the CGRA component dynamically adjusts the internal hardware structure of the CGRA according to the task requirements (it can be understood that there are many computing units and storage units inside the CGRA, and what is adjusted is the interconnection, combination method and data transmission of the internal units, so as to realize the task function and accelerate the task calculation), and performs task calculation. The CGRA component then returns the operation result to the CPU component through the SST framework, and the CPU component outputs the operation result, thereby realizing the simulation of multiple CGRA die.

[0041] In this solution, the responsibilities of the CPU and the CGRA are clearly divided. The CPU is responsible for logical control and task scheduling, and the CGRA focuses on task calculation. Through a standardized interface, efficient cooperation is achieved, improving the flexibility and scalability of the simulation system.

[0042] Based on the above SST simulation framework, this specification provides an embodiment of a multi-die simulation method, and the method is used to test an application program through a simulator.

[0043] As Figure 4 shown, Figure 4 FIG. Figure 4 is a flowchart of a method shown in this specification according to an exemplary embodiment, including the following steps: In step 102, the CPU sends a data packet to the CGRA component running the CGRA task through the communication connection, and the data packet is the CGRA task obtained by the CPU running the application program and the data packet required to run the CGRA task.

[0044] As Figure 5 shown, Figure 5This is a schematic diagram showing the communication method between the CGRA component and the SST framework as illustrated in an exemplary embodiment of this specification. The SST framework is responsible for global component management, clock scheduling, and data routing. The kernel of the SST framework drives the CGRA component through events and clocks.

[0045] Through the SST framework for component management and the interconnection between dielets, a communication connection between the CPU and the CGRA component is established, and the CGRA clock can be driven to run by the SST clock to achieve the interaction task between the CPU and the CGRA component.

[0046] In some embodiments, establishing the communication connection between the CPU and the CGRA component through the structural simulation toolkit includes: Configuring the CPU and the CGRA component through the structural simulation toolkit, and instantiating the CPU and the CGRA component according to the configuration; According to the configuration information, establishing a communication link between the CPU and the CGRA component; Wherein, the configuration includes configuring a unique address and number for each of the CPU and the CGRA component.

[0047] Continue to refer to Figure 2 , the SST framework includes one CPU and n CGRA components. Configure the CPU and each CGRA component and store them in the SST, and then the SST uses the configuration to connect several simulated hardware objects for simulation. The configuration includes but is not limited to defining variables such as frequency, storage, address, and number, and the configuration function interface. Among them, the address is the address of each device in the address space of the entire system, so that the network can send data to the correct target address during data transmission; the number is for the convenience of CPU management and control, as well as application task division, similar to the device id of the GPU.

[0048] The SST framework obtains the preset configuration information to instantiate each dielet component (i.e., the CPU and the CGRA component), and completes the component interconnection through the address and number, constructs the interconnection system of the CPU and multiple CGRAs, and simulates the topology structure of the real hardware. It can be understood that by assigning a unique address and number to each CPU and CGRA component, the SST framework establishes a communication link between the CPU component and the CGRA component based on this information, which is equivalent to implementing the bus interconnection in the hardware, thus simulating the scenario of multiple dielets working in parallel.

[0049] In this embodiment, through the address and number mechanism, it supports instantiating multiple CGRA components simultaneously in a single SST framework, simulating the scenario of multiple dielets parallel computing, breaking through the limitation that traditional simulation tools only support single CGRA.

[0050] After establishing the communication connections between the CPU and each CGRA component, when the application program and data are loaded to determine the tasks that need to be executed by the CGRA component, the CPU sends data packets to the CGRA component through the communication connection with the CGRA component that executes the CGRA task.

[0051] As an example, the CPU sends data packets to the CGRA component that runs the CGRA task through the communication connection, including: The CPU runs the application program to determine the CGRA task and the target CGRA component that executes the CGRA task; Pack the CGRA task and the information required to run the CGRA task into a data packet; Send the data packet to the target CGRA component through the target communication link between the CPU and the target CGRA component.

[0052] The CPU is the main body for running and controlling the application program. The program includes CPU code and CGRA code. Among them, the CPU part is directly executed, and the CGRA part requires the CPU to control and manage the operation of the CGRA component.

[0053] When the CPU runs the application program, that is, when the CPU obtains and parses the CGRA code, extracts the tasks that need to be executed by the CGRA component and the target CGRA component that executes the CGRA task, the CPU calls different control functions of the SST to control the CGRA component, and packs the CGRA tasks, data, and configurations that the CGRA component needs to run into data packets and distributes them to the target CGRA component. Among them, according to the virtual target communication link established based on the address and number information of the target CGRA component and the CPU, the SST framework ensures that the data packets sent by the CPU can accurately reach the target CGRA component through the target communication link.

[0054] As Figure 6 shown, Figure 6 is a schematic diagram of the CPU's control and management of the CGRA simulator component shown in this specification according to an exemplary embodiment.

[0055] The CPU controls and manages the CGRA component by calling different control functions of the SST, including but not limited to CGRA initialization and operation, setting parameters such as the operating frequency, status query, transferring the configuration file and input data required by the CGRA, starting CGRA calculation, obtaining the operation result, CGRA shutdown, etc.

[0056] In this solution, the CPU is responsible for executing serial logic, and distributes computationally intensive tasks to the CGRA component, giving full play to the advantages of the CGRA's reconfigurable computing and realizing heterogeneous computing collaboration.

[0057] In step 104, the CGRA front-end interface of the CGRA component receives the data packet. After sending the information in the data packet to the back-end CGRA simulator for calculation and obtaining the operation result, the operation result is returned to the CPU through the communication connection for the CPU to continue running the application program.

[0058] After receiving the data packet, the CGRA component decodes it and performs reconfigurable computing according to tasks, data, and configurations.

[0059] The communication architecture of the CGRA component adopts a two-layer architecture including a CGRA front-end interface and a back-end CGRA simulator. Among them, the CGRA front-end interface is responsible for communicating with the SST kernel and the CPU component, such as receiving clock signals, data packets, etc. The back-end CGRA simulator is developed based on SystemC and compiled into a dynamic link library to implement the reconfigurable computing logic of the CGRA (such as instruction execution, resource configuration). Therefore, the data packet packaged by the CPU is sent to the CGRA component through the CGRA front-end interface. The CGRA front-end interface receives the data packet (including task algorithms, input data, configuration parameters, etc.) transmitted by the SST framework, decodes the received data packet, obtains the task algorithm, input data, and reconfigurable configuration, and converts the data into a format recognizable by the back-end. Then, the CGRA front-end interface calls the back-end interface function to transfer this information to the back-end CGRA simulator for reconfigurable computing, and sets the CGRA status to the computing status.

[0060] The back-end CGRA simulator includes reconfigurable computing logic, and its operation process is as follows: The back-end of the CGRA component is based on the SystemC simulator. By executing the reconfigurable computing logic corresponding to the reconfigurable computing function configuration file, it simulates the computing logic of the real CGRA. Based on this computing logic, it performs task calculations based on the information sent by the CGRA front-end interface, obtains the operation result, and returns the operation result to the CGRA front-end interface.

[0061] In some embodiments, the SST framework has a global control function, including providing a clock driving function. During the process of the CGRA component executing the CGRA task, each step clock of the CGRA is driven by the SST clock to ensure the collaborative work of multiple components.

[0062] Exemplarily, during the process of the back-end CGRA simulator of the CGRA component performing calculations, the method further includes: The back-end CGRA simulator in the CGRA component performs task calculations according to the clock of the triggered back-end CGRA simulator and executes the operations of one clock cycle; The triggering of the clock is achieved by the structural simulation tool calling the clock control function through the CGRA front-end interface.

[0063] The clock operation of the CGRA component depends on the driver call of the SST framework. The SST framework, as a global clock source, drives the clock of its back-end SystemC simulator through the front-end interface of the CGRA component.

[0064] The backend CGRA simulator also includes a clock control function. The SST framework triggers the clock of the backend CGRA simulator by calling the clock control function, so that each calculation step of the CGRA component is triggered by the SST clock, ensuring the timing consistency between components.

[0065] That is to say, the SST framework periodically calls the clock control function through the front-end interface of the CGRA component according to the clock cycle of the back-end CGRA simulator, driving the CGRA component to perform operations for one clock cycle.

[0066] As an example, the clock period of each backend CGRA simulator is determined according to the configuration of the corresponding CGRA component, wherein the configuration includes a frequency parameter.

[0067] The clock cycle of each CGRA component is calculated by its own configuration (such as frequency parameters), that is, different CGRA components can be set with different frequencies, and the corresponding time periods of each CGRA component can also be different. The clock cycle calculated according to the configuration parameters of each CGRA component is driven at the corresponding time point. This ensures that multiple CGRA components perform calculations according to the preset timing in the simulation, ensures the coordination of multiple components in timing, and avoids simulation result deviations caused by clock asynchrony.

[0068] In this embodiment, the frequency parameters of each CGRA component are allowed to be defined to simulate the performance of the multi-chip system under different configurations. SST, as a global controller, accurately triggers the clock according to the period parameters of each CGRA component to ensure that each operation is executed in order in the simulation time.

[0069] After the CGRA component completes the calculation task, it sends the task running result back to the CPU side and notifies the receiving module on the CPU side to receive the task running result.

[0070] In some embodiments, returning the running result to the CPU through the communication connection so that the CPU continues to run the application program includes: After the CGRA component is completed, the running state is updated to the completed state, and an event notification of task completion is sent to the CPU; When the CPU obtains the event notification and determines that the CGRA component is in the completed state, it obtains the operation result.

[0071] The CGRA component performs task calculations by clock cycle, writes the log to the specified location. After the calculation task is completed, the CGRA component returns the operation result to the CPU side, notifies the CPU receiving module to receive the task operation result through a function, and sets the CGRA status to the "completed" state at the same time.

[0072] The CPU side can query the status of the CGRA component (such as in calculation, completed) through the SST framework. The CPU side obtains the CGRA status notification, gets the completed state of the CGRA, and then obtains the operation result.

[0073] The CPU side continues to run the application program. This operation result can be used in other task calculations and also supports repeating the previous steps to continue using CGRA for calculation. When the application program has finished running, the simulation process ends.

[0074] In this embodiment, the clock and task scheduling are uniformly managed through the SST framework to ensure the coordination of multiple CGRAs in terms of timing and logic, and the full life cycle management of heterogeneous computing tasks is realized through control functions.

[0075] This specification provides a multi-die simulation method, device, and computer-readable storage medium. The die includes a CPU and multiple CGRA components. The CGRA component includes a CGRA front-end interface and a back-end CGRA simulator. The back-end CGRA simulator based on SystemC is encapsulated as a dynamic link library recognizable by SST. At runtime, the CGRA front-end interface is used as a connection to interact with SST, solving the compatibility problem between SystemC and the SST framework. In the SST simulation framework, an application program is run and the CGRA tasks to be executed and the data packets required for running the CGRA tasks are determined. The communication connection between the CPU and the CGRA components is established through a preset structural simulation toolkit, and the CGRA tasks and data packets are transmitted to the corresponding CGRA components. The data packets are received through the CGRA front-end interface of the CGRA component to drive the back-end CGRA simulator to perform task operations, realizing the simulation of multi-dies, which can be used to accurately verify the cooperation efficiency of multiple CGRAs in a large-scale parallel computing system.

[0076] This specification also provides a multi-die simulation system, including the multi-die simulation method described above and multiple dies. The die includes a CPU and multiple CGRA components. The CGRA component includes a CGRA front-end interface and a back-end CGRA simulator; the communication connection between the CPU and the CGRA component is established through a preset structural simulation toolkit.

[0077] The implementation process of the multi-die simulation method of the above system can be specifically referred to the implementation process of the corresponding steps in the above method, which can achieve the same technical effect and will not be elaborated here.

[0078] As Figure 7 shown, Figure 7 FIG. is a block diagram of a device according to an exemplary embodiment of the present specification. The device includes: A task distribution module, configured to send a data packet from the CPU to a CGRA component running a CGRA task through the communication connection. The data packet is a CGRA task obtained by the CPU running the application program and a data packet required for running the CGRA task. Among them, the die includes a CPU and multiple CGRA components, and the CGRA component includes a CGRA front-end interface and a back-end CGRA simulator. A communication connection between the CPU and the CGRA component is established through a preset structural simulation toolkit.

[0079] A task execution module, configured to receive the data packet by the CGRA front-end interface of the CGRA component, and after sending the information in the data packet to the back-end CGRA simulator for operation and obtaining an operation result, return the operation result to the CPU through the communication connection for the CPU to continue running the application program.

[0080] The implementation process of the functions and roles of each module / sub-module / unit in the above device can be specifically referred to the implementation process of the corresponding steps in the above method, which can achieve the same technical effect and will not be elaborated here.

[0081] For the device embodiment, since it basically corresponds to the method embodiment, the relevant parts can refer to the partial description of the method embodiment. The device embodiments described above are only illustrative. The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed to multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of the present specification. Those of ordinary skill in the art can understand and implement it without creative efforts.

[0082] Figure 8 FIG. illustrates a schematic physical structure diagram of an electronic device. As Figure 8As shown, the electronic device may include: a processor 810, a communications interface 820, a memory 830, and a communication bus 840. Among them, the processor 810, the communications interface 820, and the memory 830 communicate with each other via the communication bus 840. The processor 810 may invoke the logical instructions in the memory 830 to execute the multi-die simulation method.

[0083] In addition, when the logical instructions in the above-mentioned memory 830 are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs that can store program codes.

[0084] On the other hand, this application also provides a computer program product. The computer program product includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the multi-die simulation method provided by the above-mentioned various methods.

[0085] On yet another hand, this application also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it is implemented to execute the multi-die simulation method provided by the above-mentioned various methods.

[0086] The specific embodiments of this specification are described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be executed in a different order than in the embodiments and still achieve the desired result. Additionally, the processes depicted in the drawings do not necessarily require the specific order or sequential order shown to achieve the desired result. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0087] Those skilled in the art will readily conceive of other embodiments of the present specification after considering the specification and practicing the invention claimed herein. This specification is intended to cover any variations, uses, or adaptations of the present specification, which follow the general principles of the present specification and include known common general knowledge or conventional technical means in the technical field not claimed in the present specification. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present specification are pointed out by the following claims.

[0088] It should be understood that the present specification is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present specification is only limited by the appended claims.

[0089] The above are only the preferred embodiments of the present specification and are not intended to limit the present specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present specification shall be included within the scope of protection of the present specification.

Claims

1. A multi-die simulation method, characterized in that, The method is used to test an application through an emulator. The chiplet includes a CPU and multiple CGRA components. The CGRA components include a CGRA front-end interface and a back-end CGRA simulator. A communication connection between the CPU and the CGRA components is established through a preset structural simulation toolkit. The method includes: The CPU sends a data packet to the CGRA component running the CGRA task through the communication connection. The data packet is the CGRA task obtained by the CPU running the application and the data packet required for running the CGRA task. The CGRA front-end interface of the CGRA component receives the data packet, and after sending the information in the data packet to the back-end CGRA simulator for calculation and obtaining the operation result, returns the operation result to the CPU through the communication connection for the CPU to continue running the application.

2. The multi-die simulation method according to claim 1, wherein Establishing the communication connection between the CPU and the CGRA components through the preset structural simulation toolkit includes: Configuring the CPU and the CGRA components through the structural simulation toolkit, and instantiating the CPU and the CGRA components according to the configuration. Establishing a communication link between the CPU and the CGRA components according to the configuration information. Among them, the configuration includes configuring a unique address and number for each of the CPU and the CGRA components.

3. The multi-die simulation method according to claim 2, wherein The CPU sending a data packet to the CGRA component running the CGRA task through the communication connection includes: The CPU runs the application to determine the CGRA task and the target CGRA component for executing the CGRA task. Packaging the CGRA task and the information required for running the CGRA task into a data packet. Sending the data packet to the target CGRA component through the target communication link between the CPU and the target CGRA component.

4. The multi-die simulation method according to claim 3, wherein The target communication link is established according to the address and number information of the target CGRA component and the CPU.

5. The multi-die simulation method according to claim 1, characterized in that, The CGRA simulator includes reconfigurable computing logic. The CGRA front-end interface of the CGRA component receiving the data packet and sending the information in the data packet to the back-end CGRA simulator for calculation and obtaining the operation result includes: The back-end CGRA simulator performs task calculations based on the reconfigurable computing logic and the information sent by the CGRA front-end interface to obtain the operation result, and returns the operation result to the CGRA front-end interface.

6. The multi-die simulation method according to claim 1, wherein, The back-end CGRA simulator also includes a clock control function. During the operation of the back-end CGRA simulator of the CGRA component, the method further includes: The back-end CGRA simulator in the CGRA component performs task calculations according to the clock of the triggered back-end CGRA simulator and executes an operation for one clock cycle. Among them, the triggering of the clock is realized by the structural simulation tool calling the clock control function through the CGRA front-end interface.

7. The multi-die simulation method according to claim 6, wherein, The method further includes: The structure simulation tool periodically calls the clock control function according to the clock cycle of the backend CGRA simulator to trigger the clock of the backend CGRA simulator; Among them, the clock cycle of the backend CGRA simulator is determined according to the configuration of the CGRA component to which it belongs, and the configuration includes frequency parameters.

8. The multi-die simulation method according to claim 1, characterized in that Returning the operation result to the CPU through the communication connection for the CPU to continue running the application program includes: After the CGRA component finishes running, update the running state to the completed state and send an event notification of task completion to the CPU; When the CPU obtains the event notification and determines that the CGRA component is in the completed state, the CPU obtains the operation result.

9. A multi-die simulation system, characterized in that, It includes the multi-die simulation method according to any one of claims 1-8, and multiple dies. The die includes a CPU and multiple CGRA components. The CGRA component includes a CGRA front-end interface and a backend CGRA simulator; establish a communication connection between the CPU and the CGRA component through a preset structure simulation tool package.

10. A computer device, characterized in that, It includes a memory, a processor, and a multi-die simulation program stored on the memory and executable on the processor. When the processor executes the multi-die simulation program, it implements the steps of the multi-die simulation method according to any one of claims 1-8.

11. A computer-readable storage medium, characterized in that, A multi-die simulation program is stored on the computer-readable storage medium. When the multi-die simulation program is executed, it implements the steps of the multi-die simulation method according to any one of claims 1-8.

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