Driving circuit, driving chip and display device

Abstract

The invention discloses a driving circuit, a driving chip and a display device. The driving circuit comprises a current source which comprises a source branch and a plurality of mirror image branches, each mirror image branch comprises a first driving transistor, at least part of the first driving transistors are gated to provide driving current for a load in the output stage of the driving circuit, and a plurality of gate end charging and discharging units are arranged on the source branch and the mirror image branches. Each gate end charging and discharging unit is used for providing gate end charging current or gate end discharging current for the first driving transistor in the corresponding mirror image branch; and the bias unit is used for providing adjustable bias current for the plurality of gate end charging and discharging units so as to adjust the gate voltage rising / falling slope of the first driving transistors in the plurality of mirror image branches. The grid voltage rising / falling slope of the grid end of the first driving transistor in each mirror image branch is adjusted through the adjustable current source and the grid end charging and discharging unit, so that the change rate of the driving current is adjusted, and electromagnetic interference caused by rapid change of the driving current can be avoided.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a driving circuit, a driving chip, and a display device. Background Art

[0002] The pixel elements used in LED display devices are LEDs. LED display devices have the following advantages: high brightness, wide viewing angles, rich colors, and customizable screen shapes. Therefore, LED display devices are widely used in various fields such as industry, transportation, commercial advertising, information dissemination, and sports competitions.

[0003] Figure 1 is a schematic structural diagram of an LED display driving circuit in the prior art. The basic working principle is that the operational amplifier OP2 compares the voltage VC and Vref2, and controls the conduction of M0 according to the comparison result. The operational amplifier OP1 compares the voltage VB and Vref1, and controls VA according to the comparison result, so as to accurately copy the Iref current by M2, M3... Mn, and control the current flowing through the LED lamp by controlling the conduction conditions of the branches of M2, M3... Mn, thereby realizing the adjustment of the brightness of the LED lamp.

[0004] However, in this driving circuit, after the brightness of the LED lamp is determined, the driving current provided by the driving circuit is constant. That is to say, the conduction conditions of M2, M3... Mn are fixed. Therefore, the rising slew rate of the driving current is constant. Thus, at the moment when the circuit starts, the driving circuit will generate a transient large current, and the transient large current change will cause electromagnetic radiation and generate electromagnetic waves, thereby causing electromagnetic interference (EMI, Electromagnetic Interference). Summary of the Invention

[0005] In view of the above problems, the purpose of the present application is to provide a driving circuit, a driving chip, and a display device, which can control the change slope of the driving current, thereby avoiding electromagnetic interference caused by rapid current changes.

[0006] According to one aspect of the present application, a driving circuit is provided, which includes: a current source including a source branch and a plurality of mirror branches, each mirror branch including a first driving transistor, and at least part of the first driving transistors are selected to conduct in the output stage of the driving circuit to provide a driving current to a load; a plurality of gate charge and discharge units, each gate charge and discharge unit being configured to provide a gate charging current or a gate discharging current to the first driving transistor in the corresponding mirror branch; and a bias unit configured to provide an adjustable bias current to the plurality of gate charge and discharge units to adjust the rising / falling slope of the gate voltage of the first driving transistors in the plurality of mirror branches.

[0007] Optionally, the bias unit includes: a first branch for providing a first bias current, and the gate charging and discharging unit mirrors the first bias current proportionally to provide the charging current; and a second branch for providing a second bias current, and the gate charging and discharging unit mirrors the second bias current proportionally to provide the discharging current.

[0008] Optionally, the first branch includes a first transistor and a first current source with adjustable current magnitude. The first end of the first transistor is connected to the first power supply terminal, the second end is connected to the gate terminal and grounded through the first current source; the second branch includes a second transistor and a second current source with adjustable current magnitude. The first end of the second transistor is connected to the gate terminal and connected to the first power supply terminal through the second current source, and the second end is grounded. Wherein, the gate terminals of the first transistor and the second transistor are also connected to the gate charging and discharging unit.

[0009] Optionally, the source branch includes a second driving transistor, and the driving circuit further includes: a control unit for providing an on voltage for turning on the second driving transistor and the corresponding first driving transistor during the output stage; and a selection unit adapted to each of the mirror branches for providing the on voltage to the selected mirror branch or providing a cut-off voltage to the non-selected mirror branch during the output stage.

[0010] Optionally, the gate terminal of the first driving transistor is connected to the corresponding selection unit to receive the on voltage or the cut-off voltage. The first end provides a mirror current, and the second end is grounded through a first resistor; the gate terminal of the second driving transistor is connected to the control unit, the first end provides a source current, and the second end is grounded through a second resistor. Wherein, the ratio of the first driving transistor in each mirror branch to the second driving transistor in the source branch is the same as the ratio of the first resistor in this mirror branch to the second resistor in the source branch.

[0011] Optionally, the control unit includes: an operational amplifier, the non-inverting input terminal receives a reference voltage, the inverting input terminal is connected to the second end of the second driving transistor, and the output terminal provides the on voltage; and an output module connected between the output terminal of the operational amplifier and each selection unit for providing the on voltage to each selection unit.

[0012] Optionally, the output module includes: a comparator, with the non-inverting input terminal connected to the gate terminals of the first driving transistors in all the mirror branches, and the inverting input terminal connected to the output terminal of the operational amplifier; a D flip-flop, with the clock input terminal connected to the output terminal of the comparator, and the data input terminal receiving a first signal; a first enabling switch, connected between the output terminal of the operational amplifier and each of the selection units, and the first enabling switch is controlled by the output signal of the D flip-flop to provide the turn-on voltage to the selection unit when closed.

[0013] Optionally, each of the selection units includes: a second enabling switch, connected between the first enabling switch and the gate terminal of the first driving transistor in the corresponding mirror branch, and controlled by the strobe signal of this mirror branch to close and provide the turn-on voltage to the gate terminal of the first driving transistor in this mirror branch when this mirror branch is strobed; and a third enabling switch, connected between the gate terminal of the first driving transistor in the corresponding mirror branch and the ground, and controlled by the corresponding strobe signal to close and provide the cut-off voltage to the gate terminal of the first driving transistor in this mirror branch when this mirror branch is not strobed.

[0014] Optionally, each of the gate terminal charge and discharge units includes a first mirror transistor, a fourth enabling switch, a fifth enabling switch, and a second mirror transistor connected in sequence between the first power supply terminal and the ground. The gate terminal of the first mirror transistor is connected to the first branch to mirror the first bias current proportionally. The gate terminal of the second mirror transistor is connected to the second branch to mirror the second bias current proportionally. The intermediate node of the fourth enabling switch and the fifth enabling switch is connected to the gate terminal of the corresponding first driving transistor. The fourth enabling switch is controlled by a first enabling signal to close and provide the charging current when the corresponding mirror branch is strobed; the fifth enabling switch is controlled by a second enabling signal to close and provide the discharging current when the corresponding mirror branch is not strobed.

[0015] Optionally, the driving circuit further includes: a reset unit for turning off the source branch in a non-output stage.

[0016] Optionally, the reset unit includes: a reset transistor, with the first end connected to the gate terminal of the second driving transistor, the second end grounded, and the gate terminal receiving a reset pulse signal through an inverter, and the reset pulse signal is also used to reset the D flip-flop.

[0017] Optionally, the load includes a light-emitting element, and the driving circuit further includes a processing unit for providing the corresponding strobe signal to each of the mirror branches according to the target brightness of the light-emitting element.

[0018] Optionally, it further includes: an enable signal generation unit, configured to provide the first enable signal and the second enable signal according to the strobe signal, the reset pulse signal, and the output signal of the D flip-flop.

[0019] Optionally, the enable signal generation unit includes: a NAND gate circuit, receiving the inverted signal of the output signal of the D flip-flop, the strobe signal corresponding to each mirror branch, and the reset pulse signal, and providing the first enable signal corresponding to each mirror branch; and an AND gate circuit, receiving the strobe signal corresponding to each mirror branch and the inverted signal of the reset pulse signal, and providing the second enable signal corresponding to each mirror branch.

[0020] According to another aspect of the present application, a driving chip is provided, which includes: the driving circuit as described in any one of the above.

[0021] According to a third aspect of the present application, a display device is provided, which includes: a display panel; and the driving chip as described above.

[0022] According to the driving circuit, driving chip, and display device provided by the present application, by setting an adjustable current source and a gate charging and discharging unit to adjust the rising / falling slope of the gate voltage at the gate of the first driving transistor in each mirror branch, and further adjusting the change rate of the driving current, electromagnetic interference caused by the rapid change of the driving current can be avoided. Description of the Drawings

[0023] Through the following description of the embodiments of the present invention with reference to the drawings, the above and other objects, features, and advantages of the present invention will become clearer. In the drawings: Figure 1 A schematic structural diagram of an LED display driving circuit in the prior art is shown; Figure 2 A schematic structural diagram of a display device is shown; Figure 3 A schematic structural diagram of the driving circuit according to an embodiment of the present application is shown; Figure 4 Shows Figure 3 A schematic structural diagram of multiple components in; Figure 5 Shows Figure 3 A schematic structural diagram of the enable signal generation unit in; Figure 6 A schematic diagram of the working waveform of the driving circuit according to an embodiment of the present application is shown. Detailed Embodiments

[0024] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In the respective drawings, the same elements are denoted by the same or similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale.

[0025] Meanwhile, in this specification and the claims, certain terms are used to refer to specific components. Those of ordinary skill in the art should understand that manufacturers may use different names to refer to the same component. This specification and the claims do not use the difference in names as a way to distinguish components, but use the difference in functions of components as the criterion for distinction.

[0026] It should be understood that in the following description, a "circuit" may include a single or a combination of multiple hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected to" another element or when an element or circuit is said to be "connected between" two nodes, it can be directly coupled or connected to another element or there may be intermediate elements, and the connection between the elements can be physical, logical, or a combination thereof. In contrast, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between the two.

[0027] In addition, it should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including the said element.

[0028] Taking the load to be driven as an LED as an example, Figure 2 is a schematic structural diagram of a display device. Referring to Figure 2 , the display device 10 includes an LED display screen and a driving chip 100. The LED display screen includes a plurality of LED lamp groups D1 to Dn. The driving chip 100 includes driving circuits 110 corresponding to the respective LED lamp groups to provide driving current to the respective LED lamp groups. As an example, in Figure 2 only the driving circuit 110 for providing the driving current Id1 to the lamp group D1 is shown.

[0029] To avoid electromagnetic interference caused by rapid changes in the driving current, the present application discloses a driving circuit. The driving circuit disclosed in the present application can be applied to the display device as described above, and serves as the driving circuit 110 corresponding to each LED lamp group. Figure 3 shows a schematic structural diagram of the driving circuit. Refer to Figure 3 , the driving circuit 110 includes: a current source, a bias unit 112, a gate charge and discharge unit 113, a control unit, a selection unit 115, a reset unit, a processing unit 116, and an enable signal generation unit 117.

[0030] Figure 4 shows Figure 3 a schematic structural diagram of the bias unit 112, the gate charge and discharge unit 113, the output module 114 in the control unit, and the selection unit 115 in Figure 5 shows Figure 3 a schematic structural diagram of the enable signal generation unit 117 in Figure 4 . It should be noted that the structures of the gate charge and discharge unit 113 and the selection unit 115 connected to different mirror branches should be the same. In Figures 3 to 5 , only the gate charge and discharge unit 113 and the selection unit 115 connected to the mirror branch where the first driving transistor MSN1 is located are shown as an example. The driving circuit of the embodiment of the present application will be further described below with reference to

[0031] The current source is used to provide a driving current to the load. The current source can be a proportional current source. Refer to Figure 3 , the current source includes a source branch 111a and multiple mirror branches 111b. For the display device, the load can be an LED. The current source selects the corresponding mirror branch 111b according to the brightness of the LED, so as to adjust the magnitude of the driving current. Specifically, the processing unit 116 is used to provide the selection signals Sel1, Sel2... Seln of each mirror branch 111b according to the received display data Data. The selection signals Sel1, Sel2... Seln select the corresponding mirror branches 111b during their respective valid levels to adjust the magnitude of the driving current.

[0032] Each mirror branch 111b includes a first driving transistor and a first resistor. In Figure 3Among them, the first driving transistors of each mirror branch 111b are MSN1, MSN2... MSNn respectively, and their control terminal voltages are VG1, VG2... VGn respectively. The first resistors of each mirror branch 111b are R1, R2... Rn respectively. For the first driving transistor in each mirror branch 111b, its first terminal is used to provide the mirror current of the mirror branch 111b, and the second terminal is grounded through the first resistor of the mirror branch. The control terminals of the first driving transistors of each mirror branch are connected to the first node Q. For clarity, the specific position of the first node Q is shown in Figure 4 and the voltage of the first node Q is VQ.

[0033] The source branch 111a includes a second driving transistor MSN0 and a second resistor R0. The first terminal of the second driving transistor MSN0 is connected to the first terminals of each first driving transistor and provides a source current. The second terminal is grounded through the second resistor R0, and its control terminal voltage is VG0.

[0034] It should be noted that the sizes of the first driving transistors in each mirror branch 111b are proportional to the size of the second driving transistor MSN0. At the same time, the resistance ratio of the first resistor in each mirror branch 111b to the second resistor R0 is the same as the size ratio of the first driving transistor and the second driving transistor MSN0 in the mirror branch 111b. Usually, the size ratio of the second driving transistor MSN0 to each first driving transistor MSN1, MSN2... MSNn is 1:2:4...:2 （n-1） , and correspondingly, the ratio of the second resistor R0 to each first resistor R1, R2... Rn is also 1:2:4...:2 （n-1） . At the same time, this ratio is also the ratio of the mirror current provided by each mirror branch 111b to the source current.

[0035] The control unit is used to provide the turn-on voltages for turning on the second driving transistor MSN0 and each first driving transistor during the output stage of the driving circuit 110. Referring to Figure 3 , the control unit includes an operational amplifier A1 and an output module 114.

[0036] The non-inverting input terminal of the operational amplifier A1 receives the reference voltage Vref, the inverting input terminal is connected to the second terminal of the second driving transistor MSN0, and the output terminal is connected to the gate terminal of the second driving transistor MSN0 to provide the turn-on voltage during the output stage.

[0037] The output module 114 is connected between the output terminal of the operational amplifier A1 and each selection unit 115, and is used to provide the turn-on voltage to each selection unit 115. Referring to Figure 4, the output module 114 includes a comparator C1, a D flip-flop, and a first enable switch S1. The non-inverting input terminal of the comparator C1 is connected to the gate terminal of the first driving transistor in all the mirror branches 111b at a first node Q, and the inverting input terminal of the comparator C1 is connected to the output terminal of the operational amplifier A1. The clock input terminal CLK of the D flip-flop is connected to the output terminal of the comparator C1, the data input terminal receives a first signal TIEH, and the reset terminal receives a reset pulse signal PWM. When the reset pulse signal PWM is at a first level, for example, a low level, the D flip-flop is reset; when the reset pulse signal PWM is at a second level, for example, a high level, the D flip-flop operates normally and samples and outputs the first signal TIEH at the active edge of the clock signal. One end of the first enable switch S1 is connected to the output terminal of the operational amplifier A1, and the other end is connected to each selection unit 115. The first enable switch S1 is controlled to be closed or opened by the output signal CMP of the D flip-flop. Exemplarily, the first enable switch S1 is closed when the output signal CMP is at a high level. Then, the first signal TIEH is set to be always at a high level. Therefore, when the D flip-flop outputs the first signal TIEH, the first enable switch S1 is closed and provides an enabling voltage to each selection unit 115.

[0038] A plurality of selection units 115 are respectively adapted to the corresponding mirror branches 111b. The selection unit 115 is configured to provide an enabling voltage to the gate terminal of the first driving transistor in the corresponding mirror branch 111b when the corresponding mirror branch 111b is selected; or provide a cut-off voltage to the gate terminal of the first driving transistor in the corresponding mirror branch 111b when the corresponding mirror branch 111b is not selected. Wherein, when each first driving transistor is an NMOS, the cut-off voltage can be a ground voltage. Exemplarily, each selection unit 115 includes a second enable switch S2 and a third enable switch S3. The second enable switch S2 is connected between the output module 114 and the corresponding mirror branch 111b. Specifically, one end of the second enable switch S2 is connected to the first enable switch S1, and the other end is connected to the gate terminal of the first driving transistor in the corresponding mirror branch 111b. The third enable switch S3 is connected between the corresponding mirror branch 111b and the cut-off voltage. For the case where the first driving transistor is an NMOS, specifically, one end of the third enable switch S3 is connected to the gate terminal of the first driving transistor in the corresponding mirror branch 111b, and the other end is grounded.

[0039] Specifically, taking the mirror branch 111b where the first driving transistor MSN1 is located as an example, the selection unit 115 is further described. Refer to Figure 4, one end of the second enable switch S2 is connected to the first enable switch S1, and the other end is connected to the gate terminal of the first driving transistor MSN1. One end of the third enable switch S3 is connected to the gate terminal of the first driving transistor MSN1, and the other end is grounded. Both the second enable switch S2 and the third enable switch S3 are controlled by the selection signal Sel1 of the mirror branch 111b. Among them, the second enable switch S2 is closed when the corresponding selection signal Sel1 is at an effective level to provide an opening voltage to the gate terminal of the first driving transistor MSN1; the third enable switch S3 is closed when the corresponding selection signal Sel1 is at an invalid level to provide a cut-off voltage to the gate terminal of the first driving transistor MSN1. In Figure 4 , in order to reflect that the closing / opening states of the second enable switch S2 and the third enable switch S3 are opposite, the third enable switch S3 is controlled by the inverted signal Sel1_B of the selection signal Sel1.

[0040] To achieve adjustable driving current change rate, the driving circuit provided by the present application further includes a bias unit 112 and a gate charge / discharge unit 113 corresponding to each mirror branch 111b.

[0041] Each gate charge / discharge unit 113 is used to provide a gate charging current or a gate discharging current to the first driving transistor in the corresponding mirror branch. The bias unit 112 is used to provide an adjustable bias current I0 to each gate charge / discharge unit 113 to adjust the rising / falling slope of the gate voltage of the first driving transistor in each mirror branch 111b.

[0042] The bias unit 112 includes a first branch and a second branch. Among them, the gate charge / discharge unit 113 mirrors the first bias current provided by the first branch in proportion to provide the gate charging current of the first driving transistor in the corresponding mirror branch 111b; or mirrors the second bias current provided by the second branch in proportion to provide the gate discharging current of the first driving transistor in the corresponding mirror branch 111b.

[0043] Further, the first branch includes a first transistor MP0 and a first current source IP0 with adjustable current magnitude. The first end of the first transistor MP0 is connected to the first power supply terminal AVDD, the second end is connected to the gate terminal and grounded through the first current source IP0. The first transistor MP0 is also connected to each gate charge / discharge unit 113.

[0044] The second branch includes a second transistor MN0 and a second current source IN0 with adjustable current magnitude. The second end of the second transistor MN0 is grounded, the first end and the gate terminal are connected and connected to the first power supply terminal AVDD through the second current source IN0. The second transistor MN0 is also connected to each gate charge / discharge unit 113.

[0045] Each gate terminal charge and discharge unit 113 includes a first mirror transistor, a fourth enable switch, a fifth enable switch, and a second mirror transistor that are sequentially connected between the first power supply terminal AVDD and the ground. The gate terminal of the first mirror transistor is connected to the first branch of the bias unit 112, specifically, to the gate terminal of the first transistor MP0. The gate terminal of the second mirror transistor is connected to the second branch of the bias unit 112, specifically, to the gate terminal of the second transistor MN0. The fourth enable switch in each gate terminal charge and discharge unit 113 is controlled to be closed / open by the corresponding first enable signal; the fifth enable switch in each gate terminal charge and discharge unit 113 is controlled to be closed / open by the corresponding second enable signal. As an example, in Figure 3 the gate terminal charge and discharge units 113 connected to the respective mirror branches 111b receive the first enable signals SP1, SP2... SPn and the second enable signals SN1, SN2... SNn respectively.

[0046] It should be understood that in order to make the gate terminal charge and discharge speeds of the first drive transistors in the respective mirror branches 111b consistent, the mirror ratios of the first bias current / second bias current of each gate terminal charge and discharge unit 113 are the same as the ratios between the mirror currents and the source currents provided by the corresponding mirror branches. For example, the above current ratios can be achieved by adjusting the sizes of the first mirror transistor and the second mirror transistor in each gate terminal charge and discharge unit 113. For example, the size ratio of the second drive transistor MSN0 to the first drive transistors MSN1, MSN2... MSNn is 1:2:4...:2 （n-1） Accordingly, in each gate terminal charge and discharge unit 113, the ratios of the first mirror transistor to the first transistor MP0, and the second mirror transistor to the second transistor MN0 are both 1:2:4...:2 （n-1） .

[0047] Specifically, taking the gate terminal charge and discharge unit 113 corresponding to the mirror branch 111b where the first drive transistor MSN1 is located as an example, the bias unit 112 and the gate terminal charge and discharge unit 113 will be further introduced.

[0048] This gate terminal charge and discharge unit 113 includes a first mirror transistor MP1, a fourth enable switch S4, a fifth enable switch S5, and a second mirror transistor MN1 that are sequentially connected between the first power supply terminal AVDD and the ground.

[0049] The gate terminal of the first mirror transistor MP1 is connected to the first branch and mirrors the first bias current proportionally. The second mirror transistor MN1 is connected to the second branch and mirrors the second bias current proportionally. The intermediate node of the fourth enable switch S4 and the fifth enable switch S5 is connected to the gate terminal of the corresponding first driving transistor MSN1. Among them, the fourth enable switch S4 is controlled by the first enable signal SP1 and closes to provide a charging current when the corresponding mirror branch 111b is gated; the fifth enable switch S5 is controlled by the second enable signal SN1 and closes to provide a discharging current when the corresponding mirror branch 111b is not gated.

[0050] Further, in combination with the above Figure 3 and Figure 5 , the first enable signal and the second enable signal received by each gate terminal charge and discharge unit 113 are generated by the enable signal generation unit 117 according to the output signal CMP of the D flip-flop, the gating signal Sel of the corresponding mirror branch, and the reset pulse signal PWM.

[0051] Refer to Figure 5 , exemplarily, the enable signal generation unit 117 includes a NAND gate circuit and an AND gate circuit. The NAND gate circuit is used to provide the first enable signal SP of the mirror branch 111b according to the inverted signal of the D flip-flop output signal CMP, the gating signal Sel of the corresponding mirror branch 111b, and the reset pulse signal PWM. The AND gate circuit is used to provide the second enable signal SN of the mirror branch according to the gating signal Sel of the corresponding mirror branch 111b and the inverted signal of the reset pulse signal PWM.

[0052] Further, the driving circuit provided by the present application further includes a reset unit, which is used to reset the gate terminal voltage of the second driving transistor MSN0 in the non-output stage. The reset unit includes a reset transistor MNR. The first end of the reset transistor MNR is connected to the gate terminal of the second driving transistor MSN0, the second end is grounded, and the gate terminal receives the reset pulse signal PWM through an inverter INV1.

[0053] Figure 6 is a schematic diagram of the working waveform of the driving circuit according to the embodiment of the present application. Still taking the first mirror branch as an example, where PWM is the reset pulse signal, Id1 is the driving current provided by the driving circuit for the LED lamp bead D1, VG1 is the gate terminal voltage of the first driving transistor MSN1, and IR1 is the mirror current provided by the mirror branch where MSN1 is located. Among them, the anode of the LED lamp bead is connected to the power supply terminal VCC.

[0054] Taking the mirror branch 111b where the first driving transistor MSN1 is located as an example, the working process of the driving circuit will be briefly introduced. The low level of each signal is represented by "0" for example, and the high level is represented by "1" for example. Among them, taking the first level of the reset pulse signal PWM as the low level, the second level as the high level, the effective levels of the strobe signal Sel as the high level, the fourth enable switch S4 conducting when the level is low, and the fifth enable switch S5 conducting when the level is high as an example.

[0055] When the mirror branch 111b where the first driving transistor MSN1 is located is not strobed, Sel1 = 0, the second enable switch S2 is disconnected, the third enable switch S3 is closed, and the gate terminal of the first driving transistor MSN1 is grounded through the closed third enable switch S3. At the same time, SP1 = 1, SN1 = 0, both the fourth enable switch S4 and the fifth enable switch S5 are disconnected, and the gate charge and discharge unit 113 has no effect on the gate voltage of the first driving transistor MSN1.

[0056] When the mirror branch 111b where the first driving transistor MSN1 is located is strobed, Sel1 = 1, and there are the following situations: When the reset pulse signal PWM is at the low level, the reset transistor MNR resets the gate terminal of the second driving transistor MSN0, making the gate voltage VG0 of the second driving transistor MSN0 the ground voltage. The low-level reset pulse signal PWM also resets the D flip-flop, making its output signal CMP = 0, and the first enable switch S1 is disconnected. At this time, SP1 = 1, SN1 = 1, the fourth enable switch S4 is disconnected, the fifth enable switch S5 is closed, and the gate terminal of the first driving transistor MSN1 is grounded.

[0057] When the rising edge of the reset pulse signal PWM arrives, the output signal CMP of the D flip-flop still remains 0. At this time, SP1 = 0, SN1 = 0, the fourth enable switch S4 is closed, the fifth enable switch S5 is disconnected, and the first mirror transistor MP1 provides a charging current to the gate terminal of the first driving transistor MSN1. When the gate voltage VG1 of the first driving transistor MSN1 is slightly higher than the gate voltage VG0 of the second driving transistor MSN0, the comparator C1 outputs 1, the D flip-flop outputs the first signal TIEH = 1, and the first enable switch S1 is closed, connecting the control terminals of the first driving transistor MSN1 and the second driving transistor MSN2 in an equipotential manner. At the same time, SP = 1, SN1 = 0, and the gate charge and discharge unit 113 stops providing the charging current.

[0058] When the PWM falling edge arrives, the process of PWM = 0 is repeated.

[0059] The working principles of other mirror branches are the same and will not be exemplified one by one.

[0060] Since the charging and discharging speeds of the gate voltages of the first driving transistors in each mirror branch are the same, in the embodiments provided in the present application, the rising / falling slope of the gate voltage can be controlled by adjusting the currents of the first current source IP0 and the second current source IN0, and further the change rate of the driving current can be adjusted, thereby avoiding electromagnetic interference caused by the rapid change of the driving current.

[0061] Furthermore, the present application also provides a driving chip and a display device. The driving chip includes the above driving circuit. The display device includes the above chip and a display panel. The driving chip and the display device also have the above beneficial effects, which will not be elaborated here.

[0062] According to the embodiments of the present application as above, these embodiments do not describe all details in detail, nor do they limit the present application to only specific embodiments. Obviously, according to the above description, many modifications and variations can be made. The present specification selects and specifically describes these embodiments in order to better explain the principle and practical application of the present application, so that those skilled in the art can make good use of the present application and its modified use based on the present application. The protection scope of the present application shall be subject to the scope defined by the claims of the present application.

Claims

1. A drive circuit, wherein, Comprising: A current source, including a source branch and a plurality of mirror branches. Each mirror branch includes a first driving transistor. In the output stage of the driving circuit, at least part of the first driving transistors are turned on to provide a driving current to a load. A plurality of gate charge / discharge units, each of which is configured to provide a gate charging current or a gate discharging current to the first driving transistor in a corresponding mirror branch. And A bias unit, configured to provide an adjustable bias current to the plurality of gate charge / discharge units to adjust the rising / falling slope of the gate voltage of the first driving transistors in the plurality of mirror branches.

2. The drive circuit according to claim 1, wherein, The bias unit includes: A first branch, configured to provide a first bias current, and the gate charge / discharge units mirror the first bias current proportionally to provide the charging current; and A second branch, configured to provide a second bias current, and the gate charge / discharge units mirror the second bias current proportionally to provide the discharging current.

3. The driving circuit according to claim 2, wherein The first branch includes a first transistor and a first current source with adjustable current magnitude. A first end of the first transistor is connected to a first power supply terminal, a second end is connected to the gate terminal and grounded through the first current source. The second branch includes a second transistor and a second current source with adjustable current magnitude. A first end of the second transistor is connected to the gate terminal and connected to the first power supply terminal through the second current source, and a second end is grounded. Wherein, the gate terminals of the first transistor and the second transistor are further connected to the gate charge / discharge units.

4. The drive circuit according to claim 3, wherein, The source branch includes a second driving transistor. The driving circuit further includes: A control unit, configured to provide a turn-on voltage for turning on the second driving transistor and the corresponding first driving transistor in the output stage; and A selection unit adapted to each of the mirror branches, configured to provide the turn-on voltage to the selected mirror branch or provide a cut-off voltage to the unselected mirror branch in the output stage.

5. The driving circuit according to claim 4, wherein The gate terminal of the first driving transistor is connected to the corresponding selection unit to receive the turn-on voltage or the cut-off voltage, a first end provides a mirror current, and a second end is grounded through a first resistor. The gate terminal of the second driving transistor is connected to the control unit, a first end provides a source current, and a second end is grounded through a second resistor. Wherein, the ratio of the first driving transistor in each mirror branch to the second driving transistor in the source branch is the same as the ratio of the first resistor in the mirror branch to the second resistor in the source branch.

6. The drive circuit according to claim 5, wherein, The control unit includes: An operational amplifier, having a non-inverting input terminal receiving a reference voltage, an inverting input terminal connected to the second end of the second driving transistor, and an output terminal providing the turn-on voltage; and An output module, connected between the output terminal of the operational amplifier and each of the selection units, configured to provide the turn-on voltage to each of the selection units.

7. The drive circuit according to claim 6, wherein, The output module includes: A comparator, the non-inverting input terminal of which is connected to the gate terminals of the first driving transistors in all the mirror branches, and the inverting input terminal of which is connected to the output terminal of the operational amplifier; A D flip-flop, the clock input terminal of which is connected to the output terminal of the comparator, and the data input terminal of which receives a first signal; A first enabling switch, connected between the output terminal of the operational amplifier and each of the selection units, and the first enabling switch is controlled by the output signal of the D flip-flop to provide the turn-on voltage to the selection unit when closed.

8. The drive circuit according to claim 7, wherein Each of the selection units includes: A second enabling switch, connected between the first enabling switch and the gate terminal of the first driving transistor in the corresponding mirror branch, and controlled by the gating signal of this mirror branch to close and provide the turn-on voltage to the gate terminal of the first driving transistor in this mirror branch when this mirror branch is gated; and A third enabling switch, connected between the gate terminal of the first driving transistor in the corresponding mirror branch and the ground, and controlled by the corresponding gating signal to close and provide the cut-off voltage to the gate terminal of the first driving transistor in this mirror branch when this mirror branch is not gated.

9. The drive circuit according to claim 8, wherein Each of the gate charge and discharge units includes a first mirror transistor, a fourth enabling switch, a fifth enabling switch, and a second mirror transistor connected in sequence between a first power supply terminal and the ground, The gate terminal of the first mirror transistor is connected to the first branch to mirror the first bias current proportionally, The gate terminal of the second mirror transistor is connected to the second branch to mirror the second bias current proportionally, The intermediate node of the fourth enabling switch and the fifth enabling switch is connected to the gate terminal of the corresponding first driving transistor, The fourth enabling switch is controlled by a first enabling signal to close to provide the charging current when the corresponding mirror branch is gated; The fifth enabling switch is controlled by a second enabling signal to close to provide the discharging current when the corresponding mirror branch is not gated.

10. The drive circuit according to claim 9, wherein, The driving circuit further includes: A reset unit, used to turn off the source branch in a non-output stage.

11. The drive circuit according to claim 10, wherein, The reset unit includes: A reset transistor, the first end of which is connected to the gate terminal of the second driving transistor, the second end of which is grounded, and the gate terminal of which receives a reset pulse signal through an inverter, The reset pulse signal is also used to reset the D flip-flop.

12. The driving circuit according to claim 11, wherein, The load includes a light-emitting element, The driving circuit further includes a processing unit, used to provide the corresponding gating signal to each of the mirror branches according to the target brightness of the light-emitting element.

13. The drive circuit according to claim 12, wherein, It further includes: An enabling signal generating unit, used to provide the first enabling signal and the second enabling signal according to the gating signal, the reset pulse signal, and the output signal of the D flip-flop.

14. The drive circuit according to claim 13, wherein, The enabling signal generating unit includes: A NAND gate circuit, receiving the inverted signal of the output signal of the D flip-flop, the gating signal corresponding to each of the mirror branches, and the reset pulse signal, and providing the first enabling signal corresponding to each of the mirror branches; and An AND gate circuit receives the gating signals corresponding to the respective mirror branches and the inverted signals of the reset pulse signals, and provides the second enable signals corresponding to the respective mirror branches.

15. A driving chip, wherein, Comprising: The driving circuit according to any one of claims 1-14.

16. A display device, wherein, Comprising: A display panel; And The driving chip according to claim 15.

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