Read-write circuit, storage circuit and memory
By designing a read and write circuit compatible with 1T1MTJ and 2T2MTJ, and using bit line selection signals to achieve free switching, the problem of traditional 1T1MTJ STT-MRAM reading window reduction and read and write circuit overhead is solved, and the read margin and reliability of the memory cell are improved, and the cost is reduced.
Patent Information
- Application Number
- CN202510362887.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-26
- Publication Date
- 2025-07-11
AI Technical Summary
The traditional 1T1MTJ STT-MRAM has a smaller reading window due to temperature and process deviations, and the yield is low. The 1T1MTJ and 2T2MTJ memory cells have different reading and writing methods, which increases the overhead of reading and writing circuits.
A read and write circuit is designed to realize read and write compatibility between 1T1MTJ and 2T2MTJ storage units through bit line selection signals, and a first write driver and a second write driver are used to connect adjacent bit lines, combining the address selection unit and the data selection unit to realize free switching.
Without adding additional circuit overhead, read and write compatibility of 1T1MTJ and 2T2MTJ memory cells is achieved, which improves the read margin and reliability of 2T2MTJ and reduces the cost loss caused by the low yield of 1T1MTJ.
Smart Images
Figure CN120299484A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of circuit technologies, and in particular, to a read / write circuit, a storage circuit, and a memory. Background Art
[0002] 1T1MTJ memory cells and 2T2MTJ memory cells are two typical cell structures in magnetic random access memory (MRAM). 1T1MTJ STT-MRAM realizes information writing through spin current. Its memory cell consists of a MOS transistor, a magnetic tunnel junction (MTJ), and several connection lines, and has the advantages of simple structure, high storage density, and high speed.
[0003] However, due to the deviation caused by temperature and process deviation, the read window of traditional 1T1MTJ STT-MRAM is reduced, ultimately resulting in cost losses due to low yield. Moreover, the read / write methods of 1T1MTJ cells and 2T2MTJ cells are different, and two sets of read / write circuits need to be designed for different cells, which greatly increases the overhead of the read / write circuit. Summary of the Invention
[0004] In view of the above deficiencies in the prior art, the present application provides a read / write circuit, a storage circuit, and a memory to solve the problems existing in the prior art.
[0005] The technical solutions adopted in the embodiments of the present application are as follows:
[0006] In a first aspect, an embodiment of the present application provides a read / write circuit, including: a first write driver, a second write driver, a write circuit, and a read circuit;
[0007] Wherein, a first input end of the write circuit is used to receive a write address signal, a second input end of the write circuit is used to receive data to be written, a third input end of the write circuit is used to receive a bit line selection signal, and a first output end and a second output end of the write circuit are respectively connected to two adjacent bit lines through the first write driver and the second write driver, and are used to write the data to be written into one of the two first storage cells on the two adjacent bit lines, or into both of the two storage cells based on the bit line selection signal; wherein, the two first storage cells are two storage cells corresponding to a first word line selection signal;
[0008] Two data input ends of the read circuit are respectively connected to the two adjacent bit lines, and two address input ends of the read circuit are respectively used to receive a read address signal, so that the read circuit reads data from one of the two second storage cells on the two adjacent bit lines, or from both of the two storage cells based on the read address signal; wherein, the two second storage cells are two storage cells corresponding to a second word line selection signal.
[0009] In one embodiment, the write circuit includes: an address selection unit, a data selection unit, a first write unit, and a second write unit;
[0010] A first input end of the address selection unit is a first input end of the write circuit, and is used for receiving the write address signal. A first output end and a second output end of the address selection unit are respectively connected to a first input end of the first write unit and a first input end of the second write unit;
[0011] A first input end of the data selection unit and a second input end of the first write unit are second input ends of the write circuit, and are used for receiving the data to be written. A second input end of the address selection unit and a second input end of the data selection unit are third input ends of the write circuit. An output end of the data selection unit is connected to a second input end of the second write unit;
[0012] An output end of the first write unit and an output end of the second write unit are respectively a first output end and a second output end of the write circuit.
[0013] In one embodiment, the address selection unit includes: a first NOT gate, a first NAND gate, and a second NAND gate. An input end of the first NOT gate and a first input end of the second NAND gate are first input ends of the address selection unit. An output end of the first NOT gate is connected to a first input end of the first NAND gate. A second input end of the first NAND gate and a second input end of the second NAND gate are second input ends of the address selection unit. An output end of the second NAND gate and an output end of the first NAND gate are a first output end and a second output end of the address selection unit.
[0014] In one embodiment, the data selection unit includes: a second NOT gate, a third NOT gate, a third NAND gate, a fourth NAND gate, and a fifth NAND gate. An input end of the second NOT gate and a first input end of the fourth NAND gate are first input ends of the data selection unit. An output end of the second NOT gate is connected to a first input end of the third NAND gate. An input end of the third NOT gate and a second input end of the fourth NAND gate are second input ends of the data selection unit. An output end of the third NOT gate is connected to a second input end of the third NAND gate. Output ends of the third NAND gate and the fourth NAND gate are respectively connected to two input ends of the fifth NAND gate. An output end of the fifth NAND gate is an output end of the data selection unit.
[0015] In one embodiment, each write unit in the first write unit and the second write unit includes: a NAND gate, a NOT gate, and a buffer connected in series in sequence.
[0016] In one embodiment, the read circuit includes: a cross-coupled amplifier, a latch amplifier, and a read unit. Two first input terminals of the read unit are respectively two data input terminals of the read circuit, and two second input terminals of the read unit are respectively two address input terminals of the read circuit. Two output terminals of the read unit are connected to the cross-coupled amplifier, and the cross-coupled amplifier is further connected to two input terminals of the latch amplifier. An output terminal of the latch amplifier is an output terminal of the read circuit.
[0017] In one embodiment, the read unit includes: a first sub-read unit, a second sub-read unit, and a reference resistor;
[0018] A first input terminal of the first sub-read unit and a first input terminal of the second sub-read unit are respectively two first input terminals of the read unit, and a second input terminal of the first sub-read unit and a second input terminal of the second sub-read unit are respectively two second input terminals of the read unit;
[0019] An output terminal of the first sub-read unit and an output terminal of the second sub-read unit are respectively two output terminals of the read unit;
[0020] The first sub-read unit and the second sub-read unit are grounded through the reference resistor.
[0021] In one embodiment, the first sub-read unit includes: a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor; the second sub-read unit includes: a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor;
[0022] A collector of the first NMOS transistor is a first input terminal of the first sub-read unit, and a base of the first NMOS transistor is a second input terminal of the first sub-read unit; the collector of the first NMOS transistor is connected to an emitter of the second NMOS transistor, and a collector of the second NMOS transistor is an output terminal of the first sub-read unit; the collector of the first NMOS transistor is further grounded through the third NMOS transistor;
[0023] A collector of the fourth NMOS transistor is a first input terminal of the second sub-read unit, and a base of the fourth NMOS transistor is a second input terminal of the second sub-read unit; the collector of the fourth NMOS transistor is connected to an emitter of the fifth NMOS transistor, and a collector of the fifth NMOS transistor is an output terminal of the second sub-read unit; the collector of the fourth NMOS transistor is further grounded through the sixth NMOS transistor;
[0024] Emitters of the first NMOS transistor and the fourth NMOS transistor are grounded through the reference resistor.
[0025] In a second aspect, an embodiment of the present application further provides a storage circuit, including: a storage array composed of M×N storage units, a plurality of input / output interfaces, and multiple groups of read / write circuits, where each read / write circuit in each group of read / write circuits is the read / write circuit described in any of the above embodiments;
[0026] Each input / output interface is connected to multiple bit lines of the storage array, and each input / output interface is connected to a group of read / write circuits.
[0027] In a third aspect, an embodiment of the present application further provides a memory, including: at least one storage circuit.
[0028] The beneficial effects of the present application are as follows: The present application provides a read / write circuit that can achieve read / write compatibility and free switching between 1T1MTJ storage units and 2T2MTJ storage units through a bit line selection signal without increasing additional circuit overhead. Moreover, the 2T2MTJ storage unit has a higher read margin and reliability, so the yield is also higher. For chips that fail the 1T1MTJ test, by using the bit line selection signal to switch the chip's storage array from 1T1MTJ to 2T2MTJ, the cost loss caused by the low yield of 1T1MTJ can be effectively reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of the present application and should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can also be obtained based on these drawings without creative efforts.
[0030] FIG. 1(a) is a schematic structural diagram of a 1T1MTJ storage unit;
[0031] FIG. 1(b) is a schematic structural diagram of a 2T2MTJ storage unit;
[0032] FIG. 1(c) is a schematic structural diagram of a 1T1MTJ read circuit;
[0033] FIG. 1(d) is a schematic structural diagram of a 2T2MTJ read circuit;
[0034] Figure 2 is one of the schematic structural diagrams of the read / write circuit provided by the embodiment of the present application;
[0035] Figure 3 is a schematic diagram of the storage array provided by the present application;
[0036] Figure 4 is the second schematic structural diagram of the read / write circuit provided by the embodiment of the present application;
[0037] Figure 5 Schematic diagram of the write logic circuit provided by an embodiment of the present application;
[0038] Figure 6 Schematic diagram of the write circuit provided by an embodiment of the present application;
[0039] Figure 7 Schematic diagram of 1Mb and 2Mb address conversion provided by an embodiment of the present application;
[0040] Figure 8 Schematic diagram of the read circuit provided by an embodiment of the present application;
[0041] Figure 9 Schematic diagram of the latch amplifier provided by an embodiment of the present application;
[0042] Figures 10(a) and 10(b) are respectively the simulation signal timing diagrams when the sense amplifier works under the selected 2Mb and 1Mb capacities. Detailed implementation manners
[0043] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some, but not all, of the embodiments of the present application.
[0044] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the present application claimed, but merely represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the scope of protection of the present application.
[0045] In the description of the present application, it should be noted that if terms such as "upper", "lower", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of this application is usually placed during use, it is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present application.
[0046] In addition, the terms "first", "second", etc. in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of this application described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.
[0047] In the description of this application, it should also be noted that, unless otherwise clearly specified and defined, the terms "arranged" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection. It can be a direct connection or an indirect connection through an intermediate medium, and it can be the communication inside two elements. For those skilled in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0048] It should be noted that, without conflict, the features in the embodiments of this application can be combined with each other.
[0049] FIG. 1(a) is a schematic structural diagram of a 1T1MTJ memory cell, FIG. 1(b) is a schematic structural diagram of a 2T2MTJ memory cell, FIG. 1(c) is a schematic structural diagram of a 1T1MTJ read circuit, and FIG. 1(d) is a schematic structural diagram of a 2T2MTJ read circuit.
[0050] As shown in FIG. 1(a), a 1T1MTJ memory cell (One Transistor One Magnetic Tunnel Junction) is composed of a MOS transistor and a magnetic tunnel junction (MTJ). The cell has a small area overhead and is suitable for high-density storage. When the MTJ is in the parallel state (low resistance state), the stored value is "0", and when the MTJ is in the anti-parallel state (high resistance state), the stored value is "1".
[0051] Referring to Fig. 1(c), the writing method of 1T1MTJ is as follows: when writing "0", the corresponding word line (WL) is selected, the bit line (BL) is connected to the write driving voltage, and the source line (SL) is grounded; when writing "1", the corresponding WL is selected, BL is grounded, and a high voltage is applied to SL. Among them, Bit-Line (BL), Source-Line (SL), and Word-Line (WL) are three important signal lines used to implement the read and write operations of the memory cell. The Bit-Line is the bit line connecting the memory cell, responsible for transmitting data signals. When performing a read operation, the data value stored in the memory cell is received through the Bit-Line. When performing a write operation, the data to be written is also transmitted to the memory cell through the Bit-Line. The Source-Line is the line connecting the source terminal of the transistor, used to transmit control signals. When performing a read operation, the Source-Line is activated to turn on the transistor, enabling the data on the Bit-Line to flow into the read circuit. When performing a write operation, the Source-Line is activated to control the on / off of the transistor, thereby controlling the write operation.
[0052] Word-Line (WL): The Word-Line is the word line connecting the memory cell, used to select the memory cell to be operated on. When performing a read operation, the Word-Line is activated to turn on a specific memory cell, enabling it to be connected to the Bit-Line. When performing a write operation, the Word-Line is activated to select the memory cell that needs to write data.
[0053] The reading method of 1T1MTJ is as follows: the corresponding WL is selected, BL is connected to the two input terminals of the sensitive amplifier (SA) with a reference resistor, and the BL terminal is clamped at a lower voltage (about a few hundred millivolts) through the clamping transistors NM0 and NM1. Due to the small tunneling magnetoresistance ratio (TMR) between the high-resistance state and the low-resistance state resistances, the read window of the STT-MRAM is very small, the reading speed is slow, and the reliability is low.
[0054] As shown in Fig. 1(b), the 2T2MTJ unit (2-Transistor 2-Magnetic Tunnel Junction unit) is composed of two MOS transistors and two MTJs. This unit has a large area overhead and low density storage. The two forms combined by the two opposite MTJ states correspond to "0" and "1" in logic.
[0055] Referring to FIG. 1(d), the 2T2MTJ writing method is as follows: when writing "0", BL0 and SL1 are connected to the write driving voltage, and BL1 and SL0 are grounded; when writing "1", the opposite operation is performed.
[0056] The 2T2MTJ reading method is as follows: select the corresponding WL, connect BL0 and BL1 to the two input terminals of the sense amplifier, and clamp the BL0 and BL1 terminals at a relatively low voltage (about a few hundred millivolts) through a clamping tube. Since the two MTJs are in opposite states and the resistance difference is large, the reading speed is fast and the reliability is high.
[0057] The existing 1T1MTJ memory cell and 2T2MTJ memory cell have the following disadvantages: the read window of 1T1MTJ STT-MRAM is reduced due to the deviation caused by temperature and process deviation, which ultimately leads to the cost loss caused by low yield. Moreover, the read and write methods of 1T1MTJ cells and 2T2MTJ cells are different, and two sets of read and write circuits need to be designed for different cells, which greatly increases the design overhead of the read and write circuits.
[0058] Therefore, in view of the above problems, the present application provides a read and write circuit, a storage circuit and a memory. The read and write circuit, the storage circuit and the memory provided by the present application will be specifically described by multiple examples in conjunction with the accompanying drawings.
[0059] Figure 2 FIG. [FIGURE NUMBER] is one of the schematic structural diagrams of the read and write circuit provided by the embodiment of the present application. As Figure 2 shown, the read and write circuit includes a first write driver, a second write driver, a write circuit and a read circuit.
[0060] Among them, the first input terminal of the write circuit is used to receive the write address signal A0, the second input terminal of the write circuit is used to receive the data to be written DATA, the third input terminal of the write circuit is used to receive the bit line selection signal OP2M, and the first output terminal DBL_L and the second output terminal DBL_H of the write circuit are respectively connected to two bit lines of any two adjacent first memory cells in the memory array through the first write driver DRIVE_L and the second write driver DRIVE_H, and are used to write the data to be written into one of the two first memory cells on the adjacent two bit lines, or into both memory cells based on the bit line selection signal; among them, the two first memory cells are the two memory cells corresponding to the first word line selection signal (the signal received through the word line WL of the first memory cell), that is, the two first memory cells are the memory cells determined in the memory array through the first word line selection signal.
[0061] Among them, the memory array is as Figure 3 shown, and includes M×N memory cells (only 8 are shown in the figure, and actually there are M rows and N columns of memory cells). As Figure 3As shown, the storage array designs a spin transfer torque magnetoresistive random access memory (STT-MRAM) with optional 1Mb and 2Mb capacities based on two types of cell arrays, 1T1MTJ and 2T2MTJ. Figure 3 The storage array architecture is shown. Among them, 2Mb is implemented based on 1T1MTJ storage cells, and 1Mb is implemented based on 2T2MTJ cells composed of two adjacent 1T1MTJs. For example, M is 512 and N is 1024, that is, there are 512 word lines WL and 1024 bit lines BL in the storage array. When the 1T1MTJ storage cell is selected, the storage array can store 2Mb of data. When the 2T2MTJ storage cell is selected, since the number of MOS transistors and magnetic tunnel junctions MTJ used by the 2T2MTJ storage cell in this case is twice that of the 1T1MTJ storage cell, the storage array can only store 1Mb of data.
[0062] Figure 4 This is the second schematic diagram of the structure of the read-write circuit provided by the embodiment of the present application. Refer to Figure 4 , the two data input terminals of the read circuit ( Figure 4 ports 1 and 2 shown) are respectively connected to two adjacent bit lines, so as to be connected to two adjacent second storage cells; the two address input terminals of the read circuit ( Figure 4 ports 3 and 4 shown) are respectively used to receive read address signals, so that the read circuit reads data from one storage cell or two storage cells among two second storage cells on two adjacent bit lines based on the read address signals; among them, the two second storage cells are two storage cells corresponding to the second word line selection signal (the signal received through the word line WL of the second storage cell), that is, the two second storage cells are storage cells determined in the storage array through the second word line selection signal.
[0063] In summary, the present embodiment provides a read-write circuit, which can realize the read-write compatibility of 1T1MTJ storage cells and 2T2MTJ storage cells and realize free switching without increasing additional circuit overhead through the bit line selection signal. Moreover, the 2T2MTJ storage cell has a higher read margin and reliability, so the yield is also higher. For chips that fail the 1T1MTJ test, by switching the chip storage array from 1T1MTJ to 2T2MTJ using the bit line selection signal, the cost loss caused by the low yield of 1T1MTJ can be effectively reduced.
[0064] In one embodiment, the write circuit includes an address selection unit, a data selection unit, a first write unit, and a second write unit. The first input terminal of the address selection unit is the first input terminal of the write circuit and is used to receive the write address signal A0. The first output terminal and the second output terminal of the address selection unit are respectively connected to the first input terminal of the first write unit and the first input terminal of the second write unit.
[0065] The first input terminal of the data selection unit and the second input terminal of the first writing unit are the second input terminals of the writing circuit, which are used to receive the data to be written DATA. The second input terminal of the address selection unit and the second input terminal of the data selection unit are the third input terminals of the writing circuit, which are used to receive the bit line selection signal OP2M. The output terminal of the data selection unit is connected to the second input terminal of the second writing unit.
[0066] The output terminals of the first writing unit and the second writing unit are respectively the first output terminal and the second output terminal of the writing circuit, which are used to be connected to two adjacent bit lines through the first writing driver and the second writing driver.
[0067] Specifically, as Figure 5 shown, the address selection unit includes a first NOT gate NOT1, a first NAND gate NAND1 and a second NAND gate NAND2. The input terminal of the first NOT gate NOT1 and the first input terminal of the second NAND gate NAND2 are the first input terminals of the address selection unit, which are used to receive the write address signal A0. The output terminal of the first NOT gate NOT1 is connected to the first input terminal of the first NAND gate NAND1. The second input terminal of the first NAND gate NAND1 and the second input terminal of the second NAND gate NAND2 are the second input terminals of the address selection unit, which are used to receive the bit line selection signal OP2M. The output terminal B_L of the second NAND gate NAND2 is the first output terminal of the address selection unit, which is used to be connected to the first input terminal B_L of the first writing unit. The output terminal B_H of the first NAND gate NAND1 is the second output terminal of the address selection unit, which is used to be connected to the first input terminal B_H of the second writing unit. Among them, both the first writing unit and the second writing unit include a NAND gate, a NOT gate and a buffer connected in series in sequence. For example, the first writing unit includes a NAND gate NAND6, a NOT gate NOT4 and a buffer D1, and the second writing unit includes a NAND gate NAND7, a NOT gate NOT5 and a buffer D2.
[0068] The output terminals of the buffer D1 and the buffer D2 are respectively the output terminals of the first writing unit and the second writing unit, that is, the first output terminal and the second output terminal of the writing circuit, and are respectively connected to two adjacent bit lines through the first writing driver and the second writing driver, so as to write the data to be written into one of the two first storage units on the two adjacent bit lines, or into both storage units based on the bit line selection signal.
[0069] Continue to refer to Figure 5, the data selection unit includes: the second NOT gate NOT2, the third NOT gate NOT3, the third NAND gate NAND3, the fourth NAND gate NAND4, and the fifth NAND gate NAND5. The input terminal of the second NOT gate NOT2 and the first input terminal of the fourth NAND gate NAND4 are the first input terminal of the data selection unit, which is used to receive the data to be written DATA. The output terminal of the second NOT gate NOT2 is connected to the first input terminal of the third NAND gate NAND3. The input terminal of the third NOT gate NOT3 and the second input terminal of the fourth NAND gate NAND4 are the second input terminal of the data selection unit, which is used to receive the bit line selection signal OP2M. The output terminal of the third NOT gate NOT3 is connected to the second input terminal of the third NAND gate NAND3. The output terminals of the third NAND gate NAND3 and the fourth NAND gate NAND4 are respectively connected to the two input terminals of the fifth NAND gate NAND5. The output terminal of the fifth NAND gate NAND5 is the output terminal of the data selection unit, which is used to connect to the second input terminal of the second writing unit.
[0070] As Figure 6 shown, the two write driver circuits DRIVE_L and DRIVE_H drive adjacent bit lines respectively. When the memory array is used to store 2Mb of data, the data written in every two adjacent memory cells (MTJ) are independent of each other. However, when it is 1Mb, the states written in every two adjacent MTJs are opposite, that is, one writes "0" and the other writes "1". This design realizes the 1Mb and 2Mb capacity selection and the write circuit function switching in different situations by introducing a bit selection signal OP2M.
[0071] Referring to Figure 5 , when the memory array is used to store 2Mb of data, OP2M is 1, and B_L and B_H are determined by the address A0, corresponding to the high and low bits in two adjacent memory cells respectively. When the memory array is used to store 1Mb of data, OP2M is 0, and at this time S_L and S_H are locked to 1. Finally, DBL_L and DBL_H are two opposite states determined by DATA, thus realizing that for the same memory array, one write circuit can complete the writing of 1Mb or 2Mb of data, saving the circuit cost.
[0072] It should also be noted that according to the different capacities, as Figure 7 shown, the number of address bits of 1Mb is one less than that of 2Mb, and the 1Mb unit is composed of 2Mb units with adjacent addresses. Therefore, the lowest address bit A0 (determining the transition between two adjacent units) corresponding to the 2Mb capacity can be set to "0", and the address bit A1 is used as the lowest address bit when it is 1Mb.
[0073] Among them, the 1Mb cell is composed of 2Mb cells with adjacent addresses (the same A1 and different A0). For example, when it is 2Mb, the adjacent two-bit cell addresses are obtained by the jump of the least significant bit address A0. For example, for the A1 and A0 bits of the lower unit address in the adjacent ones, they are 00, and for the A1 and A0 bits of the higher address in the adjacent ones, they are 01; if the A1 and A0 bits of the lower unit address in the adjacent two cells are 10, the A1 and A0 bits of the higher address in the adjacent ones are 11. Therefore, when it is 1Mb, the address corresponding to the 2T2MTJ cell composed of these two adjacent 1T1MTJ cells can use A1 as the least significant bit address.
[0074] As Figure 8 shown, the read circuit includes a cross-coupled amplifier (i.e., the first-stage amplification in Figure 8 ), a latch amplifier (i.e., the second-stage amplification in Figure 8 ), and a read unit. The two first input terminals of the read unit are respectively the two data input terminals (BL_L, BL_R) of the read circuit, and the two second input terminals of the read unit are respectively the two address input terminals (AX2, AX2B) of the read circuit; the two output terminals of the read unit are connected to the cross-coupled amplifier, and the cross-coupled amplifier is also connected to the two input terminals of the latch amplifier. The output terminal OUT of the latch amplifier is the output terminal of the read circuit.
[0075] Specifically, the read unit includes a first sub-read unit, a second sub-read unit, and a reference resistor R ref . The first input terminals of the first sub-read unit and the second sub-read unit are respectively the two first input terminals of the read unit, and the second input terminals of the first sub-read unit and the second sub-read unit are respectively the two second input terminals of the read unit; the output terminals of the first sub-read unit and the second sub-read unit are respectively the two output terminals of the read unit. The first sub-read unit and the second sub-read unit are grounded through the reference resistor R ref .
[0076] Referring to Figure 8 , the first sub-read unit includes a first NMOS transistor NM2, a second NMOS transistor NM0, and a third NMOS transistor NM4, and the second sub-read unit includes a fourth NMOS transistor NM3, a fifth NMOS transistor NM1, and a sixth NMOS transistor NM5.
[0077] The source of the first NMOS transistor NM2 is the first input terminal of the first sub-read unit, and the gate of the first NMOS transistor NM2 is the second input terminal of the first sub-read unit; the source of the first NMOS transistor NM2 is connected to the drain of the second NMOS transistor NM0, and the source of the second NMOS transistor NM0 is the output terminal of the first sub-read unit; the source of the first NMOS transistor NM2 is also grounded through the third NMOS transistor NM4.
[0078] The source of the fourth NMOS transistor NM3 is the first input terminal of the second sub-read unit, and the gate of the fourth NMOS transistor NM3 is the second input terminal of the second sub-read unit; the source of the fourth NMOS transistor NM3 is connected to the drain of the fifth NMOS transistor NM1, and the source of the fifth NMOS transistor NM1 is the output terminal of the second sub-read unit; the source of the fourth NMOS transistor NM3 is also grounded through the sixth NMOS transistor NM5. The drains of the first NMOS transistor NM2 and the fourth NMOS transistor are also grounded through a reference resistor.
[0079] Refer to Figure 8 and Figure 9 in the read circuit, the PMOS pair tubes PM1 and PM2 that are cross-coupled in the first stage and have an amplifying effect, and Figure 9 the second-stage latch amplifier shown. The signals SAENB and ENLAT are the enable signals of the sense amplifier and the latch amplifier respectively. Among them, the signal lines BL_L and BL_R are respectively connected to the bit lines of two adjacent memory cells. When 2Mb is selected (that is, when the type of the memory cell is 1T1MTJ), the signals AX2 and AX2B are determined by the address position A0. When AX2 is "1", AX2B is "0". At this time, the NM2 tube is turned on, and BL_L is connected to the reference resistor R below ref , the NM3 tube is turned off, and BL_R is connected to one of the bit lines of two adjacent 1T1MTJ cells through the address, so as to read the data stored in the 1T1MTJ memory cell corresponding to this bit line; in another case, when AX2 is "0", AX2B is "1". At this time, the NM3 tube is turned on, and BL_R is connected to the reference resistor R below ref , the NM2 tube is turned off, and BL_L is connected to the other bit line in the adjacent cell through the address, so as to read the data stored in another 1T1MTJ memory cell corresponding to the other bit line. And the on-resistance when NM3 and NM2 are selected and turned on can reduce the influence of the on-resistance of the NMOS transistor in the 1T1MTJ cell on the read window.
[0080] When 1Mb is selected, the signals AX2 and AX2B are both set to "0". At this time, the MOS transistors NM2 and NM3 are turned off at the same time, and BL_L and BL_R are respectively connected to the bit lines of two adjacent cells, that is, the two bit lines in the 2T2MTJ cell, so as to read the data of the 2T2MTJ cell.
[0081] Figures 10(a) and 10(b) are respectively the simulation signal timing diagrams of the sense amplifier when operating at selected 2Mb and 1Mb capacities. Its main operating mode can be divided into three stages: T0 - T1 is the pre - charge stage; T1 - T2 is the stage of strong positive - feedback amplification development; T2 - T3 is the latching stage. Before entering all stages, the sense amplifier is in the initialization state. At this time, the SA enable signal SAENB (active low) and the PCHGB (active low) signal are at high level, the DMWLY signal is pulled high, and the floating charges on the BL are released through the NM4 and NM5 transistors.
[0082] In the pre - charge stage, the SAENB signal and the PCHGB signal are pulled from high level to low level, the PM3 and PM4 transistors are turned on, and SOUTA and SOUTB are charged to the same potential.
[0083] In the amplification development stage, the signal PCHGB is pulled high, and through the clamping voltage VLIM, the BL_L and BL_R points are clamped at the same read voltage V LIM -V thn (V thn is the threshold voltage of the NM4 and NM5 transistors). Due to the different resistances of the two branches, the discharge speeds of the two branches are different, which ultimately leads to a potential difference between SOUTA and SOUTB. And through the positive feedback of the cross - coupled PMOS group, the potential difference between the SOUTA and SOUTB points is rapidly increased.
[0084] Finally, in the latching stage, the enable signal ENLAT of the latch - type amplifier is pulled high, amplifying and latching the difference between SOUTA and SOUTB, and finally reading out the data.
[0085] In summary, the embodiment of the present application provides a read - write circuit with the following advantages:
[0086] 1. By adding a selection signal OP2M, the read - write circuit of the 1T1MTJ cell and the read - write circuit of the 2T2MTJ cell are integrated. Without increasing the additional overhead of the read - write circuit, the free switching between 1Mb and 2Mb capacity STT - MRAM is realized.
[0087] 2. The 1T1MTJ STT - MRAM with high storage density and the 2T2MTJ STT - MRAM with high reliability are realized. For the chips that fail the 1T1MTJ test, by using the selection signal, the storage cells of the chip are switched from 1T1MTJ to the highly reliable 2T2MTJ for use, which can effectively reduce the cost loss caused by the low yield of 1T1MTJ.
[0088] The present application also provides a storage circuit, including as Figure 3A memory array composed of M×N memory cells as shown, multiple input / output interfaces, and multiple groups of read / write circuits. Each read / write circuit in each group of read / write circuits is the read / write circuit provided in any of the above embodiments. Each input / output interface is connected to multiple bit lines of the memory array, and each input / output interface is connected to a group of read / write circuits.
[0089] Among them, M is 512 and N is 1024. That is, the memory array is composed of 512 rows and 1024 columns of memory cells. Each input / output interface can be connected to, for example, 32 bit lines of the memory array. Each input / output interface is connected to a group of read / write circuits. That is, every 32 bit lines are connected to a group of read / write circuits through the same input / output interface.
[0090] This application also provides a memory, including at least one memory circuit. Each memory circuit in this memory can achieve the storage switching of 1Mb or 2Mb of data.
[0091] It should also be noted that in practical applications, the read / write circuits, memory circuits, and memories provided in this application are not limited to the above operations for 1Mb and 2Mb, but can also be applied to the storage and read / write of NMb and 2NMb (where N represents any positive integer). For example, the write / read switching between 2Mb and 4Mb, the write / read switching between 3Mb and 6Mb, and the write / read switching between 4Mb and 8Mb.
[0092] The above is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed in this application should be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.
Claims
1. A read-write circuit, characterized in that, Including: A first write driver, a second write driver, a write circuit, and a read circuit; Wherein, a first input terminal of the write circuit is used for receiving a write address signal, a second input terminal of the write circuit is used for receiving data to be written, a third input terminal of the write circuit is used for receiving a bit line selection signal, and a first output terminal and a second output terminal of the write circuit are respectively connected to two adjacent bit lines through the first write driver and the second write driver, and are used for writing the data to be written into one of two first storage units on the two adjacent bit lines, or into both of the two storage units; wherein, the two first storage units are two storage units corresponding to a first word line selection signal; Two data input terminals of the read circuit are respectively connected to the two adjacent bit lines, and two address input terminals of the read circuit are respectively used for receiving a read address signal, so that the read circuit reads data from one of two second storage units on the two adjacent bit lines, or from both of the two storage units; wherein, the two second storage units are two storage units corresponding to a second word line selection signal.
2. The read-write circuit according to claim 1, wherein The write circuit includes: an address selection unit, a data selection unit, a first write unit, and a second write unit; A first input terminal of the address selection unit is the first input terminal of the write circuit and is used for receiving the write address signal, and a first output terminal and a second output terminal of the address selection unit are respectively connected to a first input terminal of the first write unit and a first input terminal of the second write unit; A first input terminal of the data selection unit and a second input terminal of the first write unit are the second input terminal of the write circuit and are used for receiving the data to be written, a second input terminal of the address selection unit and a second input terminal of the data selection unit are the third input terminal of the write circuit, and an output terminal of the data selection unit is connected to a second input terminal of the second write unit; An output terminal of the first write unit and an output terminal of the second write unit are respectively the first output terminal and the second output terminal of the write circuit.
3. The read / write circuit according to claim 2, wherein The address selection unit includes: a first NOT gate, a first NAND gate, and a second NAND gate; An input terminal of the first NOT gate and a first input terminal of the second NAND gate are the first input terminal of the address selection unit, an output terminal of the first NOT gate is connected to a first input terminal of the first NAND gate, a second input terminal of the first NAND gate and a second input terminal of the second NAND gate are the second input terminal of the address selection unit, and an output terminal of the second NAND gate and an output terminal of the first NAND gate are the first output terminal and the second output terminal of the address selection unit.
4. The read / write circuit according to claim 2, wherein The data selection unit includes: a second NOT gate, a third NOT gate, a third NAND gate, a fourth NAND gate, and a fifth NAND gate; The input terminal of the second NOT gate and the first input terminal of the fourth NAND gate are the first input terminal of the data selection unit. The output terminal of the second NOT gate is connected to the first input terminal of the third NAND gate. The input terminal of the third NOT gate and the second input terminal of the fourth NAND gate are the second input terminal of the data selection unit. The output terminal of the third NOT gate is connected to the second input terminal of the third NAND gate. The output terminals of the third NAND gate and the fourth NAND gate are respectively connected to the two input terminals of the fifth NAND gate. The output terminal of the fifth NAND gate is the output terminal of the data selection unit.
5. The read / write circuit according to claim 2, wherein Each writing unit in the first writing unit and the second writing unit includes: a NAND gate, a NOT gate, and a buffer connected in series in sequence.
6. The read / write circuit according to claim 1, wherein The reading circuit includes: a cross-coupled amplifier, a latch amplifier, and a reading unit; The two first input terminals of the reading unit are respectively the two data input terminals of the reading circuit. The two second input terminals of the reading unit are respectively the two address input terminals of the reading circuit. The two output terminals of the reading unit are connected to the cross-coupled amplifier. The cross-coupled amplifier is further connected to the two input terminals of the latch amplifier. The output terminal of the latch amplifier is the output terminal of the reading circuit.
7. The read-write circuit according to claim 6, characterized in that, The reading unit includes: a first sub-reading unit, a second sub-reading unit, and a reference resistor; The first input terminal of the first sub-reading unit and the first input terminal of the second sub-reading unit are respectively the two first input terminals of the reading unit. The second input terminal of the first sub-reading unit and the second input terminal of the second sub-reading unit are respectively the two second input terminals of the reading unit; The output terminal of the first sub-reading unit and the output terminal of the second sub-reading unit are respectively the two output terminals of the reading unit; The first sub-reading unit and the second sub-reading unit are grounded through the reference resistor.
8. The read-write circuit according to claim 7, characterized in that, The first sub-reading unit includes: a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor; the second sub-reading unit includes: a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; The collector of the first NMOS transistor is the first input terminal of the first sub-reading unit. The base of the first NMOS transistor is the second input terminal of the first sub-reading unit. The collector of the first NMOS transistor is connected to the emitter of the second NMOS transistor. The collector of the second NMOS transistor is the output terminal of the first sub-reading unit. The collector of the first NMOS transistor is also grounded through the third NMOS transistor; The collector of the fourth NMOS transistor is the first input terminal of the second sub-reading unit. The base of the fourth NMOS transistor is the second input terminal of the second sub-reading unit. The collector of the fourth NMOS transistor is connected to the emitter of the fifth NMOS transistor. The collector of the fifth NMOS transistor is the output terminal of the second sub-reading unit. The collector of the fourth NMOS transistor is also grounded through the sixth NMOS transistor; The emitters of the first NMOS transistor and the fourth NMOS transistor are grounded through the reference resistor.
9. A storage circuit, characterized in that, Including: A memory array composed of M×N memory cells, a plurality of input / output interfaces, and multiple groups of read / write circuits, where each read / write circuit in each group of read / write circuits is the read / write circuit described in any one of the above claims 1-8; Each input / output interface is connected to multiple bit lines of the memory array, and each input / output interface is connected to a group of read / write circuits.
10. A memory, characterized in that, Comprising: At least one memory circuit described in claim 9.