Memory module and method of operating the same

Abstract

The invention provides a memory module and a method of operating the same. The memory module includes a plurality of receivers that collectively receive signals. Each of the plurality of receivers includes an amplifier configured to apply a bias filtered voltage through a high pass filter. In an enabled receiver among the plurality of receivers, a filter bias terminal connected to the high pass filter is connected to the bias power supply terminal, and in a disabled receiver among the plurality of receivers, the filter bias terminal is not connected to the bias power supply terminal.

Description

Technical Field

[0001] The present disclosure relates to a memory module and a method of operating the same. Background Art

[0002] Generally, a memory module provided as a low-power mobile memory may be composed of two or more ranks. In other words, in a dual-rank structure, a plurality of semiconductor memory devices mounted on a substrate of the memory module may be classified into two ranks, and the semiconductor memory devices belonging to the same rank may be accessed simultaneously. Ultimately, a rank refers to a unit through which a memory controller may input data to and output data from a semiconductor memory device. As the number of ranks increases, a larger-capacity memory may be configured. Summary of the Invention

[0003] Embodiments provide a memory module with extended bandwidth and a method of operating the same.

[0004] Embodiments provide a memory module with reduced input capacitance and a method of operating the same.

[0005] According to an embodiment, a memory module includes a plurality of receivers that commonly receive a signal. Each of the plurality of receivers includes an amplifier having a corresponding filter, and each amplifier is configured to selectively apply a bias filtering voltage through the corresponding filter. Among the enabled receivers among the plurality of receivers, a filter bias terminal connected to the corresponding filter is selectively connected to a bias power terminal; and among the disabled receivers among the plurality of receivers, a filter bias terminal connected to the corresponding filter is selectively disconnected from the bias power terminal.

[0006] According to an embodiment, a memory module includes: a first rank having a first memory device; a second rank having a second memory device; a power management chip that supplies power to the first rank and the second rank; and a serial presence detect chip that stores module information. Each of the first memory device and the second memory device has at least one receiver, and at least one receiver includes an amplifier that amplifies a differential input signal. When the first rank is enabled, a first filter bias terminal of a first high-pass filter connected to a first amplifier included in the first rank is selectively connected to a bias power terminal. When the second rank is disabled, a second filter bias terminal of a second high-pass filter connected to a second amplifier included in the second rank is selectively not connected to the bias power terminal.

[0007] According to an embodiment, a method of operating a memory module having a plurality of blocks includes: adjusting a resistor or a capacitor of a high-pass filter that receives a differential input signal from a receiver corresponding to each of the plurality of blocks according to a channel environment; and adjusting a bias applied to the high-pass filter. Adjusting the bias includes applying a bias voltage to a filter bias terminal of the high-pass filter included in an enabled block among the plurality of blocks. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram illustrating a structure of a memory system according to an embodiment; Figure 2 is a block diagram illustrating a memory device according to an embodiment; Figure 3 is a block diagram illustrating a concept of a memory module according to an embodiment; Figure 4 is a circuit diagram illustrating an amplifier according to an embodiment by way of example; Figure 5 is a circuit diagram illustrating an amplifier according to an embodiment by way of example; Figure 6A and Figure 6B is a comparative graphical diagram illustrating simulation results of a memory module according to an embodiment by way of example; Figure 7 is a flowchart illustrating an operation of a memory module according to an embodiment by way of example; Figure 8 is a layout diagram illustrating a memory module according to an embodiment; Figure 9 is a layout diagram illustrating a memory system according to an embodiment; and Figure 10 is a layout diagram illustrating an on-die chip according to an embodiment. DETAILED DESCRIPTION

[0009] Hereinafter, illustrative embodiments of the present disclosure will be described by way of example with reference to the accompanying drawings.

[0010] A memory module according to an embodiment of the present disclosure may include an alternating current (AC) coupled booster (ACCB) having variable bandwidth and low input capacitance. The memory module may include an analog amplifier, a high-pass filter (HPF), a switched resistor array, a voltage-controlled capacitor, and a bias on / off controller. The memory module may extend the bandwidth by substantially passing the AC component of a signal through the high-pass filter and then amplifying the passed signal. The memory module may adjust the bandwidth by controlling the biasing of the resistor array and the capacitor. The memory module may mitigate the input capacitance superposition caused by the AC coupling capacitor through bias on / off control.

[0011] In an embodiment, the memory module of the present disclosure may be applied to amplifiers of other topologies in addition to the folded cascode amplifier. In an embodiment, the application point of the high-pass filter need not be limited to the first bias. In an embodiment, the bandwidth may be adjusted by a voltage-controlled capacitor in addition to the resistor array.

[0012] As the big data and artificial intelligence (AI) markets expand, the demand for high-density memories is increasing, leading to the application of topologies such as multi-block and byte mode to maximize the dynamic random access memory (DRAM) capacity. As a result, the signal integrity (SI) characteristics observed in the channel may deteriorate. In particular, systems like the low-power compression additional memory module (LPCAMM) have limitations in increasing the operating frequency due to the channel characteristics caused by heavy loading. Therefore, equalizers and / or circuit techniques for compensating input SI may be applied to the DRAM receiver.

[0013] For example, equalization may be achieved by adding a high-pass filter (HPF) to the differential input terminal to filter only the AC component and applying it to a bias transistor that serves as a current source. The bandwidth may be extended by the complementary operation of the main input transistor and the transistor connected to the current source of the HPF. However, in order to be suitable for various channel environments and input frequencies of a single DRAM chip, it may be necessary to adjust the frequency response characteristics of the HPF. The present disclosure may adjust the frequency response by controlling resistors and capacitors. Therefore, the present disclosure provides a flexible adjustment means.

[0014] Additionally, the capacitor configuring the HPF may act as an input load in a multi-block environment, degrading the SI quality. The present disclosure adds bias control to make the HPF capacitance of other deactivated block DRAMs invisible as an input load.

[0015] The bandwidth of an amplifier can be extended by substantially passing the AC component of an input signal through an HPF connected to the input terminals of two differential amplifiers and then amplifying the passed signal. To be suitable for various channel environments, the resistors and capacitors configuring the HPF can be adjustable. In a memory module, a bias control section can be added to minimize the increase in input capacitance caused by deactivated DRAMs. For example, it can have a bias level for a buffer when activated and a high impedance (Hi-Z) when deactivated.

[0016] Figure 1 The structure of a memory system according to an embodiment is illustrated. Refer to Figure 1 , the memory system 10 may include a memory module 11 and a controller 12.

[0017] The memory system 10 may be implemented to be included in a personal computer (PC) or a mobile device. For example, the mobile device may be implemented as a laptop computer, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device or a portable navigation device (PND), a handheld game console, a mobile Internet device (MID), a wearable computer, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, or a drone, but is not limited thereto.

[0018] The memory module 11 may include a plurality of banks RANK1 to RANKi, where i is an integer of 2 or greater. Each of the plurality of banks RANK1 to RANKi may include a plurality of memory devices MEM1 to MEMj, where j is an integer of 2 or greater. Each of the memory banks RANK1 to RANKi refers to a plurality of memory devices and / or memory chips that receive and respond to commands and / or addresses from the controller 12.

[0019] Each of the memory devices MEM1 to MEMj may include a memory cell array having a plurality of memory cells. In an embodiment, the memory cells may be volatile memory cells. For example, the memory device may be a dynamic random access memory (DRAM), a static random access memory (SRAM), a mobile DRAM, a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power DDR (LPDDR) SDRAM, a graphics DDR (GDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), etc.

[0020] In an embodiment, the storage unit may be a non-volatile storage unit. For example, the storage device may be a non-volatile memory such as an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), etc. Hereinafter, the storage device is described as a DRAM, but it should be understood that the storage device is not limited thereto.

[0021] A bank generally refers to a plurality of storage devices and / or memory chips that all receive and respond to a common command from an associated memory controller and / or control unit. As Figure 1 illustrated, each of the banks RANK1 to RANKi includes a plurality of storage devices MEM1 to MEMj connected in parallel. The storage devices MEM1 to MEMj share a data (DQ) bus, a data strobe (DQS) bus, a command / address (CMD / ADDR) bus, and a clock signal (CLK) line. Discrete devices within a bank may receive dedicated clock enable, chip select, and on-die termination signals.

[0022] Additionally, each of the banks RANK1 to RANKi has an adjustable bandwidth and may be embodied as an amplifier implemented as an AC coupled booster (ACCB) with a low input capacitance. In an embodiment, the amplifier may change the bandwidth of the amplifier by substantially passing the AC component of the input signal through a high-pass filter connected to two input terminals of a differential amplifier. In an embodiment, the amplifier may adjust resistors and capacitors that form the high-pass filter to respond to various channel environments. In an embodiment, the amplifier may control the bias to significantly reduce the increase in input capacitance caused by deactivated storage devices.

[0023] The controller 12 may be implemented to simultaneously send commands to some or all of the memory banks RANK1 to RANKi. The controller 12 may be implemented to perform a write operation for writing data to the memory module 11 or a read operation for reading data stored in the memory module 11. The controller 12 may write data to the memory module 11 or generate commands and addresses for reading data stored in the memory module 11. The controller 12 may be at least one of a chipset for controlling the memory module 11, a system-on-chip such as a mobile application processor (AP), a central processing unit (CPU), a graphics processing unit (GPU), and / or a data processing unit (DPU).

[0024] Memory system 10 according to an embodiment includes a memory module 12 having an amplifier implemented as an AC coupled booster (ACCB), so that the bandwidth can be adjusted and an increase in input capacitance due to deactivated memory devices can be significantly reduced.

[0025] Figure 2 An illustration of a memory device according to an embodiment is provided. Refer to Figure 2 , the memory device 200 may include a memory cell array 210, a row decoder 220, a column decoder 230, a sense amplifier circuit 240, an address register 250, a bank control logic 252, a refresh counter 254, a row address multiplexer 256, a column address latch 258, a control logic circuit 260, a timing control circuit 264, a repair control circuit 266, an input / output gating circuit 270, an error correction circuit 280, and a data input / output buffer 282.

[0026] The memory cell array 210 may include first to eighth bank arrays 211 to 218. In addition, it should be understood that the number of bank arrays constituting the memory cell array 210 is not limited thereto. The first to eighth bank arrays 211 to 218, the first to eighth bank row decoders 221 to 228, the first to eighth bank column decoders 231 to 238, and the first to eighth bank sense amplifiers 241 to 248 may respectively configure the first to eighth banks. Each of the first to eighth bank arrays 211 to 218 may include a plurality of memory cells MC formed between a word line WL and a bit line BL.

[0027] The row decoder 220 may include the first to eighth bank row decoders 221 to 228 respectively connected to the first to eighth bank arrays 211 to 218. In an embodiment, each of the first to eighth bank row decoders 221 to 228 may be configured to perform a repair operation using an address swapping function. In an embodiment, among the first to eighth bank row decoders 221 to 228, the bank row decoder activated by the bank control logic 252 decodes the row address RA output from the row address multiplexer 256, and may activate the word lines corresponding to each row address. For example, the enabled bank row decoder may apply a word line drive voltage to the word lines corresponding to the row address. Additionally, the enabled bank row decoder activates the word lines corresponding to the row address, and at the same time, may activate the redundant word lines corresponding to the spare row address (SRA or "redundant row address") output from the repair control circuit 266.

[0028] The column decoder 230 may include a first bank column decoder 231 to an eighth bank column decoder 238 respectively connected to the first bank array 211 to the eighth bank array 218. In an embodiment, among the first bank column decoder 231 to the eighth bank column decoder 238, the bank column decoder activated by the bank control logic 252 may activate the sense amplification corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the input / output gating circuit 270. Additionally, the enabled bank column decoder may perform a column repair operation in response to the column repair signal CRP output from the repair control circuit 266.

[0029] The sense amplifier circuit 240 may include a first bank sense amplifier 241 to an eighth bank sense amplifier 248 respectively connected to the first bank array 211 to the eighth bank array 218.

[0030] The address register 250 may receive and store the address ADDR having the bank address BANK_ADDR, the row address ROW_ADDR, and the column address COL_ADDR from an external memory controller (such as Figure 1 the memory controller 12 but not limited thereto). The address register 250 provides the received bank address BANK_ADDR to the bank control logic 252, provides the received row address ROW_ADDR to the row address multiplexer 256, and may provide the received column address COL_ADDR to the column address latch 258. In an alternative embodiment, the address register 250 may provide the received column address COL_ADDR to the column decoder 230 when not operating in burst mode.

[0031] The bank control logic 252 may generate bank control signals in response to the bank address BANK_ADDR. In response to some bank control signals, the bank row decoder corresponding to the bank address BANK_ADDR among the first bank row decoder 221 to the eighth bank row decoder 228 may be activated. In response to other bank control signals, the bank column decoder corresponding to the bank address BANK_ADDR among the first bank column decoder 231 to the eighth bank column decoder 238 may be activated.

[0032] The row address multiplexer 256 can receive the row address ROW_ADDR from the address register 250 and the refresh row address REF_ADDR from the refresh counter 254. The row address multiplexer 256 can selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 256 can be applied to the first bank row decoder 221 to the eighth bank row decoder 228, respectively.

[0033] The column address latch 258 can receive the column address COL_ADDR from the address register 250 and temporarily store the received column address COL_ADDR. Additionally, the column address latch 258 can increment the received column address COL_ADDR gradually in burst mode. The column address latch 258 can apply the temporarily stored or gradually incremented column address COL_ADDR to the first bank column decoder 231 to the eighth bank column decoder 238, respectively.

[0034] The control logic circuit 260 can be implemented to control the operation of the memory device 200. For example, the control logic circuit 260 can generate control signals such that the semiconductor memory device 200 performs a write operation or a read operation. The control logic circuit 260 can include a command decoder 261 for decoding a command CMD received from an external memory controller and a mode register 262 for setting the operation mode of the memory device 200. For example, the command decoder 261 can decode a write enable signal / WE, a row address strobe signal / RAS, a column address strobe signal / CAS, a chip select signal / CS, etc., so as to generate an operation control signal corresponding to the command CMD. The generated operation control signals can include an activation signal ACT, a precharge signal PCH, a write signal WR, and a read signal RD, but are not limited thereto.

[0035] The control logic circuit 260 can provide the operation control signals ACT, PCH, WR, and RD to the timing control circuit 264. The timing control circuit 264 can generate a first control signal CTL1 for controlling the voltage level of the control word line WL and a second control signal CTL2 for controlling the voltage level of the control bit line BL in response to the operation control signals ACT, PCH, WR, and RD, and can provide the generated first control signal CTL1 and second control signal CTL2 to the memory cell array 210.

[0036] The repair control circuit 266 may generate a repair control signal based on the fuse information of each word line, the row address ROW_ADDR and the column address COL_ADDR of the address ADDR (or access address), and the repair control signal controls the repair operations of the first cell region and the second cell region of at least one memory bank array. The generated repair control signal may include an alternate row address SRA (or redundant row address) to be provided to the corresponding memory bank row decoder, a column repair signal CRP to be provided to the corresponding memory bank column decoder, a selection signal SEL and an enable signal EN to be provided to the block control circuit associated with the corresponding alternate array block (or redundant array block). The repair control circuit 266 may change the repair unit based on the address ADDR and the fuse information. For example, the repair control circuit 266 may use the address ADDR and the fuse information to change the type and number of repair address bits.

[0037] Each of the plurality of input / output gates of the input / output gating circuit 270 may include input data masking logic, a read data latch for storing data output from the first memory bank array 211 to the eighth memory bank array 218, a write driver for writing data to the first memory bank array 211 to the eighth memory bank array 218, and a circuit for gating the input data and / or the output data.

[0038] The error correction circuit 280 may generate parity bits based on the data bits of the data DQ provided from the data input / output buffer 282 during a write operation, and provide a codeword CW including the data DQ and the parity bits to the input / output gating circuit 270, and the input / output gating circuit 270 may write the codeword CW to the memory cell array 210. Additionally, the error correction circuit 280 may receive the codeword CW read from one memory bank array through the input / output gating circuit 270 during a read operation. The error correction circuit 280 performs error correction code (ECC) decoding on the data DQ using the parity bits included in the read codeword CW. At least one error bit included in the data DQ may be corrected and provided to the data input / output buffer 282.

[0039] The codeword CW to be read from one of the first memory bank array 211 to the eighth memory bank array 218 may be detected by a sense amplifier corresponding to one memory bank array and stored in the read data latch of the input / output gating circuit 270. After the ECC decoding is performed by the error correction circuit 280, the codeword CW stored in the read data latch may be provided to an external memory controller through the data input / output buffer 282. After the ECC decoding is performed in the error correction circuit 280, the data DQ written to one of the first memory bank array 211 to the eighth memory bank array 218 may be written to the one memory bank array through the write driver.

[0040] In a write operation, the data input / output buffer 282 provides data DQ to the error correction circuit 280 based on a clock signal CLK provided from an external memory controller, and in a read operation, the data DQ provided from the error correction circuit 280 can be provided to the external memory controller.

[0041] In addition, in an embodiment of the present disclosure, bias control can be performed in a multi-block system.

[0042] Figure 3 The concept of a memory module 30 according to an embodiment is illustrated. Refer to Figure 3 , the memory module 30 may include a plurality of receivers 31 to 34. In a multi-block system, each of the plurality of receivers 31 to 34 may be included in a corresponding block. Signals may be shared by the plurality of receivers 31 to 34. In Figure 3 , receivers corresponding to four blocks are illustrated for ease of explanation, but it should be understood that the number of blocks in the present disclosure is not limited thereto.

[0043] Each of the plurality of receivers 31 to 34 may include an amplifier AMP. The amplifier AMP may change the bias of the amplification operation depending on whether the receiver RX is enabled. In an embodiment, when the receiver RX is enabled, such as when the corresponding block is selected, the filter bias terminal VB_HPF of the amplifier AMP may receive the voltage of the bias power terminal VB. And when the receiver RX is disabled, such as when the corresponding block is not selected, the filter bias terminal VB_HPF of the amplifier AMP may be in a high impedance state Hi-Z, thereby preventing it from receiving the voltage of the bias power terminal VB.

[0044] Figure 4 An amplifier according to an embodiment is illustrated. Refer to Figure 4 , the amplifier 40 may be implemented as a common-source amplifier, but is not limited thereto. As Figure 4 illustrated, the amplifier 40 may include a current source CS, P-channel metal-oxide-semiconductor (PMOS) transistors PM1 and PM2, N-channel metal-oxide-semiconductor (NMOS) transistors NM1 and NM2, a high-pass filter 41, and a switch SW.

[0045] The current source CS may be connected to a power supply terminal VDD. The current source CS may generate a common current.

[0046] The first PMOS transistor PM1 is connected between the current source CS and the first node N1 and may have a gate that receives a first input signal IN+. The first node (N1) may output a second output signal OUT-.

[0047] The second PMOS transistor PM2 is connected between the current source CS and the second node N2 and may have a gate receiving the second input signal IN-. In this case, the first input signal IN+ and the second input signal IN- are differential signals. The second node N2 may output the first output signal OUT+. In this case, the first output signal OUT+ and the second output signal OUT- are differential signals.

[0048] The first NMOS transistor NM1 is connected between the first node N1 and the ground terminal GND and may have a gate receiving the first filtered voltage. In this case, the first filtered voltage is a voltage obtained by filtering the first input signal IN+ by the high-pass filter 41.

[0049] The second NMOS transistor NM2 is connected between the second node N2 and the ground terminal GND and may have a gate receiving the second filtered voltage. In this case, the second filtered voltage is a voltage obtained by filtering the second input signal IN- by the high-pass filter 41.

[0050] The high-pass filter 41 (HPF) may include a first capacitor C1, a second capacitor C2, a first resistor R1, and a second resistor R2. In this embodiment, each of the first capacitor C1 and the second capacitor C2 may be a variable capacitor. Additionally, each of the first resistor R1 and the second resistor R2 may be a variable resistor.

[0051] The first capacitor C1 may be connected between the first input terminal receiving the first input signal IN+ and the gate of the first NMOS transistor NM1. The second capacitor C2 may be connected between the second input terminal receiving the second input signal IN- and the gate of the second NMOS transistor NM2.

[0052] The first resistor R1 may be connected between the filter bias terminal VB_HPF and the gate of the first NMOS transistor NM1. The second resistor R2 may be connected between the filter bias terminal VB_HPF and the gate of the second NMOS transistor NM2. The switch SW may be connected between the filter bias terminal VB_HPF and the bias power supply terminal VB.

[0053] In an embodiment, when a block is enabled (such as in response to activation of a block enable signal), switch SW is turned on, such that a filter bias terminal VB_HPF and a bias power terminal VB can be electrically connected. Accordingly, the voltage of the bias power terminal VB can be applied to the filter bias terminal VB_HPF. When the block is disabled, switch SW is turned off, such that the filter bias terminal VB_HPF and the bias power terminal VB are resistively disconnected. Accordingly, the filter bias terminal VB_HPF is in a high impedance state Hi-Z. In an embodiment, switch SW can be implemented as a transistor.

[0054] Generally, when multiple DRAM receivers are configured in a multi-block environment, first and second inputs SI may degrade due to capacitors that make up the HPF. The input SI is highly affected by input capacitance. However, the capacitors of the HPF connected multiple times through the multi-block configuration may greatly increase the input capacitance.

[0055] As Figure 3 illustrated, in the multi-block environment of the present disclosure, the bias between an enabled receiver and a disabled receiver can be distinguished. The capacitors of the disabled receiver cut off the analog bias path to create a Hi-Z state and significantly reduce the increase in input capacitance caused by the HPF capacitors. Additionally, through a voltage combination for capacitance adjustment of variable capacitors C1 and C2 used for Figure 4 the increase in input capacitance can be further suppressed.

[0056] As Figure 4 illustrated, a booster of an amplifier according to an embodiment can also be applied to a basic common-source amplifier. Additionally, the booster of the present disclosure can be applied to a bias node different from the first bias node or included in addition to the first bias node. For example, an amplifier according to an embodiment can be implemented as a folded cascode amplifier.

[0057] Figure 5 An amplifier 50 according to an embodiment is illustrated. Referring to Figure 5 , amplifier 50 can be implemented as a folded cascode amplifier. As Figure 5 illustrated, amplifier 50 can include a current source CS, PMOS transistors PT1 to PT4, NMOS transistors NT1 to NT4, a high-pass filter 51, and a switch SW.

[0058] The first PMOS transistor PT1 is connected between the current source CS and the first node ND1 and may have a gate receiving the first input signal IN+. The second PMOS transistor PT2 is connected between the current source CS and the second node ND2 and may have a gate receiving the second input signal IN-. The third PMOS transistor PT3 is connected between the power supply terminal VDD and the second output terminal and may have a gate receiving the first filtered voltage. In this case, the second output terminal may output the second output signal OUT-. Additionally, the first filtered voltage is a voltage obtained by filtering the first input signal IN+ by the high-pass filter 51. The fourth PMOS transistor PT4 is connected between the power supply terminal VDD and the first output terminal and may have a gate receiving the second filtered voltage. In this case, the first output terminal may output the first output signal OUT+. Additionally, the second filtered voltage is a voltage obtained by filtering the second input signal IN- by the high-pass filter 51.

[0059] The first NMOS transistor NT1 may be connected between the first node ND1 and the ground terminal GND and may have a gate connected to the first bias terminal VB1 receiving the first bias voltage. The second NMOS transistor NT2 may be connected between the second node ND2 and the ground terminal GND and may have a gate connected to the first bias terminal VB1 receiving the first bias voltage. The third NMOS transistor NT3 is connected between the second output terminal and the first node ND1 and may have a gate connected to the second bias terminal VB2 receiving the second bias voltage. The fourth NMOS transistor NT4 is connected between the first output terminal and the second node ND2 and may have a gate connected to the second bias terminal VB2 receiving the second bias voltage.

[0060] The high-pass filter (HPF) 51 may include a first capacitor C1, a second capacitor C2, a first resistor R1, and a second resistor R2. In an embodiment, at least one of the first capacitor C1, the second capacitor C2, the first resistor R1, and the second resistor R2 may be variably controlled.

[0061] The switch SW may be connected between the filter bias terminal VB_HPF and the bias power supply terminal VB. In an embodiment, when the block is enabled, the switch SW is turned on so that the filter bias terminal VB_HPF and the bias power supply terminal VB may be electrically connected. Accordingly, the voltage of the bias power supply terminal VB may be applied to the filter bias terminal VB_HPF. In an embodiment, when the block is disabled, the switch SW is turned off so that the filter bias terminal VB_HPF and the bias power supply terminal VB are resistively disconnected. Accordingly, the filter bias terminal VB_HPF is in a high impedance state Hi-Z.

[0062] In addition, inFigure 5 In this case, integrated device technology or the like can be used to connect VB_HPF to the first bias node VB1 and / or the second bias node VB2 at the base of the folded cascode amplifier structure. However, the scope of the amplifier applicable to the present disclosure is not limited to the folded cascode amplifier, and the topology of the amplifier can be extended. From the perspective of the resistors and capacitors that make up the HPF, the bandwidth can be adjusted more flexibly by additionally borrowing a capacitor whose capacitance changes with a voltage change in a structure that adjusts the bandwidth using an existing resistor array.

[0063] Figure 6A and Figure 6B The simulation results of a memory module according to an embodiment are illustrated by way of example, generally indicated by reference numerals 600 and 650, respectively. The simulation results of the effects when applying an AC coupled booster (ACCB) are as follows. As Figure 6A illustrated, compared with when the ACCB is not applied, the swing width of the differential output signal 610 when the ACCB is not applied may be further amplified in the differential output signal 620 when the ACCB is applied. As Figure 6B illustrated, the bandwidth of the signal 660 can be extended by 3 dB to be the same as the bandwidth of the signal 670. The 3 dB bandwidth can be adjusted by adjusting the capacitance via a voltage change, but is not limited thereto.

[0064] Figure 7 The operation of a memory module according to an embodiment is illustrated, generally indicated by reference numeral 70. Referring Figure 7 , the operation of the memory module can be performed as follows: Depending on the channel environment, the resistors and / or capacitors of a high-pass filter (HPF) that receives a differential input signal from a receiver corresponding to each of a plurality of blocks can be adjusted (S110). The bias of the high-pass filter (HPF) can also be adjusted (S120). In this case, a bias voltage can be applied to the filter bias terminal of the high-pass filter included in the enabled blocks among the plurality of blocks. In an embodiment, the bias power terminal and the filter bias terminal can be connected in response to a block enable signal. In an embodiment, the filter bias terminal of the high-pass filter included in the disabled blocks among the plurality of blocks can be disconnected from the bias power terminal and / or placed in a high impedance state. In an embodiment, one of the plurality of blocks can be enabled, and the remaining blocks among the plurality of blocks except the one enabled block can be disabled. In an embodiment, each of the plurality of blocks includes a memory chip, and each of the memory chips can include at least one differential amplifier that amplifies the input signal passing through the high-pass filter.

[0065] In addition, in the present disclosure, a low power compression additional memory module (LPCAMM) can be used.

[0066] Figure 8 illustrates a memory module according to an embodiment. Refer to Figure 8 , the memory module 700 may include a Serial Presence Detect (SPD) integrated circuit or chip 701, a first block 710, a second block 720, and a Power Management Integrated Circuit (PMIC) 730. For each memory block, two memory channels may be included. Each memory channel may include two memory chips (e.g., DRAM) dedicated to storing data. In this case, it should be understood that the number of blocks, the number or type of memory chips are not limited thereto. Additionally, as described above with respect to Figures 1 to 7 , each of the first block 710 and the second block 720 may be implemented as an amplifier having a low input capacitance and an adjustable bandwidth ACCB.

[0067] The SPD chip 701 may include device information of the memory module 700. As an example, the SPD chip 701 may include initial information or device information of the memory module 700, such as module type, module configuration, storage capacity, module type, execution environment, etc.

[0068] When the memory system is started, the memory controller may read device information from the SPD chip 701 of the memory module 700 and identify the memory module 700 based on the read device information. The memory controller may control the memory module 700 based on the device information from the SPD chip 701. The PMIC chip 730 may generate a power voltage based on an input voltage and supply the generated power voltage to the memory chips. The memory chips may operate based on the power voltage.

[0069] In addition, the memory module 700 may further include a Register Clock Driver (RCD) chip. The RCD chip may control the blocks 710 and 720 and the PMIC chip 730 under the control of the memory controller. For example, the RCD chip may receive commands, addresses, clock signals, and control signals from the memory controller via a memory bus, and may perform a buffer function to distribute the received signals to the first memory channel and / or the second memory channel. The memory chips of each memory channel will exchange data with the memory controller in response to the commands, addresses, clock signals, and control signals provided from the RCD chip 780.

[0070] Figure 9 illustrates a memory system according to an embodiment. Refer to Figure 9 , the memory system 3000 may include a memory controller 3100 and a memory module 3200. The memory module 3200 may include multi-layer storage devices 3210 and 3230 each configured with four blocks, but is not limited thereto.

[0071] The memory controller 3100 may perform access operations to write data to the memory module 3200 or read data stored in the memory module 3200. The memory controller 3100 may write data to the memory module 3200 or generate a command CMD and an address ADDR for reading data stored in the memory module 3200. The memory controller 3100 may be a chipset for controlling the memory module 3200, a system-on-chip (SoC) such as a mobile application processor (AP), a CPU, a GPU, a DPU, and / or a neural processing unit (NPU), but is not limited thereto.

[0072] The memory module 3200 may include a plurality of stacked memory devices corresponding to a plurality of ranks (multi-ranks) Rank0, Rank1, Rank2, and Rank3. In this case, each of the multi-ranks Rank0, Rank1, Rank2, and Rank3 may be implemented as having an amplifier with an ACCB as described above in Figures 1 to 7 . In each 2-rank structure, four stacked memory devices 3210 may each share a command / address signal CA and a clock signal CK. The four stacked memory devices 3210 may be connected to the memory controller 3100 in a structure where two ranks each form a channel. For example, a first rank Rank0 and a second rank Rank1 among the memory devices 3210 may be connected by wire bonding to share the command / address signal CA and the clock signal CK. Additionally, a third rank Rank2 and a fourth rank Rank3 may be interconnected by wire bonding to share the command / address signal CA and the clock signal CK. The memory device 3230 may also be connected to the memory controller 3100 in the same rank structure as the memory device 3210 through a PCB 3001, and the PCB 3001 includes signal lines for the command / address signal CA and the clock signal CK.

[0073] In addition, the present disclosure is applicable to a high bandwidth memory (HBM)-processing in memory (PIM) configuration.

[0074] Figure 10 A chip-on-device according to an embodiment is illustrated. Refer to Figure 10, on the device, the chip 4000 may include at least one processing unit (GPU) 4100 and at least one storage device (HBM-PIM) 4200. The processing unit (GPU) 4100 may be a processor for processing data. The storage device (HBM-PIM) 4200 may be implemented to store data and / or process data. The storage device 4200 may include a buffer die and a plurality of PIM-DRAM die layers disposed above the buffer die. Each of the plurality of layers may include DRAM cells and in-memory processors (PIM). In an embodiment, the multiple layers of the stacked structure may be connected to each other through corresponding through-silicon vias (TSV). The buffer die may communicate with the processing unit 4100 and route transmit signals and receive signals between the multiple layers and the processing unit 4100. In addition, the buffer die may queue signals received from the processing unit 4100 or the multiple layers. Additionally, the buffer die may include at least one training block. The buffer die may use the available training blocks to perform training operations on the multiple layers.

[0075] The above-described apparatus may be implemented using hardware components, software components, and / or a combination of hardware components and software components. For example, the described apparatus and elements may be implemented using one or more general-purpose computers or special-purpose computers such as: processors, controllers, arithmetic logic units (ALU), digital signal processors, microcomputers, field programmable gate arrays (FPGA), programmable logic units (PLU), microprocessors, or any other device capable of executing instructions and responding thereto. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. Additionally, the processing device may access, store, manipulate, process, and generate data in response to the execution of software. For ease of understanding, a processing device may be described as being used in some cases, but those of ordinary skill in the relevant art will understand that the processing device may include multiple processing elements or multiple types of processing elements. For example, the processing device may include multiple processors or one processor and one controller. Additionally, other processing configurations, such as parallel processors, may be applied in alternative embodiments.

[0076] The software may include a computer program, code, instructions, or a combination of one or more of them, or an external configuration device may configure the processing device to work as needed or independently or jointly command the processing device. The software and / or data may be embodied in any type of machine, component, physical device, virtual device, computer storage medium, or device to be interpreted by the processing device and / or provide instructions or data to the processing device. The software may be distributed over a networked computer system and may be stored or executed in a distributed manner. The software and data may be stored on one or more non-transitory computer-readable recording media.

[0077] A memory module according to an embodiment may include, in a differential amplifier structure, a high-pass filter (HPF) connected to both ends of an input for high-frequency (HF) boosting, a resistor and / or capacitor (RC) control unit for RC control of a variable resistor or capacitor within the HPF, and a control unit for adjusting a bias applied to the HPF. The present disclosure may be particularly applicable to differential amplifier structures such as a common-source and / or folded cascode structure, rather than a clocked sense amplifier, but is not limited thereto. In an embodiment, the memory module may add a tunable RC application to adjust the peak of the HPF. In an embodiment, the memory module may add a bias control to reduce an increase in input capacitance due to high-pass filtering in a multi-block environment. The memory module according to an embodiment is applicable to DRAM receivers in mobile, discrete, server, and LPCAMM environments, but is not limited thereto.

[0078] A memory module and an operation method thereof according to an embodiment of the present disclosure may extend a bandwidth (BW) of an amplifier by substantially passing an AC component of an input signal through a high-pass filter (HPF) connected to differential input terminals of a differential amplifier and then amplifying the passed signal. The memory module and the operation method may adjust resistors and capacitors configuring the HPF to respond to various channel environments. In a multi-block system, the memory module and the operation method may add a bias control section such as setting a buffer to a bias level when activated and / or setting the buffer to a high impedance state Hi-Z when deactivated to minimize an increase in input capacitance caused by one or more deactivated DRAMs. As set forth above, in the memory module and the method of operating the same according to an embodiment, the bandwidth may be changed by an AC-coupled booster.

[0079] In a memory module and an operation method thereof according to an embodiment, the bandwidth may be extended after substantially passing an AC component of a signal through a high-pass filter.

[0080] In a memory module and an operation method thereof according to an embodiment, the bandwidth may be adjusted by bias control of a resistor array and a capacitor.

[0081] In a memory module and an operation method thereof according to an embodiment, an input capacitance superposition caused by an AC-coupled capacitor may be alleviated by using bias on / off control in a multi-block system.

[0082] Although illustrative embodiments have been shown and described, it will be apparent to those of ordinary skill in the relevant art that modifications and variations can be made without departing from the scope and spirit of the present disclosure as defined by the appended claims.

Claims

1. A memory module, the memory module comprising: a plurality of receivers configured to commonly receive signals, wherein each of the plurality of receivers includes an amplifier having a respective filter, wherein each amplifier is configured to selectively apply a bias filtering voltage through the respective filter, wherein, among the enabled receivers of the plurality of receivers, a filter bias terminal connected to the respective filter is selectively connected to a bias power terminal, and wherein, among the disabled receivers of the plurality of receivers, the filter bias terminal connected to the respective filter is selectively disconnected from the bias power terminal.

2. The memory module according to claim 1, Among them, each amplifier having a switch connected between the bias power terminal and the filter bias terminal, wherein each filter includes a high-pass filter.

3. The memory module according to claim 2, Among them, each of the plurality of receivers corresponding to each of a plurality of blocks having a plurality of storage devices, and wherein each switch connects the bias power terminal and the filter bias terminal in response to a block enable signal activating one of the plurality of blocks.

4. The memory module according to claim 1, wherein, Each amplifier includes a common-source amplifier.

5. The memory module according to claim 4, wherein, Each amplifier includes: a current source connected to a power terminal; a first PMOS transistor connected between the current source and a first node outputting a first differential output signal and having a gate receiving a first differential input signal; a second PMOS transistor connected between the current source and a second node outputting a second differential output signal and having a gate receiving a second differential input signal; a first NMOS transistor connected between the first node and a ground terminal and having a gate receiving a first bias filtering voltage; a second NMOS transistor connected between the second node and the ground terminal and having a gate receiving a second bias filtering voltage; a high-pass filter connected to the filter bias terminal, receiving the first differential input signal and the second differential input signal, and outputting the first bias filtering voltage and the second bias filtering voltage; and a switch that connects the bias power terminal to the filter bias terminal in response to a block enable signal.

6. The memory module according to claim 5, wherein, Each respective filter includes: a first capacitor connected between a first input terminal receiving the first differential input signal and the gate of the first NMOS transistor; a second capacitor connected between a second input terminal receiving the second differential input signal and the gate of the second NMOS transistor; a first resistor connected between the filter bias terminal and the gate of the first NMOS transistor; and A second resistor connected between the filter bias terminal and the gate of the second NMOS transistor.

7. The memory module according to claim 1, wherein, Each amplifier includes a folded cascode amplifier.

8. The memory module according to claim 7, wherein, Each amplifier includes: A current source connected to a power supply terminal; A first PMOS transistor connected between the current source and a first node and having a gate receiving a first differential input signal; A second PMOS transistor connected between the current source and a second node and having a gate receiving a second differential input signal; A third PMOS transistor connected between the power supply terminal and a second output terminal outputting a second differential output signal and having a gate receiving a first bias filter voltage; A fourth PMOS transistor connected between the power supply terminal and a first output terminal outputting a first differential output signal and having a gate receiving a second bias filter voltage; A first NMOS transistor connected between the first node and a ground terminal and having a gate connected to a first bias power supply terminal; A second NMOS transistor connected between the second node and the ground terminal and having a gate connected to the first bias power supply terminal; A third NMOS transistor connected between the second output terminal and the first node and having a gate connected to a second bias power supply terminal; A fourth NMOS transistor connected between the first output terminal and the second node and having a gate connected to the second bias power supply terminal; A high-pass filter connected to the filter bias terminal, receiving the first differential input signal and the second differential input signal, and outputting the first bias filter voltage and the second bias filter voltage; and A switch that connects the bias power supply terminal to the filter bias terminal in response to a block enable signal.

9. The memory module according to claim 8, wherein, The high-pass filter includes: A first capacitor connected between a first input terminal receiving the first differential input signal and the gate of the first NMOS transistor; A second capacitor connected between a second input terminal receiving the second differential input signal and the gate of the second NMOS transistor; A first resistor connected between the filter bias terminal and the gate of the first NMOS transistor; and A second resistor connected between the filter bias terminal and the gate of the second NMOS transistor.

10. The memory module according to claim 9, Among them, Each of the first capacitor and the second capacitor is a variable capacitor, and wherein each of the first resistor and the second resistor is a variable resistor.

11. A memory module, the memory module includes: The first block, the first block having a first storage device; The second block, the second block having a second storage device; A power management chip configured to supply a power supply voltage to the first block and the second block; And A serial presence detection chip configured to store module information, wherein each of the first storage device and the second storage device has at least one receiver, wherein the at least one receiver includes an amplifier that amplifies a differential input signal, wherein when the first block is enabled, a first filter bias terminal of a first high-pass filter connected to a first amplifier included in the first block is selectively connected to a bias power terminal, and wherein when the second block is disabled, a second filter bias terminal of a second high-pass filter connected to a second amplifier included in the second block is selectively not connected to the bias power terminal.

12. The memory module according to claim 11, wherein, A resistor or a capacitor of each of the first high-pass filter and the second high-pass filter is variable.

13. The memory module according to claim 11, wherein, The bias of each of the first high-pass filter and the second high-pass filter is adjustable.

14. The memory module according to claim 11, wherein, The amplifier includes: A current source connected to a power terminal; A first PMOS transistor connected between the current source and a first node that outputs a first differential output signal and having a gate that receives a first differential input signal; A second PMOS transistor connected between the current source and a second node that outputs a second differential output signal and having a gate that receives a second differential input signal; A first NMOS transistor connected between the first node and a ground terminal and having a gate that receives a first bias filter voltage; A second NMOS transistor connected between the second node and the ground terminal and having a gate that receives a second bias filter voltage; A high-pass filter connected to the filter bias terminal, receiving the first differential input signal and the second differential input signal, and outputting the first bias filter voltage and the second bias filter voltage; and A switch that connects the bias power terminal to the filter bias terminal in response to a block enable signal.

15. The memory module according to claim 11, wherein, The amplifier includes: A current source connected to a current source terminal; A first PMOS transistor connected between the current source and a first node and having a gate that receives a first differential input signal; A second PMOS transistor connected between the current source and a second node and having a gate that receives a second differential input signal; A third PMOS transistor connected between the power terminal and a second output terminal that outputs a second differential output signal and having a gate that receives a first bias filter voltage; A fourth PMOS transistor, the fourth PMOS transistor being connected between the power supply terminal and a first output terminal for outputting a first differential output signal and having a gate receiving a second bias filtered voltage; A first NMOS transistor, the first NMOS transistor being connected between the first node and the ground terminal and having a gate connected to a first bias power supply terminal; A second NMOS transistor, the second NMOS transistor being connected between the second node and the ground terminal and having a gate connected to the first bias power supply terminal; A third NMOS transistor, the third NMOS transistor being connected between the second output terminal and the first node and having a gate connected to a second bias power supply terminal; A fourth NMOS transistor, the fourth NMOS transistor being connected between the first output terminal and the second node and having a gate connected to the second bias power supply terminal; A high-pass filter, the high-pass filter being connected to the filter bias terminal, receiving the first differential input signal and the second differential input signal, and outputting the first bias filtered voltage and the second bias filtered voltage; and A switch, the switch connecting the bias power supply terminal to the filter bias terminal in response to a block enable signal.

16. A method of operating a memory module having a plurality of blocks, the method comprising: Adjusting a resistor or a capacitor of a high-pass filter according to a channel environment, the high-pass filter receiving a differential input signal from a receiver corresponding to each of the plurality of blocks; And Adjusting a bias applied to the high-pass filter, wherein adjusting the bias includes applying a bias voltage to a filter bias terminal of the high-pass filter included in an enabled block among the plurality of blocks.

17. The method according to claim 16, wherein, Applying the bias voltage includes connecting a bias power supply terminal to the filter bias terminal in response to a block enable signal.

18. The method according to claim 16, wherein Adjusting the bias further includes disconnecting a filter bias terminal of the high-pass filter included in a disabled block among the plurality of blocks from the bias power supply terminal.

19. The method according to claim 16, the method further comprising: Activating one of the plurality of blocks; And Deactivating blocks other than the one block among the plurality of blocks.

20. The method according to claim 16, Among them, each of the plurality of blocks includes a memory chip, wherein each of the memory chips includes at least one differential amplifier for amplifying an input signal input through the high-pass filter.

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