Memory circuit, memory and method for performing write operation

Abstract

The invention discloses a memory circuit, a memory and a method for performing write operation. The storage circuit comprises a bit line and a source line, wherein at least two storage units are connected between the bit line and the source line; the bit line is provided with a bit line near end and a bit line far end, the source line is provided with a source line near end and a source line far end, and at least three ports of the bit line near end, the bit line far end, the source line near end and the source line far end are connected with a voltage gate for executing write operation on the storage unit. Through the scheme of the embodiment of the invention, relatively large driving voltage drop and gate-induced drain electrode leakage current caused by overlong wiring distance can be prevented, so that the requirement on the driving voltage on the source line / bit line is reduced, the overhead of relatively large layout area caused by the requirement is avoided, meanwhile, more storage units can be integrated, and the storage efficiency is improved. The storage density of the storage circuit is improved.

Description

Technical Field

[0001] This disclosure generally relates to the field of memory technologies. More specifically, this disclosure relates to a storage circuit, a memory, and a method for performing a write operation. Background Art

[0002] With the rapid development of information technology, the memory industry has continuously raised the performance requirements for memories, including higher access speeds, larger storage capacities, and lower power consumptions. Traditional memories (such as SRAMs and DRAMs) have limitations in integration density and non-volatility, and it is difficult to meet the growing storage demands.

[0003] New memories such as resistive random-access memories (RRAMs) have advantages such as non-volatility, high integration density, and low power consumption, and can effectively solve the limitations of the above traditional memories. Therefore, they are widely used in various industries. In order to further improve the performance and reliability of memories, a storage circuit using a 1T1R architecture has emerged. The storage circuit using a 1T1R architecture realizes precise control of each storage unit by integrating a transistor and a non-volatile two-terminal storage part in each storage unit.

[0004] However, in order to achieve a high-density storage structure, the storage circuit using a 1T1R architecture needs to integrate a large number of storage units, which results in a large number of word lines in the storage circuit. The increase in the number of word lines will lead to an increase in the wiring resistance of the source line and / or the bit line and introduce more gate-induced drain leakage (GIDL) currents. Furthermore, a higher requirement is imposed on the driving voltage on the source line / bit line to ensure the smooth execution of the write operation, thereby bringing a large overhead in layout area. If the original driving voltage level needs to be maintained, it will impose certain limitations on the storage density.

[0005] In view of this, there is an urgent need to provide a storage circuit solution to reduce the gate-induced drain leakage current and the driving voltage drop caused by the wiring resistance, so as to achieve a high-density and low-overhead storage circuit. Summary of the Invention

[0006] In order to solve at least one or more of the above-mentioned technical problems, this disclosure proposes a storage circuit solution in multiple aspects.

[0007] In a first aspect, this disclosure provides a storage circuit including: a bit line and a source line, with at least two storage units connected between the bit line and the source line; the bit line has a bit line proximal end and a bit line distal end, the source line has a source line proximal end and a source line distal end, and at least three ports among the bit line proximal end, the bit line distal end, the source line proximal end, and the source line distal end are connected with voltage selectors for performing a write operation on the storage unit.

[0008] In some embodiments, the voltage gater includes at least three of the following: a first programming voltage gater connected to the proximal end of the bit line; a second programming voltage gater connected to the distal end of the bit line; a first erasing voltage gater connected to the proximal end of the source line; and a second erasing voltage gater connected to the distal end of the source line.

[0009] In some embodiments, each of at least two memory cells includes: a gating portion and a non-volatile two-terminal memory portion, the gating portion including: a first end and a second end; wherein, the first end of the gating portion is connected to one of the source line and the bit line, the second end of the gating portion is connected to the first end of the non-volatile two-terminal memory portion, and the second end of the non-volatile two-terminal memory portion is connected to the other of the source line and the bit line.

[0010] In some embodiments, the memory circuit further includes: a word line; the gating portion further includes: a third end, and the third end of the gating portion is connected to the word line.

[0011] In some embodiments, if the voltage gater includes a first programming voltage gater and a second programming voltage gater, the programming voltages gated by the first programming voltage gater and the second programming voltage gater are the same; if the voltage gater includes a first erasing voltage gater and a second erasing voltage gater, the erasing voltages gated by the first erasing voltage gater and the second erasing voltage gater are the same.

[0012] In some embodiments, the first programming voltage gater and the second programming voltage gater are connected to the same voltage source, and / or the first erasing voltage gater and the second erasing voltage gater are connected to the same voltage source.

[0013] In some embodiments, the memory circuit is configured to: if a write operation is performed, control the programming voltage gated by the first programming voltage gater and / or the second programming voltage gater to be not equal to the erasing voltage gated by the first erasing voltage gater and / or the second erasing voltage gater.

[0014] In some embodiments, the memory circuit is configured to: if a write operation is not performed, control the programming voltage gated by the first programming voltage gater and / or the second programming voltage gater to be equal to the erasing voltage gated by the first erasing voltage gater and / or the second erasing voltage gater.

[0015] In some embodiments, the memory circuit is further configured to: if the write operation is a SET operation, control the programming voltage gated by the first programming voltage gater and / or the second programming voltage gater to be greater than the erasing voltage gated by the first erasing voltage gater and / or the second erasing voltage gater; if the write operation is a RESET operation, control the programming voltage gated by the first programming voltage gater and / or the second programming voltage gater to be less than the erasing voltage gated by the first erasing voltage gater and / or the second erasing voltage gater.

[0016] In a second aspect, the present disclosure provides a memory including: a storage circuit as in any one of the first aspect.

[0017] In a third aspect, the present disclosure provides a method for performing a write operation, which is applied to the memory as in the second aspect. The memory further includes a strobe control circuit connected to the storage circuit. The method is executed by the strobe control circuit as follows: reading a write operation instruction; in response to not reading a write operation instruction or reading an invalid write operation instruction, controlling the voltage strobes connected to the bit lines and the voltage strobes connected to the source lines to be strobed to the same voltage; and in response to reading a valid write operation instruction, controlling the voltage strobes connected to the bit lines and the voltage strobes connected to the source lines to be strobed to different voltages.

[0018] In some embodiments, the controlling the voltage strobes connected to the bit lines and the voltage strobes connected to the source lines to be strobed to different voltages in response to reading a valid write operation instruction includes: in response to reading a valid write operation instruction, determining the type of the write operation instruction; in response to the write operation instruction being a SET operation instruction, controlling the voltage strobes connected to the proximal end and / or the distal end of the bit line to be strobed to a first voltage, and controlling the voltage strobes connected to the proximal end and / or the distal end of the source line to be strobed to a second voltage, where the first voltage is greater than the second voltage; and in response to the write operation instruction being a RESET operation instruction, controlling the voltage strobes connected to the proximal end and / or the distal end of the bit line to be strobed to a third voltage, and controlling the voltage strobes connected to the proximal end and / or the distal end of the source line to be strobed to a fourth voltage, where the third voltage is less than the fourth voltage.

[0019] With the storage circuit provided as above, in the embodiments of the present disclosure, by connecting voltage strobes to at least three ports among the proximal end of the bit line, the distal end of the bit line, the proximal end of the source line, and the distal end of the source line respectively, when a write operation is executed, any storage cell between the bit line and the source line can obtain sufficient driving voltage / driving current from a voltage strobe closer to it, so as to ensure that the storage cell is activated and the write operation can be smoothly executed. Compared with the existing storage circuit using a 1T1R architecture, the storage cell farthest from the voltage strobe has a large voltage drop of the driving voltage due to the excessive wiring distance and wiring resistance. In the embodiments of the present disclosure, the wiring distance of the storage cell farthest from the voltage strobe in the storage circuit can be greatly shortened, thereby reducing the wiring resistance and GIDL current, significantly reducing the maximum driving voltage drop existing in the storage circuit, and thus reducing the requirement for the driving voltage on the source line / bit line, so as to meet the market demand for high-density and low-overhead storage circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] By reading the following detailed description with reference to the accompanying drawings, the above and other objects, features, and advantages of the exemplary embodiments of the present disclosure will become readily understandable. In the drawings, several embodiments of the present disclosure are shown in an exemplary rather than restrictive manner, and the same or corresponding reference numerals represent the same or corresponding parts, where:

[0021] Figure 1 A schematic diagram of an existing storage circuit using a 1T1R architecture is shown;

[0022] Figure 2 An exemplary structural diagram of a storage circuit according to some embodiments of the present disclosure is shown;

[0023] Figure 3 Another schematic diagram of an existing storage circuit using a 1T1R architecture is shown;

[0024] Figure 4 An exemplary structural diagram of a storage circuit according to some other embodiments of the present disclosure is shown;

[0025] Figure 5 An exemplary structural diagram of a storage circuit according to still some other embodiments of the present disclosure is shown;

[0026] Figure 6 An exemplary structural diagram of a memory according to some embodiments of the present disclosure is shown;

[0027] Figure 7 An exemplary flowchart of a method for performing a write operation according to some embodiments of the present disclosure is shown;

[0028] Figure 8 An exemplary flowchart of a method for performing a write operation according to some other embodiments of the present disclosure is shown. Detailed Embodiments

[0029] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present disclosure.

[0030] It should be understood that the terms "including" and "comprising" used in the specification and claims of the present disclosure indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0031] It should also be understood that the terms used in this disclosure specification are only for the purpose of describing specific embodiments and are not intended to limit the disclosure. As used in this disclosure specification and the claims, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms. It should be further understood that the term "and / or" used in this disclosure specification and the claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0032] As used in this specification and the claims, the term "if" can be interpreted as "when", "once", "in response to determining", or "in response to detecting" depending on the context. Similarly, the phrase "if determined" or "if [the described condition or event] is detected" can be interpreted as meaning "once determined", "in response to determining", "once [the described condition or event] is detected", or "in response to detecting [the described condition or event]" depending on the context.

[0033] The specific embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0034] Exemplary application scenarios

[0035] New memories such as resistive random access memories (RRAMs) have solved the limitations of traditional memories (such as SRAMs and DRAMs) in terms of integration density and non-volatility due to advantages such as non-volatility, high integration density, and low power consumption. On this basis, in order to further improve the performance and reliability of the memory, some existing storage solutions provide a storage circuit using a 1T1R architecture, which realizes precise control of each storage unit by integrating a transistor and a non-volatile two-terminal storage part in each storage unit.

[0036] Figure 1 A schematic diagram of an existing storage circuit using a 1T1R architecture is shown, as Figure 1 shown, in a storage circuit using a 1T1R architecture, the storage units can be distributed in an array and connected to a source line SL, a bit line BL, and a word line WL. As the number of storage units increases, the number of word lines in the storage circuit also increases accordingly. As Figure 1 shown, as the number of word lines increases, the drive current on the source line / bit line needs to travel a longer distance to reach the storage units at the far end. During the transmission of the drive current, a certain amount of GIDL current is generated at each storage unit, and as the distance of the trace increases, the voltage drop caused by the thermal loss of the trace resistance also increases, which results in a large voltage drop in the drive voltage obtained by the storage units at the far end, and further causes the storage units at the far end to be unable to achieve the same write operation execution effect as the storage units at the proximal end.

[0037] If it is necessary to ensure the smooth execution of the write operation at the remote storage unit, it is required that the low dropout linear regulator (LDO) on the source line / bit line has higher voltage capability and larger current capability, which will result in a large overhead in layout area. If the original low dropout linear regulator is to be maintained, the number of storage units in the storage circuit will be restricted to a certain extent, and there are certain limitations in storage density.

[0038] Exemplary application scenarios

[0039] In view of this, embodiments of the present disclosure provide a storage circuit solution. By connecting voltage selectors to at least three ports among the proximal end of the bit line, the distal end of the bit line, the proximal end of the source line, and the distal end of the source line respectively, it can significantly reduce the routing resistance and GIDL current, greatly reducing the maximum driving voltage drop in the storage circuit, thereby achieving a high-density and low-overhead storage circuit.

[0040] Figure 2 An exemplary structural diagram of the storage circuit according to some embodiments of the present disclosure is shown, as Figure 2 shown, the storage circuit includes: a bit line BL, a source line SL, and at least two storage units Cell, and these storage units are connected between the bit line and the source line.

[0041] Further, among the above at least two storage units, each storage unit includes: a gating part and a non-volatile two-terminal storage part. The gating part includes: a first end and a second end. Among them, the first end of the gating part is connected to one of the source line and the bit line, the second end of the gating part is connected to the first end of the non-volatile two-terminal storage part, and the second end of the non-volatile two-terminal storage part is connected to the other of the source line and the bit line. For example, if the first end of the gating part is connected to the source line, the second end of the non-volatile two-terminal storage part is connected to the bit line; if the first end of the gating part is connected to the bit line, the second end of the non-volatile two-terminal storage part is connected to the source line. Thus, the connection between the storage unit and the bit line and the source line is realized.

[0042] In some embodiments, the non-volatile two-terminal storage part includes but is not limited to: resistive memory, phase change memory, magnetic random access memory, and ferroelectric memory.

[0043] As an example, the gating part can adopt a two-terminal gating part, for example, a selector. At this time, the storage unit adopts a 1S1R structure. After the selector is connected in series with the non-volatile two-terminal storage part, it is connected between the source line and the bit line.

[0044] Further, the storage circuit may further include: a word line WL, and each of the at least two storage units is respectively connected to a bit line, a source line, and a word line. Specifically, each storage unit includes: a gating part and a non-volatile two-terminal storage part. The gating part includes: a first end, a second end, and a third end. Among them, the first end of the gating part is connected to one of the source line and the bit line, the second end of the gating part is connected to the first end of the non-volatile two-terminal storage part, the second end of the non-volatile two-terminal storage part is connected to the other of the source line and the bit line, and the third end of the gating part is connected to the word line. At this time, the gating part is a three-terminal gating part, for example, a transistor.

[0045] As an example, the storage unit adopts a 1T1R structure. At this time, each storage unit includes: a transistor and a non-volatile two-terminal storage part. Among them, the gate of the transistor is connected to the word line, the source of the transistor is connected to the source line, and the drain of the transistor is connected to the bit line via the non-volatile two-terminal storage part, that is, the drain of the transistor is connected to one end of the non-volatile two-terminal storage part, and the other end of the non-volatile two-terminal storage part is connected to the bit line.

[0046] For ease of description, the following embodiments will take the storage unit adopting a 1T1R structure as an example to illustrate the solution of the present disclosure.

[0047] In the embodiments of the present disclosure, the bit line has a bit line proximal end and a bit line distal end. It should be noted that the bit line proximal end and the bit line distal end are the two ends of the bit line. The words "proximal end" and "distal end" are only used to distinguish the two ends of the bit line from each other. Without departing from the scope of the present application, the bit line proximal end may also be referred to as the bit line distal end, and the bit line distal end may also be referred to as the bit line proximal end.

[0048] In the embodiments of the present disclosure, the source line also has a source line proximal end and a source line distal end. Similar to the bit line, the source line proximal end and the source line distal end are the two ends of the source line. Without departing from the scope of the present application, the source line proximal end may also be referred to as the source line distal end, and the source line distal end may also be referred to as the source line proximal end.

[0049] Figure 3 Shows another schematic diagram of an existing storage circuit using a 1T1R architecture, as Figure 3 shown, in the existing storage circuit using a 1T1R architecture, voltage gating devices for providing a driving voltage are only connected to the bit line proximal end and the source line proximal end. This results in that the driving current obtained by the storage units near the bit line distal end and near the source line distal end needs to pass through a relatively long routing distance. For example Figure 3 the storage unit located in the lower right corner of the array in Figure 3 causes a large voltage drop of the driving voltage and a large GIDL current at that place, resulting in

[0050] In the embodiments of the present disclosure, at least three ports among the proximal end of the bit line, the distal end of the bit line, the proximal end of the source line, and the distal end of the source line are connected with voltage selectors for performing a write operation on the storage unit. Specifically, the voltage selector includes at least three of the voltage selectors shown below: a first programming voltage selector connected to the proximal end of the bit line, a second programming voltage selector connected to the distal end of the bit line, a first erasing voltage selector connected to the proximal end of the source line, and a second erasing voltage selector connected to the distal end of the source line. A voltage selector is a device for controlling the selection of voltage signals, and its main function is to select a voltage signal from multiple voltage sources for output. In a storage circuit, a voltage selector is often used to control the driving voltage output to the storage unit. For example, the bit line voltage on the bit line and the source line voltage on the source line are used to achieve precise operation of the storage unit.

[0051] As an example, as Figure 2 shown, voltage selectors are respectively connected to the proximal end of the bit line, the distal end of the bit line, and the proximal end of the source line. At this time, the voltage selector includes a first programming voltage selector, a second programming voltage selector, and a first erasing voltage selector. Among them, the first programming voltage selector is connected to the proximal end of the bit line, the second programming voltage selector is connected to the distal end of the bit line, and the first erasing voltage selector is connected to the proximal end of the source line. This enables the storage units near the proximal end of the bit line to obtain sufficient bit line voltage from the first programming voltage selector and the storage units near the distal end of the bit line to obtain sufficient bit line voltage from the second programming voltage selector when the storage circuit performs a write operation. For this storage circuit, the position with the largest voltage drop due to the trace resistance and the largest GIDL current is the storage unit in the middle of the bit line. Compared with the storage unit near the distal end of the bit line in the existing storage circuit using the 1T1R architecture, its trace resistance can be reduced by at least 1 / 2, and the GIDL current is also reduced.

[0052] In other words, for the existing storage circuit using the 1T1R architecture, its worst state (i.e., the state with the largest driving voltage drop and GIDL current) appears at the distal end of the bit line. In the storage circuit shown in this embodiment, the worst state appears at the middle position of the bit line. Since the trace distance at the middle position of the bit line is less than that at the distal end of the bit line, the trace resistance is reduced, the GIDL current is also reduced, and the voltage drop due to the trace resistance is also reduced. That is to say, even in the worst state, the storage circuit shown in this embodiment can achieve a lower driving voltage drop and GIDL current compared with the existing storage circuit using the 1T1R architecture. Therefore, compared with the existing storage circuit using the 1T1R architecture, when using voltage sources with the same performance, the storage circuit shown in this embodiment can integrate more storage units, thereby achieving a higher storage density without incurring a large overhead for high-density storage requirements.

[0053] As another example, Figure 4 FIG. shows an exemplary structural diagram of a storage circuit according to some other embodiments of the present disclosure, such as Figure 4 shown, voltage selectors are respectively connected to the proximal end of the bit line, the proximal end of the source line, and the distal end of the source line. At this time, the voltage selectors include a first programming voltage selector, a first erasing voltage selector, and a second erasing voltage selector. Among them, the first programming voltage selector is connected to the proximal end of the bit line, the first erasing voltage selector is connected to the proximal end of the source line, and the second erasing voltage selector is connected to the distal end of the source line. This enables the storage circuit to obtain sufficient source line voltage from the first erasing voltage selector for the storage units near the proximal end of the source line and sufficient source line voltage from the second erasing voltage selector for the storage units near the distal end of the source line when performing a write operation. For this storage circuit, the position with the largest voltage drop due to the trace resistance and the largest GIDL current is the storage unit in the middle of the source line. Compared with the storage units near the distal end of the source line in the existing storage circuit using the 1T1R architecture, its trace resistance can be reduced by at least 1 / 2, and the GIDL current is also reduced.

[0054] Similar to Figure 2 the storage circuit shown, Figure 4 in the storage circuit shown, the worst state appears at the middle position of the source line. Since the trace distance at the middle position of the source line is less than that of the distal end of the source line, even in the worst state, the storage circuit shown in this embodiment can achieve a lower driving voltage drop and GIDL current compared with the existing storage circuit using the 1T1R architecture. When using voltage sources with the same performance, the storage circuit shown in this embodiment can achieve low-overhead and high-density storage performance.

[0055] As yet another example, Figure 5 FIG. shows an exemplary structural diagram of a storage circuit according to yet some other embodiments of the present disclosure, such as Figure 5 shown, voltage selectors are connected to the proximal end of the bit line, the distal end of the bit line, the proximal end of the source line, and the distal end of the source line. At this time, the voltage selectors include a first programming voltage selector, a second programming voltage selector, a first erasing voltage selector, and a second erasing voltage selector. Among them, the first programming voltage selector is connected to the proximal end of the bit line, the second programming voltage selector is connected to the distal end of the bit line, the first erasing voltage selector is connected to the proximal end of the source line, and the second erasing voltage selector is connected to the distal end of the source line. This enables the storage circuit to obtain sufficient bit line voltage from the first programming voltage selector for the storage units near the proximal end of the bit line, sufficient bit line voltage from the second programming voltage selector for the storage units near the distal end of the bit line, sufficient source line voltage from the first erasing voltage selector for the storage units near the proximal end of the source line, and sufficient source line voltage from the second erasing voltage selector for the storage units near the distal end of the source line when performing a write operation.

[0056] Similar to Figure 2 and Figure 4 the storage circuit shown, in Figure 5 the storage circuit shown, the worst state appears at the middle position of the bit line and the source line. The worst state can also achieve a lower driving voltage drop and GIDL current compared to the existing storage circuit using the 1T1R architecture. Therefore, in the case of using a voltage source with the same performance, the storage circuit shown in this embodiment can achieve low-overhead and high-density storage performance.

[0057] It should be noted that in a storage cell adopting a 1T1R structure, different types of write operations can be performed by controlling the voltage signals applied to the bit line and the source line. Exemplarily, writing a 1 in the storage cell can be achieved by applying a high-voltage signal to the bit line and a low-voltage signal to the source line. This write operation can be understood as a programming operation or a SET operation. Writing a 0 in the storage cell can be achieved by applying a high-voltage signal to the source line and a low-voltage signal to the bit line. This write operation can be understood as an erase operation or a RESET operation. By applying different levels of voltage to the word line, for example, by gating different voltages through a voltage selector connected to the word line, storage cells at different positions can be selected to perform the SET operation or the RESET operation described above, Figure 5 taking as an example, by applying a high-voltage signal to WL0, the source line and the bit line connected to the storage cells in the first row can be made conductive, which is equivalent to selecting the storage cells in the first row. Then, by gating a high-voltage signal through the first programming voltage selector and a low-voltage signal through the first erase voltage selector, the SET operation can be performed on the storage cells in the first row, or by gating a high-voltage signal through the first erase voltage selector and a low-voltage signal through the first programming voltage selector, the RESET operation can be performed on the storage cells in the first row.

[0058] It should be further noted that in some embodiments, one or more of the first programming voltage selector, the second programming voltage selector, the first erase voltage selector, and the second erase voltage selector can have multiple output terminals, and different output terminals can output different levels of voltage. Still taking Figure 5 as an example, by applying a high-voltage signal to WL0, the storage cells in the first row can be selected. Then, the first programming voltage selector can gate a high-voltage signal at the output terminal connected to the storage cell in the first row and the first column, and gate a low-voltage signal at the output terminal connected to the storage cell in the first row and the second column, so as to perform the SET operation on the storage cell in the first row and the first column and the RESET operation on the storage cell in the first row and the second column.

[0059] Since the purpose of setting the first programming voltage selector and the second programming voltage selector in this embodiment is only to reduce the wiring resistance on the bit line, and they provide the same level of bit line voltage for the same memory cell, therefore, in order to ensure that the write operations performed on the selected memory cell are consistent, when the voltage selector includes the first programming voltage selector and the second programming voltage selector, the programming voltages selected by the first programming voltage selector and the second programming voltage selector can be the same. It should be noted that the programming voltage here can be understood as the driving voltage on the bit line, that is, the bit line voltage.

[0060] Similarly, when the voltage selector includes the first erase voltage selector and the second erase voltage selector, the erase voltages selected by the first erase voltage selector and the second erase voltage selector can also be the same, so as to ensure that the write operations performed on the selected memory cell are consistent.

[0061] Furthermore, the first programming voltage selector and the second programming voltage selector can be connected to the same voltage source to facilitate selecting the same programming voltage. In some embodiments, the first erase voltage selector and the second erase voltage selector can also be connected to the same voltage source to facilitate selecting the same erase voltage.

[0062] In some embodiments, in addition to the write operations including SET operations and RESET operations described in the previous embodiments, the memory circuit may not perform write operations. In the memory circuit shown in this embodiment, the memory circuit can be configured to: if a write operation is performed, control the programming voltage selected by the first programming voltage selector and / or the second programming voltage selector to be not equal to the erase voltage selected by the first erase voltage selector and / or the second erase voltage selector; if no write operation is performed, control the programming voltage selected by the first programming voltage selector and / or the second programming voltage selector to be equal to the erase voltage selected by the first erase voltage selector and / or the second erase voltage selector.

[0063] As an example, if the bit line in the memory circuit is connected to the first programming voltage selector and the second programming voltage selector, and the source line is only connected to the first erase voltage selector or only connected to the second erase voltage selector, then when a write operation is performed, control the programming voltages selected by the first programming voltage selector and the second programming voltage selector to be not equal to the erase voltage selected by the first erase voltage selector or the second erase voltage selector, that is, the voltage signals at the proximal end and the distal end of the bit line are not equal to the voltage signals at the proximal end or the distal end of the source line. Similarly, for the case where no write operation is performed, control the programming voltages selected by the first programming voltage selector and the second programming voltage selector to be equal to the erase voltage selected by the first erase voltage selector or the second erase voltage selector, that is, the voltage signals at the proximal end and the distal end of the bit line are equal to the voltage signals at the proximal end / distal end of the source line.

[0064] As another example, if a first programming voltage selector and a second programming voltage selector are connected to a bit line, and a first erasing voltage selector and a second erasing voltage selector are connected to a source line in a storage circuit, when a write operation is performed, the programming voltage for controlling the selection of any one of the first programming voltage selector and the second programming voltage selector is not equal to the erasing voltage for controlling the selection of any one of the first erasing voltage selector and the second erasing voltage selector, that is, the voltage signal at the proximal end of the bit line is neither equal to the voltage signal at the proximal end of the source line nor equal to the voltage signal at the distal end of the source line, and the voltage signal at the distal end of the bit line is neither equal to the voltage signal at the proximal end of the source line nor equal to the voltage signal at the distal end of the source line. Similarly, for the case where a write operation is not performed, the programming voltage for controlling the selection of the first programming voltage selector and the second programming voltage selector is equal to the erasing voltage for controlling the selection of the first erasing voltage selector and the second erasing voltage selector, that is, the voltage signals at the proximal end of the bit line, the distal end of the bit line, the proximal end of the source line, and the distal end of the source line are all equal.

[0065] As yet another example, if only a first programming voltage selector or only a second programming voltage selector is connected to a bit line, and a first erasing voltage selector and a second erasing voltage selector are connected to a source line in a storage circuit, when a write operation is performed, the programming voltage for controlling the selection of the first programming voltage selector or the second programming voltage selector is not equal to the erasing voltage for controlling the selection of any one of the first erasing voltage selector and the second erasing voltage selector, that is, the voltage signal at the proximal end / distal end of the bit line is neither equal to the voltage signal at the proximal end of the source line nor equal to the voltage signal at the distal end of the source line. Similarly, for the case where a write operation is not performed, the programming voltage for controlling the selection of the first programming voltage selector or the second programming voltage selector is equal to the erasing voltage for controlling the selection of the first erasing voltage selector and the second erasing voltage selector, that is, the voltage signal at the proximal end / distal end of the bit line is equal to both the voltage signal at the proximal end of the source line and the voltage signal at the distal end of the source line.

[0066] According to the content disclosed in the foregoing embodiments, the write operation may include a SET operation and a RESET operation. For different write operations, the storage circuit may be configured such that if the write operation is a SET operation, the programming voltage for controlling the selection of the first programming voltage selector and / or the second programming voltage selector is greater than the erasing voltage for controlling the selection of the first erasing voltage selector and / or the second erasing voltage selector; if the write operation is a RESET operation, the programming voltage for controlling the selection of the first programming voltage selector and / or the second programming voltage selector is less than the erasing voltage for controlling the selection of the first erasing voltage selector and / or the second erasing voltage selector.

[0067] As an example, if a first programming voltage selector and a second programming voltage selector are connected to a bit line in a storage circuit, and the source line is only connected to a first erase voltage selector or only connected to a second erase voltage selector, then when performing a SET operation, which is a write operation, the programming voltage that controls the first programming voltage selector to turn on is greater than the erase voltage that turns on the first erase voltage selector or the second erase voltage selector. At the same time, the programming voltage that controls the second programming voltage selector to turn on is also greater than the erase voltage that turns on the first erase voltage selector or the second erase voltage selector. Similarly, for the case of performing a RESET operation, which is also a write operation, the programming voltage that controls the first programming voltage selector to turn on is less than the erase voltage that turns on the first erase voltage selector or the second erase voltage selector. At the same time, the programming voltage that controls the second programming voltage selector to turn on is also less than the erase voltage that turns on the first erase voltage selector or the second erase voltage selector.

[0068] As another example, if a first programming voltage selector and a second programming voltage selector are connected to a bit line in a storage circuit, and a first erase voltage selector and a second erase voltage selector are connected to the source line, then when performing a SET operation, which is a write operation, the programming voltage that controls the first programming voltage selector to turn on is greater than the erase voltage that turns on the first erase voltage selector, the programming voltage that controls the first programming voltage selector to turn on is greater than the erase voltage that turns on the second erase voltage selector, the programming voltage that controls the second programming voltage selector to turn on is greater than the erase voltage that turns on the first erase voltage selector, and the programming voltage that controls the second programming voltage selector to turn on is greater than the erase voltage that turns on the second erase voltage selector. Similarly, for the case of performing a RESET operation, which is also a write operation, the programming voltage that controls the first programming voltage selector to turn on is less than the erase voltage that turns on the first erase voltage selector, the programming voltage that controls the first programming voltage selector to turn on is less than the erase voltage that turns on the second erase voltage selector, the programming voltage that controls the second programming voltage selector to turn on is less than the erase voltage that turns on the first erase voltage selector, and the programming voltage that controls the second programming voltage selector to turn on is less than the erase voltage that turns on the second erase voltage selector.

[0069] As another example, if only the first programming voltage selector or only the second programming voltage selector is connected to the bit line in the storage circuit, and the source line is connected to the first erasure voltage selector and the second erasure voltage selector, when performing the SET operation, which is a write operation, the programming voltage that controls the first programming voltage selector or the second programming voltage selector to be turned on is greater than the erasure voltage of the first erasure voltage selector being turned on. At the same time, the programming voltage that controls the first programming voltage selector or the second programming voltage selector to be turned on is greater than the erasure voltage of the second erasure voltage selector being turned on. Similarly, for the case of performing the RESET operation, which is a write operation, the programming voltage that controls the first programming voltage selector or the second programming voltage selector to be turned on is less than the erasure voltage of the first erasure voltage selector being turned on. At the same time, the programming voltage that controls the first programming voltage selector or the second programming voltage selector to be turned on is less than the erasure voltage of the second erasure voltage selector being turned on.

[0070] Further, in some embodiments, the programming voltages of the first programming voltage selector and the second programming voltage selector being turned on are the same, and the erasure voltages of the first erasure voltage selector and the second erasure voltage selector being turned on are the same. At this time, if no write operation is performed, the control programming voltage is equal to the erasure voltage; if the SET operation, which is a write operation, is performed, the control programming voltage is greater than the erasure voltage; if the RESET operation, which is a write operation, is performed, the control programming voltage is less than the erasure voltage.

[0071] The following provides a differential voltage data table of the existing solution and the storage circuit solution of the present disclosure embodiment, so as to facilitate those skilled in the art to understand the execution effect of the storage circuit solution shown in the present disclosure.

[0072]

[0073]

[0074] In the above table, the designed differential voltage represents the difference between the bit line voltage provided by the voltage selector on the bit line and the source line voltage provided by the voltage selector on the source line, and the actual differential voltage represents the difference between the actual bit line voltage and the actual source line voltage of the storage unit in the worst state in the storage circuit. The differential voltage between the bit line voltage and the source line voltage must be precisely controlled to ensure that the storage unit can correctly switch between the high resistance state and the low resistance state. If the differential voltage is insufficient, the state switch may not be completed.

[0075] According to the data in the above table, on the premise of not exceeding the maximum operating voltage of the storage circuit, compared with the existing solution, the actual differential voltage achieved by the storage circuit solution of the present disclosure embodiment is closer to the designed differential voltage. Therefore, it is more conducive to the write operations of the storage unit, including the SET operation and the RESET operation.

[0076] Based on the storage circuit provided in any of the foregoing embodiments, some embodiments of the present disclosure further provide a memory, which includes the above storage circuit and performs a write operation by the voltage gating method described in the foregoing embodiments.

[0077] Further, in addition to the storage circuit, other functional circuits may be included in the memory, for example, a gater control circuit. Figure 6 An exemplary structural diagram of the memory according to some embodiments of the present disclosure is shown, as Figure 6 shown, the gater control circuit is connected to the voltage gater in the storage circuit for controlling the voltage gater to select a voltage signal to perform a write operation.

[0078] Figure 7 An exemplary flowchart of method 700 for performing a write operation according to some embodiments of the present disclosure is shown. The above gater control circuit can execute the method as Figure 7 shown, including:

[0079] In step S701, a write operation instruction is read;

[0080] In step S702, in response to not reading a write operation instruction or reading an invalid write operation instruction, the voltage gater connected to the bit line and the voltage gater connected to the source line are gated to the same voltage;

[0081] In step S703, in response to reading a valid write operation instruction, the voltage gater connected to the bit line and the voltage gater connected to the source line are gated to different voltages.

[0082] In the above process, the output end of the gater control circuit can be connected to the voltage gater in the storage circuit. Taking Figure 5 the shown storage circuit as an example, the output end of the gater control circuit can be respectively connected to the first programming voltage gater, the second programming voltage gater, the first erasure voltage gater, and the second erasure voltage gater to send control signals to the above voltage gaters.

[0083] The input terminal of the selector control circuit is used to receive and parse write operation instructions. In one embodiment, when the selector control circuit does not read a write operation instruction or reads an invalid write operation instruction, there is no need to perform a write operation on the storage unit, that is, the resistance state of the storage unit does not need to be switched. To maintain the original resistance state of the storage unit, at this time, the selector control circuit controls the selector to be the same voltage, that is, controls at least three of the voltage selectors connected to the proximal end of the bit line, the distal end of the bit line, the proximal end of the source line, and the distal end of the source line to be selected to the same voltage, so as to prevent the resistance state of the storage unit from changing due to the voltage difference between the bit line voltage and the source line voltage. For example, if the bit line in the storage circuit is connected to a first programming voltage selector and a second programming voltage selector, and the source line is only connected to a first erase voltage selector, then control the first programming voltage selector, the second programming voltage selector, and the first erase voltage selector to be selected to the same voltage. Another example is that if the bit line in the storage circuit is only connected to a first programming voltage selector, and the source line is connected to a first erase voltage selector and a second erase voltage selector, then control the first programming voltage selector, the first erase voltage selector, and the second erase voltage selector to be selected to the same voltage. Another example is that if the bit line in the storage circuit is connected to a first programming voltage selector and a second programming voltage selector, and the source line is connected to a first erase voltage selector and a second erase voltage selector, then control the first programming voltage selector, the second programming voltage selector, the first erase voltage selector, and the second erase voltage selector to be selected to the same voltage. The voltage selection logic corresponding to other voltage selector-port connection methods can be deduced by analogy, and will not be elaborated here.

[0084] In another embodiment, when the selector control circuit reads a valid write operation instruction, at this time, it is necessary to control the voltage selector connected to the proximal end of the bit line and / or the distal end of the bit line to be selected to a different voltage from the voltage selector connected to the proximal end of the source line and / or the distal end of the source line, so as to form a voltage difference between the bit line voltage and the source line voltage, so as to realize the resistance state switching of the storage unit.

[0085] Furthermore, the resistance state switching methods corresponding to different write operation instruction types are different. For example, the SET operation needs to apply a positive voltage between the bit line and the source line to make the storage unit change from a high resistance state to a low resistance state. Conversely, the RESET operation needs to apply a reverse voltage between the bit line and the source line to make the storage unit change from a low resistance state to a high resistance state.

[0086] Figure 8 An exemplary flowchart of a method 800 for performing a write operation according to some other embodiments of the present disclosure is shown. The selector control circuit can execute the method as Figure 8 shown to complete the write operation, including:

[0087] In step S801, read the write operation instruction;

[0088] In step S802, in response to reading a valid write operation instruction, determine the type of the write operation instruction;

[0089] In step S803, in response to the write operation instruction being a SET operation instruction, control the voltage selector connected to the bit line to be gated to a first voltage, and control the voltage selector connected to the source line to be gated to a second voltage;

[0090] In step S804, in response to the write operation instruction being a RESET operation instruction, control the voltage selector connected to the bit line to be gated to a third voltage, and control the voltage selector connected to the source line to be gated to a fourth voltage;

[0091] In step S805, in response to not reading a write operation instruction or reading an invalid write operation instruction, control the voltage selector to be gated to the same voltage.

[0092] Similar to the Figure 7 shown method, during the above process, the output terminal of the selector control circuit can be connected to the voltage selector in the storage circuit, and the input terminal of the selector control circuit is used to receive and parse the write operation instruction. When the selector control circuit reads a valid write operation instruction, the selector control circuit needs to judge the type of the write operation instruction. If the write operation instruction is a SET operation instruction, the voltage gated at the proximal end and / or the distal end of the bit line needs to be greater than the voltage gated by the voltage selector connected to the proximal end and / or the distal end of the source line, that is, the first voltage is greater than the second voltage. If the write operation instruction is a RESET operation instruction, the voltage gated by the voltage selector connected to the proximal end and / or the distal end of the bit line needs to be less than the voltage gated by the voltage selector connected to the proximal end and / or the distal end of the source line, that is, the third voltage is less than the fourth voltage.

[0093] Take Figure 5Taking the shown memory circuit as an example, when the strobe control circuit does not read a write operation instruction or reads an invalid write operation instruction, the strobe control circuit will issue a first control signal to control the first programming voltage strobe, the second programming voltage strobe, the first erase voltage strobe, and the second erase voltage strobe to be strobed to the same voltage. When the strobe control circuit reads a valid write operation instruction, by parsing the write operation instruction, the type of the write operation instruction can be identified. If the write operation instruction is a SET operation instruction, the strobe control circuit issues a second control signal to control the first programming voltage strobe and the second programming voltage strobe to be strobed to a first voltage, and to control the first erase voltage strobe and the second erase voltage strobe to be strobed to a second voltage, where the first voltage is greater than the second voltage, that is, a positive voltage is applied between the bit line and the source line to cause the memory cell to transition from a high-resistance state to a low-resistance state; if the write operation instruction is a RESET operation instruction, the strobe control circuit issues a third control signal to control the first programming voltage strobe and the second programming voltage strobe to be strobed to a third voltage, and to control the first erase voltage strobe and the second erase voltage strobe to be strobed to a fourth voltage, where the third voltage is less than the fourth voltage, that is, a negative voltage is applied between the bit line and the source line to cause the memory cell to transition from a low-resistance state to a high-resistance state.

[0094] In summary, the embodiments of the present disclosure provide a memory circuit, which respectively connects voltage strobes to at least three ports among the proximal end of the bit line, the distal end of the bit line, the proximal end of the source line, and the distal end of the source line, so that when a write operation is executed, any memory cell between the bit line and the source line can obtain sufficient driving voltage from a voltage strobe closer to it, preventing a large voltage drop of the driving voltage and GIDL current caused by too long wiring distance, thereby reducing the requirement for the driving voltage on the source line / bit line, avoiding the large layout area overhead caused thereby, and at the same time, facilitating the integration of more memory cells and improving the storage density of the memory circuit.

[0095] Although multiple embodiments of the present disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many changes, variations, and alternative means may occur to those skilled in the art without departing from the spirit and scope of the present disclosure. It should be understood that various alternatives to the embodiments of the present disclosure described herein may be employed in practicing the present disclosure. The appended claims are intended to define the scope of protection of the present disclosure and thus cover equivalents or alternative means within the scope of these claims.

[0096] The collection and acquisition of various data in this disclosure comply with relevant laws and regulations and are authorized by the data providers. Any organization or individual that needs to obtain external data shall obtain authorization in accordance with the law and ensure data security, and shall not illegally collect, use, process, or transmit unauthorized or unprotected data, nor illegally buy, sell, provide, or disclose unauthorized or unprotected data.

Claims

1. A storage circuit, characterized in that, Comprising: A bit line and a source line, with at least two memory cells connected between the bit line and the source line; The bit line has a bit line proximal end and a bit line distal end, the source line has a source line proximal end and a source line distal end, and at least three of the ports of the bit line proximal end, the bit line distal end, the source line proximal end, and the source line distal end are connected to voltage selectors for performing a write operation on the memory cell.

2. The storage circuit according to claim 1, wherein The voltage selector includes at least three of the following: A first programming voltage selector connected to the bit line proximal end; A second programming voltage selector connected to the bit line distal end; A first erase voltage selector connected to the source line proximal end; A second erase voltage selector connected to the source line distal end.

3. The storage circuit according to claim 1 or 2, characterized in that, Each of the at least two memory cells includes: a selector part and a non-volatile two-terminal memory part, and the selector part includes: a first end and a second end; Wherein, the first end of the selector part is connected to one of the source line and the bit line, the second end of the selector part is connected to the first end of the non-volatile two-terminal memory part, and the second end of the non-volatile two-terminal memory part is connected to the other of the source line and the bit line.

4. The storage circuit according to claim 3, wherein Further comprising: A word line; The selector part further includes: a third end, and the third end of the selector part is connected to the word line.

5. The memory circuit according to claim 2, wherein If the voltage selector includes a first programming voltage selector and a second programming voltage selector, the programming voltages selected by the first programming voltage selector and the second programming voltage selector are the same; If the voltage selector includes a first erase voltage selector and a second erase voltage selector, the erase voltages selected by the first erase voltage selector and the second erase voltage selector are the same.

6. The storage circuit according to claim 5, wherein The first programming voltage selector and the second programming voltage selector are connected to the same voltage source, and / or the first erase voltage selector and the second erase voltage selector are connected to the same voltage source.

7. The storage circuit according to claim 2, characterized in that, The memory circuit is configured to: If a write operation is performed, control the programming voltage selected by the first programming voltage selector and / or the second programming voltage selector to be not equal to the erase voltage selected by the first erase voltage selector and / or the second erase voltage selector.

8. The storage circuit according to claim 2, wherein The memory circuit is configured to: If a write operation is not performed, control the programming voltage selected by the first programming voltage selector and / or the second programming voltage selector to be equal to the erase voltage selected by the first erase voltage selector and / or the second erase voltage selector.

9. The storage circuit according to claim 7, wherein The memory circuit is further configured to: If the write operation is a SET operation, control the programming voltage selected by the first programming voltage selector and / or the second programming voltage selector to be greater than the erase voltage selected by the first erase voltage selector and / or the second erase voltage selector; If the write operation is a RESET operation, control the programming voltage selected by the first programming voltage selector and / or the second programming voltage selector to be less than the erase voltage selected by the first erase voltage selector and / or the second erase voltage selector.

10. A memory, characterized in that, Comprising: The memory circuit according to any one of claims 1-9.

11. A method for performing a write operation, characterized in that, The method is applied to the memory as described in claim 10. The memory further includes a strobe control circuit connected to the storage circuit. The method is executed by the strobe control circuit as follows: Read a write operation instruction; In response to not reading the write operation instruction or reading an invalid write operation instruction, control the voltage strobes connected to the bit lines and the voltage strobes connected to the source lines to be strobed to the same voltage; And In response to reading a valid write operation instruction, control the voltage strobes connected to the bit lines and the voltage strobes connected to the source lines to be strobed to different voltages.

12. The method according to claim 11, wherein Wherein, in response to reading a valid write operation instruction, controlling the voltage strobes connected to the bit lines and the voltage strobes connected to the source lines to be strobed to different voltages includes: In response to reading a valid write operation instruction, determine the type of the write operation instruction; In response to the write operation instruction being a SET operation instruction, control the voltage strobes connected to the proximal end and / or the distal end of the bit line to be strobed to a first voltage, and control the voltage strobes connected to the proximal end and / or the distal end of the source line to be strobed to a second voltage, wherein the first voltage is greater than the second voltage; and In response to the write operation instruction being a RESET operation instruction, control the voltage strobes connected to the proximal end and / or the distal end of the bit line to be strobed to a third voltage, and control the voltage strobes connected to the proximal end and / or the distal end of the source line to be strobed to a fourth voltage, wherein the third voltage is less than the fourth voltage.

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