Radiation-proof reinforcing chip, reinforcing method and satellite-borne baseband board

Abstract

The invention discloses an anti-radiation reinforcing chip, a reinforcing method and a satellite-borne baseband board. The anti-radiation reinforced chip comprises a frequency reduction module which is used for detecting the temperature of the chip and the operation frequency of each core in the chip, and reducing the operation frequency of the cores when the temperature is higher than a first preset temperature and / or the operation frequency is higher than a first preset frequency; and the transmission rate of each interface in the chip is reduced. According to the technical scheme provided by the embodiment of the invention, the anti-radiation reinforcing effect is improved.

Description

Technical Field

[0001] The present invention relates to the field of satellite communication technology, and particularly to an anti-radiation hardened chip, a hardening method and a satellite-borne baseband board. Background Art

[0002] As the main space irradiation environment, charged particle radiation can easily cause the chips in the satellite-borne baseband board to malfunction and cannot work properly. Therefore, in order to ensure the stable operation of the chips in the satellite-borne baseband board, it is necessary to carry out anti-radiation hardening design on the satellite-borne baseband board to ensure the stable operation of the chips in the satellite-borne baseband board.

[0003] The prior art generally achieves the hardening effect by installing a physical shielding cover on the satellite-borne baseband board. This setting method increases the weight and volume of the satellite-borne baseband board and has a poor anti-radiation hardening effect. Summary of the Invention

[0004] The present invention provides an anti-radiation hardened chip, a hardening method and a satellite-borne baseband board to improve the anti-radiation hardening effect.

[0005] According to one aspect of the present invention, an anti-radiation hardened chip is provided, including:

[0006] A frequency reduction module, configured to detect the temperature of the chip and the operating frequencies of each core in the chip, and reduce the operating frequency of the core when the temperature is higher than a first preset temperature, and / or the operating frequency is higher than a first preset frequency; and reduce the transmission rate of each interface in the chip.

[0007] Optionally, the anti-radiation hardened chip further includes:

[0008] A memory error correction module, configured to correct the memory data information in the memory when the memory data information in the memory does not match the memory data information written into the memory;

[0009] A cache error correction module, configured to correct the cache data information in the cache when the cache data information in the cache does not match the cache data information written into the cache.

[0010] Optionally, the memory error correction module includes: an embedded error correction unit and a sideband error correction unit;

[0011] Both the embedded error correction unit and the sideband error correction unit are configured to detect the memory data information in the memory, and correct the memory data information when the memory data information is abnormal;

[0012] Wherein, the embedded error correction unit and the sideband error correction unit are backup to each other.

[0013] Optionally, the radiation-hardened chip further includes:

[0014] A data update module, configured to rewrite the cache data information into the cache when the cache error correction module fails to correct errors.

[0015] Optionally, the radiation-hardened chip further includes: a decision module, configured to detect data information processed by each of the cores. When the data result processed by one core is different from the data results processed by the other cores, and the data results processed by the other cores are the same, the decision module takes the data results processed by the other cores and outputs them.

[0016] Optionally, the core includes: an upstream core and a downstream core;

[0017] The upstream core is configured to process upstream data information. When the upstream data result processed by one upstream core is different from the upstream data results processed by the other upstream cores, and the upstream data results processed by the other upstream cores are the same, the decision module takes the upstream data results processed by the other upstream cores and outputs them;

[0018] The downstream core is configured to process downstream data information. When the downstream data result processed by one downstream core is different from the downstream data results processed by the other downstream cores, and the downstream data results processed by the other downstream cores are the same, the decision module takes the downstream data results processed by the other downstream cores and outputs them.

[0019] Optionally, the radiation-hardened chip further includes: a coprocessing module, configured to detect the running states of all the cores in the radiation-hardened chip in real time;

[0020] When a core fails, the coprocessing module is configured to restart the failed core.

[0021] According to another aspect of the present invention, there is provided a radiation-hardened method, which is applied to the radiation-hardened chip provided in any embodiment of the present invention. The radiation-hardened method includes:

[0022] When the temperature of the chip is higher than a first preset temperature, and / or the operating frequency of any core in the chip is higher than a first preset frequency, the operating frequency of the core and the transmission rate of each interface are reduced by a frequency reduction module;

[0023] The memory error correction module is used to detect the memory data information in the memory, and correct the memory data information when the memory data information is abnormal;

[0024] The cache error correction module detects the cache data information in the cache, and corrects the cache data information when the cache data information is abnormal.

[0025] Optionally, the radiation hardening method further includes:

[0026] The decision module detects in real time the data information processed by each of the cores. When the data result processed by one of the cores is different from the data results processed by the other cores, and the data results processed by the other cores are the same, the data result of the other cores is taken and output.

[0027] The coprocessing module detects in real time the operating states of the cores in the radiation hardening chip; when a core fails, the coprocessing module restarts the failed core.

[0028] According to another aspect of the present invention, there is provided an on-board baseband board, including: the radiation hardening chip provided in any embodiment of the present invention.

[0029] The technical solution provided by the embodiments of the present invention realizes the adjustment of the chip temperature and the operating frequencies of the cores by setting a frequency reduction module, and when the temperature or the operating frequency is relatively high, reduces the operating frequency of the cores and the transmission rates of the interfaces in the chip, so as to reduce the power consumption and the operating temperature of the chip, and further reduce the occurrence probability of the single event effect. The present invention does not need to be equipped with a physical shielding cover and does not add a new structure, and has a good radiation hardening effect.

[0030] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0032] Figure 1 is a schematic structural diagram of a radiation hardening chip provided according to an embodiment of the present invention;

[0033] Figure 2 is a schematic structural diagram of another radiation hardening chip provided according to an embodiment of the present invention;

[0034] Figure 3It is a flowchart of an anti - radiation hardening method provided according to an embodiment of the present invention;

[0035] Figure 4 It is a flowchart of another anti - radiation hardening method provided according to an embodiment of the present invention. Specific embodiments

[0036] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0037] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above - mentioned drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order different from those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non - exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0038] The embodiments of the present invention provide an anti - radiation hardened chip. Figure 1 It is a schematic structural diagram of an anti - radiation hardened chip provided by an embodiment of the present invention. Refer to Figure 1 , the anti - radiation hardened chip includes: a frequency - down module 1, configured to detect the temperature of the chip 10 and the operating frequencies of each core 6 in the chip 10, and when the temperature is higher than a first preset temperature, and / or the operating frequency is higher than a first preset frequency, reduce the operating frequency of the core 6; and reduce the transmission rate of each interface in the chip 10.

[0039] Among them, when the satellite operates in the Earth's orbit, ground - to - space communication can be carried out through the on - board baseband board. Due to the special operating position of the on - board baseband board, manual maintenance cannot be performed. Therefore, ensuring the normal operation of the chip 10 in the on - board baseband board is crucial.

[0040] When the chip 10 in the on-board baseband board is running, it can process various data information through the kernel 6 and transmit the data information through each interface, such as satellite control instructions, remote sensing image data, meteorological observation data, communication user data, etc. The data processing speed of the kernel 6 is proportional to the operating frequency. When the operating frequency is higher, the data processing speed is faster. At the same time, the interface will also have a higher data transmission rate. At this time, the chip 10 will generate more heat due to the large power consumption.

[0041] If the chip is irradiated by a single particle at this time, due to the ionization effect, the high-energy charged particle will cause the chip 10 to generate additional charges, causing the chip 10 to generate more heat, resulting in interference or even failure of its function, and causing the occurrence of single-event effects. Therefore, when the chip 10 is running, it is necessary to control the internal temperature of the chip to reduce the occurrence probability of single-event effects.

[0042] Specifically, the frequency reduction module 1 can detect the internal temperature of the chip 10 and the operating frequency of each kernel 6 in real time, and intervene in the operation of the chip 10 when the temperature exceeds the first preset temperature or the operating frequency of the kernel 6 is higher than the first preset frequency.

[0043] For example, when the temperature inside the chip 10 is higher than the first preset temperature, the frequency reduction module 1 reduces the operating frequency of the kernel 6 and the transmission rate of each interface in the chip 10, so that the power of the chip 10 is reduced, and then the operating temperature of the chip 10 is reduced. At the same time, when the operating frequency of the kernel 6 in the chip 10 is higher than the first preset frequency, the operating temperature of the chip 10 can also be limited by reducing the operating frequency of the kernel 6 and the transmission rate of each interface in the chip 10.

[0044] Exemplarily, the first preset frequency can be 1.7 GHz. When the main frequency of the kernel 6 is higher than 1.7 GHz, it can be reduced to a range less than 1.7 GHz to reduce the operating power of the chip 10. At the same time, the interface standard can be reduced from PCIe (peripheral component interconnect express, high-speed serial computer expansion bus standard) GEN4 to PCIe GEN3 to reduce the transmission rate of the chip interface. Through this setting method, although it will have a certain impact on the performance of the chip 10, it will reduce the occurrence probability of single-event effects.

[0045] The technical solution provided by the embodiments of the present invention realizes the adjustment of the chip temperature and the operating frequency of each core by setting a frequency reduction module. When the temperature or operating frequency is relatively high, the operating frequency of the core is reduced and the transmission rate of each interface in the chip is reduced to reduce the power consumption and operating temperature of the chip, thereby reducing the occurrence probability of single-event effects. The present invention does not require adding a physical shielding cover and does not add a new structure, and has a good anti-radiation hardening effect.

[0046] Continuing to refer to Figure 1 , on the basis of the above embodiments, optionally, the anti-radiation hardened chip further includes: a memory error correction module 2 and a cache error correction module 3. The memory error correction module 2 is used to correct the memory data information in the memory when the memory data information in the memory does not match the memory data information written into the memory. The cache error correction module 3 is used to correct the cache data information in the cache when the cache data information in the cache does not match the cache data information written into the cache.

[0047] Among them, both the memory error correction module 2 and the cache error correction module 3 support the ECC (Error Correcting Code) function, and can detect and correct errors during data transmission and storage.

[0048] The memory error correction module 2 is used to correct the memory data information in the memory. Exemplarily, when the memory writes memory data information, the memory error correction module 2 can encode according to the memory data information in the memory and add additional parity bits. These parity bits are generated according to the content of the memory data information according to certain rules and together with the memory data information form encoded data with error correction ability. When the memory data information written into the memory is inconsistent with the stored parity bits, it indicates that an error has occurred in the memory data information in the memory. At this time, the memory error correction module 2 can confirm the position of the error according to the parity bits and correct the error, thereby restoring the correct memory data information and ensuring the correct transmission of the memory data information.

[0049] The working principle of the cache error correction module 3 is similar to that of the memory error correction module 2. It is used to generate check information when the cache receives data. When the cache data information in the cache does not match the cache data information written into the cache, it indicates that there is an error in the cache data. The cache error correction module 3 can confirm the position of the error according to the parity bits and correct the error, thereby restoring the correct cache data information and ensuring the correct transmission of the cache data information.

[0050] By setting the memory error correction module and the cache error correction module in the embodiments of the present invention, the error correction of data in the memory and the cache is realized, the data abnormality in the chip caused by charged particle radiation is reduced, and the chip has more accurate data output.

[0051] Based on the above embodiments, optionally, the memory error correction module includes: an embedded error correction unit and a sideband error correction unit. Both the embedded error correction unit and the sideband error correction unit are used to detect the memory data information in the memory, and correct the memory data information when the memory data information is abnormal. The embedded error correction unit and the sideband error correction unit are backup to each other.

[0052] Among them, the embedded error correction unit may include Inline ECC (Embedded Error Correction Code). In the embedded error correction unit, the error correction code is transmitted and processed in the same channel as the memory data information. Exemplarily, the embedded error correction unit needs to be connected to 64-bit grains in the memory, and 8-bit error correction codes are serially stored therein, that is, 64-bit memory data information is first stored, and then 8-bit error correction codes are stored. The memory data information and the error correction code are time-division multiplexed and written into the 64-bit grains. Therefore, there will be a loss of bandwidth in actual transmission.

[0053] The sideband error correction unit may include Sideband ECC (Sideband Error Correction Code). In the sideband error correction unit, every 64-bit memory data information corresponds to an additional 8-bit check code, that is, it needs to be connected to 64 + 8-bit grains. Among them, the 64-bit grains store the memory data information, and the 8-bit grains store the check code. The memory data information and the check code are parallelly stored in the memory grains. Therefore, the sideband error correction unit does not lose memory bandwidth and capacity, but will increase certain hardware costs.

[0054] In the embodiment of the present invention, by setting the embedded error correction unit and the sideband error correction unit, the error correction of the memory data information is realized, and the two are backup to each other, with high reliability.

[0055] Continuing to refer to Figure 1 , based on the above embodiments, optionally, the radiation-hardened chip further includes: a data update module 4, configured to re-write the cache data information into the cache when the cache error correction module 3 fails to correct the error.

[0056] Exemplarily, when there is a 1-bit error in the cache data information in the cache, it means that a certain value changes from 1 to 0, or from 0 to 1. For example, the originally stored binary number is "10101010". If a certain bit (such as the 3rd bit) has a 1-bit error, it may become "10001010". The cache error correction module can detect the error and correct "10001010" to "10101010".

[0057] If there is a 2-bit error in the cache data information in the cache, for example, if the originally stored binary number is "10101010" and the data in the 2nd and 3rd bits changes to "11001010", at this time, the cache error correction module may not be able to correct the 2-bit error. To prevent the outflow of incorrect data, the data update module 4 can rewrite the cache data information into the cache, enabling the cache to store the data again.

[0058] In the embodiment of the present invention, when the cache error correction module cannot perform error correction, the data update module can rewrite the cache data information into the cache again, which is equivalent to updating the original data in the cache, avoiding the outflow of incorrect data in the cache, and improving the reliability of the cache data information.

[0059] Continue to refer to Figure 1 , based on the above embodiments, optionally, the radiation-hardened chip further includes: a decision module 5, configured to detect the data information processed by each core 6. When the data result processed by one core 6 is different from the data results processed by other cores 6, and the data results processed by other cores 6 are the same, the data result processed by other cores 6 is selected and output.

[0060] Among them, the decision module 5 can compare the data results processed by each core 6 to determine the differences between the data results processed by each core 6.

[0061] Exemplarily, when the chip 10 has eight cores 6, the eight cores 6 can process the same data information. Therefore, in an ideal state, the data results processed by the eight cores 6 should all be the same. If the data result processed by one core 6 is different from the data results processed by the other seven cores 6, it indicates that there is a fault in that core 6. Therefore, when selecting the data result, the data result processed by the faulty core 6 needs to be excluded.

[0062] Figure 2 is a schematic structural diagram of another radiation-hardened chip provided by the embodiment of the present invention. Combining Figure 1 and Figure 2, based on the above embodiments, optionally, the kernel 6 includes: an uplink kernel 61 and a downlink kernel 62. The uplink kernel 61 is used to process uplink data information. When the uplink data result processed by one uplink kernel 61 is different from the uplink data results processed by other uplink kernels 61, and the uplink data results processed by other uplink kernels 61 are the same, the decision module 5 selects the uplink data results processed by other uplink kernels 61 and outputs them. The downlink kernel 62 is used to process downlink data information. When the downlink data result processed by one downlink kernel 62 is different from the downlink data results processed by other downlink kernels 62, and the downlink data results processed by other downlink kernels 62 are the same, the decision module 5 selects the downlink data results processed by other downlink kernels 62 and outputs them.

[0063] Exemplarily, eight kernels can be provided in the chip 10, including the uplink kernel APE0, the uplink kernel APE1, the uplink kernel APE2, and the uplink kernel APE3; the downlink kernel APE4, the downlink kernel APE5, the downlink kernel APE6, and the downlink kernel APE7. The uplink kernel 61 can be used to process the uplink data information of the uplink beam 8. The uplink beam 8 refers to the electromagnetic beam used when the ground station transmits signals to the on-board baseband board. The ground station uses an antenna array or phased array technology to concentrate the signal energy in a specific direction to form an uplink beam 8 with a certain directivity to achieve communication with the on-board baseband board. The downlink kernel 62 can be used to process the downlink data information of the downlink beam 9. The downlink beam 9 refers to the electromagnetic beam used when the on-board baseband board sends signals to the ground station. The on-board baseband board broadcasts or directionally transmits the processed signals to a specific ground area in the form of a specific downlink beam 9 through its own transmitting antenna.

[0064] Among them, the uplink kernel APE3 and the downlink kernel APE7 can be used as standby kernels. The uplink kernel APE3 can replace the uplink kernel 61 to work when other uplink kernels 61 fail. The downlink kernel APE7 can replace the downlink kernel 62 to work when other downlink kernels 62 fail. By setting up standby kernels, the reliability of the operation of the chip 10 can be improved.

[0065] The uplink kernel APE0, the uplink kernel APE1, and the uplink kernel APE2 can be used to process the same uplink data information. Therefore, in an ideal state, the uplink data results processed by the three uplink kernels 61 should all be the same. If the data result processed by one uplink kernel 61 is different from the uplink data results processed by other uplink kernels 61, for example, the uplink data result processed by the uplink kernel APE0 is different from the uplink data results processed by the uplink kernel APE1 and the uplink kernel APE2, it means that the uplink kernel APE0 has a fault. Therefore, when selecting the data result, the data result processed by the uplink kernel APE0 needs to be excluded.

[0066] Similarly, the downlink kernels APE4, APE5, and APE6 can be used to process the same downlink data information. Therefore, in an ideal state, the downlink data results processed by the three downlink kernels 62 should all be the same. If the data result processed by one of the downlink kernels 62 is different from the downlink data results processed by the other downlink kernels 62, for example, the downlink data result processed by the downlink kernel APE4 is different from the downlink data results processed by the downlink kernels APE5 and APE6, it indicates that the downlink kernel APE4 has a fault. Therefore, when selecting the data result, it is necessary to exclude the data result processed by the faulty downlink kernel APE4.

[0067] In the embodiment of the present invention, by setting up the decision module, the detection of the data processed by the uplink kernel and the downlink kernel is realized, and when the data is abnormal, the data result processed by the faulty kernel is excluded, thereby avoiding the outflow of incorrect data and improving the reliability of data transmission.

[0068] Continuing to refer to Figure 1 , based on the above embodiments, optionally, the radiation-hardened chip further includes: a coprocessing module 7, configured to detect the operating status of each kernel in the radiation-hardened chip in real time. When the kernel 6 fails, the coprocessing module 7 is configured to restart the faulty kernel 6.

[0069] Among them, the coprocessing module 7 can be an SPU (System Processing Unit), which is used to monitor and detect the operating status of each kernel 6 in the chip 10. For example, when a certain kernel 6 fails, the SPU can detect the faulty kernel 6 and restart the faulty kernel 6 so that it can restore its original capabilities.

[0070] The embodiment of the present invention also provides a radiation-hardening method, which is applied to the radiation-hardened chip provided in any embodiment of the present invention. Figure 3 It is a flowchart of a radiation-hardening method provided by an embodiment of the present invention. Referring to Figure 3 , the radiation-hardening method includes:

[0071] S110, when the temperature of the chip is higher than the first preset temperature, and / or the operating frequency of any kernel in the chip is higher than the first preset frequency, reduce the operating frequency of the kernel and the transmission rate of each interface through the frequency reduction module.

[0072] Among them, when the operating frequency of the chip core is relatively high, the amount of data information it processes will also increase, causing the transmission rates of each interface to increase accordingly. At this time, the chip will generate more heat due to the high power. If the temperature cannot be controlled in a timely manner, when the chip is irradiated by single particles, the chip will further heat up, resulting in interference or even failure of its functions, causing the occurrence of single-event effects.

[0073] Therefore, when the temperature of the chip is too high or the operating frequency of the chip core is relatively high, the operating frequency of the core and the transmission rates of each interface can be reduced through a frequency reduction module, so as to reduce the power of the chip and further reduce the operating temperature of the chip.

[0074] S120. Detect the memory data information in the memory through a memory error correction module, and correct the memory data information when the memory data information is abnormal.

[0075] Among them, during the operation of the chip, due to being irradiated by single particles in space, the data in the memory may be incorrect. Therefore, the memory error correction module can detect the memory data information in the memory and the memory data information written into the memory in real time. If the two do not match, the memory data information in the memory is corrected to keep the memory data information in the memory at the correct value.

[0076] S130. Detect the cache data information in the cache through a cache error correction module, and correct the cache data information when the cache data information is abnormal.

[0077] Among them, the cache error correction module can be used to generate check information when the cache receives data. When the cache data information in the cache does not match the cache data information written into the cache, it indicates that there is an error in the data in the cache. The cache error correction module can confirm the location of the error according to the check bits and correct the error, and then restore the correct cache data information, thereby ensuring the correct transmission of the cache data information.

[0078] The technical solution provided by the embodiments of the present invention detects the temperature of the chip and the operating frequency of the core, and reduces the occurrence of single-event effects by reducing the operating frequency of the core and the transmission rates of each interface. The present invention also detects the memory data information and the cache data information, realizes the error correction of the data in the memory and the cache, thereby ensuring the correct transmission of the memory data information and the cache data information, and has high reliability.

[0079] Figure 4 It is a flowchart of an anti-radiation hardening method provided by an embodiment of the present invention. Refer to Figure 4 , on the basis of the above embodiments, optionally, the anti-radiation hardening method further includes:

[0080] S210. Detect the data information processed by each core in real time through the judgment module. When the data result processed by one core is different from the data results processed by other cores, and the data results processed by other cores are the same, take the data results processed by other cores and output them.

[0081] Among them, when each core in the chip processes the same data information, the data results processed by each core should all be the same. If the data result processed by one core is different from the data results processed by other cores, it means that this core has a fault. Therefore, when outputting the data results, it is necessary to exclude the data results processed by the faulty core.

[0082] S220. Detect the running states of each core in the radiation-hardened chip in real time through the coprocessing module; when a core fails, restart the faulty core through the coprocessing module.

[0083] Among them, the coprocessing module can monitor and detect the running states of each core in the chip. If a certain core fails, the coprocessing module can detect the faulty core and restart the faulty core so that the core can restore its original capabilities and continue to process data.

[0084] In the embodiment of the present invention, through the detection of the data information processed by each core, faulty cores and their processed data results can be screened out, thus ensuring the accuracy of the data. And through the detection of the running states of each core, the restoration of the functions of faulty cores is realized, and the reliability of the chip operation is improved.

[0085] The embodiment of the present invention also provides a spaceborne baseband board. The spaceborne baseband board includes: the radiation-hardened chip provided in any embodiment of the present invention, which has beneficial effects similar to those of the radiation-hardened chip provided in any of the above embodiments, and will not be elaborated here.

[0086] It should be understood that various forms of the processes shown above can be used, reordering, adding or deleting steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and no limitation is made herein.

[0087] The above specific embodiments do not constitute a limitation to the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. An anti-radiation hardened chip, characterized in that, Comprising: A frequency reduction module, configured to detect the temperature of the chip and the operating frequencies of each core in the chip, and when the temperature is higher than a first preset temperature, and / or the operating frequency is higher than a first preset frequency, reduce the operating frequency of the core; and reduce the transmission rate of each interface in the chip.

2. The radiation-hardened chip according to claim 1, wherein Further comprising: A memory error correction module, configured to correct the memory data information in the memory when the memory data information in the memory does not match the memory data information written into the memory; A cache error correction module, configured to correct the cache data information in the cache when the cache data information in the cache does not match the cache data information written into the cache.

3. The anti-radiation hardened chip according to claim 2, wherein The memory error correction module includes: an embedded error correction unit and a sideband error correction unit; Both the embedded error correction unit and the sideband error correction unit are configured to detect the memory data information in the memory, and when the memory data information is abnormal, correct the memory data information; Wherein, the embedded error correction unit and the sideband error correction unit are backup to each other.

4. The anti-radiation hardened chip according to claim 2, characterized in that, The radiation-hardened chip further includes: A data update module, configured to rewrite the cache data information into the cache when the cache error correction module fails to correct the error.

5. The radiation-hardened chip according to claim 1, wherein The radiation-hardened chip further includes: a decision module, configured to detect the data information processed by each core, and when the data result processed by one core is different from the data results processed by other cores, and the data results processed by other cores are the same, take the data results processed by other cores and output them.

6. The anti-radiation hardened chip according to claim 5, wherein The core includes: an upstream core and a downstream core; The upstream core is configured to process upstream data information. When the upstream data result processed by one upstream core is different from the upstream data results processed by other upstream cores, and the upstream data results processed by other upstream cores are the same, the decision module takes the upstream data results processed by other upstream cores and outputs them; The downstream core is configured to process downstream data information. When the downstream data result processed by one downstream core is different from the downstream data results processed by other downstream cores, and the downstream data results processed by other downstream cores are the same, the decision module takes the downstream data results processed by other downstream cores and outputs them.

7. The radiation-hardened chip according to claim 1, wherein The radiation-hardened chip further includes: a coprocessing module, configured to detect the operating states of each core in the radiation-hardened chip in real time; When a core fails, the coprocessing module is configured to restart the failed core.

8. A radiation-hardening method, characterized in that, Applied to the radiation-hardened chip according to any one of claims 1-7, the radiation-hardened method includes: When the temperature of the chip is higher than a first preset temperature, and / or the operating frequency of any core in the chip is higher than a first preset frequency, reduce the operating frequency of the core and the transmission rate of each interface through the frequency reduction module; Detect the memory data information in the memory through the memory error correction module, and correct the memory data information when the memory data information is abnormal; The cache error correction module detects the cache data information in the cache, and corrects the cache data information when the cache data information is abnormal.

9. The anti-radiation hardening method according to claim 8, characterized in that It further includes: The decision module detects the data information processed by each of the cores in real time. When the data result processed by one of the cores is different from the data results processed by the other cores, and the data results processed by the other cores are the same, the data result processed by the other cores is taken and output. The coprocessing module detects the operating states of the cores in the radiation-hardened chip in real time; when a core fails, the coprocessing module restarts the faulty core.

10. A spaceborne baseband board, characterized in that, It includes: The radiation-hardened chip according to any one of claims 1-7.

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