OLT (Optical Line Terminal) equipment test system and method based on FPGA (Field Programmable Gate Array) and computer medium

Abstract

The invention discloses an OLT (Optical Line Terminal) equipment testing system and testing method based on an FPGA (Field Programmable Gate Array) and a computer medium, which are used for testing OLT equipment to be tested, the system comprises a plurality of optical modules, one end of each optical module is connected with the OLT equipment to be tested through an optical splitter, the other end of each optical module is connected with an FPGA module, and the FPGA module is connected with the optical splitter. The plurality of optical modules realize photoelectric conversion; the FPGA module is internally provided with a plurality of internal processing units, each internal processing unit is connected with one optical module, and different test functions are completed according to signals transmitted by the optical modules and signals of the test control module; and the test control module is connected with each internal processing unit of the FPGA module through a serial port. According to the ONU terminal simulating the XG-PON / XGS-PON, the characteristic that multiple threads of the FPGA can be executed at the same time and do not influence one another is utilized, and the ONU terminal simulating the XG-PON / XGS-PON is used, so that the effect of simulating the multiple ONU terminals of the XG-PON / XGS-PON can be achieved only by externally hanging FPGA equipment when OLT equipment is tested.

Description

Technical Field

[0001] The present invention relates to the field of communication technologies, and more particularly, to an OLT device test system, a test method, and a computer medium based on an FPGA. Background Art

[0002] As a new generation of GPON technology, XG-PON / XGS-PON has a higher rate, better meets the growing network requirements, and is more suitable for future networks. However, the devices of XG-PON / XGS-PON are also more expensive than the previous GPON devices. When developing / testing the OLT devices of XG-PON / XGS-PON, in order to test the OLT performance, multiple XG-PON / XGS-PON ONU terminals need to be externally connected during full-load testing. For example, for a 16-port XG-PON / XGS-PON OLT device, more than 1000 XG-PON / XGS-PON ONU terminals are required, which occupies a large amount of funds and is also inconvenient to build the environment. When developing the chassis OLT of XG-PON / XGS-PON, if full-load testing is to be performed, it becomes unrealistic to rely on externally connected XG-PON / XGS-PON ONU terminals. Currently, there are software-simulated ONU terminals on the market, but the software-simulated terminals execute in a single thread and cannot truly simulate the actual usage environment.

[0003] The prior art discloses a function of a simulation optical network unit (ONU) platform to execute multiple simulated ONUs to implement traffic simulation in a gigabit-capable passive optical network (GPON) for data traffic, control traffic, and management traffic. The simulated ONU platform generates OMCI messages, PLOAM messages, DBRu messages, data services, and control services according to the respective statistical specifications in the respective configuration files of the simulated ONUs. The simulated ONU platform formats and encapsulates the simulated traffic according to the dynamic bandwidth allocation instructions received from the OLT system for upstream transmission to the OLT system. Then, the simulated ONU platform sends the simulated traffic to the upstream of the OLT system and receives the downstream traffic from the OLT system. However, the prior art does not involve the test of the large-batch registration / deregistration process. Summary of the Invention

[0004] One of the objectives of the present invention is to provide an OLT device test system based on an FPGA to solve the technical problems in the prior art that when full-load testing the OLT devices of XG-PON / XGS-PON, multiple XG-PON / XGS-PON ONU terminals need to be externally connected, resulting in too high test costs and difficult environment construction. The second objective of the present invention is to provide an OLT device test method based on an FPGA; the third objective of the present invention is to provide a computer medium.

[0005] To solve the above technical problems, the technical solution of the present invention is as follows:

[0006] A first aspect of the present invention provides an OLT device test system based on FPGA for testing a to-be-tested OLT device, including:

[0007] A plurality of optical modules, one end of each of the plurality of optical modules is connected to the to-be-tested OLT device through a splitter, and the other ends of the plurality of optical modules are all connected to the FPGA module. The plurality of optical modules perform optoelectronic conversion;

[0008] An FPGA module, in which a plurality of internal processing units are provided. Each internal processing unit is connected to an optical module and completes different test functions according to the signals transmitted by the optical module and the signals of the test control module;

[0009] A test control module, and the test control module is connected to each internal processing unit of the FPGA module through a serial port.

[0010] In the above technical means, taking advantage of the characteristic that FPGA multi-threading can execute simultaneously without mutual influence, an ONU terminal simulating XG-PON / XGS-PON is used, so that when testing an OLT device, only an external FPGA device is required to achieve the effect of simulating multiple XG-PON / XGS-PON ONU terminals, solving the technical problem in the prior art that when fully loading and testing an OLT device of XG-PON / XGS-PON, multiple XG-PON / XGS-PON ONU terminals need to be externally connected, resulting in too high test costs. At the same time, since there is no need to externally connect multiple devices, the overall layout becomes simple, solving the technical problem in the prior art that it is difficult to build the environment when fully loading and testing an OLT device of XG-PON / XGS-PON.

[0011] Further, the internal processing unit includes:

[0012] A mode detection subunit, and the mode detection subunit determines whether it is an XGS-PON mode or an XG-PON mode according to the signal transmitted by the optical module.

[0013] Further, the internal processing unit further includes:

[0014] A time slot control subunit, and the time slot control subunit realizes synchronization and time slot allocation according to the signal transmitted by the optical module;

[0015] A registration subunit, and the registration subunit realizes the registration information interaction with the to-be-detected OLT device at the rate corresponding to the mode determined by the mode detection subunit;

[0016] A deregistration subunit, which implements deregistration information interaction with the OLT device to be detected at a rate corresponding to the mode determined by the mode detection subunit;

[0017] A power-off alarm subunit, which completes the power-off alarm function test;

[0018] A rogue ONU subunit, which tests the handling of rogue ONUs by the OLT device to be detected.

[0019] The second aspect of the present invention provides an FPGA-based OLT device test method, which is applied to the FPGA-based OLT device test, and the test method includes:

[0020] Initialize several of the optical modules, FPGA modules, and test control modules;

[0021] The internal processing unit in the FPGA module receives the signal sent by the OLT device to be tested through the corresponding optical module;

[0022] The internal processing unit in the FPGA module determines whether it is in the XGS-PON mode or the XG-PON mode based on the received signal sent by the OLT device to be tested; if it is in the XGS-PON mode, set the FPGA rate to the first rate; if it is in the XG-PON mode, set the FPGA rate to the second rate;

[0023] The internal processing unit in the FPGA module completes the functions to be tested according to the FPGA rate, and completes the test of the OLT device to be tested.

[0024] Further, the internal processing unit in the FPGA module completes the functions to be tested according to the FPGA rate, including:

[0025] The time slot control subunit realizes synchronization and time slot allocation according to the signal transmitted by the optical module.

[0026] Further, the internal processing unit in the FPGA module completes the functions to be tested according to the FPGA rate, including:

[0027] The registration subunit realizes registration information interaction with the OLT device to be detected according to the FPGA rate.

[0028] Further, the internal processing unit in the FPGA module completes the functions to be tested according to the FPGA rate, including:

[0029] The deregistration subunit automatically disconnects the information interaction with the OLT device to be tested according to the FPGA rate, realizing deregistration.

[0030] Further, the internal processing unit in the FPGA module completes the functions to be tested according to the FPGA rate, including:

[0031] The power-off alarm subunit reports a power-off message, then automatically interrupts the communication with the OLT device to be tested, and deregisters.

[0032] Further, the internal processing unit in the FPGA module completes the functions to be tested according to the FPGA rate, including:

[0033] The rogue ONU subunit controls the transmission control pin of the optical module to keep the light-emitting operation on for a long time and occupy the time slots of other optical modules;

[0034] If the rogue ONU subunit receives the operation of turning off the light emission of the OLT device to be tested, the test is successful, and the long light emission is terminated, and the light emission is switched to the normal time slot control.

[0035] The third aspect of the present invention provides a computer storage medium, on which a computer program is stored. When the computer program is executed by a computer, the provided FPGA-based OLT device test method is implemented.

[0036] Compared with the prior art, the beneficial effects of the technical solution of the present invention are:

[0037] The present invention provides a method for testing an OLT device by using an FPGA to simulate an ONU terminal device of XG-PON / XGS-PON, which greatly reduces the cost and space compared with an externally connected actual ONU terminal device of XG-PON / XGS-PON. Compared with software simulation, it solves the problem that the software simulation load cannot truly reflect the usage scenario. The technical solution of the present invention takes into account cost, space, and real-scenario application. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a schematic structural diagram of an FPGA-based OLT device test system provided by an embodiment of the present invention;

[0039] Figure 2 It is a schematic diagram of the internal processing unit of the FPGA provided by an embodiment of the present invention;

[0040] Figure 3 It is a schematic flowchart of an FPGA-based OLT device test method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0041] The accompanying drawings are only for illustrative purposes and should not be construed as limiting the present patent;

[0042] To better illustrate this embodiment, some components in the accompanying drawings are omitted, enlarged or reduced, which does not represent the size of the actual product;

[0043] For those skilled in the art, it is understandable that some well-known structures and their descriptions in the accompanying drawings may be omitted.

[0044] The technical solutions of the present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0045] Embodiment 1

[0046] The embodiment of the present invention provides an OLT device test system based on FPGA for testing the OLT device to be tested. As Figure 1 shown, the OLT device test system includes:

[0047] A plurality of optical modules, one end of each of the plurality of optical modules is connected to the OLT device to be tested through an optical splitter, and the other end of each of the plurality of optical modules is connected to the FPGA module. The plurality of optical modules perform optoelectronic conversion;

[0048] An FPGA module, in which a plurality of internal processing units are provided. Each internal processing unit is connected to an optical module and completes different test functions according to the signals transmitted by the optical module and the signals of the test control module;

[0049] A test control module, and the test control module is connected to each internal processing unit of the FPGA module through a serial port.

[0050] FPGA (Field-Programmable Gate Array), that is, a field-programmable gate array, is a highly flexible integrated circuit. The CLB is the basic building block of the FPGA, which contains configurable logic circuits. These logic circuits can be programmed to perform various logic functions, such as basic logic operations like AND gates, OR gates, and NOT gates, and can also be combined into more complex circuits, such as counters and state machines. The FPGA has the characteristics of high flexibility and strong parallel processing ability and can execute multiple operations simultaneously because it can implement multiple independent logic modules through configuration, and these modules can process data in parallel, greatly improving the efficiency of data processing.

[0051] In the above technical means, taking advantage of the characteristic that multiple threads of the FPGA can be executed simultaneously without mutual influence, an ONU terminal that simulates XG-PON / XGS-PON is used, so that when testing the OLT device, only an external FPGA device is required to achieve the effect of simulating multiple XG-PON / XGS-PON ONU terminals, solving the technical problem in the prior art that when fully loading and testing an OLT device of XG-PON / XGS-PON, multiple XG-PON / XGS-PON ONU terminals need to be externally connected, resulting in too high testing costs. At the same time, since there is no need to externally connect multiple devices, the overall layout becomes simple, solving the technical problem in the prior art that it is difficult to build the environment when fully loading and testing an OLT device of XG-PON / XGS-PON.

[0052] Further, the optical module is connected to the OLT device to be tested through an optical splitter. Among them, the optical module performs optoelectronic conversion, realizes converting an optical signal into an electrical signal and inputting it to the FPGA for processing, and at the same time realizes converting the electrical signal of the FPGA into an optical signal and uploading it to the optical fiber for transmission.

[0053] Further, the internal processing unit is as Figure 2 shown and includes:

[0054] A mode detection subunit, which determines whether it is in the XGS-PON mode or the XG-PON mode according to the signal transmitted by the optical module.

[0055] In this embodiment, when the mode detection subunit determines that the OLT device to be tested is in the XG-PON mode according to the signal transmitted by the optical module, the data processing rate of the FPGA is set to the data processing rate of XG-PON; when the mode detection subunit determines that the OLT device to be tested is in the XGS-PON mode according to the signal transmitted by the optical module, the data processing rate of the FPGA is set to the data processing rate of XGS-PON. This is the first step for the FPGA to simulate XG-PON / XGS-PON.

[0056] Further, the internal processing unit further includes:

[0057] A time slot control subunit, which realizes synchronization and time slot allocation according to the signal transmitted by the optical module;

[0058] A registration subunit, which realizes the interaction of registration information with the OLT device to be detected at the rate corresponding to the mode determined by the mode detection subunit;

[0059] A deregistration subunit, which realizes the interaction of deregistration information with the OLT device to be detected at the rate corresponding to the mode determined by the mode detection subunit;

[0060] Power-off alarm subunit, and the power-off alarm subunit completes the power-off alarm function test;

[0061] Rogue ONU subunit, and the rogue ONU subunit tests the processing of the rogue ONU by the OLT device to be detected.

[0062] In this embodiment, the time slot control subunit realizes synchronization and time slot allocation according to the synchronization frame signal sent by the OLT device to be detected, avoiding time slot conflicts of different ONUs;

[0063] The registration subunit realizes the registration information interaction with the OLT device to be detected according to the rate corresponding to the mode judged by the mode detection subunit, simulating the registration of the ONU terminal on the OLT;

[0064] Deregistration subunit, and the deregistration subunit realizes the deregistration information interaction with the OLT device to be detected according to the rate corresponding to the mode judged by the mode detection subunit, simulating the automatic disconnection of the ONU terminal from the OLT information interaction and realizing deregistration;

[0065] Power-off alarm subunit, and the power-off alarm subunit completes the power-off alarm function test, simulating the power-off alarm function test;

[0066] Rogue ONU subunit, and the rogue ONU subunit tests the processing of the rogue ONU by the OLT device to be detected, simulating long light emission and testing the processing of the rogue ONU by the OLT;

[0067] Embodiment 2

[0068] The second aspect of the present invention provides an FPGA-based OLT device testing method, and the testing method is applied to the FPGA-based OLT device testing as Figure 3 shown, and the testing method includes:

[0069] Initialize a plurality of the optical modules, FPGA modules and test control modules;

[0070] The internal processing unit in the FPGA module receives the signal sent by the OLT device to be tested through the corresponding optical module;

[0071] The internal processing unit in the FPGA module judges whether it is in the XGS-PON mode or the XG-PON mode according to the signal sent by the OLT device to be tested received; if it is in the XGS-PON mode, the FPGA rate is set to the first rate; if it is in the XG-PON mode, the FPGA rate is set to the second rate;

[0072] The internal processing unit in the FPGA module completes the functions to be tested according to the FPGA rate, and completes the test of the OLT device to be tested.

[0073] In this embodiment, the time slot control subunit realizes synchronization and time slot allocation according to the synchronization frame signal sent by the OLT device to be detected, avoiding time slot conflicts of different ONUs;

[0074] The registration subunit realizes the interaction of registration information with the OLT device to be detected according to the rate corresponding to the mode judged by the mode detection subunit, simulating the registration of the ONU terminal on the OLT;

[0075] The deregistration subunit, the deregistration subunit realizes the interaction of deregistration information with the OLT device to be detected according to the rate corresponding to the mode judged by the mode detection subunit, simulating the automatic disconnection of the ONU terminal from the information interaction of the OLT and realizing deregistration;

[0076] The power-off alarm subunit, the power-off alarm subunit completes the power-off alarm function test, simulating the power-off alarm function test;

[0077] The rogue ONU subunit, the rogue ONU subunit tests the processing of the rogue ONU by the OLT device to be detected, simulating long light emission and testing the processing of the rogue ONU by the OLT.

[0078] Furthermore, the internal processing unit in the FPGA module completes the functions to be tested according to the FPGA rate, including:

[0079] The time slot control subunit realizes synchronization and time slot allocation according to the signal transmitted by the optical module.

[0080] Furthermore, the internal processing unit in the FPGA module completes the functions to be tested according to the FPGA rate, including:

[0081] The registration subunit realizes the interaction of registration information with the OLT device to be detected according to the FPGA rate.

[0082] Furthermore, the internal processing unit in the FPGA module completes the functions to be tested according to the FPGA rate, including:

[0083] The deregistration subunit automatically disconnects the information interaction with the OLT device to be tested according to the FPGA rate, realizing deregistration.

[0084] Furthermore, the internal processing unit in the FPGA module completes the functions to be tested according to the FPGA rate, including:

[0085] The power-off alarm sub-unit reports a power-off message, then automatically interrupts the communication with the OLT device to be tested, and deregisters.

[0086] Further, the internal processing unit in the FPGA module completes the functions to be tested according to the FPGA rate, including:

[0087] The rogue ONU sub-unit occupies the time slots of other optical modules by controlling the transmission control pin of the optical module to keep the light-emitting operation on for a long time;

[0088] If the rogue ONU sub-unit receives the operation of turning off the light emission of the OLT device to be tested, the test is successful, the long light emission is terminated, and the light emission is switched to normal time slot control.

[0089] Embodiment 3

[0090] An embodiment of the present invention provides a computer storage medium, on which a computer program is stored. When the computer program is executed by a computer, the above-mentioned OLT device testing method based on FPGA is implemented.

[0091] The same or similar reference numerals correspond to the same or similar components;

[0092] The terms describing the positional relationship in the drawings are only for illustrative purposes and should not be construed as a limitation of this patent;

[0093] Obviously, the above embodiments of the present invention are only examples for clearly illustrating the present invention, and are not limitations on the implementation manners of the present invention. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all the implementation manners here. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the claims of the present invention.

Claims

1. An OLT device test system based on FPGA, which is used to test the OLT device to be tested, is characterized in that, Including: A plurality of optical modules, one end of the plurality of optical modules is connected to the OLT device to be tested through an optical splitter, the other ends of the plurality of optical modules are all connected to the FPGA module, and the plurality of optical modules perform optoelectronic conversion; The FPGA module, a plurality of internal processing units are arranged in the FPGA module, each internal processing unit is connected to an optical module, and according to the signals transmitted by the optical module and the signals of the test control module, different test functions are completed; The test control module, the test control module is connected to each internal processing unit of the FPGA module through a serial port.

2. The OLT device test system based on FPGA according to claim 1, characterized in that The internal processing unit includes: A mode detection subunit, the mode detection subunit determines whether it is an XGS-PON mode or an XG-PON mode according to the signal transmitted by the optical module.

3. The OLT device test system based on FPGA according to claim 2, characterized in that The internal processing unit further includes: A time slot control subunit, the time slot control subunit realizes synchronization and time slot allocation according to the signal transmitted by the optical module; A registration subunit, the registration subunit realizes the registration information interaction with the OLT device to be detected according to the rate corresponding to the mode determined by the mode detection subunit; A deregistration subunit, the deregistration subunit realizes the deregistration information interaction with the OLT device to be detected according to the rate corresponding to the mode determined by the mode detection subunit; A power-off alarm subunit, the power-off alarm subunit completes the power-off alarm function test; A rogue ONU subunit, the rogue ONU subunit tests the processing of the rogue ONU by the OLT device to be detected.

4. A test method for an OLT device based on FPGA, characterized in that, The test method is applied to the FPGA-based OLT device test according to any one of claims 1 to 3, and the test method includes: Initializing a plurality of the optical modules, the FPGA module and the test control module; The internal processing unit in the FPGA module receives the signal sent by the OLT device to be tested through the corresponding optical module; The internal processing unit in the FPGA module determines whether it is an XGS-PON mode or an XG-PON mode according to the signal sent by the OLT device to be tested received; if it is the XGS-PON mode, the FPGA rate is set to the first rate; if it is the XG-PON mode, the FPGA rate is set to the second rate; The internal processing unit in the FPGA module completes the functions to be tested according to the FPGA rate, and completes the test of the OLT device to be tested.

5. The method for testing the OLT device based on FPGA according to claim 4, wherein The internal processing unit in the FPGA module completes the functions to be tested according to the FPGA rate, including: The time slot control subunit realizes synchronization and time slot allocation according to the signal transmitted by the optical module.

6. The test method for the OLT device based on FPGA according to claim 4, characterized in that The internal processing unit in the FPGA module completes the functions to be tested according to the FPGA rate, including: The registration subunit realizes the registration information interaction with the OLT device to be detected according to the FPGA rate.

7. The method for testing an OLT device based on FPGA according to claim 4, wherein The internal processing unit in the FPGA module completes the functions to be tested according to the FPGA rate, including: The deregistration subunit automatically disconnects the information interaction with the OLT device to be tested according to the FPGA rate, and realizes deregistration.

8. The method for testing an OLT device based on FPGA according to claim 4, wherein The internal processing unit in the FPGA module completes the functions to be tested according to the FPGA rate, including: The power-off alarm subunit reports a power-off message, then automatically interrupts the communication with the OLT device to be tested, and deregisters.

9. The OLT device testing method based on FPGA according to claim 4, wherein The internal processing unit in the FPGA module completes the functions to be tested according to the FPGA rate, including: The rogue ONU subunit occupies the time slots of other optical modules by controlling the transmission control pin of the optical module to turn on the light-emitting operation for a long time; If the rogue ONU subunit receives the light-emitting operation shutdown of the OLT device to be tested, the test is successful, and the long light-emitting is terminated and converted to normal time slot control for light emission.

10. A computer storage medium, characterized in that, A computer program is stored on the computer storage medium. When the computer program is executed by a computer, the FPGA-based OLT device test method according to any one of claims 4 to 9 is implemented.

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