Universal multi-terminal address automatic sorting and distributing algorithm

Abstract

The invention provides a general multi-terminal address automatic sorting and distributing algorithm, which relates to the technical field of sorting algorithms, and is characterized by comprising the following steps that: step 1, original address information is cleared, a host sends a broadcast instruction ''cascade switch opening instruction'', ''a broadcast address'' is 0xFF, after a slave receives and executes the broadcast instruction, a cascade switch is closed, and the original address information is cleared; the address of the slave is cleared as 0 * 00; step 2, the host is powered on again, the slave switches disconnect the cascade switches due to the fact that the addresses of the slave switches are 0 * 00, at the moment, only the first terminal directly connected with the host is in a power-on state, and after it is judged that the first terminal distributes the addresses, the cascade switches of the first terminal are switched on, so that the next-level slave terminal is powered on; and step 3, after the slave machines complete address allocation, the master machines are powered off and powered on again, so that all the slave machines complete power-on and restarting once and enter a normal use state. The method has the advantages that the overall operation steps are simplified, and the overall arrangement and operation are more efficient.

Description

Technical Field

[0001] The present invention relates to the field of sorting algorithms, and particularly relates to a general multi-terminal address automatic sorting and allocation algorithm. Background Art

[0002] RS-485 is a commonly used serial communication interface standard. It has the advantages of strong anti-interference ability, long transmission distance, and support for multi-node communication, and is widely used in industrial automation, building control, security monitoring and other fields.

[0003] RS-485 is only a physical layer interface standard and does not stipulate a communication protocol itself. After multiple terminals share and are connected to the AB communication line of RS-485, the addresses of the terminals need to be set manually to distinguish the device identities.

[0004] For fixed terminals (fixed quantity, fixed position), during use, the communication addresses of each terminal need to be set manually, which is already cumbersome.

[0005] In the case of non-fixed terminal placement scenarios (such as: the number of terminals placed each time is not fixed, the physical position of each terminal is not fixed, and all terminals need to have a definite sequence number), before communication starts, the addresses of the terminals need to be set according to the physical position or physical order. When the physical position needs to be represented by the address, if the RS485 communication addresses are still set manually one by one, the whole work will become very cumbersome. And when the work site is in some harsh environments and there are many terminals to be set at the same time, this will make the work of setting addresses very difficult and inefficient. Summary of the Invention

[0006] The purpose of the present invention is to provide a general multi-terminal address automatic sorting and allocation algorithm, which solves the technical problem that the operation of the existing device is cumbersome and requires a lot of effort to operate and adjust, and realizes the technical effects of simplifying the overall operation and improving the overall operation efficiency.

[0007] In order to achieve the above invention purpose, the technical solution adopted by the present invention is as follows:

[0008] A general multi-terminal address automatic sorting and allocation algorithm includes the following steps: Step 1, clear the original address information. The host will send a broadcast instruction "open cascade switch instruction", the "broadcast address" is 0xFF. After the slave machine receives the broadcast instruction and executes it, it will close the cascade switch so that all terminals can be normally connected to the 485 communication bus. The host will send a broadcast instruction "clear address instruction", and all slave machines on the 485 communication bus will receive and execute this broadcast instruction, and the address of the slave machine will be cleared to 0x00;

[0009] Step 2: The host is powered on again. Since the slave's own address is 0x00, it will disconnect the cascading switch. At this time, only the first terminal directly connected to the host is powered on. The host then sends a broadcast instruction "Set Address Instruction", and the data of the instruction contains an address value of 0x01. At this time, only the first powered-on terminal receives and executes the instruction. Its own address will be set to 0x01 and the function will be executed simultaneously. When it determines that its own address has been assigned, it will close its own cascading switch to power on the next-level terminal slave.

[0010] Step 3: When the slave has completed address assignment, the host will be powered off and then on again to cause all slaves to complete a power-on restart and enter the normal use state.

[0011] As an improvement, in Step 2, after the first group of slaves completes the instruction, the second group of slaves will be powered on. At this time, the host will send another broadcast instruction "Set Address Instruction" again. The address contained in the data of this instruction is 0x02. At this time, the first group and the second group of slaves will receive the instruction simultaneously, but the first group of slaves will compare and discard the instruction after determining that the instruction address value is different from its own.

[0012] As an improvement, when the second group of slaves finds that its own address is 0, it will receive and execute this instruction, modify its own address to 0x02 at the same time, and close the cascading switch to power on the next-level terminal slave, and so on in a cycle.

[0013] The beneficial effects of the present invention are as follows: Multiple terminals can be automatically assigned communication addresses according to the order of physical placement, solving the problem that in a harsh environment, it is necessary to assign communication addresses according to the order of the physical placement of the terminals, and assigning communication addresses to each terminal's communication address in an orderly manner, greatly improving the work efficiency and the efficiency of on-site placement of the terminals. Brief Description of the Drawings

[0014] Figure 1 It is the corresponding circuit diagram of a general multi-terminal address automatic sorting and allocation algorithm of the present invention;

[0015] Figure 2 It is a schematic diagram of an RS485 transmission bus-type communication architecture;

[0016] Figure 3 It is a schematic diagram of an RS485 communication architecture that automatically senses the physical position order. Detailed Embodiment

[0017] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0018] It should be noted that the terms "first" and "second" in the present application are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present application, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products, or devices.

[0019] A data acquisition device A is connected to sensor terminals B1, B2, B3... Bn through an RS485 communication bus. During operation, the acquisition device A needs to communicate with terminals B1... Bn respectively through RS485 and collect the data on the terminals. The relevance between these data lies in the order. It is necessary to know which data is uploaded by which sensor. These terminal devices are in different physical positions during different measurements. Each time a measurement is taken, it is necessary to know its physical position again and associate it with the communication address.

[0020] In the above scenario, it is essentially still a traditional master-slave RS485 communication architecture. The difference lies in the repeated use of the terminals. In different scenarios, the same terminal is in different physical positions, and when the host device collects data from the slave terminal, it must accurately associate the data with its physical position.

[0021] The traditional master-slave bus connection method in hardware. Although the host can access each terminal device through the preset communication address. However, the host cannot perceive the physical position of each device. This is the characteristic of the bus connection and also the drawback when it is necessary to perceive the physical sequential position.

[0022] The hardware of this design has a basic structure similar to that of the traditional bus. However, the hardware terminal is divided into two working states. One is the address allocation state, and the other is the communication working state. The final physical wiring method in the communication working state is the same as Figure 2in the same traditional way. Different from the traditional way, the power supplies of all slave devices are also controlled by the master device.

[0023] When the entire system is in the address allocation state, the hardware connection status is as Figure 3 shown. The 485 chips in all terminals are connected to the 485 communication bus. This bus has two directions, the direction to the previous terminal and the direction to the subsequent terminal. As shown in the figure, at this time, the RS485 chip of each terminal is conductive to the previous stage, but there is a switch in the direction to the subsequent stage, and the switch is open at this time.

[0024] RS485 is the physical layer. When the master device sends data, in fact, each slave device connected to the same bus receives it synchronously. Therefore, it is necessary to process the received data of the slave device at the application layer. So the so-called slave device address is actually the address at the application layer. Therefore, the implementation of the "RS485 general multi-terminal address automatic sorting and allocation algorithm" requires full cooperation between the master and slave devices. In the system, the master device needs to have a fixed and unchanging address, such as 0xFE. The control of the slave device is mainly completed in the following steps:

[0025] A general multi-terminal address automatic sorting and allocation algorithm includes the following steps: Step 1, clear the original address information. The master device will send a broadcast instruction "Open cascade switch instruction", and the "Broadcast address" is 0xFF. After the slave device receives the broadcast instruction and executes it, it will close the cascade switch so that all terminals can be normally connected to the 485 communication bus. The master device will send a broadcast instruction "Clear address instruction", and all slave devices on the 485 communication bus will receive and execute this broadcast instruction, and the address of the slave device will be cleared to 0x00; Step 2, the master device is powered on again. Because the address of the slave device is 0x00, it will disconnect the cascade switch. At this time, only the first terminal directly connected to the master device is in the powered-on state. At this time, the master device sends a broadcast instruction "Set address instruction", and the data of the instruction contains the address value of 0x01. At this time, only the first powered-on terminal receives and executes this instruction, sets its own address to 0x01 and executes the function. When it judges that its own address has been allocated, it will close its own cascade switch to power on the subsequent terminal slave device; Step 3, when the slave device completes the address allocation, the master device will be powered off and then powered on again to make all slave devices complete a power-on restart and enter the normal use state.

[0026] In step 2, after the first group of slaves complete the instruction, the second group of slaves will be powered on. At this time, the master will send another broadcast instruction "Set Address Instruction" again. The address included in the data of this instruction is 0x02. At this time, both the first group and the second group of slaves will receive the instruction simultaneously. However, the first group of slaves will compare and discard the instruction after determining that the instruction address value is different from its own. When the second group of slaves find that their own address is 0, they will receive and execute this instruction, and at the same time modify their own address to 0x02, and close the cascade switch to power on the next-level terminal slave, and so on in a loop.

[0027] According to the algorithm, when the slave cooperates with the instructions of each stage of the master, it is necessary to focus on controlling the lower-level cascade switch of the bus. Therefore, the corresponding hardware principle part also needs to have a corresponding circuit. As Figure 1 shown, the connection mode of the 485 bus is the same as the traditional way, except that there is an additional relay controlled by a single-chip microcomputer to control the power supply after the lower line. This is the "lower-level cascade switch". The on / off of the relay is controlled according to the AB_CTRL signal of the slave single-chip microcomputer and a driving circuit. The object of the on / off is the power supply of the next level.

[0028] The above are only the preferred embodiments of the present invention for patent, and are not intended to limit the present invention for patent. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention for patent shall be included within the protection scope of the present invention for patent.

Claims

1. A general multi-terminal address automatic sorting and allocation algorithm, characterized in that The steps include the following: Step 1: Clear the original address information. The host will send a broadcast instruction "Open cascade switch instruction", and the "Broadcast address" is 0xFF. After the slave receives the broadcast instruction and executes it, it will close the cascade switch so that all terminals can be normally connected to the 485 communication bus. The host will send a broadcast instruction "Clear address instruction", and all slaves on the 485 communication bus will receive and execute this broadcast instruction, and the address of the slave will be cleared to 0x00. Step 2: The host powers on again. Since the address of the slave is 0x00, it will disconnect the cascade switch. At this time, only the first terminal directly connected to the host is in the powered-on state. At this time, the host issues a broadcast instruction "Set address instruction", and the data of the instruction contains an address value of 0x01. At this time, only the first powered-on terminal receives and executes this instruction, sets its own address to 0x01 and executes the function. When it determines that its address has been allocated, it closes its own cascade switch to power on the next-level terminal slave. Step 3: After the slave completes the address allocation, the host will power off and then power on again to cause all slaves to complete a power-on restart and enter the normal use state.

2. The general multi-terminal address automatic sorting and allocation algorithm according to claim 1, characterized in that In step 2, after the first group of slaves completes the instruction, the second group of slaves will power on. At this time, the host will issue another broadcast instruction "Set address instruction", and the address contained in the data of this instruction is 0x02. At this time, the first group and the second group of slaves will receive the instruction at the same time, but the first group of slaves will compare and discard the instruction after determining that the instruction address value is different from its own.

3. A general multi-terminal address automatic sorting and allocation algorithm according to claim 2, characterized in that When the second group of slaves finds that its own address is 0, it will receive and execute this instruction, modify its own address to 0x02 at the same time, and close the cascade switch to power on the next-level terminal slave, and so on in a cycle.

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