Semiconductor device

Abstract

A semiconductor device includes: a word line on a substrate and extending in a first direction perpendicular to a surface of the substrate; a plurality of channel regions at least partially surrounding the word line and spaced apart from each other in the first direction; a bit line at one side of the plurality of channel regions and extending in a second direction perpendicular to the first direction; and a plurality of capacitor structures at least partially surrounding the word line, where the plurality of capacitor structures have a width greater than a width of the plurality of channel regions in a second direction or in a third direction intersecting the first direction and the second direction.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0003635, filed with the Korean Intellectual Property Office on January 9, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Example embodiments of the present disclosure relate to a semiconductor device including semiconductor memory elements arranged in a three-dimensional manner. Background Art

[0003] With the requirements for miniaturization, multi-functionality, and high performance of electronic products, high-capacity semiconductor memory elements are needed. To provide high-capacity semiconductor memory elements, increased integration is required. Since the integration of two-dimensional semiconductor memory elements is mainly determined by the area occupied by a unit memory cell, the integration of two-dimensional semiconductor memory elements is increasing but still limited.

[0004] The information disclosed in this background art section has been known or derived by the inventors before or during the implementation of the embodiments of the present application, or is technical information obtained during the implementation of the embodiments. Therefore, it may include information that does not form the prior art known to the public. Summary of the Invention

[0005] One or more example embodiments provide a semiconductor device having increased integration.

[0006] Additional aspects will be set forth in part in the description that follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments.

[0007] According to an aspect of an example embodiment, a semiconductor device may include: a word line on a substrate and extending in a first direction perpendicular to the surface of the substrate; a plurality of channel regions at least partially surrounding the word line and spaced apart from each other in the first direction; a bit line at one side of the plurality of channel regions and extending in a second direction perpendicular to the first direction; and a plurality of capacitor structures at least partially surrounding the word line, wherein, in the second direction or in a third direction intersecting the first and second directions, the plurality of capacitor structures have a width greater than the width of the plurality of channel regions.

[0008] According to an aspect of an exemplary embodiment, a semiconductor device may include: a plurality of word lines on a substrate and extending in a first direction perpendicular to a surface of the substrate, the plurality of word lines being arranged in a second direction intersecting the first direction and a third direction intersecting the second direction, wherein each of the plurality of word lines is at least partially surrounded by a plurality of channel regions spaced apart from each other in the first direction; and a plurality of capacitor structures, each having a width greater than a width of one of the plurality of channel regions in the second direction or the third direction; bit lines at one side of the plurality of channel regions and extending in the third direction; plate electrodes between two word lines adjacent to each other in the second direction among the plurality of word lines; and extended plate electrodes contacting the plate electrodes and at least one capacitor structure.

[0009] According to an aspect of an exemplary embodiment, a semiconductor device may include: a plurality of word lines on a substrate along a first direction perpendicular to a surface of the substrate, the plurality of word lines being arranged in a second direction intersecting the first direction and a third direction intersecting the second direction, wherein each of the plurality of word lines is at least partially surrounded by a plurality of channel regions, each of the plurality of channel regions having an annular shape and being spaced apart from each other in the first direction; and a plurality of capacitor structures, each having an annular shape and having a width greater than a width of one of the plurality of channel regions in the second direction or the third direction; bit lines at one side of the plurality of channel regions and extending in the third direction; contacts between a first capacitor structure among the plurality of capacitor structures and a first channel region among the plurality of channel regions adjacent to each other in the first direction; plate electrodes between two word lines adjacent to each other in the second direction among the plurality of word lines; and extended plate electrodes having an annular shape and at least partially surrounding the plate electrodes, the extended plate electrodes contacting the plate electrodes and at least one capacitor structure among the plurality of capacitor structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features, and advantages of certain exemplary embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a perspective view showing a semiconductor device according to one or more embodiments;

[0012] Figure 2 is a cross-sectional view showing a semiconductor device according to one or more embodiments;

[0013] Figure 3A is a plan view at a first vertical height according to one or more embodiments at Figure 2 ;

[0014] Figure 3B is at according to one or more embodiments atFigure 2 A plan view at the second vertical height;

[0015] Figure 3C is a plan view at the Figure 2 third vertical height according to one or more embodiments;

[0016] Figure 3D is a plan view at the Figure 2 fourth vertical height according to one or more embodiments;

[0017] Figure 4A and Figure 4B is a plan view showing a semiconductor device according to one or more embodiments;

[0018] Figure 5 is a perspective view showing a semiconductor device according to one or more embodiments;

[0019] Figure 6 is at the third vertical height according to one or more embodiments Figure 5 of the semiconductor device;

[0020] Figure 7 is a perspective view showing a semiconductor device according to one or more embodiments;

[0021] Figure 8 is at the third vertical height according to one or more embodiments Figure 7 of the semiconductor device; and

[0022] Figure 9A 、 Figure 9B 、 Figure 10A 、 Figure 10B 、 Figure 11A 、 Figure 11B 、 Figure 12A 、 Figure 12B 、 Figure 13A 、 Figure 13B 、 Figure 14A 、 Figure 14B 、 Figure 15A 、 Figure 15B 、 Figure 16A 、 Figure 16B 、 Figure 17A 、 Figure 17B 、 Figure 18A 、 Figure 18B 、 Figure 19A and Figure 19B is a diagram showing a manufacturing method of a semiconductor device according to one or more embodiments. Detailed Description

[0023] In the following, example embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions thereof will be omitted. The embodiments described herein are example embodiments, and thus, the disclosure is not limited thereto and may be implemented in various other forms.

[0024] As used herein, a phrase such as "at least one of" when following a list of elements modifies the entire list of elements and not each element in the list. For example, the phrase "at least one of a, b, and c" should be understood to mean only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0025] It will be understood that when an element or layer is referred to as being "on," "above," "over," "under," "below," "beneath," "connected to," or "coupled to" another element or layer, it can be directly on, above, over, under, below, beneath, directly connected to, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly above," "directly over," "directly under," "directly below," "directly beneath," "directly connected to," or "directly coupled to" another element or layer, no intervening elements or layers are present.

[0026] As used herein, unless otherwise specified, as will be understood by those of ordinary skill in the art from the present disclosure, the term "around" and its equivalent expressions may include complete surrounding in all directions or partial surrounding in fewer directions than all directions. As used herein, unless otherwise specified, as will be understood by those of ordinary skill in the art from the present disclosure, the term "cover" and its equivalent expressions may include complete covering or partial covering.

[0027] Figure 1 is a perspective view showing a semiconductor device 100 according to one or more embodiments. Figure 2 is a cross-sectional view showing a semiconductor device 100 according to one or more embodiments. Figure 3A is a plan view at a first vertical height Lv1 of Figure 2 according to one or more embodiments, Figure 3B is a plan view at a second vertical height Lv2 of Figure 2 according to one or more embodiments, Figure 3C is a plan view at a third vertical height Lv3 of Figure 2 according to one or more embodiments, and Figure 3D is a plan view atFigure 2 A plan view at the fourth vertical height Lv4.

[0028] Referring to Figure 1 、 Figure 2 、 Figure 3A 、 Figure 3B 、 Figure 3C and Figure 3D ,the semiconductor device 100 may include a substrate 110, a plurality of word lines WL disposed on the substrate 110, a plurality of channel regions CH surrounding each of the plurality of word lines WL, and a plurality of capacitor structures CAP surrounding each of the plurality of word lines WL.

[0029] The substrate 110 may include a semiconductor material (such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor). For example, the Group IV semiconductor may include silicon (Si), germanium (Ge), or silicon-germanium. The substrate 110 may also be provided as a bulk wafer or an epitaxial layer. In one or more embodiments, the substrate 110 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

[0030] Peripheral circuits and wiring layers connected to the peripheral circuits may be further formed in some regions of the substrate 110. For example, the peripheral circuits may include planar metal-oxide-semiconductor (MOS) field-effect transistors (FETs) (MOSFETs) constituting a sub-word line driver, sense amplifiers, etc., but are not limited thereto. In addition, a lower insulating layer disposed on the substrate 110 and covering the peripheral circuits and the wiring layers may be further formed.

[0031] Each of the plurality of word lines WL may longitudinally extend in a vertical direction (e.g., the Z direction) on the substrate 110. The plurality of word lines WL may be arranged and spaced apart from each other in a first horizontal direction (e.g., the X direction) and a second horizontal direction (e.g., the Y direction) on the substrate 110.

[0032] Each of the plurality of word lines WL may include, for example, at least one of a doped semiconductor material, a conductive metal nitride, a metal, and a metal-semiconductor compound.

[0033] Each of the plurality of channel regions CH may surround one of the plurality of word lines WL. The plurality of channel regions CH surrounding one word line WL may be spaced apart from each other in a vertical direction (e.g., the Z direction) and may be stacked on each other in a vertical direction (e.g., the Z direction). In one or more embodiments, the channel region CH may have an annular shape surrounding the word line WL. Each of the plurality of channel regions CH may include source / drain regions. For example, the source / drain regions may include a semiconductor material doped with impurities.

[0034] In one or more embodiments, the plurality of channel regions CH may each be made of polysilicon. In one or more embodiments, the plurality of channel regions CH may each include an amorphous metal oxide, a polycrystalline metal oxide, or a combination of an amorphous metal oxide and a polycrystalline metal oxide. For example, the plurality of channel regions CH may each include at least one of an In-Ga-based oxide (IGO), an In-Zn-based oxide (IZO), and an In-Ga-Zn-based oxide (IGZO).

[0035] A plurality of gate insulating films GD may be located between the word line WL and the plurality of channel regions CH surrounding the word line WL. The channel regions CH may be horizontally spaced apart from the word line WL, and the gate insulating film GD is located between the channel region CH and the word line WL. In one or more embodiments, the gate insulating film GD may have an annular shape surrounding the word line WL. In one or more embodiments, the plurality of gate insulating films GD may each include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or a combination thereof. In one or more embodiments, the plurality of gate insulating films GD may each include a high-k material. The high-k material may have a dielectric constant of about 10 to about 25. The high-k material may include, for example, hafnium oxide (HfO), aluminum oxide (Al2O3), zirconium oxide (e.g., ZrO2), or a combination thereof, but is not limited thereto.

[0036] A plurality of bit lines BL may be arranged on one side of each of the plurality of channel regions CH in a first horizontal direction (e.g., the X direction). The plurality of bit lines BL may contact each of the plurality of channel regions CH on one side of each of the plurality of channel regions CH. The plurality of bit lines BL may each longitudinally extend in a second horizontal direction (e.g., the Y direction). The plurality of bit lines BL may be spaced apart from each other in a vertical direction (e.g., the Z direction) and may be stacked on top of each other in the vertical direction (e.g., the Z direction). In one or more embodiments, the bit line BL may be at the same vertical height as the channel region CH.

[0037] An inter-cell group insulating film 136 may be arranged on a side of each of the plurality of bit lines BL that does not contact the channel region CH. The inter-cell group insulating film 136 may extend in a vertical direction (e.g., the Z direction) and may longitudinally extend in a second horizontal direction (e.g., the Y direction). The inter-cell group insulating film 136 may contact each of the plurality of bit lines BL. The inter-cell group insulating film 136 may include, for example, silicon oxide (SiO2), but is not limited thereto.

[0038] In addition, the polysilicon layer 124 may be disposed between the inter-cell group insulating film 136 and the capacitor structure CAP that are adjacent to each other in the horizontal direction, and the second insulating layer 126 may be disposed between the inter-cell group insulating film 136 and the word line WL that are adjacent to each other in the horizontal direction (e.g., in the X direction and / or Y direction). The polysilicon layer 124 may be at the same vertical height as the capacitor structure CAP, and the second insulating layer 126 may be at the same vertical height as the contact BC. The polysilicon layer 124 may include, for example, doped polysilicon. The second insulating layer 126 may include, for example, doped silicon nitride.

[0039] Each of the plurality of capacitor structures CAP may surround one of the plurality of word lines WL and may be disposed between the plurality of channel regions CH. The plurality of capacitor structures CAP surrounding one word line WL may be spaced apart from each other in the vertical direction (e.g., the Z direction) and may be stacked on top of each other in the vertical direction (e.g., the Z direction). In addition, each of the plurality of capacitor structures CAP surrounding one word line WL and each of the plurality of channel regions CH surrounding the one word line WL may be spaced apart from each other in the vertical direction (e.g., the Z direction) and may be stacked on top of each other in the vertical direction (e.g., the Z direction). That is, in the X direction and / or Y direction, the width of the capacitor structure CAP may be greater than the width of the channel region CH. In one or more embodiments, each capacitor structure CAP may be at a vertical height different from the vertical height of each channel region CH. In one or more embodiments, the capacitor structure CAP may have an annular shape surrounding the word line WL. Each of the plurality of capacitor structures CAP may include a first electrode IE, a capacitor dielectric film ED, and a second electrode OE. The first electrode IE, the capacitor dielectric film ED, and the second electrode OE may have an annular shape surrounding the word line WL. In one or more embodiments, the first electrode IE, the capacitor dielectric film ED, and the second electrode OE may be at the same vertical height.

[0040] In one or more embodiments, both the first electrode IE and the second electrode OE may include doped semiconductor materials, conductive metal nitrides (such as titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), or tungsten nitride (WNx)), metals (such as ruthenium (Ru), iridium (Ir), titanium (Ti), or tantalum (Ta)), and conductive metal oxides (such as iridium oxide (IrO2) or niobium pentoxide (Nb2O5)).

[0041] In one or more embodiments, the capacitor dielectric film ED may include a high dielectric constant material. The high dielectric constant material may include, for example, hafnium oxide (HfO), aluminum oxide (Al2O3), zirconium oxide (e.g., ZrO2), or a combination thereof, but is not limited thereto. In one or more embodiments, the capacitor dielectric film ED may include a ferroelectric material. The ferroelectric material may include at least one of, for example, hafnium (Hf), zirconium (Zr), silicon (Si), yttrium (Yt), aluminum (Al), gadolinium (Gd), strontium (Sr), lanthanum (La), titanium (Ti), scandium (Sc), and their oxides.

[0042] A plurality of first buried insulating layers 132 may be located between the word line WL and a plurality of capacitor structures CAP surrounding the word line WL. The capacitor structures CAP may be horizontally spaced apart from the word line WL (e.g., in the X direction and / or Y direction), and the first buried insulating layer 132 is located between the capacitor structure CAP and the word line WL. In one or more embodiments, the first buried insulating layer 132 may have an annular shape surrounding the word line WL. The first buried insulating layer 132 may include, for example, silicon dioxide (SiO2).

[0043] In the semiconductor device 100, one memory cell may include one channel region CH, one capacitor structure CAP adjacent to the one channel region CH in the vertical direction (e.g., Z direction) and connected to the one channel region CH through a contact BC described below, one bit line BL disposed on one side of the one channel region CH, and one word line WL surrounded by the one channel region CH and the one capacitor structure CAP. In addition, the semiconductor device 100 may include a plurality of memory cells, and the plurality of memory cells all include the above configuration and are repeatedly arranged in a first horizontal direction (e.g., X direction), a second horizontal direction (e.g., Y direction), and a vertical direction (e.g., Z direction).

[0044] The plate electrode PP may be disposed between two word lines WL adjacent to each other in the first horizontal direction (e.g., X direction). The plate electrode PP may extend longitudinally in the vertical direction (e.g., Z direction). For example, the plate electrode PP may have a cylindrical shape.

[0045] A plurality of extended plate electrodes PPC surrounding the plate electrode PP may be disposed on the surface of the plate electrode PP. Each of the plurality of extended plate electrodes PPC may surround the plate electrode PP. The plurality of extended plate electrodes PPC surrounding one plate electrode PP may be spaced apart from each other in the vertical direction (e.g., the Z direction) and may be stacked on top of each other in the vertical direction (e.g., the Z direction). In one or more embodiments, the extended plate electrode PPC may have an annular shape surrounding the plate electrode PP. The inner side of the extended plate electrode PPC may contact the surface of the plate electrode PP, and the outer side of the extended plate electrode PPC may contact the second electrode OE of the capacitor structure CAP. In one or more embodiments, the extended plate electrode PPC may be at the same vertical height as the capacitor structure CAP.

[0046] One plate electrode PP may be connected via the extended plate electrode PPC surrounding the one plate electrode PP to the second electrode OE of each of the plurality of capacitor structures CAP surrounding two word lines WL adjacent to the one plate electrode PP in the first horizontal direction (e.g., the X direction). That is, the plurality of capacitor structures CAP surrounding "each of the two word lines WL adjacent to one plate electrode PP in the first horizontal direction (e.g., the X direction)" may share the one plate electrode PP. In addition, the second electrode OE of one capacitor structure CAP included in the plurality of capacitor structures CAP surrounding each of the two word lines WL, one extended plate electrode PPC contacting the second electrode OE of the one capacitor structure CAP, and the plate electrode PP connected to the second electrode OE of the one capacitor structure CAP through the one extended plate electrode PPC may be used together as the electrodes of the one capacitor structure CAP.

[0047] In Figures 1 to 3D , the plate electrode PP and the extended plate electrode PPC are shown as separate components having a boundary distinction between the plate electrode PP and the extended plate electrode PPC, but the embodiments are not limited thereto. For example, the plate electrode PP and the extended plate electrode PPC may be integrally formed as described below with reference to Figure 18A and Figure 18B and the plate electrode PP and the extended plate electrode PPC may also become integral without a boundary distinction therebetween.

[0048] The contact BC can be arranged between the word line WL and the plate electrode PP adjacent to each other along the first horizontal direction (e.g., the X direction). The upper surface of the contact BC can contact a channel region CH surrounding the word line WL, and the lower surface of the contact BC can contact a first electrode IE of a capacitor structure CAP surrounding the word line WL and adjacent to the one channel region CH in the vertical direction (e.g., the Z direction). The one channel region CH and the one capacitor structure CAP adjacent to each other in the vertical direction (e.g., the Z direction) can be connected to each other through the contact BC. In one or more embodiments, the contact BC can include at least one of doped semiconductor materials, conductive metal nitrides, metals, and metal-semiconductor compounds.

[0049] The second buried insulating layer 134 can be located between the contact BC and the plate electrode PP. One side of the second buried insulating layer 134 can contact the contact BC, and the other side of the second buried insulating layer 134 facing this side can contact the plate electrode PP. The second buried insulating layer 134 can insulate the plate electrode PP from the contact BC. The second buried insulating layer 134 can include, for example, silicon oxide (SiO2).

[0050] The first insulating layer 122 can be arranged between the word line WL and the plate electrode PP adjacent to each other along the first horizontal direction (e.g., the X direction) and between the word line WL and the inter-cell group insulating film 136 adjacent to each other along the first horizontal direction (e.g., the X direction). The first insulating layer 122 can be at a different vertical height from the channel region CH, the capacitor structure CAP, and the contact BC. The first insulating layer 122 can include, for example, silicon oxide (SiO2).

[0051] The third insulating layer 128 can be arranged between a plurality of channel regions CH surrounding the word line WL and the plate electrode PP adjacent to the word line WL in the first horizontal direction (e.g., the X direction). The third insulating layer 128 can insulate the plate electrode PP from the channel region CH. The third insulating layer 128 can include, for example, silicon nitride (Si3N4).

[0052] A semiconductor device 100 according to one or more embodiments may include word lines WL disposed on a substrate 110 and extending in a vertical direction (e.g., the Z direction), a plurality of channel regions CH surrounding the word lines WL and spaced apart from each other in the vertical direction (e.g., the Z direction), and a plurality of capacitor structures CAP surrounding the word lines WL and disposed between the plurality of channel regions CH. The capacitor structures CAP may be arranged to overlap the channel regions CH in the vertical direction rather than in the horizontal direction, thereby reducing the horizontal area occupied by one memory cell including one capacitor structure CAP and one channel region CH, and thus improving the integration degree of the semiconductor device 100. That is, in the X direction and / or the Y direction, the width of the capacitor structures CAP may be greater than the width of the channel regions CH.

[0053] Figure 4A is a plan view of a semiconductor device 100a according to one or more embodiments. Figure 4B is a plan view of a semiconductor device 100b according to one or more embodiments. Specifically, Figure 4A is a plan view of the semiconductor device 100a at a first vertical height Lv1 (see Figure 2 ), and Figure 4B is a plan view of the semiconductor device 100b at a first vertical height Lv1 (see Figure 2 ). Figure 4A Aspects of the semiconductor device 100a shown in Figure 4B and aspects of the semiconductor device 100b shown in Figure 1 、 Figure 2 、 Figure 3A 、 Figure 3B 、 Figure 3C and Figure 3D may be similar to each component of the semiconductor device 100 described with reference to

[0054] refer to Figure 4A , and except that the semiconductor device 100a includes a first shielding structure SL1, the semiconductor device 100a may have substantially the same configuration as the semiconductor device 100 shown in Figure 1 、 Figure 2 、 Figure 3A 、 Figure 3B 、 Figure 3C and Figure 3D .

[0055] The first shielding structure SL1 can be disposed between word lines WL adjacent to each other in the second horizontal direction (e.g., the Y direction). In one or more embodiments, the first shielding structure SL1 can be at the same vertical height as the channel region CH. Between two bit lines BL adjacent to each other in the first horizontal direction (e.g., the X direction), one first shielding structure SL1 can be disposed between two pairs of word lines WL adjacent to each other in the second horizontal direction (e.g., the Y direction), and compared with Figure 4B the second shielding structure SL2 of the semiconductor device 100b shown in

[0056] Referring to Figure 4B , except that the semiconductor device 100b includes the second shielding structure SL2, the semiconductor device 100b can have substantially the same configuration as the semiconductor devices 100 shown in Figure 1 , Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D .

[0057] The second shielding structure SL2 can be disposed between word lines WL adjacent to each other in the second horizontal direction (e.g., the Y direction). In one or more embodiments, the second shielding structure SL2 can be at the same vertical height as the channel region CH. Between two bit lines BL adjacent to each other in the first horizontal direction (e.g., the X direction), two second shielding structures SL2 can be respectively disposed between two pairs of word lines WL adjacent to each other in the second horizontal direction (e.g., the Y direction), and the two second shielding structures SL2 can be spaced apart from each other in the first horizontal direction (e.g., the X direction). Compared with Figure 4A the first shielding structure SL1 of the semiconductor device 100a shown in

[0058] Figure 5 FIG. is a perspective view of a semiconductor device 200 according to one or more embodiments. Figure 6 FIG. is at a third vertical height according to one or more embodiments (see Figure 2 ) of Figure 5Plan view of the semiconductor device 200. Figure 5 and Figure 6 Aspects of the semiconductor device 200 shown in Figure 1 、 Figure 2 、 Figure 3A 、 Figure 3B 、 Figure 3C and Figure 3D may be similar to the aspects of the semiconductor device 100 described with reference to

[0059] Referring to Figure 5 and Figure 6 , except that the semiconductor device 200 includes an extended plate electrode PPC1 having a rectangular shape, the semiconductor device 200 may have substantially the same structure as the semiconductor device 100 shown in Figure 1 、 Figure 2 、 Figure 3A 、 Figure 3B 、 Figure 3C and Figure 3D .

[0060] Each of the plurality of extended plate electrodes PPC1 may protrude from the surface of the plate electrode PP and extend in a first horizontal direction (e.g., the X direction) toward each of the plurality of capacitor structures CAP surrounding "each of the two word lines WL adjacent to the plate electrode PP in the first horizontal direction (e.g., the X direction)". One side of the extended plate electrode PPC1 may contact the surface of the plate electrode PP, and the other side of the extended plate electrode PPC1 facing this side in the first horizontal direction (e.g., the X direction) may contact the second electrode OE of the capacitor structure CAP. The plurality of extended plate electrodes PPC1 may be spaced apart from each other in the vertical direction (e.g., the Z direction) and stacked on top of each other in the vertical direction (e.g., the Z direction). In one or more embodiments, the extended plate electrode PPC1 may be at the same vertical height as the capacitor structure CAP. In one or more embodiments, the extended plate electrode PPC1 may have a rectangular shape.

[0061] Figure 7 is a perspective view showing a semiconductor device 300 according to one or more embodiments. Figure 8 is a plan view of the semiconductor device 300 at a third vertical height (see Figure 2 ) of Figure 7 . Figure 7 and Figure 8 Aspects of the semiconductor device 300 shown in Figure 1 、 Figure 2 、 Figure 3A 、 Figure 3B 、 Figure 3C and Figure 3DAspects of the described semiconductor device 100 are the same or similar, and thus repeated descriptions may be omitted.

[0062] Referring to Figure 7 and Figure 8 , except that the semiconductor device 300 includes an extended plate electrode PPC2 having a rectangular shape with a curved side surface, the semiconductor device 300 may be Figure 1 , Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D shown in having substantially the same construction as the semiconductor device 100.

[0063] A plurality of extended plate electrodes PPC2 may surround the plate electrode PP. The plurality of extended plate electrodes PPC2 may be spaced apart from each other in the vertical direction (e.g., the Z direction) and stacked on top of each other in the vertical direction (e.g., the Z direction). In one or more embodiments, the extended plate electrode PPC2 may be at the same vertical height as the capacitor structure CAP. In one or more embodiments, the extended plate electrode PPC2 may have a rectangular shape with a curved side surface and an opening surrounding the plate electrode PP at the center of the extended plate electrode PPC2. The curved side surface of the extended plate electrode PPC2 may have a shape that is recessed toward the plate electrode PP. The curved side surface of the extended plate electrode PPC2 may contact the second electrode OE of the capacitor structure CAP having an annular shape.

[0064] Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A and Figure 19B are diagrams showing a method of manufacturing the semiconductor device 100 according to one or more embodiments. Specifically, Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A ,Figure 17A , Figure 18A and Figure 19A are cross-sectional views showing a method of manufacturing a semiconductor device 100 according to one or more embodiments, Figure 9B , Figure 10B , Figure 11B , Figure 12B and Figure 19B are plan views at a first vertical height Lv1 (see Figure 2 ), Figure 13B , Figure 14B , Figure 17B and Figure 18B are plan views at a third vertical height Lv3 (see Figure 2 ), Figure 15B and 16B are plan views at a second vertical height Lv2 (see Figure 2 ).

[0065] Referring to Figure 9A and Figure 9B , the first insulating layer 122, the polysilicon layer 124, the second insulating layer 126, and the third insulating layer 128 can be repeatedly stacked on the substrate 110. In one or more embodiments, the first insulating layer 122, the polysilicon layer 124, the second insulating layer 126, and the third insulating layer 128 can each include materials having an etching selectivity with respect to each other. For example, the first insulating layer 122 can include silicon oxide (SiO2), the polysilicon layer 124 can include polysilicon, the second insulating layer 126 can include doped silicon nitride, and the third insulating layer 128 can include undoped silicon nitride.

[0066] First holes H1 and third holes H3 that penetrate the first insulating layer 122, the polysilicon layer 124, the second insulating layer 126, and the third insulating layer 128 in a vertical direction (e.g., the Z direction) can be formed, and second holes H2 that penetrate the first insulating layer 122, the polysilicon layer 124, the second insulating layer 126, and the third insulating layer 128 in a vertical direction (e.g., the Z direction) and extend longitudinally in a second horizontal direction (e.g., the Y direction) can be formed.

[0067] Referring to Figure 10A and Figure 10B , a first sacrificial film SM1 that fills the first hole H1 (see Figure 9A ) and a second sacrificial film SM2 that fills the second hole H2 can be formed. The first sacrificial film SM1 and the second sacrificial film SM2 can include, for example, silicon oxide (SiO2).

[0068] Referring to Figure 11A and Figure 11B, the first recess RS1 can be formed by removing a part of the third insulating layer 128 through the third hole H3 and making it horizontally recessed. The first recess RS1 can be formed by an etching process. For example, an etching process can be performed using an etchant having an etching selectivity with respect to the third insulating layer 128. The first recess RS1 can communicate with the third hole H3. The first recess RS1 can have an annular shape surrounding the third hole H3.

[0069] Referring to Figure 12A and Figure 12B , a channel region CH and a gate insulating film GD that sequentially fill the first recess RS1 (see Figure 11A ) can be formed. The channel region CH can cover the surface of the third insulating layer 128 exposed by the first recess RS1 (see Figure 11A ), and the gate insulating film GD can cover the surface of the channel region CH. Since the first recess RS1 has an annular shape surrounding the third hole H3, the channel region CH and the gate insulating film GD filling the first recess RS1 can have an annular shape surrounding the third hole H3.

[0070] Referring to Figure 13A and Figure 13B , a recess can be formed by removing a part of the polysilicon layer 124 through the third hole H3 and making it horizontally recessed, and a capacitor structure CAP and a first buried insulating layer 132 that sequentially fill the recess can be formed. The capacitor structure CAP can include a second electrode OE covering the surface of the polysilicon layer 124 exposed by the recess, a capacitor dielectric film ED covering the surface of the second electrode OE, and a first electrode IE covering the surface of the capacitor dielectric film ED. The recess can have an annular shape surrounding the third hole H3, and the capacitor structure CAP filling the recess can also have an annular shape surrounding the third hole H3. The first buried insulating layer 132 can cover the surface of the first electrode IE of the capacitor structure CAP.

[0071] Referring to Figure 14A and Figure 14B , a word line WL that fills the third hole H3 (see Figure 13A ) can be formed.

[0072] Referring to Figure 15A and Figure 15B , a fourth hole H4 can be formed by removing the first sacrificial film SM1 (see Figure 14A ), and a second recess RS2 can be formed by removing the second insulating layer 126 through the fourth hole H4 and making it horizontally recessed. The second recess RS2 can expose a part of the side surface of the word line WL. The second recess RS2 can be formed by an etching process. For example, an etching process can be performed using an etchant having an etching selectivity with respect to the second insulating layer 126. The second recess RS2 can communicate with the fourth hole H4. The second recess RS2 can have a rectangular shape.

[0073] Referring to Figure 16A and Figure 16B , a contact BC and a second buried insulating layer 134 that sequentially fill the second recess RS2 (see Figure 15A ) can be formed. The contact BC can cover the surface of the word line WL exposed by the second recess RS2 (see Figure 15A ), and the second buried insulating layer 134 can cover the surface of the contact BC. The upper surface of the contact BC can contact the lower surface of the channel region CH, and the lower surface of the contact BC can contact the first electrode IE of the capacitor structure CAP. Since the second recess RS2 has a rectangular shape, the contact BC and the second buried insulating layer 134 that fill the second recess RS2 can have a rectangular shape.

[0074] Referring to Figure 17A and Figure 17B , a third recess RS3 can be formed by removing the polysilicon layer 124 through the fourth hole H4 and horizontally recessing it. The third recess RS3 can expose the second electrode OE of the capacitor structure CAP. The third recess RS3 can be formed by an etching process. For example, an etching process can be performed using an etchant that has an etching selectivity with respect to the polysilicon layer 124. The third recess RS3 can communicate with the fourth hole H4. In one or more embodiments, the third recess RS3 can have an annular shape surrounding the fourth hole H4. In one or more embodiments, the third recess RS3 can also be formed to have a rectangular shape protruding from the fourth hole H4. In this case, the semiconductor device 200 shown in Figure 5 and Figure 6 can be manufactured by performing the processes described below. In one or more embodiments, the third recess RS3 can also be formed to have a rectangular shape with curved side surfaces and surrounding the plate electrode PP at the center. In this case, the semiconductor device 300 shown in Figure 7 and Figure 8 can be manufactured by performing the processes described below.

[0075] Referring to Figure 18A and Figure 18B , an extended plate electrode PPC that fills the third recess RS3 (see Figure 17A ) can be formed, and a plate electrode PP that fills the fourth hole H4 ( Figure 17A ) can be formed. The plate electrode PP and the extended plate electrode PPC can be integrally formed. Accordingly, the plate electrode PP and the extended plate electrode PPC can be integrated.

[0076] Referring to Figure 19A and Figure 19B, the fifth hole H5 can be formed by removing the second sacrificial film SM2, and the fourth recess RS4 can be formed by removing the third insulating layer 128 exposed through the fifth hole H5 and making it horizontally recessed. The fifth hole H5 and the fourth recess RS4 can extend longitudinally in the second horizontal direction (e.g., the Y direction).

[0077] By forming a bit line BL filling the fourth recess RS4 (see Figure 19A ), and forming an inter-cell group insulating film 136 filling the fifth hole H5, the semiconductor device 100 described with reference to Figures 1 to 3D can be manufactured.

[0078] Each of the embodiments provided in the above description does not exclude being associated with one or more features of additional examples or additional embodiments that are also provided herein or not provided herein but consistent with the disclosure.

[0079] Although the disclosure has been specifically shown and described with reference to the disclosed embodiments, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: A word line on a substrate and extending in a first direction perpendicular to the surface of the substrate; A plurality of channel regions at least partially surrounding the word line and spaced apart from each other in the first direction; A bit line at one side of the plurality of channel regions and extending in a second direction perpendicular to the first direction; And A plurality of capacitor structures at least partially surrounding the word line, Wherein the plurality of capacitor structures and the plurality of channel regions are aligned in the first direction, and wherein the plurality of capacitor structures are spaced apart from the plurality of channel regions in the first direction.

2. The semiconductor device according to claim 1, wherein, Each of the plurality of capacitor structures has an annular shape.

3. The semiconductor device according to claim 1, wherein, Each of the plurality of channel regions has an annular shape.

4. The semiconductor device according to claim 1, wherein, At least one of the plurality of channel regions is at the same height as the bit line.

5. The semiconductor device according to claim 1, wherein, The plurality of capacitor structures are at a different height from the plurality of channel regions.

6. The semiconductor device according to claim 1, further comprising: A contact between a first capacitor structure among the plurality of capacitor structures and a first channel region among the plurality of channel regions, the first capacitor structure being adjacent to the first channel region in the first direction.

7. The semiconductor device according to claim 6, wherein, The first capacitor structure includes a first electrode, Wherein the upper surface of the contact contacts the first channel region, and Wherein the lower surface of the contact contacts the first electrode.

8. A semiconductor device, comprising: A plurality of word lines on a substrate and extending in a first direction perpendicular to the surface of the substrate, the plurality of word lines being arranged in a second direction intersecting the first direction and a third direction intersecting the second direction, wherein each of the plurality of word lines is at least partially surrounded by a plurality of channel regions and a plurality of capacitor structures, the plurality of channel regions being spaced apart from each other in the first direction, Wherein the plurality of capacitor structures and the plurality of channel regions are aligned in the first direction, and wherein the plurality of capacitor structures are spaced apart from the plurality of channel regions in the first direction; A bit line at one side of the plurality of channel regions and extending in the third direction; A plate electrode between two word lines adjacent to each other in the second direction among the plurality of word lines; and An extended plate electrode contacting the plate electrode and at least one of the plurality of capacitor structures.

9. The semiconductor device according to claim 8, wherein, The plurality of capacitor structures and the plurality of channel regions have an annular shape.

10. The semiconductor device according to claim 8, wherein, At least one of the plurality of channel regions is at the same height as the bit line, and Wherein at least one of the plurality of channel regions is at a different height from at least one of the plurality of capacitor structures.

11. The semiconductor device according to claim 8, further comprising: A shielding structure between word lines adjacent to each other in the third direction among the plurality of word lines.

12. The semiconductor device according to claim 11, wherein, The shielding structure is at the same height as at least one of the plurality of channel regions.

13. The semiconductor device according to claim 8, wherein, The extended plate electrode is at the same height as at least one of the plurality of capacitor structures.

14. The semiconductor device according to claim 8, wherein The extended plate electrode has an annular shape at least partially surrounding the plate electrode.

15. The semiconductor device according to claim 8, wherein, The extended plate electrode extends in the second direction from the surface of the plate electrode toward at least one of the plurality of capacitor structures.

16. The semiconductor device according to claim 15, wherein, The extended plate electrode has a rectangular shape.

17. The semiconductor device according to claim 8, wherein, The extended plate electrode has a rectangular shape with a curved side surface, wherein the extended plate electrode includes an opening at the center of the extended plate electrode, and wherein the extended plate electrode at least partially surrounds the plate electrode at the opening.

18. The semiconductor device according to claim 17, wherein, The first capacitor structure among the plurality of capacitor structures includes a second electrode, and wherein the curved side surface of the extended plate electrode contacts the second electrode.

19. A semiconductor device, comprising: a plurality of word lines along a first direction perpendicular to the surface of a substrate on the substrate, the plurality of word lines being arranged in a second direction intersecting the first direction and a third direction intersecting the second direction, wherein each of the plurality of word lines is at least partially surrounded by a plurality of channel regions and a plurality of capacitor structures, the plurality of channel regions each having an annular shape and being spaced apart from each other in the first direction, wherein the plurality of capacitor structures and the plurality of channel regions are aligned in the first direction, and wherein the plurality of capacitor structures are spaced apart from the plurality of channel regions in the first direction; bit lines extending at one side of the plurality of channel regions and in the third direction; a contact between the first capacitor structure among the plurality of capacitor structures and the first channel region among the plurality of channel regions, the first capacitor structure and the first channel region being adjacent to each other in the first direction; a plate electrode between two word lines among the plurality of word lines adjacent to each other in the second direction; and an extended plate electrode having an annular shape and at least partially surrounding the plate electrode, the extended plate electrode contacting the plate electrode and at least one of the plurality of capacitor structures.

20. The semiconductor device according to claim 19, wherein, At least one of the plurality of channel regions is at the same height as the bit line, and wherein at least one of the plurality of capacitor structures is at the same height as the extended plate electrode.

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