On-chip integrated ferroelectric memory and preparation method and application thereof

Abstract

The invention discloses an on-chip integrated ferroelectric memory device and a preparation method and application thereof, and is characterized in that a BaTiO3 ferroelectric film with gradient thickness change is prepared on a substrate by adopting a high-throughput deposition technology, the film is utilized to realize integration of a resistor, a ferroelectric tunnel junction and a ferroelectric diode, and the device is applied to an artificial neural network as a ferroelectric memristor. And excellent performance is shown. Compared with the prior art, the method has the advantages that the linearity and symmetry of conductance change are optimized through a self-adaptive conductance compensation mechanism, the classification precision and fault tolerance of the neural network are improved, an MNIST handwritten digital data set is used for testing, the classification precision of the optimized FTJ device is improved to 95.7% from 91.3%, and the classification precision of the optimized FTJ device is improved to 95.7% from 91.3%. Compared with the prior art, the method has the advantages that high classification precision can still be kept when the Gaussian noise level is 0.4, experimental basis is provided for design of high-performance neuromorphic electronic devices, and the method is expected to play an important role in the field of brain-like calculation with low power consumption and high efficiency, has very important significance and is good in application prospect.

Description

Technical Field

[0001] The present invention relates to the technical field of ferroelectric memories and application technologies, and particularly to an on-chip integrated ferroelectric memory based on high-throughput BaTiO3 thin films, a preparation method thereof, and an application in neuromorphic computing. Background Art

[0002] With the increasing demand of electronic devices for non-volatile, fast-response, low-power and highly integrated memories, ferroelectric materials have become a research hotspot for next-generation electronic devices due to their spontaneous polarization and non-volatile storage characteristics. Ferroelectric tunnel junctions (FTJs) and ferroelectric diodes (FDs), as potential artificial synaptic devices, show broad application prospects in storage, logic operations and multifunctional integrated circuits. Ferroelectric thin films are the core of these devices, and their thickness directly affects the tunneling current, polarization reversal efficiency and device performance. In FTJs, the tunneling current is closely related to the film thickness, which significantly affects the polarization reversal efficiency and storage performance. Similarly, in FDs, the thickness of the thin film determines the polarization reversal characteristics, which directly affects the current-voltage characteristics and switching performance of the diode. In addition, research is also exploring ferroelectric thin films for neuromorphic computing and synaptic devices. For example, adjusting the film thickness can control the synaptic strength and simulate low-power and efficient biological neural networks. However, in the prior art, the thickness of ferroelectric thin films has a significant impact on their performance, and traditional preparation methods are time-consuming and laborious, making it difficult to efficiently study the thickness-dependent behavior.

[0003] During the process of regulating the memristor conductance by a pulsed voltage, the linearity and symmetry of the conductance increase and decrease are closely related to the noise level of the neural synaptic device. The lower the non-linearity, the higher the classification accuracy. By adjusting the amplitude, duration and interval of the voltage pulses for long-term potentiation (LTP) and long-term depression (LTD), their linear characteristics can be optimized. For example, using gradually increasing voltage pulses can solve the problem of sudden conductance changes in LTD / LTP characteristics. However, these pulse schemes require fine adjustment of the amplitude, duration and interval of the applied voltage pulses, which makes them difficult to implement in large-scale integration. In addition, a single FTJ device usually exhibits high non-linearity during the LTP / LTD process, which limits its recognition accuracy in artificial neural network calculations.

[0004] In summary, in the prior art, it is difficult to optimize the thickness of the ferroelectric layer, the experimental error is large, the non-linearity of the memristor during the LTP / LTD process is high, and it is impossible to integrate resistors, ferroelectric tunnel junctions (FTJs) and ferroelectric diodes (FDs) through a thickness gradient, which greatly affects the polarization reversal efficiency and storage performance, as well as the recognition accuracy in artificial neural network calculations. Summary of the Invention

[0005] The object of the present invention is to provide an on-chip integrated ferroelectric memory, its preparation method and application in view of the deficiencies of the prior art. A BaTiO3 (BTO) ferroelectric thin film with a thickness gradient change is prepared on a single substrate by using a high-throughput deposition technique, and a high-performance ferroelectric memristor integrating a resistor, a ferroelectric tunnel junction (FTJ) and a ferroelectric diode (FD) is formed. The device structure is optimized by an adaptive conductance compensation method to realize the characteristic transformation from a linear resistor to an FTJ and then to an FD, effectively avoiding the complex pulse regulation process. The thickness of the ferroelectric layer can be continuously regulated in a single sample, greatly reducing the non-linearity difficulty of the memristor during the conductance regulation process, so that the influence of the thickness on the device performance can be efficiently studied. This ferroelectric memory shows excellent handwritten digit recognition accuracy in the application of artificial neural network (ANN), which is improved from 91.3% to 95.7%, and still maintains a relatively high fault tolerance under Gaussian noise interference. The present invention provides a new method for the design of high-performance neuromorphic electronic devices, greatly improving the classification accuracy of synaptic devices in neuromorphic computing, enhancing the fault tolerance of the system, and laying a foundation for providing an efficient and highly repeatable preparation method of high-performance electronic synapses for mass production to meet the requirements of different application scenarios, and has good application prospects and commercial development value. (FTJ) and ferroelectric diode (FD) The object of the present invention is achieved as follows: An on-chip integrated ferroelectric storage device, characterized in that the ferroelectric storage device is a ferroelectric tunnel junction (FTJ) unit composed of a ferroelectric layer, a top electrode and a bottom electrode, and the ferroelectric tunnel junction (FTJ) unit and a compensation element are integrated on the same chip to optimize the linearity of the device conductance change; the compensation element adopts a ferroelectric diode (FD) and a linear resistor (R); the ferroelectric layer is a BaTiO3 thin film arranged between the top electrode and the bottom electrode, with a thickness of 1 to 30 unit cells, and shows the characteristics of a resistor, a ferroelectric tunnel junction (FTJ) and a ferroelectric diode (FD) in different thickness regions respectively; the top electrode is a Pt thin film layer with a thickness of 90 to 100 nm; the bottom electrode is a La2 / 3Sr1 / 3MnO3 thin film layer with a thickness of 20 nm.

[0006] A preparation method of an on-chip integrated ferroelectric storage device, characterized in that the preparation of the ferroelectric storage device specifically includes the following steps: Step 1: Preparation of the bottom electrode Grow a layer of La2 / 3Sr1 / 3MnO3 (LSMO) thin film on a SrTiO3 (STO) substrate as the bottom electrode, with a thickness of 20 nm; Step 2: Preparation of the ferroelectric layer Deposit a BaTiO3 (BTO) ferroelectric thin film with a thickness gradient change on the bottom electrode by using a high-throughput deposition technique, with a thickness of 1 to 30 UC; Step 3: Preparation of the protective layer Deposit a LaAlO3 thin film with a thickness of 40 - 50 nm on the BaTiO3 (BTO) ferroelectric thin film as the insulating layer; Step 3: Preparation of the top electrode Use photolithography and lift-off processes to form several holes exposing the ferroelectric layer on the insulating layer, with a size of 5 × 5 μm2, and deposit Pt as the top electrode in the holes, with the size of the Pt electrode being 50 × 50 μm2.

[0007] The high-throughput deposition is a pulsed laser deposition process, with the oxygen pressure controlled at 100 mTorr, and the thickness gradient of the BaTiO3 (BTO) thin film is controlled by moving the mask plate during the deposition process; the deposition temperature of the BaTiO3 (BTO) thin film is 700 °C, and it is naturally cooled after deposition, with a cooling rate of 30 °C / min.

[0008] During the deposition of the La2 / 3Sr1 / 3MnO3 (LSMO) thin film, the oxygen pressure is controlled at 180 mTorr, and the deposition temperature is 800 °C.

[0009] The photolithography process includes: The first step: Use positive photoresist to form holes with a size of 5 × 5 μm2 on the BaTiO3 (BTO) thin film; The second step: Use negative photoresist to form a pattern with a size of 50 × 50 μm2 on the holes.

[0010] An application of an on-chip integrated ferroelectric memory device, characterized in that the ferroelectric memory device is applied in a neuromorphic computing system, which includes multiple ferroelectric memory devices, and the linearity and symmetry of the conductance change are optimized through an adaptive conductance compensation mechanism, thereby improving the classification accuracy and fault tolerance of the neural network.

[0011] The present invention specifically includes: 1) Preparation of a gradient-thickness BaTiO3 thin film The present invention proposes a gradient-thickness BaTiO3 (BTO) thin film based on high-throughput preparation technology. By realizing a thickness gradient in a single sample, the experimental error problem caused by differences between samples in the traditional method is solved. The thickness of the thin film continuously changes from 1 to 30 unit cells (UC), and different thickness regions exhibit different electrical properties.

[0012] 2) Integration of electronic components Integrate three basic electronic components on the same gradient thin film: a linear resistor, a ferroelectric tunnel junction (FTJ), and a ferroelectric diode (FD). By adjusting the thickness of the BTO thin film, the characteristic transformation from a linear resistor to an FTJ and then to an FD is realized, so as to integrate multiple functions in one device.

[0013] 3) Adaptive conductance compensation mechanism The present invention proposes an adaptive conductance compensation mechanism, which compensates for the nonlinearity of FTJ by using the rectifying characteristic of FD and the linear characteristic of resistance. Through this compensation mechanism, the nonlinear behavior of the FTJ device is significantly improved, and its accuracy and fault tolerance in neuromorphic computing are enhanced.

[0014] 4) Application in neuromorphic computing Applying the above integrated device to neuromorphic computing, through the adaptive conductance compensation mechanism, the accuracy of handwritten digit recognition is significantly improved. The recognition accuracy of the uncompensated FTJ device is 91.3%, while that of the FTJ device compensated by FD+R is increased to 95.7%, approaching 97.8% of the ideal device.

[0015] The present invention has the following beneficial technical effects and significant technological progress compared with the prior art: 1) High-throughput preparation technology: By achieving a thickness gradient in a single sample, the experimental error problem caused by differences between samples in the traditional method is effectively solved, and the research efficiency is improved.

[0016] 2) Multifunctional integration: The integration of three basic electronic components, namely resistance, FTJ, and FD, is realized on the same gradient thin film, providing a new idea for the design of multifunctional devices.

[0017] 3) Adaptive conductance compensation: Through the compensation mechanism of FD and resistance, the nonlinear problem of the FTJ device is significantly improved, and the accuracy and fault tolerance of neuromorphic computing are enhanced.

[0018] 4) Application in neuromorphic computing: The invention provides an experimental basis for the design of high-performance neuromorphic electronic devices, and is expected to play an important role in the field of low-power and high-efficiency brain-like computing.

[0019] 5) By optimizing the linearity and symmetry of conductance change through the adaptive conductance compensation mechanism, the classification accuracy and fault tolerance of the neural network are improved. Using the MNIST handwritten digit dataset for testing, the classification accuracy of the optimized FTJ device is increased from 91.3% to 95.7%, and it can still maintain a high classification accuracy when the Gaussian noise level is 0.4. It provides an experimental basis for the design of high-performance neuromorphic electronic devices, is expected to play an important role in the field of low-power and high-efficiency brain-like computing, has very important significance, and has good application prospects. Description of the Drawings

[0020] Figure 1 It is a schematic diagram of the device structure of the gradient BTO thin film; Figure 2For the resistive switching characteristics of the gradient BTO thin film; Figure 3 For the normalized non-linear conductance-pulse curve of the synaptic device of the FTJ; Figure 4 For the accuracy and round graph of the FTJ synaptic device in neuromorphic computing. Detailed implementation manners

[0021] Refer to Figure 1 The ferroelectric memory device is a ferroelectric tunnel junction unit composed of a ferroelectric layer, a top electrode and a bottom electrode, which is integrated with a compensation element on the same chip to optimize the linearity of the device conductance change; the compensation element uses a ferroelectric diode and a linear resistor; the ferroelectric layer is a BaTiO3 thin film disposed between the top electrode and the bottom electrode, with a thickness of 1 to 30 unit cells, and exhibits the characteristics of resistance, ferroelectric tunnel junction and ferroelectric diode in different thickness regions; the top electrode is a Pt thin film layer of 90 - 100 nm; the bottom electrode is a La2 / 3Sr1 / 3MnO3 thin film layer of 20 - 30 nm.

[0022] The present invention is further described in detail through the following specific implementation manners. Embodiment

[0023] Refer to Figure 1 The specific preparation of the on-chip integrated ferroelectric memory device of the BaTiO3 thin film is as follows: I. Preparation of the gradient BTO thin film 1) Preparation of the bottom electrode and the substrate First, a 20-nm-thick La2 / 3Sr1 / 3MnO3 (LSMO) is grown on a (001)-oriented strontium titanate (SrTiO3, STO) substrate by pulsed laser deposition (PLD) technology as the bottom electrode. The growth conditions of the LSMO layer are: deposition temperature 800 °C, oxygen pressure 150 mTorr. The LSMO layer serves as the bottom electrode, providing a good electrical and structural basis for the epitaxial growth of the subsequent BTO thin film.

[0024] 2) Deposition of the gradient BTO thin film On the LSMO layer, the BTO thin film is deposited by moving a mask. The deposition conditions are: temperature 700 °C, oxygen pressure 100 mTorr. The mask moves from right to left, so that the thickness of the BTO thin film gradually increases from left to right, forming a gradient structure with a thickness ranging from 1 to 30 unit cells (UC). By adjusting the moving speed of the mask, the thickness distribution of the gradient thin film can be precisely controlled.

[0025] 3) Post-treatment of the thin film After deposition, the BTO thin film was annealed at a rate of 30 °C / min to optimize the crystalline quality and electrical properties of the thin film.

[0026] II. Device Fabrication Step 1: Preparation of 5×5 μm2 holes 1-1: A positive photoresist (such as AZ5214) was spin-coated on the BTO thin film at a speed of 8000 rpm for 60 s. Before spin-coating, the BTO thin film was dried at a temperature of 90 °C for 60 s.

[0027] 1-2: The substrate spin-coated with photoresist was aligned with the photomask, and ultraviolet light (wavelength 365 nm) was used for exposure for 3 s.

[0028] 1-3: AZ developer was used for development for 50 s to form a square column array of 5×5 μm2.

[0029] 1-4: A 40-nm-thick LaAlO3 (LAO) protective layer was deposited on the developed pattern by pulsed laser deposition (PLD) technology.

[0030] 1-5: A lift-off process was carried out in acetone for about 1 min to form square holes in the LAO layer.

[0031] Step 2: Preparation of the top electrode 2-1: A positive photoresist (such as AZ5214) was spin-coated again on the BTO thin film with LAO square holes and pre-baked at a temperature of 90 °C for 60 s.

[0032] 2-2: The substrate spin-coated with photoresist was aligned with the secondary photomask, and ultraviolet light (wavelength 365 nm) was used for exposure for 3 s.

[0033] 2-3: Post-baking was carried out at a temperature of 130 °C for 30 s.

[0034] 2-4: Flood exposure (wavelength 365 nm, exposure time 8 s) was carried out to activate the image inversion mechanism.

[0035] 2-5: AZ developer was used for development for 50 s to form 50×50 μm2 large holes aligned with the initial 5×5 μm2 pattern.

[0036] 2-6: A 100-nm-thick platinum (Pt) top electrode was deposited at room temperature by pulsed laser deposition (PLD) technology.

[0037] 2-7: A lift-off process was carried out in acetone for about 1 min to complete the preparation of the top electrode.

[0038] III. Electrical Property Measurement and Analysis Refer to Figure 2 , the current-voltage (I-V) characteristics of the devices in different thickness regions were measured. When the BTO thickness is less than 5 UC (Location A), the device exhibits near-ideal ohmic characteristics; when the thickness is greater than 5 UC (Location D), the device shows bipolar resistive switching characteristics of the FTJ, and as the thickness increases, the on / off ratio of the device increases significantly; when the thickness further increases to more than 25 UC (Location I), the I-V characteristics of the device transform into the rectifying characteristics of the FD, showing obvious asymmetry.

[0039] IV. Adaptive Conductance Compensation Mechanism Refer to Figure 3 , in order to improve the performance of the FTJ device in neuromorphic computing, the present invention adopts an adaptive conductance compensation mechanism based on a ferroelectric diode (FD) and a resistor (R). By connecting the FD and the resistor in parallel or in series with the FTJ, the nonlinear behavior of the FTJ can be significantly reduced, making the conductance change of the device closer to the ideal linearity.

[0040] Refer to Figure 4 , the experimental results show that the accuracy rate of the uncompensated FTJ device in handwritten digit recognition is 91.3%, while the accuracy rate of the FTJ device compensated with FD+R is increased to 95.7%. Through the preparation of the above embodiments and their application in the neuromorphic computing system, the experimental results show that a high classification accuracy can still be maintained when the Gaussian noise level is 0.4. The technical solution of the present invention to significantly improve the linearity and symmetry of the memristor through the adaptive conductance compensation mechanism optimizes the device structure and working mechanism, reduces the nonlinearity of the memristor during the conductance regulation process, thereby improving its classification accuracy in neuromorphic computing and enhancing the fault tolerance of the system.

[0041] The above specific embodiments are only for further explaining the present invention, and are not intended to limit the patent of the present invention. All equivalent implementations of the present invention should be included within the scope of the claims of the present invention.

Claims

1. An on-chip integrated ferroelectric memory device, characterized in that, The ferroelectric memory device is a ferroelectric tunnel junction unit composed of a ferroelectric layer, a top electrode, and a bottom electrode. It is integrated with a compensation element on the same chip to optimize the linearity of the device conductance change. The compensation element uses a ferroelectric diode and a linear resistor. The ferroelectric layer is a BaTiO3 thin film disposed between the top electrode and the bottom electrode, with a thickness of 1 to 30 unit cells, and exhibits the characteristics of resistance, ferroelectric tunnel junction, and ferroelectric diode in different thickness regions. The top electrode is a Pt thin film layer with a thickness of 90 - 100 nm. The bottom electrode is a La2 / 3Sr1 / 3MnO3 thin film layer with a thickness of 20 - 30 nm.

2. The preparation method of the on-chip integrated ferroelectric memory device according to claim 1, characterized in that, The preparation of the ferroelectric memory device specifically includes the following steps: Step 1: Preparation of the bottom electrode Grow a layer of La2 / 3Sr1 / 3MnO3 thin film on the SrTiO3 substrate as the bottom electrode, with a thickness of 20 - 30 nm. Step 2: Preparation of the ferroelectric layer Deposit a BaTiO3 ferroelectric thin film with a thickness gradient change by high-throughput deposition on the bottom electrode, with a thickness of 1 - 30 UC. Step 3: Preparation of the protective layer Deposit a LaAlO3 thin film with a thickness of 40 - 50 nm on the BaTiO3 ferroelectric thin film as the insulating layer. Step 3: Preparation of the top electrode Use photolithography and lift-off processes to form several holes exposing the ferroelectric layer on the insulating layer, with a size of 5 × 5 μm2, and deposit Pt as the top electrode in the holes, with a size of the Pt electrode of 50 × 50 μm2.

3. The preparation method of the on-chip integrated ferroelectric memory device according to claim 2, characterized in that, The high-throughput deposition is a pulsed laser deposition process, with the oxygen pressure controlled at 100 mTorr. During the deposition process, the thickness gradient of the BaTiO3 thin film is controlled by moving the mask plate. The deposition temperature of the BaTiO3 thin film is 700°C, and it is naturally cooled after deposition, with a cooling rate of 30°C / min.

4. The preparation method of the on-chip integrated ferroelectric memory device according to claim 2, characterized in that, During the deposition process of the La2 / 3Sr1 / 3MnO3 thin film, the oxygen pressure is controlled at 180 mTorr, and the deposition temperature is 800°C.

5. The method for preparing the on-chip integrated ferroelectric memory device according to claim 2, wherein The photolithography process includes: The first step: Use a positive photoresist to form holes with a size of 5 × 5 μm2 on the BaTiO3 thin film. The second step: Use a negative photoresist to form a pattern with a size of 50 × 50 μm2 on the holes.

6. The application of the on-chip integrated ferroelectric memory device according to claim 1, characterized in that, The application of the ferroelectric memory device in a neuromorphic computing system. The system includes multiple ferroelectric memory devices, and optimizes the linearity and symmetry of the conductance change through an adaptive conductance compensation mechanism, thereby improving the classification accuracy and fault tolerance of the neural network.

Images