Semiconductor memory device including memory cells

Abstract

A semiconductor memory device including memory cells, the semiconductor memory device including: a first memory cell including a first variable resistor element and a first cell transistor connected to the first variable resistor element through a first source-drain; a substrate having a first surface and a second surface opposite to the first surface, the first surface being connected to a second source-drain of the first cell transistor; a first bit line connected to the first source-drain of the first cell transistor through the first variable resistor element; and a first source line disposed on the second surface of the substrate and connected to the second source-drain electrode.

Description

Technical Field

[0001] An exemplary embodiment relates to a semiconductor memory device, and more particularly, to a non-volatile semiconductor memory device configured to reduce read margin errors. Background Art

[0002] A non-volatile semiconductor memory device can retain stored data even when not powered on. Examples of non-volatile semiconductor memory devices include magnetic random access memory (MRAM) and resistive random access memory (RRAM).

[0003] Magnetic random access memory (MRAM) stores data in a memory cell by using a resistance change of a magnetic tunnel junction (MTJ) element. The resistance of the magnetic tunnel junction (MTJ) element changes depending on whether the magnetization direction of the free layer is the same as that of the pinned layer.

[0004] Resistive random access memory (RRAM) stores data by using a resistance change caused by the movement of oxygen vacancies. The resistive random access memory (RRAM) can have different resistances depending on the characteristic that the resistance changes due to a magnetic field change formed in an insulating layer provided between two metal layers.

[0005] Recently, with the increasing demand for the miniaturization, high integration, and fine process development of semiconductor devices, the size (or width) of the metal wires for read or write operations of a memory device has also been decreasing.

[0006] However, in the structure of a memory cell, the resistance of the metal wire increases as the size of the metal wire decreases. The increased resistance reduces the read margin of the memory device. In addition, when the resistance of the metal wire increases, a mismatch in the read margin may occur between the memory cells close to the sense amplifier and those far from the sense amplifier. Therefore, the read operation may not be performed properly. Summary of the Invention

[0007] An exemplary embodiment provides a semiconductor memory device for significantly reducing the resistance of metal wires in a memory cell array and the influence caused by the metal wire resistance.

[0008] According to an exemplary embodiment, a semiconductor memory device includes a first memory cell, a substrate, a first bit line, and a first source line. The first memory cell includes a first variable resistor element and a first cell transistor, and the first cell transistor is connected to the first variable resistor element through a first source-drain. The substrate includes a first surface and a second surface opposite to the first surface, and the first surface is connected to a second source-drain of the first cell transistor. The first bit line is connected to the first source-drain of the first cell transistor through the first variable resistor element. The first source line is disposed on the second surface of the substrate to have a first width and is connected to the second source-drain.

[0009] According to an exemplary embodiment, a semiconductor memory device includes a memory cell array, a first bit line, a first source line, and a substrate. The memory cell array includes a plurality of memory cells, and each memory cell includes a variable resistor element and a cell transistor. The first bit line and the first source line are connected to a first memory cell among the plurality of memory cells. The substrate is connected between the first memory cell and the first source line. The substrate includes a first surface and a second surface opposite to the first surface, and the first surface is adjacent to a first cell transistor. The first bit line is connected to the first cell transistor through a first variable resistor element of the first memory cell. The first source line is disposed on the second surface of the substrate and is connected to the first cell transistor.

[0010] According to an exemplary embodiment, a semiconductor memory device includes a first memory cell, a substrate, a first bit line, a first word line, and a first additional word line. The first memory cell includes a first variable resistor element and a first cell transistor, and the first transistor is connected to the first variable resistor element through a first source-drain. The substrate includes a first surface and a second surface opposite to the first surface, and the first surface is connected to a second source-drain of the first cell transistor. The first bit line is connected to the first source-drain of the first cell transistor through the first variable resistor element. The first word line is disposed on the first surface to be connected to a first gate electrode of the first cell transistor. The first additional word line is disposed on the second surface of the substrate and is connected to the first gate electrode. Description of the Drawings

[0011] The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0012] Figure 1 is a block diagram of a semiconductor memory device according to an exemplary embodiment.

[0013] Figure 2 It is a diagram showing the configuration of a first memory cell included in a memory cell array according to an exemplary embodiment.

[0014] Figure 3A It is a diagram showing a first memory cell including a first variable resistor element according to an exemplary embodiment.

[0015] Figure 3B It is a diagram showing a first memory cell including a first variable resistor element according to an exemplary embodiment.

[0016] Figure 4A It is a top view of a first surface of a substrate according to an exemplary embodiment, on which a plurality of metal lines are provided.

[0017] Figure 4B It shows Figure 4A a bottom view of a second surface of the substrate, on which a first source line is provided.

[0018] Figure 4C It is Figure 4A and Figure 4B a cross-sectional view of the substrate taken along line A-A'.

[0019] Figure 5A It is a top view of a first surface of a substrate according to an exemplary embodiment, on which a plurality of metal lines are provided.

[0020] Figure 5B It shows Figure 5A a bottom view of a second surface of the substrate, on which a first source line is provided.

[0021] Figure 5C It is Figure 5A and Figure 5B a cross-sectional view of the substrate taken along line B-B'.

[0022] Figure 6A It is a top view of a first surface of a substrate according to an exemplary embodiment, on which a plurality of metal lines are provided.

[0023] Figure 6B It shows Figure 6A a bottom view of a second surface of the substrate, on which a first additional word line and a second additional word line are provided.

[0024] Figure 6C It is Figure 6A and Figure 6B a cross-sectional view of the substrate taken along line C-C'.

[0025] Figure 7A It is a top view of a first surface of a substrate according to an exemplary embodiment, on which a plurality of metal lines are provided.

[0026] Figure 7B is a bottom view of a second surface of a substrate, on which a first additional word line and a second additional word line are provided. Figure 7A is a cross-sectional view taken along line D-D' of a substrate of

[0027] Figure 7C and Figure 7A and Figure 7B is a cross-sectional view taken along line E-E' of a substrate of

[0028] Figure 7D is Figure 7A and Figure 7B is a cross-sectional view taken along line F-F' of a substrate of

[0029] Figure 8A is a top view of a first surface of a substrate according to an exemplary embodiment, on which a plurality of metal lines are provided.

[0030] Figure 8B is a bottom view of a second surface of a substrate of Figure 8A on which a first additional word line and a first source line are provided.

[0031] Figure 8C is Figure 8A and Figure 8B is a cross-sectional view taken along line F-F' of a substrate of

[0032] Figure 9 is a circuit diagram showing a configuration in which a control logic circuit reads data stored in a memory cell array using a sense amplifier according to an exemplary embodiment. DETAILED DESCRIPTION

[0033] Hereinafter, exemplary embodiments will be described with reference to the accompanying drawings.

[0034] Figure 1 is a block diagram of a semiconductor memory device according to an exemplary embodiment. Figure 2 is a diagram showing a configuration of a first memory cell included in a memory cell array according to an exemplary embodiment.

[0035] Referring to Figure 1 , a semiconductor memory device 100 according to an exemplary embodiment includes a memory cell array 110, a row decoder 121 (e.g., a first decoder circuit), a column decoder 122 (e.g., a second decoder circuit), and a control logic circuit 150.

[0036] According to an exemplary embodiment, the semiconductor memory device 100 includes a memory cell array 110, which includes a plurality of memory cells MC1 to MCn.

[0037] For example, the memory cell array 110 may include a plurality of memory cells MC1, MC2 to MCn arranged in a matrix of rows and columns. Each of the plurality of memory cells MC1, MC2 to MCn may be connected to a plurality of word lines WL1 to WLn, a plurality of bit lines BL1 to BLn, and a plurality of source lines SL1 to SLn (where n is a positive integer).

[0038] According to an exemplary embodiment, the memory cell array 110 includes non-volatile memory cells.

[0039] For example, the memory cell array 110 may include a plurality of memory cells MC1 to MCn, which are resistive memory cells, such as phase change random access memory (PRAM) cells or resistive random access memory (RRAM) cells, nano floating gate memory (NFGM) cells, polymer random access memory (PoRAM) cells, magnetic random access memory (MRAM) cells, or ferroelectric random access memory (FRAM) cells.

[0040] In addition, according to an exemplary embodiment, the memory cell array 110 may include spin transfer torque magnetoresistive random access memory (STT-MRAM) cells.

[0041] An example will be provided below in which the memory cell array 110 includes spin transfer torque magnetoresistive random access memory (STT-MRAM) cells or resistive random access memory (RRAM) cells.

[0042] At least a portion of the plurality of memory cells MC1, MC2 to MCn may be selected by a row address XADD and a column address YADD.

[0043] For example, at least one word line may be selected by the row address XADD. In addition, at least one bit line and at least one source line may be selected by the column address YADD.

[0044] For example, among the plurality of memory cells MC1, MC2 to MCn, a memory cell connected to the word line selected by the row address XADD and the bit line and source line selected by the column address YADD may be selected.

[0045] According to an exemplary embodiment, the semiconductor memory device 100 includes a row decoder 121 that selects at least a portion of the plurality of word lines WL1 to WLn.

[0046] For example, the row decoder 121 may decode the row address XADD to activate the corresponding word line among the word lines WL1 to WLn.

[0047] In addition, the semiconductor memory device 100 may include a column decoder 122 that selects at least a portion of the plurality of bit lines BL1 to BLn and the plurality of source lines SL1 to SLn that correspond to each other.

[0048] In addition, the semiconductor memory device 100 may include a control logic circuit 150 connected to the row decoder 121 and the column decoder 122.

[0049] The control logic circuit 150 according to an exemplary embodiment may receive commands, addresses, or write data from a processor or a memory controller. The control logic circuit 150 may generate various control signals (e.g., a row address XADD and a column address YADD) in response to the commands and addresses for access operations on the memory cell array 110, such as a programming operation or a read operation.

[0050] For example, the control logic circuit 150 may execute software (or a program) to control at least one other component (e.g., the row decoder 121 or the column decoder 122 of the semiconductor memory device 100) and perform various data processing or operations. The control logic circuit 150 may include a central processing unit or a microprocessor and may control the overall operation of the semiconductor memory device 100. Therefore, it can be understood that the operations performed by the semiconductor memory device 100 are performed under the control of the control logic circuit 150.

[0051] According to an exemplary embodiment, the control logic circuit 150 includes an algorithm for controlling at least a part of the row decoder 121 and the column decoder 122. For example, the algorithm may be software code programmed in the control logic circuit 150. For example, the algorithm may be hard-coded in the control logic circuit 150, but the exemplary embodiment is not limited thereto.

[0052] According to the algorithm, the control logic circuit 150 may store data in each of the plurality of memory cells MC1, MC2 to MCn, or read data stored in each of the plurality of memory cells MC1, MC2 to MCn.

[0053] According to an exemplary embodiment, the control logic circuit 150 may apply a write current to the memory cells selected by the row decoder 121 and the column decoder 122 to store data.

[0054] In addition, the control logic circuit 150 may apply a read current to the memory cells selected by the row decoder 121 and the column decoder 122 to read data stored in the selected memory cells.

[0055] For example, the control logic circuit 150 may determine the resistance values of at least a part of the memory cells included in the memory cell array 110.

[0056] In addition, the control logic circuit 150 may read data stored in the memory cells based on the determined resistance values.

[0057] Among the plurality of memory cells MC1, MC2 to MCn included in the memory cell array 110, they can have different resistance values depending on the applied current or voltage. In addition, the plurality of memory cells MC1, MC2 to MCn can store different data depending on the resistance values.

[0058] Therefore, each of the plurality of memory cells MC1 to MCn included in the memory cell array 110 according to the exemplary embodiment can be referred to as a resistive memory cell. In addition, the semiconductor memory device 100 according to the exemplary embodiment can be referred to as a resistive memory device.

[0059] Reference Figure 2 , the semiconductor memory device 100 (or the memory cell array 110) according to the exemplary embodiment can include a first memory cell MC1 and a substrate 200.

[0060] The first memory cell MC1 can be connected between the substrate 200 and the first bit line BL1. For example, the first memory cell MC1 can be connected between the first bit line BL1 and the first surface 201 of the substrate 200.

[0061] According to the exemplary embodiment, the first memory cell MC1 includes a first variable resistor element VR1 connected to the first bit line BL1.

[0062] The first variable resistor element VR1 can include a plurality of layers L1, L2, and L3.

[0063] The first variable resistor element VR1 can be connected to the first bit line BL1 through the first surface of the first layer L1.

[0064] In addition, the first variable resistor element VR1 can have different resistance values depending on the current applied from at least a part of the first bit line BL1, the first source line SL1, and the first word line WL1.

[0065] According to the exemplary embodiment, the control logic circuit 150 determines the data stored in the first variable resistor element VR1 based on the resistance value of the first variable resistor element VR1.

[0066] For example, the control logic circuit 150 can determine the data stored in the first variable resistor element VR1 based on the resistance value formed by at least a part of the plurality of layers L1, L2, and L3.

[0067] For example, when the first variable resistor element VR1 has a high resistance value (or a resistance value higher than the threshold) due to the current applied from at least a part of the first bit line BL1, the first source line SL1, and the first word line WL1, the control logic circuit 150 can read the data "1".

[0068] For example, when the first variable resistor element VR1 has a low resistance value (or a resistance value less than or equal to a threshold value) due to current applied from at least a part of the first bit line BL1, the first source line SL1, and the first word line WL1, the control logic circuit 150 may read the data "0".

[0069] Although this example describes how the control logic circuit 150 may determine the data stored in the first variable resistor element VR1 based on the resistance value of the first variable resistor element VR1, the exemplary embodiments are not limited thereto.

[0070] In addition, the first memory cell MC1 according to the exemplary embodiment includes a first cell transistor CT1 connected between the first variable resistor element VR1 and the substrate 200.

[0071] For example, the first memory cell MC1 may include a first cell transistor CT1 connected between the first variable resistor element VR1 and the first surface 201 of the substrate 200.

[0072] The first source-drain SD1 of the first cell transistor CT1 may be connected to the first variable resistor element VR1. For example, the first source-drain SD1 of the first cell transistor CT1 may be connected to the first variable resistor element VR1 through a surface of the second layer L2.

[0073] For example, the first variable resistor element VR1 may be connected between the first bit line BL1 and the first source-drain SD1 of the first cell transistor CT1. In addition, the first bit line BL1 may be connected to the first source-drain SD1 of the first cell transistor CT1 through the first variable resistor element VR1.

[0074] The second source-drain SD2 of the first cell transistor CT1 may be connected to the first surface 201 of the substrate 200.

[0075] In addition, the semiconductor memory device 100 according to the exemplary embodiment may include a first source line SL1 provided on a second surface 202 parallel to the first surface 201 of the substrate 200. For example, the semiconductor memory device 100 may include a first source line SL1 having a first width W1 formed on the second surface 202 of the substrate 200.

[0076] The second source-drain SD2 of the first cell transistor CT1 may be connected to the first source line SL1 formed on the second surface 202 of the substrate 200.

[0077] In an embodiment, the second source-drain SD2 is connected to a first source line SL1 formed on a second surface 202 of a substrate 200 through a back contact (or a conductive via), and the back contact (or the conductive via) is formed from the second surface 202 into the substrate 200.

[0078] In another embodiment, the second source-drain SD2 is connected to a first source line SL1 formed on a second surface 202 of a substrate 200 through a back contact (or a conductive via), and the back contact (or the conductive via) is formed from the second surface 202 through at least a part of the substrate 200.

[0079] Therefore, the first source line SL1 formed on the second surface 202 of the substrate 200 can be connected to the second source-drain SD2 of the first unit transistor CT1. In addition, the first source line SL1 can be connected to a first variable resistor element VR1 through the first unit transistor CT1.

[0080] In addition, a first gate electrode G1 of the first unit transistor CT1 can be connected to a first word line WL1.

[0081] According to an exemplary embodiment, the first unit transistor CT1 can be controlled based on a voltage applied from the first word line WL1 through the first gate electrode G1.

[0082] For example, the first unit transistor CT1 can be turned on or off based on a voltage applied from the first word line WL1.

[0083] For example, the first word line WL1 can be formed on the first surface 201. For example, the first word line WL1 can be formed at a predetermined distance from the first surface 201.

[0084] Referring to the above configuration, a semiconductor memory device 100 according to an exemplary embodiment can include a first memory cell MC1 and a first bit line BL1 disposed on a first surface 201 of a substrate 200.

[0085] In addition, the semiconductor memory device 100 can include a first source line SL1 disposed on the second surface 202 and parallel to the first surface 201 of the substrate 200 to be connected to the first unit transistor CT1.

[0086] Compared with the case where it is formed on the first surface 201 together with the first memory cell MC1, the first word line WL1, and the first bit line BL1, the first source line SL1 can have a relatively large area (or width).

[0087] Therefore, the semiconductor memory device 100 according to an exemplary embodiment can significantly reduce the resistance value of the first source line SL1.

[0088] In addition, with reference to the above configuration, the first word line WL1 and / or the first bit line BL1 may have a relatively large area (or width) compared to the case where they are formed together with the first source line SL1 on the first surface 201.

[0089] Therefore, the semiconductor memory device 100 according to the exemplary embodiment can significantly reduce the resistance value of the first word line WL1 and / or the first bit line BL1.

[0090] In summary, the semiconductor memory device 100 can reduce the resistance value of the metal line connected to the first memory cell MC1 by the first source line SL1 provided on the second surface 202.

[0091] Due to the above configuration, the semiconductor memory device 100 can improve the power efficiency of the operation of reading the data stored in the first memory cell MC1.

[0092] For example, the semiconductor memory device 100 can reduce the read margin of the first memory cell MC1.

[0093] In addition, with reference to the above configuration, the first memory cell MC1 may have a relatively small area compared to the case where it is formed together with the first bit line BL1 and the first source line SL1 on the first surface 201.

[0094] Therefore, the semiconductor memory device 100 according to the exemplary embodiment can significantly reduce the size of the first memory cell MC1.

[0095] Figure 3A is a diagram showing a first memory cell including a first variable resistor element according to an exemplary embodiment, and Figure 3B is a diagram showing a first memory cell including a first variable resistor element according to an exemplary embodiment.

[0096] With reference to Figure 3A and Figure 3B , the first memory cell MC1a or MC1b according to the exemplary embodiment may include a first variable resistor element 310 or 320, which has different resistance values depending on the current applied from at least one of the first bit line BL1, the first source line SL1, and the first word line WL1.

[0097] Figure 3A and Figure 3B , the first memory cells MC1a and MC1b and the first variable resistor elements 310 and 320 shown in Figure 2 may be respectively understood as examples of the first memory cell MC1 and the first variable resistor element VR1 shown in

[0098] With reference toFigure 3A , the first variable resistor element 310 may include a first magnetic layer 311 and a second magnetic layer 312. In addition, the first variable resistor element 310 may include a tunnel layer 313 disposed between the first magnetic layer 311 and the second magnetic layer 312.

[0099] In an embodiment, the magnetization direction of the second magnetic layer 312 is fixed. In addition, the magnetization direction of the first magnetic layer 311 may be parallel or antiparallel to the magnetization direction of the second magnetic layer 312 depending on the situation.

[0100] Therefore, for example, the first magnetic layer 311 may be referred to as a free layer, while the second magnetic layer 312 may be referred to as a pinned layer.

[0101] During a read operation of the first memory cell MC1, the control logic circuit 150 may apply a logic high voltage to the first word line WL1. The first cell transistor CT1 may be turned on in response to the logic high voltage applied to the first word line WL1.

[0102] In addition, the control logic circuit 150 may apply a read current to the first source line SL1 in the direction of the first bit line BL1 to measure the resistance value of the first variable resistor element 310. The control logic circuit 150 may determine the data stored in the first variable resistor element 310 based on the measured resistance value.

[0103] For example, when the magnetization direction of the first magnetic layer 311 is parallel to the magnetization direction of the second magnetic layer 312, the first variable resistor element 310 may have a low resistance value. In an exemplary embodiment, when the first variable resistor element 310 has a low resistance value, the control logic circuit 150 may read the data "0" from the first variable resistor element 310.

[0104] For example, when the magnetization direction of the first magnetic layer 311 is antiparallel to the magnetization direction of the second magnetic layer 312, the first variable resistor element 310 may have a high resistance value. In an exemplary embodiment, when the first variable resistor element 310 has a high resistance value, the control logic circuit 150 may read the data "1" from the first variable resistor element 310.

[0105] Therefore, in an exemplary embodiment, the first variable resistor element 310 may be referred to as a magnetic tunnel junction (MTJ) element. In addition, the first memory cell MC1a may be referred to as a MRAM memory cell.

[0106] Although the first magnetic layer 311 and the second magnetic layer 312 of the first variable resistor element 310 are shown as horizontal magnetic elements in FIG. 3, the exemplary embodiment is not limited thereto. For example, the first magnetic layer 311 and the second magnetic layer 312 may be implemented as vertical magnetic elements.

[0107] Reference Figure 3B The first variable resistor element 320 may include a first metal layer 321 and a second metal layer 322. In addition, the first variable resistor element 320 may include an insulating layer 323 formed between the first metal layer 321 and the second metal layer 322.

[0108] The control logic circuit 150 may apply a voltage to the first bit line BL1. Therefore, the control logic circuit 150 may generate a potential difference between the first bit line BL1 and the first source line SL1.

[0109] A potential difference may be generated between the first metal layer 321 and the second metal layer 322 by the potential difference between the first bit line BL1 and the first source line SL1.

[0110] In addition, the first variable resistor element 320 may have different resistance values depending on the magnetic field E formed in the insulating layer 323 by the potential difference between the first metal layer 321 and the second metal layer 322.

[0111] For example, when the potential difference between the first metal layer 321 and the second metal layer 322 does not form a conductive path in the insulating layer 323, the first variable resistor element 320 may have a high resistance value. In an exemplary embodiment, when the first variable resistor element 320 has a high resistance value, the control logic circuit 150 may read data "0" from the first variable resistor element 320.

[0112] For example, when the potential difference between the first metal layer 321 and the second metal layer 322 forms a conductive path in the insulating layer 323, the first variable resistor element 320 may have a low resistance value. In an exemplary embodiment, when the first variable resistor element 320 has a low resistance value, the control logic circuit 150 may read data "1" from the first variable resistor element 320.

[0113] Therefore, in an exemplary embodiment, the first variable resistor element 320 may be referred to as a metal-insulator-metal (MIM) element. In addition, the first memory cell MC1b may be referred to as a RRAM memory cell.

[0114] Referring to the above configuration, the first memory cell MC1a or MC1b according to an exemplary embodiment may be referred to as a MRAM memory cell or a RRAM memory cell including a resistor element.

[0115] In addition, according to an exemplary embodiment, the first unit transistor CT1, the first variable resistor element 310 or 320, the first word line WL1, and the first bit line BL1 may be disposed on the first surface 201 of the substrate 200.

[0116] For example, at least a portion of the first unit transistor CT1, the first variable resistor elements 310 or 320, the first word line WL1, and the first bit line BL1 may be disposed adjacent to the first surface 201 of the substrate 200.

[0117] In an embodiment, the first source line SL1 is disposed on the second surface 202 of the substrate 200 and is parallel to the first surface 201.

[0118] Thus, compared with the case where it is formed on the first surface 201 of the substrate 200 together with the first memory cell MC1, the first word line WL1, and the first bit line BL1, the first source line SL1 may have a relatively large width (or area).

[0119] Therefore, the semiconductor memory device 100 according to the exemplary embodiment can reduce the resistance value of the first source line SL1.

[0120] In addition, referring to the above configuration, compared with the case where the first word line WL1 and / or the first bit line BL1 are formed on the first surface 201 of the substrate 200 together with the first source line, the first word line WL1 and / or the first bit line BL1 may have a relatively large width (or area).

[0121] Therefore, the semiconductor memory device 100 according to the exemplary embodiment can significantly reduce the resistance value of the first word line WL1 and / or the first bit line BL1.

[0122] Therefore, due to the above configuration, the semiconductor memory device 100 can improve the power efficiency of the operation of reading the data stored in the first memory cell MC1a or MC1b.

[0123] For example, the semiconductor memory device 100 can reduce the read margin of the first memory cell MC1a or MC1b.

[0124] Figure 4A is a top view of the first surface of a substrate according to an exemplary embodiment, on which a plurality of metal lines are disposed. Figure 4B is a view showing Figure 4A a bottom view of the second surface of the substrate on which the first source line is disposed. Figure 4C is Figure 4A and Figure 4B a cross-sectional view of the substrate taken along line A-A'.

[0125] Referring to Figures 4A to 4C , the memory cell array 110A according to the exemplary embodiment includes a first memory cell MC1 and a second memory cell MC2 disposed adjacent to each other.

[0126] Figures 4A to 4C The memory cell array 110A and the first memory cell MC1 shown inFigure 2 An example of the memory cell array 110 and the first memory cell MC1 shown therein.

[0127] Therefore, the same or substantially the same components are denoted by the same reference numerals, and redundant descriptions thereof will be omitted.

[0128] Reference Figure 4A , according to an example embodiment, the memory cell array 110A includes a second memory cell MC2 disposed adjacent to the first memory cell MC1.

[0129] For example, the memory cell array 110A may include a second memory cell MC2 disposed adjacent to the first memory cell MC1 in a first direction (e.g., the positive X direction).

[0130] According to an example embodiment, a first bit line BL1, a second bit line BL2, a first word line WL1, and a second word line WL2 are formed on a first surface 201 of the substrate 200.

[0131] For example, each of the first word line WL1 and the second word line WL2 may be formed to extend in a second direction (e.g., the positive Y direction) perpendicular to the first direction (e.g., the positive X direction) on the first surface 201 of the substrate 200. For example, the first bit line BL1 may overlap with the first source-drain SD1 and the first word line WL1; and the second bit line BL2 may overlap with the third source-drain SD3 and the second word line WL2.

[0132] For example, the first bit line BL1 and the second bit line BL2 may be formed to extend in the first direction (e.g., the positive X direction).

[0133] However, the shapes and arrangements of the first bit line BL1, the second bit line BL2, the first word line WL1, and the second word line WL2 are not limited to the above examples.

[0134] In addition, the first source-drain SD1 to the third source-drain SD3 may be formed to penetrate at least a part of the surface and the interior of the substrate 200. For example, the first source-drain SD1 to the third source-drain SD3 may be formed to extend from the first surface 201 of the substrate 200 into the interior of the substrate 200. For example, the first source-drain SD1 to the third source-drain SD3 may be located inside the substrate 200 and contact the first surface 201.

[0135] Reference Figure 4B , according to an example embodiment, the first source line SL1 is disposed on a second surface 202 of the substrate 200. For example, the second surface 202 may be opposite to the first surface 201.

[0136] For example, the first source line SL1 may be formed on the second surface 202 of the substrate 200 to have a first width W1 and extend in a first direction (e.g., the positive X direction). The first width W1 may be arranged in a second direction (e.g., the Y direction).

[0137] In an embodiment, the first source line SL1 is formed to pass through regions corresponding to each of the first memory cell MC1 and the second memory cell MC2 on the second surface 202 of the substrate 200.

[0138] Reference Figure 4A and Figure 4B and, when viewed from a third direction (e.g., the positive Z direction) perpendicular to the first direction (e.g., the positive X direction) and the second direction (e.g., the positive Y direction), the first source line SL1 according to the exemplary embodiment is formed to overlap at least a portion of the first bit line BL1 and the second bit line BL2.

[0139] Reference Figure 4C and, according to the exemplary embodiment, the first memory cell MC1 includes a first variable resistor element VR1 connected to the first bit line BL1. The variable resistor element VR1 may be a variable resistor or a potentiometer.

[0140] The memory cell array 110A may include a first front contact FC1 disposed on the first surface 201 of the substrate 200. The first front contact FC1 may be a conductor or include a conductive material. In addition, the memory cell array 110A may include a first metal line ML1 stacked on the first front contact FC1.

[0141] According to the exemplary embodiment, the first variable resistor element VR1 is disposed on the first metal line ML1. Thus, the first variable resistor element VR1 may be connected to the first source-drain SD1 through the first metal line ML1 and the first front contact FC1.

[0142] Reference Figure 4C and, according to the exemplary embodiment, the first memory cell MC1 includes a first variable resistor element VR1 connected to the first bit line BL1.

[0143] The memory cell array 110A may include a first front contact FC1 disposed on the first surface 201 of the substrate 200. In addition, the memory cell array 110A may include a first metal line ML1 stacked on the first front contact FC1.

[0144] According to the exemplary embodiment, the first variable resistor element VR1 is disposed on the first metal line ML1. Thus, the first variable resistor element VR1 may be connected to the first source-drain SD1 through the first metal line ML1 and the first front contact FC1.

[0145] According to an exemplary embodiment, at least a portion of the first metal line ML1 and the first front contact FC1 is omitted. Accordingly, the first variable resistor element VR1 can be connected to the first source-drain SD1 through at least a portion of the first metal line ML1 and the first front contact FC1.

[0146] In addition, the first bit line BL1 can be connected to the first source-drain SD1 through the first variable resistor element VR1, the first metal line ML1, and the first front contact FC1.

[0147] For example, the first variable resistor element VR1 can be connected between the first bit line BL1 and the first source-drain SD1.

[0148] Reference Figure 2 and Figure 4C and, the first source-drain SD1, the first gate electrode G1, and the second source-drain SD2 can form a first unit transistor CT1.

[0149] The first gate electrode G1 of the first unit transistor CT1 can be connected to a first word line WL1 provided on the first surface 201 of the substrate 200.

[0150] In addition, the second source-drain SD2 of the first unit transistor CT1 can be connected to a first source line SL1 provided on the second surface 202 of the substrate 200.

[0151] In an embodiment, the second source-drain SD2 of the first unit transistor CT1 is connected to the first source line SL1 through a first back contact BC1 that passes through at least a portion inside the substrate 200 via the second surface 202 of the substrate 200. The first back contact BC1 can be a conductor or include a conductive material.

[0152] In addition, a second memory cell MC2 according to an exemplary embodiment includes a second variable resistor element VR2 connected to a second bit line BL2. For example, the second variable resistor element VR2 can be a variable resistor or a potentiometer.

[0153] The memory cell array 110A can include a second front contact FC2 provided on the first surface 201 of the substrate 200. Additionally, the memory cell array 110A can include a second metal line ML2 stacked on the second front contact FC2. The second front contact FC2 can be a conductor or include a conductive material.

[0154] According to an exemplary embodiment, the second variable resistor VR2 is provided on the second metal line ML2. Accordingly, the second variable resistor VR2 can be connected to a third source-drain SD3 through the second metal line ML2 and the second front contact FC2.

[0155] However, according to the exemplary embodiment, at least a part of the second metal line ML2 and the second front contact FC2 is omitted. Accordingly, the second variable resistor VR2 can be connected to the third source-drain SD3 through at least a part of the second metal line ML2 and the second front contact FC2.

[0156] The second bit line BL2 can be connected to the third source-drain SD3 through the second variable resistor VR2, the second metal line ML2, and the second front contact FC2.

[0157] For example, the second variable resistor VR2 can be connected between the second bit line BL2 and the third source-drain SD3.

[0158] Reference Figure 1 and Figure 4C , the second source-drain SD2, the second gate electrode G2, and the third source-drain SD3 can form a second unit transistor CT2.

[0159] Accordingly, the second gate electrode G2 of the second unit transistor CT2 can be connected to the second word line WL2 provided on the first surface 201 of the substrate 200.

[0160] In addition, the second source-drain SD2 of the second unit transistor CT2 can be connected to the first source line SL1 provided on the second surface 202 of the substrate 200.

[0161] For example, the second source-drain SD2 of the second unit transistor CT2 can be connected to the first source line SL1 through the first back contact BC1.

[0162] Referring to the above configuration, the first unit transistor CT1 and the second unit transistor CT2 according to the embodiment share the second source-drain SD2. Additionally, the first memory cell MC1 and the second memory cell MC2 can share the first source line SL1.

[0163] Accordingly, compared with the case where source lines are separately provided for each of the first memory cell MC1 and the second memory cell MC2, the semiconductor memory device 100 according to the exemplary embodiment can include a memory cell array 110A having a relatively small area. For example, since the first memory cell MC1 and the second memory cell MC2 share the first source line SL1, only one source line instead of two source lines is required to support two memory cells.

[0164] In addition, compared with the case where the semiconductor memory device 100 is provided on the first surface 201 together with the first bit line BL1, the second bit line BL2, the first word line WL1, the second word line WL2, and the first source line SL1, the semiconductor memory device 100 can include a memory cell array 110A having a relatively small area.

[0165] As compared with the case where they are disposed on the first surface 201 together with the first bit line BL1, the second bit line BL2, the first word line WL1, the second word line WL2, and the first source line SL1, each of them may have a relatively large area.

[0166] As compared with the case where they are disposed on the first surface 201 together with the first bit line BL1, the second bit line BL2, the first word line WL1, the second word line WL2, and the first source line SL1, at least a part of the first front contact FC1, the second front contact FC2, and the first back contact BC1 may have a relatively large area.

[0167] Accordingly, the semiconductor memory device 100 may reduce the resistance value of at least a part of the components (e.g., MC1 or MC2) included in each memory cell. For example, when the semiconductor memory device 100 includes a memory cell array according to an embodiment of the inventive concept described herein, its resistance value may be a first value, but when it includes a previous memory cell array, its resistance value may be a second value higher than the first value.

[0168] Accordingly, the semiconductor memory device 100 may improve the power efficiency of an operation of reading data from each memory cell (e.g., MC1 or MC2) of the memory cell array 110A.

[0169] Figure 5A is a top view showing a first surface of a substrate according to an exemplary embodiment, on which a plurality of metal lines are disposed; Figure 5B is a view showing Figure 5A a second surface of the substrate, on which a first source line is disposed, and Figure 5C is Figure 5A and 5B a cross-sectional view of the substrate taken along line B - B'.

[0170] Referring Figures 5A to 5C , the memory cell array 110B according to the exemplary embodiment includes a second source line SL2 disposed on the first surface 201 and a first source line SL1 disposed on the second surface 202.

[0171] Figures 5A to 5C The memory cell array 110B and the first memory cell MC1 shown in Figure 2 may be understood as examples of the memory cell array 110 and the first memory cell MC1 shown in Figures 5A to 5C . Additionally, Figures 4A to 4C the second memory cell MC2 shown in

[0172] Accordingly, the same or substantially the same components are denoted by the same reference numerals, and redundant descriptions thereof will be omitted.

[0173] According to an example embodiment, the memory cell array 110B includes a second memory cell MC2 disposed adjacent to the first memory cell MC1. For example, the memory cell array 110B may include a second memory cell MC2 disposed adjacent to the first memory cell MC1 in a first direction (e.g., the positive X direction).

[0174] According to an example embodiment, a first bit line BL1, a second bit line BL2, a first word line WL1, a second word line WL2, and a second source line SL2 are formed on a first surface 201 of a substrate 200.

[0175] In an embodiment, the second source line SL2 is formed on the first surface 201. The second source line SL2 may extend in a first direction (e.g., the positive X direction). In an embodiment, the second source line SL2 has a second width W2 in a second direction (e.g., the positive Y direction), and the second width W2 is less than the first width W1.

[0176] In addition, the first source-drain SD1 to the third source-drain SD3 may be formed to penetrate at least a part of the surface and the interior of the substrate 200. For example, the first source-drain SD1 to the third source-drain SD3 may be formed to extend from the first surface 201 into the interior of the substrate 200. For example, the first source-drain SD1 to the third source-drain SD3 may extend into the interior of the substrate 200.

[0177] Reference Figure 5B According to an example embodiment, the first source line SL1 is disposed on a second surface 202 of the substrate 200.

[0178] For example, the first source line SL1 may be formed on the second surface 202 of the substrate 200, may extend in a first direction (e.g., the positive X direction), and have a first width W1 in a second direction (e.g., the positive Y direction).

[0179] Reference Figure 5A and Figure 5B According to an example embodiment, the second source line SL2 is formed to have a second width W2 that is less than the first width W1 of the first source line SL1. The widths W1 and W2 may be in a second direction (e.g., the positive Y direction).

[0180] Reference Figure 5C According to an example embodiment, the first memory cell MC1 includes a first variable resistor VR1 connected to the first bit line BL1.

[0181] According to an exemplary embodiment, a first variable resistor VR1 is connected to a first source-drain SD1 through a first metal line ML1 and a first front contact FC1. In addition, a first bit line BL1 may be connected to the first source-drain SD1 through the first variable resistor VR1, the first metal line ML1, and the first front contact FC1.

[0182] A second memory cell MC2 according to an exemplary embodiment includes a second variable resistor VR2 connected to a second bit line BL2.

[0183] According to an exemplary embodiment, the second variable resistor VR2 is connected to a third source-drain SD3 through a second metal line ML2 and a second front contact FC2. In addition, the second bit line BL2 may be connected to the third source-drain SD3 through the second variable resistor VR2, the second metal line ML2, and the second front contact FC2.

[0184] In an embodiment, the memory cell array 110B includes a connection member CM formed to penetrate the substrate 200. For example, the memory cell array 110B may include a connection member CM formed to penetrate the substrate 200 from the second surface 202. In an embodiment, the connection member CM is a conductor or includes a conductive material.

[0185] The connection member CM may be connected to a first source line SL1 through the second surface 202. In addition, the connection member CM may be connected to a third front contact FC3 provided on the first surface 201 through the first surface 201.

[0186] A second source line SL2 may be provided on the third front contact FC3.

[0187] Accordingly, the first source line SL1 and the second source line SL2 may be connected to each other through the connection member CM penetrating the substrate 200 and the third front contact FC3. In an embodiment, the connection member CM is a conductor or a conductive element.

[0188] For example, the connection member CM may be referred to as a small power tap cell (sPTC), but the exemplary embodiment is not limited thereto.

[0189] Reference Figure 2 and Figure 5C , the first source-drain SD1, the first gate electrode G1, and the second source-drain SD2 may constitute a first unit transistor CT1.

[0190] The first gate electrode G1 of the first unit transistor CT1 may be connected to a first word line WL1 provided on the first surface 201 of the substrate 200.

[0191] Reference Figure 1 and Figure 5C, the second source-drain SD2, the second gate electrode G2, and the third source-drain SD3 can form a second unit transistor CT2.

[0192] The second gate electrode G2 of the second unit transistor CT2 can be connected to a second word line WL2 provided on the first surface 201 of the substrate 200.

[0193] According to an exemplary embodiment, the second source-drain SD2 is connected to a first source line SL1 and a second source line SL2.

[0194] For example, the second source-drain SD2 can be connected to the first source line SL1 and the second source line SL2 through a connection member CM.

[0195] For example, the second source-drain SD2 can be connected to the first source line SL1 provided on the second surface 202 of the substrate 200 through at least a part of the connection member CM. In addition, the second source-drain SD2 can be connected to the second source line SL2 provided on the first surface 201 of the substrate 200 through at least a part of the connection member CM.

[0196] Referring to the above configuration, the first unit transistor CT1 and the second unit transistor CT2 according to an exemplary embodiment can share the second source-drain SD2. Additionally, the first memory cell MC1 and the second memory cell MC2 can share the first source line SL1 and the second source line SL2 to which they are connected to each other.

[0197] Therefore, compared with the case of additionally including source lines for each of the first memory cell MC1 and the second memory cell MC2, the semiconductor memory device 100 according to an exemplary embodiment can include a memory cell array 110B having a relatively small area.

[0198] In addition, the semiconductor memory device 100 can increase the area of the source lines connected to the first memory cell MC1 and the second memory cell MC2 through the source lines SL1 and SL2 respectively provided on the first surface 201 and the second surface 202.

[0199] Therefore, the semiconductor memory device 100 can reduce the resistance values of the source lines SL1 and SL2 connected to each memory cell (e.g., MC1 or MC2) of the memory cell array 110B.

[0200] Therefore, the semiconductor memory device 100 according to an exemplary embodiment can improve the power efficiency of the operation of reading data from each memory cell (e.g., MC1 or MC2) of the memory cell array 110B.

[0201] In addition, the semiconductor memory device 100 may improve the accuracy of operations for reading data from each memory cell (e.g., MC1 or MC2) of the memory cell array 110B.

[0202] Figure 6A is a top view showing a first surface of a substrate according to an exemplary embodiment, on which a plurality of metal lines are provided; Figure 6B shows Figure 6A a bottom view of a second surface of the substrate on which a first additional word line and a second additional word line are provided; and Figure 6C is Figure 6A and Figure 6B a cross-sectional view of the substrate taken along line C-C'.

[0203] Referring to Figures 6A to 6C , the memory cell array 110C according to the exemplary embodiment includes a first additional word line AWL1 and a second additional word line AWL2 formed on the second surface 202 of the substrate 200.

[0204] Figures 6A to 6C The memory cell array 110C and the first memory cell MC1 shown in Figure 2 can be understood as examples of the memory cell array 110 and the first memory cell MC1 shown in Figures 6A to 6C . Additionally, the second memory cell MC2 shown in Figures 4A to 4C can be understood as an example of the second memory cell MC2 shown in

[0205] Therefore, the same or substantially the same components are denoted by the same reference numerals, and redundant descriptions thereof will be omitted.

[0206] According to the exemplary embodiment, the memory cell array 110C includes a second memory cell MC2 disposed adjacent to the first memory cell MC1.

[0207] A first bit line BL1, a second bit line BL2, a first word line WL1, a second word line WL2, and a first source line SL1 may be formed on the first surface 201 of the substrate 200.

[0208] For example, each of the first word line WL1 and the second word line WL2 may be formed to extend in a first direction (e.g., the positive X direction) perpendicular to a second direction (e.g., the positive Y direction) on the first surface 201 of the substrate 200.

[0209] In addition, for example, the first source line SL1 may be formed to extend in the first direction (e.g., the positive X direction) on the first surface 201.

[0210] In addition, the first source-drain SD1 to the third source-drain SD3 may be formed to extend from the first surface 201 of the substrate 200 into the substrate 200. For example, the first source-drain SD1 to the third source-drain SD3 may extend inside the substrate 200.

[0211] Reference Figure 6B , according to the exemplary embodiment, the first additional word line AWL1 and the second additional word line AWL2 are disposed on the second surface 202 of the substrate 200.

[0212] For example, each of the first additional word line AWL1 and the second additional word line AWL2 may be formed to extend along a second direction (e.g., the positive Y direction) on the second surface 202 of the substrate 200. The first additional word line AWL1 and the second additional word line AWL2 may be spaced apart from each other in a first direction (e.g., the X direction).

[0213] However, the arrangement of the first additional word line AWL1 and the second additional word line AWL2 is not limited to the above example.

[0214] Reference Figure 6C , according to the exemplary embodiment, the first memory cell MC1 includes a first variable resistor element VR1 connected to the first bit line BL1.

[0215] According to the exemplary embodiment, the first variable resistor element VR1 is connected to the first source-drain SD1 through a first metal line ML1 and a first front contact FC1. In addition, the first bit line BL1 may be connected to the first source-drain SD1 through the first variable resistor element VR1, the first metal line ML1, and the first front contact FC1.

[0216] For example, the first variable resistor element VR1 may be connected between the first bit line BL1 and the first source-drain SD1.

[0217] In addition, the second memory cell MC2 according to the exemplary embodiment includes a second variable resistor element VR2 connected to the second bit line BL2.

[0218] According to the exemplary embodiment, the second variable resistor element VR2 is connected to the third source-drain SD3 through a second metal line ML2 and a second front contact FC2. In addition, the second bit line BL2 may be connected to the third source-drain SD3 through the second variable resistor element VR2, the second metal line ML2, and the second front contact FC2.

[0219] For example, the second variable resistor element VR2 may be connected between the second bit line BL2 and the third source-drain SD3.

[0220] Reference Figure 2 and Figure 6C, a first source-drain SD1, a first gate electrode G1, and a second source-drain SD2 may form a first unit transistor CT1.

[0221] According to an exemplary embodiment, the first gate electrode G1 of the first unit transistor CT1 is connected to a first word line WL1 and a first additional word line AWL1.

[0222] For example, the first gate electrode G1 may be connected to the first word line WL1 disposed on the first surface 201 of the substrate 200.

[0223] In addition, the first gate electrode G1 may be connected to the first additional word line AWL1 disposed on the second surface 202 of the substrate 200.

[0224] In an embodiment, the first additional word line AWL1 is connected to the first gate electrode G1 through a second back contact BC2 formed to extend into the interior of the substrate 200 through the second surface 202 of the substrate 200. For example, the second back contact BC2 may extend inside the substrate 200. The second back contact BC2 may be a conductor or include a conductive material.

[0225] In addition, the first source line SL1 may be connected to the second source-drain SD2 through a third front contact FC3 formed on the first surface 201.

[0226] Reference Figure 1 and Figure 6C , a second source-drain SD2, a second gate electrode G2, and a third source-drain SD3 may form a second unit transistor CT2.

[0227] According to an exemplary embodiment, the second gate electrode G2 of the second unit transistor CT2 is connected to a second word line WL2 and a second additional word line AWL2.

[0228] For example, the second gate electrode G2 may be connected to the second word line WL2 disposed on the first surface 201 of the substrate 200.

[0229] In addition, the second gate electrode G2 may be connected to the second additional word line AWL2 disposed on the second surface 202 of the substrate 200.

[0230] In an embodiment, the second additional word line AWL2 is connected to the second gate electrode G2 through a third back contact BC3 formed to extend into the interior of the substrate 200 through the second surface 202 of the substrate 200. For example, the third back contact BC3 may extend inside the substrate 200. The third back contact BC3 may be a conductor or include a conductive material.

[0231] Referring to the above configuration, each of the first memory cell MC1 and the second memory cell MC2 according to the exemplary embodiment may be connected to a word line having a large area.

[0232] For example, compared with the case where it is only connected to the first word line WL1 provided on the first surface 201, the first memory cell MC1 may be connected to the word lines WL1 and AWL1 having a relatively large area.

[0233] In addition, for example, compared with the case where it is only connected to the second word line WL2 provided on the first surface 201, the second memory cell MC2 may be connected to the word lines WL2 and AWL2 both having a large area.

[0234] For example, the semiconductor memory device 100 may increase the area of the word lines connected to each memory cell (e.g., MC1 or MC2) by the additional word lines AWL1 and AWL2 provided on the second surface 202.

[0235] Therefore, the semiconductor memory device 100 according to the exemplary embodiment may reduce the resistance values of the word lines WL1, WL2, AWL1, and AWL2 connected to each memory cell (e.g., MC1 or MC2) of the memory cell array 110C.

[0236] Therefore, the semiconductor memory device 100 may improve the power efficiency of the operation of reading data from each memory cell (e.g., MC1 or MC2) of the memory cell array 110C.

[0237] In addition, the semiconductor memory device 100 may improve the accuracy of the operation of reading data from each memory cell (e.g., MC1 or MC2) of the memory cell array 110C.

[0238] Figure 7A is a top view of a first surface of a substrate according to an exemplary embodiment, on which a plurality of metal lines are provided; Figure 7B is a view showing Figure 7A a bottom view of a second surface of the substrate, on which a first additional word line and a second additional word line are provided; Figure 7C is Figure 7A and Figure 7B a cross-sectional view of the substrate taken along line D-D', and Figure 7D is Figure 7A and Figure 7B a cross-sectional view of the substrate in

[0239] Referring to Figures 7A to 7C According to an exemplary embodiment, the memory cell array 110D may include a first additional word line AWL1 and a second additional word line AWL2 formed on the second surface 202 of the substrate 200.

[0240] Figures 7A to 7C At least a part of the memory cell array 110D shown in Figures 6A to 6C can be understood as an example of a component of the memory cell array 110C shown in

[0241] Therefore, the same or substantially the same components are denoted by the same reference numerals, and redundant descriptions thereof will be omitted.

[0242] Referring to Figure 7A , a first bit line BL1, a second bit line BL2, a first word line WL1, a second word line WL2, and a first source line SL1 can be disposed on a first surface 201 of the substrate 200. In addition, the memory cell array 110D according to the exemplary embodiment includes a first metal member MM1 and a second metal member MM2 disposed on the first surface 201 of the substrate 200.

[0243] In addition, first source-drains SD1 to fifth source-drains SD5 can be formed to penetrate at least a part of the surface and the interior of the substrate 200. For example, first source-drains SD1 to fifth source-drains SD5 can be formed to extend from the first surface 201 of the substrate 200 toward the interior of the substrate 200. For example, first source-drains SD1 to fifth source-drains SD5 can extend inside the substrate 200.

[0244] First source-drains SD1 to third source-drains SD3 can be understood as having substantially the same configuration as the Figure 4A first source-drains SD1 to third source-drains SD3 shown in

[0245] Referring to Figure 7B , a first additional word line AWL1 and a second additional word line AWL2 according to the exemplary embodiment can be disposed on a second surface 202 of the substrate 200.

[0246] Referring to Figure 7C , the memory cell array 110D can include a first connection member CM1 and a second connection member CM2, and each of the first connection member CM1 and the second connection member CM2 penetrates the substrate 200.

[0247] The first connection member CM1 can be formed to penetrate a region corresponding to the fourth source-drain SD4 in the substrate 200. In addition, the second connection member CM2 can be formed to penetrate a region corresponding to the fifth source-drain SD5 in the substrate 200.

[0248] In addition, the memory cell array 110D can include a first metal member MM1 and a second metal member MM2 respectively connected to the first connection member CM1 and the second connection member CM2 on the first surface 201.

[0249] For example, the memory cell array 110D may include a first metal member MM1 connected to a first connection member CM1 and a first word line WL1 located on the first surface 201.

[0250] In addition, the memory cell array 110D may include a second metal member MM2 connected to a second connection member CM2 and a second word line WL2 located on the first surface 201.

[0251] The first word line WL1 may be connected to a first additional word line AWL1 through the first metal member MM1 and the first connection member CM1.

[0252] The second word line WL2 may be connected to a second additional word line AWL2 through the second metal member MM2 and the second connection member CM2.

[0253] For example, each of the first connection member CM1 and the second connection member CM2 may be referred to as a small power tap cell (sPTC), but the exemplary embodiments are not limited thereto. The connection members CM1 and CM2 may be conductors or include a conductive material.

[0254] The first source line SL1 may be connected to a second source-drain SD2 through a third front contact FC3 formed on the first surface 201 of the substrate 200.

[0255] Reference Figure 7D , the first memory cell MC1 according to the exemplary embodiment includes a first variable resistor VR1 connected to a first bit line BL1.

[0256] According to the exemplary embodiment, the first variable resistor VR1 is connected to a first source-drain SD1 through a first metal line ML1 and a first front contact FC1. In addition, the first bit line BL1 may be connected to the first source-drain SD1 through the first variable resistor VR1, the first metal line ML1, and the first front contact FC1.

[0257] The second memory cell MC2 according to the exemplary embodiment includes a second variable resistor VR2 connected to a second bit line BL2.

[0258] According to the exemplary embodiment, the second variable resistor VR2 is connected to a third source-drain SD3 through a second metal line ML2 and a second front contact FC2. In addition, the second bit line BL2 may be connected to the third source-drain SD3 through the second variable resistor VR2, the second metal line ML2, and the second front contact FC2.

[0259] Reference Figure 2 , Figure 7C and Figure 7D, a first source-drain SD1, a first gate electrode G1, and a second source-drain SD2 may form a first unit transistor CT1.

[0260] The first gate electrode G1 of the first unit transistor CT1 may be connected to a first word line WL1 and a first additional word line AWL1.

[0261] For example, the first gate electrode G1 may be connected to the first word line WL1 disposed on the first surface 201.

[0262] In addition, the first gate electrode G1 may be connected to the first additional word line AWL1 disposed on the second surface 202.

[0263] For example, the first gate electrode G1 may be connected to the first additional word line AWL1 through the first word line WL1, a first connection member CM1, and a first metal member MM1.

[0264] Reference Figure 1 , Figure 7C and Figure 7D , a second source-drain SD2, a second gate electrode G2, and a third source-drain SD3 may form a second unit transistor CT2.

[0265] The second gate electrode G2 of the second unit transistor CT2 may be connected to a second word line WL2 and a second additional word line AWL2.

[0266] For example, the second gate electrode G2 may be connected to the second word line WL2 disposed on the first surface 201 of the substrate 200.

[0267] For example, the second gate electrode G2 may be connected to the second additional word line AWL2 through the second word line WL2, a second connection member CM2, and a second metal member MM2.

[0268] Referring to the above configuration, each of the first memory cell MC1 and the second memory cell MC2 according to the exemplary embodiment may be connected to a word line having a relatively large area.

[0269] For example, compared with the case where the first memory cell MC1 is only connected to the first word line WL1 disposed on the first surface 201, the first memory cell MC1 may be connected to the word lines WL1 and AWL1 having a relatively large area.

[0270] For example, compared with the case of being only connected to the second word line WL2 disposed on the first surface 201, the second memory cell MC2 may be connected to a word line having a relatively wide area.

[0271] For example, the semiconductor memory device 100 may increase the area of the word lines connected to each memory cell (e.g., MC1 or MC2) by the additional word lines AWL1 and AWL2 provided on the second surface 202.

[0272] The additional word lines AWL1 and AWL2 may be connected to the word lines WL1 and WL2 provided on the first surface 201 through connection members CM1 and CM2 formed to penetrate the substrate 200, respectively.

[0273] Therefore, the semiconductor memory device 100 according to the exemplary embodiment may reduce the resistance values of the word lines WL1, WL2, AWL1, and AWL2 connected to each memory cell (e.g., MC1 or MC2) of the memory cell array 110D.

[0274] Therefore, the semiconductor memory device 100 may improve the power efficiency of the operation of reading data from each memory cell (e.g., MC1 or MC2) of the memory cell array 110D.

[0275] In addition, the semiconductor memory device 100 may improve the accuracy of the operation of reading data from each memory cell (e.g., MC1 or MC2) of the memory cell array 110D.

[0276] Figure 8A is a top view of the first surface of a substrate according to an exemplary embodiment, on which a plurality of metal lines are provided; Figure 8B is a view showing Figure 8A a bottom view of the second surface of the substrate, on which a first additional word line and a first source line are provided; and Figure 8C is Figure 8A and Figure 8B a cross-sectional view of the substrate along line F-F'.

[0277] Referring to Figures 8A to 8C According to an exemplary embodiment, the memory cell array 110E includes a first source line SL1 and a first additional word line AWL1 provided on the second surface 202 of the substrate 200.

[0278] Figures 8A to 8C The memory cell array 110E shown in Figure 1 may be understood as an example of the memory cell array 110 shown in

[0279] Referring to Figure 8A According to an exemplary embodiment, a first bit line BL1, a second bit line BL2, a first word line WL1, and a second word line WL2 may be formed on the first surface 201 of the substrate 200.

[0280] The first source-drain SD1 to the third source-drain SD3 may be formed to extend from the first surface 201 of the substrate 200 into the substrate 200. For example, the first source-drain SD1 to the third source-drain SD3 may be formed inside the substrate 200.

[0281] Reference Figure 8B , according to an example embodiment, the first additional word line AWL1 and the first source line SL1 may be disposed on the second surface 202 of the substrate 200.

[0282] For example, the first additional word line AWL1 may be formed to extend on the second surface 202 in a second direction (e.g., the positive Y direction) perpendicular to the first direction (e.g., the positive X direction).

[0283] For example, the first source line SL1 may be formed to extend on the second surface 202 in the first direction (e.g., the positive X direction). The first source line SL1 may be formed to have a first width W1. The first width W1 may be in the second direction (e.g., the positive Y direction).

[0284] According to an example embodiment, when viewed from a third direction (the positive Z direction) perpendicular to the first direction (the positive X direction) and the second direction (the positive Y direction), the first source line SL1 is formed to overlap at least a portion of the first bit line BL1 and the second bit line BL2.

[0285] Reference Figure 8C , the memory cell array 110E may include a first back contact BC1 and a second back contact BC2, each of the first back contact BC1 and the second back contact BC2 being formed to extend from the second surface 202 into the substrate 200. For example, the first back contact BC1 and the second back contact BC2 may extend inside the substrate 200. The first back contact BC1 and the second back contact BC2 may be conductors or include conductive materials.

[0286] For example, the memory cell array 110E may include a first back contact BC1 formed to extend from the second surface 202 into the substrate 200.

[0287] In addition, the memory cell array 110E may include a first additional back contact BC1' disposed on the second surface 202, the first additional back contact BC1' being connected to the first back contact BC1 on the second surface 202. The first additional back contact BC1' may be a conductor or include conductive materials.

[0288] In addition, the memory cell array 110E may include a second back contact BC2 formed to extend into the substrate 200.

[0289] Reference Figure 2 andFigure 8C The first source-drain SD1, the first gate electrode G1, and the second source-drain SD2 may form a first unit transistor CT1.

[0290] The first gate electrode G1 of the first unit transistor CT1 may be connected to a first word line WL1 and a first additional word line AWL1.

[0291] For example, the first gate electrode G1 may be connected to the first word line WL1 disposed on the first surface 201 of the substrate 200.

[0292] In addition, the first gate electrode G1 may be connected to the first additional word line AWL1 disposed on the second surface 202 of the substrate 200. The first additional word line AWL1 may be connected to the first gate electrode G1 through the second back contact BC2.

[0293] Reference Figure 1 and Figure 8C the second source-drain SD2, the second gate electrode G2, and the third source-drain SD3 may form a second unit transistor CT2.

[0294] The second source-drain SD2 may be connected to the first source line SL1 through the first back contact BC1 and the first additional back contact BC1'.

[0295] Referring to the above configuration, the first memory cell MC1 according to the exemplary embodiment may be connected to a word line having a relatively large area.

[0296] For example, compared with the case of being only connected to the first word line WL1 disposed on the first surface 201, the first memory cell MC1 may be connected to the word lines WL1 and AWL1 having a relatively large area.

[0297] For example, the semiconductor memory device 100 may increase the area of the word line connected to the first memory cell MC1 through the first additional word line AWL1 disposed on the second surface 202.

[0298] Therefore, the semiconductor memory device 100 according to the exemplary embodiment may reduce the resistance values of the word lines WL1 and AWL1 connected to each memory cell (e.g., MC1) of the memory cell array 110E.

[0299] In addition, referring to the above configuration, compared with the case where the first memory cell MC1, the first word line WL1, the first bit line BL1, and the first source line SL1 are formed together on the first surface 201, the first source line SL1 according to the exemplary embodiment may have a relatively large width (or area).

[0300] Therefore, the semiconductor memory device 100 may reduce the resistance value of the first source line SL1.

[0301] Accordingly, the semiconductor memory device 100 can improve the power efficiency of an operation of reading data from each memory cell (e.g., MC1 or MC2) of the memory cell array 110E.

[0302] In addition, the semiconductor memory device 100 can improve the accuracy of an operation of reading data from each memory cell (e.g., MC1 or MC2) of the memory cell array 110E.

[0303] Figure 9 is a circuit diagram showing a configuration in which a control logic circuit reads data stored in a memory cell array using a sense amplifier according to an exemplary embodiment.

[0304] Reference Figure 9 , a semiconductor memory device 100A according to an exemplary embodiment includes a control logic circuit 150, a sense amplifier 123, a memory cell array 110, and a reference cell array 910.

[0305] Figure 9 The illustrated semiconductor memory device 100A may be understood as Figure 1 an example of the illustrated semiconductor memory device 100. Accordingly, the same or substantially the same components are denoted by the same reference numerals, and redundant descriptions thereof will be omitted.

[0306] According to an exemplary embodiment, the semiconductor memory device 100A includes a sense amplifier 123 connected to the memory cell array 110 and the reference cell array 910.

[0307] For example, the sense amplifier 123 may apply a current to the memory cell array 110 and the reference cell array 910 under the control of the control logic circuit 150.

[0308] According to an exemplary embodiment, the control logic circuit 150 uses the sense amplifier 123 to apply a read current to at least some of the memory cells included in the reference cell array 910 and the memory cell array 110.

[0309] For example, the control logic circuit 150 may apply a read current to at least some of the memory cells MC1 to MCn included in the memory cell array 110 through a plurality of bit lines BL.

[0310] The control logic circuit 150 may apply a read current to the reference cells included in the reference cell array 910 through a reference bit line BLref. For example, the read current applied to the reference cell array 910 may be referred to as a reference current.

[0311] The reference cell array 910 may be understood as including a single reference cell, but the exemplary embodiment is not limited thereto. The reference cell array 910 may also be understood as including at least two reference cells.

[0312] In addition, the control logic circuit 150 can compare the current output from the reference cell array 910 with the current output from the memory cell array 110.

[0313] For example, the control logic circuit 150 can identify the current output from the memory cell array 110 through multiple source lines SL. In addition, the control logic circuit 150 can identify the current output from the reference cell array 910 through the reference source line SLref.

[0314] Therefore, the control logic circuit 150 can compare the current output through multiple source lines SL with the current output through the reference source line SLref.

[0315] The control logic circuit 150 can read the data stored in at least a part of the memory cells MC1 to MCn included in the memory cell array 110 based on the comparison result.

[0316] Reference Figure 2 and Figure 9 , the semiconductor memory device 100A can increase the areas of the source line SL1 and the bit line BL1 by providing the first source line SL1 and the first bit line BL1 on different surfaces of the substrate 200.

[0317] For example, in the semiconductor memory device 100A, the source lines connected to each of the memory cells MC1 to MCn can be provided on the second surface 202 of the substrate 200.

[0318] Therefore, the semiconductor memory device 100A according to the exemplary embodiment can increase the areas of the source lines and / or bit lines connected to each of the memory cells MC1 to MCn.

[0319] In addition, the semiconductor memory device 100A can reduce the resistance values of the source lines and / or bit lines connected to each of the memory cells MC1 to MCn.

[0320] Therefore, the semiconductor memory device 100A can reduce the influence of the resistance values of the source lines and / or bit lines on applying a read current to each of the memory cells MC1 to MCn included in the memory cell array 110 and identifying the output current.

[0321] Therefore, the semiconductor memory device 100A can reduce the mismatch occurring based on the relative positions of each of the memory cells MC1 to MCn in the sense amplifier 123 and the memory cell array 110.

[0322] In addition, the semiconductor memory device 100A according to the exemplary embodiment can improve the accuracy of the operation of reading the data stored in the memory cell array 110.

[0323] As described above, the semiconductor memory device 100 according to the exemplary embodiment includes a first memory cell MC1 and a first bit line BL1 disposed on the first surface 201 of the substrate 200.

[0324] In addition, the semiconductor memory device 100 may include a first source line SL1 disposed on the second surface 202 and parallel to the first surface 201 of the substrate 200 to be connected to the first unit transistor CT1.

[0325] Compared with the case where it is formed on the first surface 201 together with the first memory cell MC1, the first word line WL1, and the first bit line BL1, the first source line SL1 may have a relatively large area (or width).

[0326] Therefore, the semiconductor memory device 100 according to the exemplary embodiment can significantly reduce the resistance value of the first source line SL1.

[0327] Due to the above configuration, the semiconductor memory device 100 according to the exemplary embodiment can improve the power efficiency of the operation of reading data stored in the first memory cell MC1.

[0328] For example, the semiconductor memory device 100 can increase the read margin of the first memory cell MC1.

[0329] In addition, compared with the case where it is formed on the first surface 201 together with the first bit line BL1 and the first source line SL1, the first memory cell MC1 according to the exemplary embodiment may have a relatively small area.

[0330] Therefore, the semiconductor memory device 100 according to the exemplary embodiment can significantly reduce the size of the first memory cell MC1 or the memory cell array 110.

[0331] According to an embodiment, the semiconductor memory device 100 can reduce the resistance value of the metal line connected to the first memory cell MC1 through the first source line SL1 disposed on the second surface 202.

[0332] Therefore, the semiconductor memory device 100A can reduce the influence of the resistance value of the source line and / or the bit line on applying a read current to each of the memory cells MC1 to MCn included in the memory cell array 110 and identifying the output current.

[0333] Therefore, the semiconductor memory device 100A can reduce the mismatch occurring based on the relative positions of each of the memory cells MC1 to MCn in the sense amplifier 123 and the memory cell array 110.

[0334] As described above, the semiconductor memory device according to the exemplary embodiment includes a source line formed on one surface of the substrate that is not adjacent to the memory cell. Accordingly, the semiconductor memory device can significantly reduce the resistance of the metal line and the effects caused by the resistance of the metal line.

[0335] Although the exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A first memory cell, the first memory cell including a first variable resistor element and a first cell transistor, the first cell transistor being connected to the first variable resistor element through a first source-drain; A substrate, the substrate including a first surface and a second surface opposite to the first surface, the first surface being connected to a second source-drain of the first cell transistor; A first bit line, the first bit line being connected to the first source-drain of the first cell transistor through the first variable resistor element; And A first source line, the first source line having a first width, the first source line being disposed on the second surface of the substrate and connected to the second source-drain.

2. The semiconductor memory device according to claim 1, the semiconductor memory device further comprising: A first back contact, the first back contact being located inside the substrate and extending from the second surface, Wherein, the first source line is connected to the second source-drain through the first back contact.

3. The semiconductor memory device according to claim 2, the semiconductor memory device further comprising: A first front contact disposed on the first surface of the substrate, the first front contact being connected to the first source-drain; And A first metal line, the first metal line being stacked on the first front contact, Wherein, the first bit line is connected to the first source-drain through the first variable resistor element, the first front contact and the first metal line.

4. The semiconductor memory device according to claim 1, wherein, The first variable resistor element includes: A first magnetic layer, a second magnetic layer, and a tunnel layer disposed between the first magnetic layer and the second magnetic layer, and Wherein, the first variable resistor element has different resistance values depending on the magnetization directions of the first magnetic layer and the second magnetic layer, and the magnetization directions of the first magnetic layer and the second magnetic layer are formed depending on the current applied through the first bit line.

5. The semiconductor memory device according to claim 1, the semiconductor memory device further comprising: A first word line disposed on the first surface of the substrate, the first word line being connected to a first gate electrode of the first cell transistor.

6. The semiconductor memory device according to claim 5, the semiconductor memory device further comprising: A first additional word line, the first additional word line being disposed on the second surface of the substrate, Wherein, the first additional word line is connected to the first gate electrode.

7. The semiconductor memory device according to claim 1, the semiconductor memory device further comprising: A second memory cell, the second memory cell being disposed adjacent to the first memory cell and including a second variable resistor element and a second cell transistor; And A second bit line, the second bit line being connected to a third source-drain of the second cell transistor through the second variable resistor element, Wherein, the second cell transistor is connected to the first source line disposed on the second surface of the substrate through the substrate.

8. The semiconductor memory device according to claim 1, wherein the semiconductor memory device further comprises: a reference unit connected between a reference bit line and a reference source line; and a control logic circuit connected to the first memory cell and the reference unit, wherein the control logic circuit is configured to: apply a read current through the first bit line, the first source line, the reference bit line, and the reference source line; and identify data stored in the first memory cell based on a difference between a resistance formed in the first variable resistor element of the first memory cell and a resistance formed in the reference unit, depending on the read current.

9. The semiconductor memory device according to claim 1, wherein, The first variable resistor element includes: a first metal layer, a second metal layer, and an insulating layer disposed between the first metal layer and the second metal layer, and wherein the first variable resistor element has different resistance values depending on a magnitude of a magnetic field formed in the insulating layer through the first metal layer and the second metal layer.

10. The semiconductor memory device according to claim 1, wherein the semiconductor memory device further comprises: a second source line disposed on the first surface and having a second width smaller than the first width, wherein the first source line is electrically connected to the second source line through a connection member penetrating the substrate.

11. A semiconductor memory device, comprising: a memory cell array including a plurality of memory cells, each memory cell including a variable resistor element and a cell transistor; a first bit line and a first source line connected to a first memory cell among the plurality of memory cells; and a substrate connected between the first memory cell and the first source line, the substrate having a first surface and a second surface opposite to the first surface, the first surface being adjacent to a first cell transistor, wherein the first bit line is connected to the first cell transistor through a first variable resistor element of the first memory cell, and wherein the first source line is disposed on the second surface of the substrate and connected to the first cell transistor.

12. The semiconductor memory device according to claim 11, wherein the semiconductor memory device further comprises: a first back contact passing through at least a part of the interior of the substrate from the second surface, wherein the first source line is connected to the first cell transistor through the first back contact.

13. The semiconductor memory device according to claim 12, wherein the semiconductor memory device further comprises: a first front contact disposed on the first surface of the substrate and connected to the first cell transistor; wherein the first bit line is connected to the first cell transistor through the first variable resistor element and the first front contact.

14. The semiconductor memory device according to claim 11, wherein, The first variable resistor element includes: A first magnetic layer, a second magnetic layer, and a tunnel layer disposed between the first magnetic layer and the second magnetic layer wherein the first variable resistor element has different resistance values depending on the magnetization directions of the first magnetic layer and the second magnetic layer formed by a current applied through the first bit line.

15. The semiconductor memory device according to claim 11, wherein, The first variable resistor element includes: a first metal layer, a second metal layer, and an insulating layer disposed between the first metal layer and the second metal layer, and wherein the first variable resistor element has different resistance values depending on the magnitude of a magnetic field formed in the insulating layer by the first metal layer and the second metal layer.

16. The semiconductor memory device according to claim 11, wherein the semiconductor memory device further includes: a second source line disposed on the first surface and having a width smaller than the width of the first source line, wherein the first source line is electrically connected to the second source line through a connection member penetrating the substrate.

17. The semiconductor memory device according to claim 11, wherein the semiconductor memory device further includes: a reference bit line and a reference source line connected to a reference cell among the plurality of memory cells; and a control logic circuit connected to the first memory cell and the reference cell, wherein the control logic circuit is configured to: apply a read current through the first bit line, the first source line, the reference bit line, and the reference source line; and identify data stored in the first memory cell based on a difference between a resistance formed in the first variable resistor element of the first memory cell and a resistance formed in the reference cell depending on the read current.

18. The semiconductor memory device according to claim 14, wherein the semiconductor memory device further includes: a first word line disposed on the first surface of the substrate and connected to a gate electrode of the first unit transistor.

19. A semiconductor memory device, the semiconductor memory device including: a first memory cell including a first variable resistor element and a first unit transistor, the first unit transistor being connected to the first variable resistor element through a first source-drain; a substrate including a first surface and a second surface opposite to the first surface, the first surface being connected to a second source-drain of the first unit transistor; a first bit line connected to the first source-drain of the first unit transistor through the first variable resistor element; a first word line disposed on the first surface to be connected to a first gate electrode of the first unit transistor; and a first additional word line disposed on the second surface of the substrate and connected to the first gate electrode.

20. The semiconductor memory device according to claim 19, wherein the semiconductor memory device further includes: a first source line disposed on the second surface; and A first back contact that passes through at least a portion of the substrate through the second surface. Wherein the first source line is connected to the second source-drain of the first unit transistor through the first back contact.

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