GaAs-based semiconductor device and preparation method and application thereof

Abstract

According to the GaAs-based semiconductor device, an epitaxial layer is located on a GaAs substrate, the epitaxial layer at least comprises a buffer layer, a channel layer and a barrier layer which are located on the GaAs substrate and sequentially stacked, a source electrode, a drain electrode and a grid electrode are located on the barrier layer, and the grid electrode is located between the source electrode and the drain electrode; a non-grid-control area between the source electrode and the drain electrode is provided with two ion injection areas, the ion injection areas extend from the surface of the barrier layer to the bottom face of the barrier layer in the direction of the GaAs substrate, and the doping concentration of the ion injection areas located between the grid electrode and the source electrode is increased in the direction from the grid electrode to the source electrode. The doping concentration of the ion implantation region between the grid electrode and the drain electrode is increased along the direction from the grid electrode to the drain electrode, the concentration of the (n + 1) th concentration region of the ion implantation region is greater than that of the first concentration region, n is greater than or equal to 1 and less than or equal to 4, and the source electrode and the drain electrode are both located on the (n + 1) th concentration region. According to the invention, the parasitic resistance and the parasitic capacitance are reduced on the whole, so that the direct current characteristic, the radio frequency characteristic and the temperature stability are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technologies, and particularly to a GaAs-based semiconductor device, a preparation method thereof, a radio frequency module, and a communication device. Background Art

[0002] pHEMT (pseudomorphic high electron mobility transistor) is an improved type of high electron mobility transistor (HEMT). Its key feature is the use of a pseudomorphic layer, that is, a very thin semiconductor material is grown under the condition of lattice mismatch, enabling it to maintain a high crystal quality without generating dislocations. GaAs-based pHEMT devices are high electron mobility field effect transistors based on the gallium arsenide (GaAs) material system. It achieves high electron mobility and high-speed performance through a special heterojunction structure. Its main characteristics include high electron mobility and low noise characteristics, and it is widely used in the field of radio frequency chips (RF Chips) for microwave and millimeter waves.

[0003] A typical GaAs-based pHEMT device includes the following key parts: Substrate: Usually a semi-insulating GaAs substrate is used to provide mechanical support and reduce parasitic capacitance. Buffer Layer: Located on top of the substrate, it is used to isolate defects and impurities in the substrate and ensure the quality of the upper-layer materials. Channel Layer: Usually an undoped InGaAs layer, which forms a two-dimensional electron gas (2DEG) at the heterojunction interface and serves as the main conduction channel. Barrier Layer: Such as an AlGaAs layer, its bandgap is higher than that of the channel layer, forming a band bending to confine electrons in the channel layer. Cap layer: Usually located on top of the barrier layer (such as AlGaAs), its main function is to improve ohmic contact. Gate: Controls the switching of the current in the channel, and usually adopts structures such as Y-shaped gates and trapezoidal gates to reduce parasitic resistance. Source and Drain: Provide paths for current to flow in and out, and usually form ohmic contacts by the contact of metal and semiconductor. The key performance parameters of GaAs-based pHEMTs applied on microwave radio frequency chips include the operating frequency range, power added efficiency (PAE), linearity, and noise figure. The material composition, surface defects, and device structure of GaAs-based pHEMTs jointly determine the intrinsic electrical characteristics and parasitic characteristics of the device, thus affecting the quality of the above key performance parameters. The ohmic contact resistance of the source and drain, as well as the parasitic resistance and parasitic capacitance caused by surface defects near the gate, are important components of the parasitic resistance and parasitic capacitance of pHEMT devices, thus affecting the intrinsic electrical characteristics and parasitic characteristics of the device. Therefore, reducing the ohmic contact resistance of the source and drain, and improving the surface defect situation near the gate can play a positive role in improving the parasitic resistance and parasitic capacitance of pHEMT devices.

[0004] In the prior art, the methods for improving the ohmic contact resistance of the source and drain mainly include increasing the carrier concentration of the source and drain and the cap layer, including the following two methods: One is to use Si doping concentration exceeding 1E19 cm -3 or planar doping (1E13cm -2 ); The other is to use a semiconductor material with a narrower bandgap and a higher electron concentration (such as InGaAs) as the cap layer.

[0005] In the prior art, the methods for improving the surface defect situation near the gate mainly include cleaning and passivating the surface of the barrier layer. The surface cleaning has the following specific methods: One is to clean with an alkaline solution (such as NH3·H2O), another is to clean with an acidic solution (such as HCl solution), and there is also a method of cleaning with N-methylpyrrolidone (NMP), etc. The interface passivation method mainly adopts depositing a passivation layer such as silicon nitride (SiNx ) Passivate the surface near the gate by means of a thin film or the like.

[0006] The above-mentioned prior art can reduce the ohmic contact resistance of the source and drain, and improve the surface defects near the gate. However, it is still difficult to solve some important practical problems in the manufacturing process of GaAs-based pHEMTs. For example: First, there is a certain potential barrier in the contact area between the source and drain of the pHEMT and the cap layer, and in the contact area between the gate metal and the barrier layer. Under pickling or alkali washing conditions, an electrochemical reaction is likely to occur, causing corrosion of the semiconductor contact area near the electrodes (source, gate, and drain), resulting in an increase in contact resistance; Second, as Figure 1 shown in the figure, the pHEMT includes a GaAs substrate 11, a buffer layer 12, a channel layer 13, a barrier layer 14, a cap layer 15, a source 16, a drain 18, and a gate 17. The prior art forms a gate trench 151 by chemically etching the cap layer 15 so that the gate 17 contacts the barrier layer 14. However, it is usually difficult to avoid process problems such as barrier layer etching residues, surface defects of the barrier layer 14, and surface oxidation, resulting in surface defects and causing parasitic capacitance. The parasitic resistance and parasitic capacitance caused by the above-mentioned manufacturing process and process factors of the prior art will have an adverse impact on the RF performance and temperature stability of GaAs-based pHEMTs. Summary of the Invention

[0007] Therefore, in order to overcome the problem of parasitic benefits caused by surface cleaning and gate trench etching in the prior art, the present invention provides a GaAs-based semiconductor device, its manufacturing method, an RF module, and a communication device, which overall reduce parasitic resistance and parasitic capacitance, and thus improve its DC characteristics, RF characteristics, and temperature stability.

[0008] To solve the above technical problems, the technical solution of the present invention is:

[0009] A GaAs-based semiconductor device includes a GaAs substrate and an epitaxial layer. The epitaxial layer is located on the GaAs substrate and at least includes a buffer layer, a channel layer, and a barrier layer that are sequentially stacked on the GaAs substrate. The source, drain, and gate are located on the barrier layer, and the gate is located between the source and the drain;

[0010] In the non-gated region between the source and the drain, there are two ion implantation regions, which are respectively located between the gate and the source and between the gate and the drain. The ion implantation regions extend from the surface of the barrier layer towards the bottom surface of the GaAs substrate in the direction of the GaAs substrate,

[0011] The doping concentration of the ion implantation region between the gate and the source increases along the direction from the gate to the source, and the doping concentration of the ion implantation region between the gate and the drain increases along the direction from the gate to the drain.

[0012] The ion implantation region forms at least a first concentration region and an (n + 1)-th concentration region, the concentration of the (n + 1)-th concentration region is greater than that of the first concentration region, 1 ≤ n ≤ 4, and the source and drain are all located on the (n + 1)-th concentration region.

[0013] Furthermore, the ion implantation region is Si-doped, the doping concentration range of the first concentration region is 1E16 - 5E17 cm -3 , and the doping concentration range of the (n + 1)-th concentration region is 5E17 - 1E19 cm -3 .

[0014] Furthermore, it further includes a lower doping layer, a lower isolation layer, an upper isolation layer, and an upper doping layer. The buffer layer, the lower doping layer, the lower isolation layer, the channel layer, the upper isolation layer, the upper doping layer, and the barrier layer are stacked in sequence. The ion implantation region extends from the barrier layer towards the GaAs substrate. The thickness of the barrier layer is H1, the thickness from the surface of the barrier layer to the bottom surface of the lower doping layer is H2, and the implantation depth of the ion implantation region is Hj, where H1 < Hj < H2.

[0015] Furthermore, the concentration range of the lower doping layer is 1E12 - 1E13 cm -2 , and the concentration of the upper doping layer is 1 - 10 times that of the lower doping layer.

[0016] Furthermore, it further includes a passivation layer, and the passivation layer covers the gate and the surface of the barrier layer not covered by the source and drain.

[0017] Furthermore, when the gate is a Y-shaped gate, the gate cap width of the Y-shaped gate is L1, the root widths of the source and the drain are the same, the root width of the source is L2, the distance between the source and the drain is L3, and the width of the ion implantation region is L6, where L6 = (L3 + 2L2 - L1) / 2.

[0018] Furthermore, when the gate is a trapezoidal gate, the gate root width of the trapezoidal gate is L4, the root widths of the source and the drain are the same, the root width of the source is L2, the distance between the source and the drain is L3, and the width of the ion implantation region is L6, where L6 = (L3 + 2L2 - L4 - X) / 2, 0.1μm ≤ X ≤ 2μm.

[0019] Furthermore, the root widths of the source and the drain are the same, the root width of the source is L2, the top widths of the source and the drain are the same, which is L8, and L8 = L2 + Y, where Y = 1 - 5μm.

[0020] Furthermore, the material of the buffer layer is Al x1 Ga 1-x1 As, where the Al component x1 = 0.2 - 0.3, and the material of the channel layer is In x2 Ga 1-x2For the As and In components, x2 = 0.2 to 0.4, and the barrier layer material is Al x3 Ga 1-x3 For the As and Al components, x3 = 0.2 to 0.3.

[0021] Furthermore, the width of the (n + 1)-th concentration region is L5, the root widths of the source and drain are the same, the root width of the source is L2, and L2 ≤ L5.

[0022] Furthermore, the GaAs-based semiconductor device is a pHEMT (pseudomorphic high electron mobility transistor) or an HFET (heterojunction field effect transistor).

[0023] A method for fabricating a GaAs-based semiconductor device includes the following steps:

[0024] Step 1, epitaxial layer preparation: Grow an epitaxial layer on a GaAs substrate, where the epitaxial layer includes a buffer layer, a channel layer, and a barrier layer stacked in sequence on the GaAs substrate;

[0025] Step 2, gate preparation: Clean the surface of the barrier layer, and perform gate preparation using a photolithography process and a gate metal deposition process;

[0026] Step 3, passivation layer preparation: Deposit a passivation layer on the surfaces of the gate and the barrier layer using plasma-enhanced chemical vapor deposition;

[0027] Step 4, preparation of the ion implantation region in the non-gate-controlled area: Through a photolithography process and an ion implantation process, lightly dope the non-gate-controlled area between the source and the drain, with a doping concentration range of 1E16 to 5E17 cm -3 , and at least form one concentration region, and the first formed concentration region is the 1st concentration region;

[0028] Step 5: Preparation of the ion implantation region under the source and the drain: Through a photolithography process and an ion implantation process, heavily dope the ohmic contact region under the source and the drain to form the (n + 1)-th concentration region, where 1 ≤ n ≤ 4, and the doping concentration range is 5E17 to 1E19 cm -3 , and complete the activation of the ions;

[0029] Step 6: Opening holes in the passivation layer in the regions of the source and the drain: Through a photolithography process and a passivation layer etching process, etch the passivation layer at the deposition positions of the source and the drain to expose the metal electrode deposition regions of the source and the drain;

[0030] Step 7: Preparation of the source and the drain: Through a photolithography process and a metal thin film deposition process, deposit metal in the metal electrode deposition regions to form the source and the drain, and perform alloying. The source and the drain are all located on the (n + 1)-th concentration region.

[0031] A radio frequency module includes the aforementioned GaAs-based semiconductor device.

[0032] A communication device includes the aforementioned radio frequency module.

[0033] After adopting the above solution, since in the present invention, a gate is fabricated on the barrier layer, ion implantation is used to perform one or more times of relatively light doping of donor impurities in a relatively large area under the source and drain, and then, ion implantation is used to perform one or more times of relatively high-concentration doping of donor impurities in a relatively small area under the source and drain, and on this basis, source and drain metal electrodes are fabricated. The present invention has the following advantages:

[0034] 1. By adopting a heavily doped concentration region, the contact resistance under the source and drain is reduced;

[0035] 2. By adopting a lightly doped concentration region, the parasitic resistance in the non-gate-controlled region between the source and drain is reduced;

[0036] 3. Near the roots of the source, drain, and gate, they are effectively protected by the metal layer and the passivation layer, reducing the electrochemical damage effect of the cleaning liquid and the etching liquid on the vicinity of the source, drain, and gate;

[0037] 4. By adopting a gate trenchless etching method, the surface defects of the barrier layer near the gate are passivated, which can well protect the interface near the gate and reduce the generation of interface defects. Description of the Drawings

[0038] Figure 1 is a schematic structural diagram of a pHEMT device in the prior art;

[0039] Figure 2 is a schematic structural diagram of the first embodiment of the present invention;

[0040] Figure 3 is a schematic diagram of the non-gate-controlled region of the present invention;

[0041] Figure 4 is a schematic structural diagram of the second embodiment of the present invention;

[0042] Figure 5 is a process flow diagram of the second embodiment of the present invention;

[0043] Figure 6 is a schematic structural diagram of the third embodiment of the present invention;

[0044] Figure 7 is a schematic structural diagram of the fourth embodiment of the present invention;

[0045] Figure 8 is a schematic diagram of three concentration regions of the ion implantation region of the present invention;

[0046] Figure 9It is a schematic diagram of 4 concentration regions in the ion implantation area of the present invention;

[0047] Figure 10 It is a schematic diagram of 5 concentration regions in the ion implantation area of the present invention.

[0048]

Explanation of Reference Numerals

[0049] GaAs substrate 11, buffer layer 12, channel layer 13, barrier layer 14, cap layer 15, source electrode 16

[0050] Drain electrode 18, gate electrode 17, ion implantation area 2, passivation layer 3, lower doping layer 4

[0051] Lower isolation layer 5, upper isolation layer 6, upper doping layer 7 Detailed Embodiment

[0052] To make the above objects, features and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below with reference to the drawings and embodiments. It should be specifically noted that the following embodiments are only used to illustrate the present invention, but do not limit the scope of the present invention. Similarly, the following embodiments are only partial embodiments of the present invention rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

[0053] In addition, the directional terms mentioned in the present invention, such as up, down, front, back, left, right, inside, outside, side, etc., are based on the orientation or position relationship shown in the drawings, or the orientation or position relationship in which the product of this application is usually placed during use. It is only for the convenience of description and should not be construed as a limitation to the present invention. In each drawing, units with similar structures are represented by the same reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown in the drawings. It should also be noted that the division of multiple embodiments in the present invention is only for the convenience of description and should not constitute a special limitation. The features in various embodiments can be combined with each other without contradiction and can be cited from each other.

[0054] In addition, the cross-sectional views shown in the drawings are schematic diagrams of idealized embodiments (and intermediate structures) of the present invention. Therefore, due to, for example, manufacturing techniques and / or tolerances, changes in the illustrated shapes are predictable. The embodiments of the present invention should not be construed as limited to the specific shapes of the regions shown herein, but include shape deviations caused by manufacturing. For example, an ion implantation region illustrated as rectangular will generally have circular or curved features and / or an implantation concentration gradient at its edges, rather than a binary change from the ion implantation region to the non-ion implantation region. Therefore, the regions shown in the drawings are essentially schematic and cannot be used to limit the actual shape of the regions and the scope of the present invention.

[0055] As Figure 2 shown, for the first embodiment, a GaAs-based semiconductor device includes a GaAs substrate 11 and an epitaxial layer located on the GaAs substrate 11. The epitaxial layer at least includes a buffer layer 12, a channel layer 13, and a barrier layer 14 that are sequentially stacked on the GaAs substrate 11. A source electrode 16, a drain electrode 18, and a gate electrode 17 are located on the barrier layer 14, and the gate electrode 17 is located between the source electrode 16 and the drain electrode 18.

[0056] In the non-gated region between the source electrode 16 and the drain electrode 18, the non-gated region (Non-gated Region) refers to the region that is not directly affected by the gate electric field. Although these regions also participate in the operation process of the device, their carrier behavior is not directly controlled by the gate voltage. As Figure 3 shown, in the present invention, the non-gated region A specifically refers to the epitaxial layer located on both sides of the gate and between the gated channel and the actual source / drain contact.

[0057] The non-gated region has two ion implantation regions 2. One ion implantation region 2 is located between the gate electrode 17 and the source electrode 16, and along the direction from the gate electrode 17 to the source electrode 16, its doping concentration increases. The other ion implantation region 2 is located between the gate electrode 17 and the drain electrode 18, and along the direction from the gate electrode 17 to the drain electrode 18, its doping concentration increases. The ion implantation region 2 extends from the surface of the barrier layer 14 along the direction of the GaAs substrate 11 to the bottom surface of the barrier layer 14.

[0058] The ion implantation region 2 at least forms a first concentration region S1 and an (n + 1)-th concentration region S n+1 , where 1 ≤ n ≤ 4, and both the source electrode 16 and the drain electrode 18 are entirely located on the (n + 1)-th concentration region S n+1 .

[0059] Along the direction from the gate electrode 17 to the source electrode 16, as Figure 8 shown, when n = 2, the ion implantation region 2 forms a first concentration region S1, a second concentration region S2, and a third concentration region S3, and the widths of the first concentration region S1 and the second concentration region S2 are equal; as Figure 9 shown, when n = 3, the ion implantation region 2 forms a first concentration region S1, a second concentration region S2, a third concentration region S3, and a fourth concentration region S4, and the widths of the first concentration region S1, the second concentration region S2, and the third concentration region S3 are equal; as Figure 10As shown, when n = 4, the ion implantation region 2 forms a first concentration region S1, a second concentration region S2, a third concentration region S3, a fourth concentration region S4, and a fifth concentration region S5. The widths of the first concentration region S1, the second concentration region S2, the third concentration region S3, and the fourth concentration region S4 are equal. In the present invention, except for the (n + 1)-th concentration region, other concentration regions have the same width structure, which simplifies the production process and can also adjust the doping concentration distribution between the gate and the source / drain, and finally optimize the electric field distribution between the gate and the source / drain.

[0060] Further, the ion implantation region is Si-doped. The doping concentration range of the first concentration region is 1E16 - 5E17 cm -3 , and the doping concentration range of the (n + 1)-th concentration region is 5E17 - 1E19 cm -3 .

[0061] The first concentration region S1 can be doped with a relatively light donor impurity in a large area one or more times by an ion implantation process. Similarly, the (n + 1)-th concentration region S n+1 can be doped with a relatively high concentration of donor impurity in a small area one or more times by an ion implantation process. That is, at least two regions with different doping concentrations are formed near the source 16 and the drain 18 to reduce the parasitic resistance of the non-gated region between the source 16 and the drain 18.

[0062] Further, it further includes a passivation layer 3. The passivation layer 3 covers the gate 17 and the surface of the barrier layer 14 not covered by the source 16 and the drain 17. The passivation layer 3 can passivate the surface defects of the barrier layer 14 near the gate 17 and can reduce the damage to the metal of the gate 17 and the surface of the barrier layer 14 in the subsequent manufacturing process.

[0063] Further, the GaAs-based semiconductor device is a pHEMT or an HFET.

[0064] Meanwhile, a method for preparing a GaAs-based semiconductor device is also provided, including the following steps:

[0065] Step 1, epitaxial layer preparation: An epitaxial layer is grown on the GaAs substrate 11. The epitaxial layer includes a buffer layer 12, a channel layer 13, and a barrier layer 14 stacked in sequence on the GaAs substrate 11;

[0066] Step 2, gate 17 preparation: The surface of the barrier layer 14 is cleaned, and the gate 17 is prepared by a photolithography process and a gate metal deposition process;

[0067] Step 3, passivation layer 3 preparation: The passivation layer 3 is deposited on the surfaces of the gate 17 and the barrier layer 14 by techniques such as plasma-enhanced chemical vapor deposition (PECVD);

[0068] Step 4, Preparation of the ion implantation region in the non-gated area: Through photolithography and ion implantation processes, the non-gated area between the source 16 and the drain 18 is lightly doped, and the doping concentration range is 1E16 - 5E17 cm -3 , at least one concentration region is formed, and the first formed concentration region is the first concentration region; alternatively, the first concentration region and the second concentration region can also be formed; alternatively, the first concentration region, the second concentration region, and the third concentration region can also be formed; alternatively, the first concentration region, the second concentration region, the third concentration region, and the fourth concentration region can also be formed;

[0069] Step 5: Preparation of the ion implantation region under the source 16 and the drain 18: Through photolithography and ion implantation processes, the ohmic contact region under the source 16 and the drain 18 is heavily doped to form the (n + 1)-th concentration region, where 1 ≤ n ≤ 4, and the doping concentration range is 5E17 - 1E19 cm -3 , and the activation of the ions is completed;

[0070] Step 6: Opening holes in the passivation layer in the regions of the source 16 and the drain 18. Through photolithography and passivation layer etching processes, the passivation layer 3 at the deposition positions of the source 16 and the drain 18 is etched to form holes, exposing the metal electrode deposition regions of the source 16 and the drain 18;

[0071] Step 7: Preparation of the source 16 and the drain 18. Through photolithography and metal thin film deposition processes, metal is deposited in the metal electrode deposition regions and extends to cover at least part of the passivation layer 3 adjacent to the holes, forming the source 16 and the drain 18, and alloying is performed. The source 16 and the drain 18 are all located on the (n + 1)-th concentration region.

[0072] As Figure 4 shown, it is the second embodiment. Different from the prior art, this embodiment has no cap layer structure. A GaAs-based pHEMT device includes a GaAs substrate 11 and an epitaxial layer. The epitaxial layer is located on the GaAs substrate 11. The epitaxial layer at least includes a buffer layer 12, a channel layer 13, and a barrier layer 14 that are sequentially stacked on the GaAs substrate 11. The source 16, the drain 18, and the gate 17 are located on the barrier layer 14, and the gate 17 is located between the source 16 and the drain 18. It also includes a lower doping layer 4, a lower isolation layer 5, an upper isolation layer 6, and an upper doping layer 7. The buffer layer 12, the lower doping layer 4, the lower isolation layer 5, the channel layer 13, the upper isolation layer 6, the upper doping layer 7, and the barrier layer 14 are sequentially stacked. The ion implantation region 2 extends from the barrier layer 14 towards the GaAs substrate 11. The lower doping layer 4 and the upper doping layer 7 adopt a high-concentration planar doping process to provide electrons for the channel layer 13. The lower isolation layer 5 separates the lower doping layer 4 and the channel layer 13, and the upper isolation layer 6 separates the upper doping layer 7 and the channel layer 13, avoiding the scattering effect of the impurities in the lower doping layer 4 and the upper doping layer 7 on the channel electrons and improving the electron mobility of the channel layer 13.

[0073] The thickness of the barrier layer 14 is H1, the thickness from the surface of the barrier layer 14 to the bottom surface of the lower doped layer 4 is H2, the implantation depth of the ion implantation region 2 is Hj, H1 = Hj, and Hj < H2. During the epitaxial layer preparation process of the pHEMT device, usually a lower doping (such as 1E17 cm -3 or less) is used in the barrier layer 14 or the barrier layer 14 is not doped, so that the depletion layer under the gate 17 is deeper, to improve the breakdown voltage, parallel conductance effect and short-channel effect of the device. However, this approach will also cause a large parasitic resistance to be introduced in the non-gated region due to the low doping concentration. Therefore, preferably, the implantation depth Hj of the ion implantation region 2 is equal to the thickness H1 of the barrier layer 14.

[0074] In this embodiment, the ion implantation region 2 is Si-doped. When n = 1, the doping concentration range of the first concentration region S1 is 1E16 - 5E17 cm -3 , and the doping concentration range of the second concentration region S2 is 5E17 - 1E19 cm -3 . When the doping concentration of S1 exceeds 5E17cm -3 , it is easy to cause a low breakdown voltage, parallel conductance effect and short-channel effect. When the doping concentration of S1 is less than 1E16cm -3 , the parasitic resistance generated in the non-gated region will have an obvious impact on the transconductance gm, resulting in the deterioration of the gain characteristics and noise characteristics of the device; the doping concentration of S2 reaches 5E17 cm -3 to enable the source and drain alloy to form a lower ohmic contact resistance with its contact surface. Exceeding 1E19 cm -3 is difficult to achieve and may cause impurity merger (impurity compensation effect), resulting in insufficient ionization and problems of impurity diffusion.

[0075] The lower doped layer 4 and the upper doped layer 7 adopt planar doping to provide electrons for the channel interface potential well to form a two-dimensional electron gas, avoiding the breakdown effect caused by the high doping of the barrier layer 14, especially the barrier layer 14 under the gate 17. The doping concentration of the lower doped layer 4 is about 1E12 - 1E13 cm -2Both the lower doping layer 4 and the upper doping layer 7 are Si-doped, and the concentration of the upper doping layer 7 is 1 to 10 times that of the lower doping layer 4. When the ratio of the lower doping layer 4 to the upper doping layer 7 is 1 to 4, the channel electron distribution will be more uniform, improving the flatness of the transconductance versus gate voltage curve, making the pHEMT of the present invention have better linearity and being applicable to the field of radio frequency power amplifiers (PAs). When the ratio of the lower doping layer 4 to the upper doping layer 7 is 4 to 10, the control ability of the gate over the channel electron concentration can be enhanced, making the transconductance versus gate voltage curve sharper, making the pHEMT of the present invention have better noise characteristics and being applicable to the field of radio frequency low noise amplifiers (LNAs).

[0076] In this embodiment, along the gate length direction, when the gate 17 is a Y-shaped gate, the gate cap width of the Y-shaped gate is L1, the root widths of the source 16 and the drain 18 are the same, the root width of the source 16 is L2, the distance between the source 16 and the drain 18 is L3, and the width of the ion implantation region 2 is L6, where L6 = (L3 + 2L2 - L1) / 2. Of course, it can also be applied to a T-shaped gate.

[0077] As Figure 5 shown, a preparation method of a GaAs-based pHEMT device includes the following steps:

[0078] Step 1, epitaxial layer preparation: Grow an epitaxial layer on the GaAs substrate 11. The epitaxial layer includes a buffer layer 12, a lower doping layer 4, a lower isolation layer 5, a channel layer 13, an upper isolation layer 6, an upper doping layer 7, and a barrier layer 14 that are sequentially stacked on the GaAs substrate 11. Among them, the GaAs substrate 11 is a semi-insulating GaAs substrate, the material of the buffer layer 12 is Al x1 Ga 1-x1 As, where the Al component x1 = 0.2 to 0.3, the material of the channel layer 13 is In x2 Ga 1-x2 As, the In component x2 = 0.2 to 0.4, and the material of the barrier layer 14 is Al x3 Ga 1-x3 As, and the Al component x3 = 0.2 to 0.3.

[0079] Step 2, gate 17 preparation: Clean the surface of the barrier layer 14, and perform gate 17 preparation using photolithography technology and gate metal deposition technology.

[0080] Step 3, passivation layer 3 preparation: Use techniques such as plasma enhanced chemical vapor deposition (PECVD) to deposit a passivation layer 3 on the surfaces of the gate 17 and the barrier layer 14. In this embodiment, the passivation layer 3 is a silicon nitride (SIN x ) dielectric thin film to passivate the surface of the barrier layer 14.

[0081] Step 4, Preparation of the ion implantation region in the non-gated area: Through photolithography, form the non-gated area between the source electrode 16 and the drain electrode 18. Through ion implantation, lightly dope the non-gated area to form the first concentration region S1, and the doping concentration range is 1E16~5E17 cm -3 .

[0082] Step 5: Preparation of the ion implantation region under the source electrode 16 and the drain electrode 18: Through photolithography, form the ohmic contact region under the source electrode 16 and the drain electrode 18. Through ion implantation, heavily dope the ohmic contact region to form the second concentration region S2, and the doping concentration range is 5E17~1E19 cm -3 , and complete the activation of the ions.

[0083] Step 6: Open holes in the passivation layer in the regions of the source electrode 16 and the drain electrode 18. Through photolithography and passivation layer etching processes, etch the SiNx at the deposition positions of the source electrode 16 and the drain electrode 17 to form holes, exposing the metal electrode deposition regions of the source electrode 16 and the drain electrode 17.

[0084] Step 7: Preparation of the source electrode 16 and the drain electrode 17. Through photolithography and metal thin film deposition processes, deposit metal in the metal electrode deposition regions, and extend to cover at least part of the passivation layer 3 adjacent to the holes, forming the source electrode 16 and the drain electrode 17, and perform alloying.

[0085] This is the best preparation method. Other preparation methods can also be used. For example, after depositing the passivation layer, first open holes in the passivation layer in the regions of the source electrode 16 and the drain electrode 18, then prepare the ion implantation region in the non-gated area, and finally prepare the ion implantation region under the source electrode 16 and the drain electrode 18.

[0086] As Figure 6 shown, it is the third embodiment. The difference from the second embodiment is that further, the second concentration region extends along the direction from the gate electrode 17 to the drain electrode 16 to form an extension region, and the width of the extension region is L7. The range of L7 is 0.5~5μm to avoid the problem that the source-drain electrode metal does not contact the second concentration region sufficiently during the preparation of the source-drain electrodes and the alloying process.

[0087] The width of the second concentration region S2 is L5. The root widths of the source electrode 16 and the drain electrode 18 are the same, and the root width of the source electrode 16 is L2, where L2<L5. The top widths of the source electrode 16 and the drain electrode 18 are the same, which is L8, and L8 = L2 + Y, where Y = 1~5μm. The tops of the source electrode 16 and the drain electrode 18 completely cover the holes in the passivation layer 3, preventing the cleaning agent solution in the subsequent process from infiltrating through the holes in the passivation layer 3 near the source electrode 16 and the drain electrode 18, and avoiding electrochemical damage caused by the contact part of the cleaning agent solution at the roots of the source electrode 16 and the drain electrode 18 and the ion implantation region.

[0088] In this embodiment, the passivation layer 3 is a SiO2 dielectric film.

[0089] As Figure 7 shown, this is the fourth embodiment, which is different from the second embodiment in that when the gate 17 is a trapezoidal gate, the root width of the trapezoidal gate is L4, the root widths of the source 16 and the drain 18 are the same. Along the gate length direction, the root width of the source 16 is L2, the distance between the source and the drain is L3, the width of the ion implantation region is L6, and L6 = (L3 + 2L2 - L4 - X) / 2, where 0.1μm ≤ X ≤ 2μm. Preferably, X is 0.15μm. Currently, the gate 17 length range of pHEMT manufacturing technology is mainly between 0.7 and 5μm. Electron beam lithography, ultraviolet lithography, and deep ultraviolet lithography technologies are used for gate lithography. To ensure that the metal preparation of the gate 17 will not cause metal misalignment (metal walk) due to process control factors and ensure there is enough area under the gate, it is reasonable to control 0.1μm ≤ X ≤ 2μm. Considering the high-frequency application of pHEMT devices, the gate 17 is preferably 0.1 - 0.15μm, and X is preferably 0.15μm.

[0090] The width of the second concentration region S2 is L5, the root widths of the source 16 and the drain 18 are the same, and the root width of the source 16 is L2, where L2 = L5. In this embodiment, the passivation layer 3 is an Al2O3 dielectric film.

[0091] The ion implantation region 2 extends from the barrier layer 14 towards the GaAs substrate 11, passing through the upper doped layer 7, the upper isolation layer 6, the channel layer 13, the lower isolation layer 5 to the lower doped layer 4. The thickness of the barrier layer 14 is H1, the thickness from the surface of the barrier layer 14 to the bottom surface of the lower doped layer 4 is H2, and the implantation depth of the ion implantation region 2 is Hj, where H1 < Hj < H2. Usually, the doping concentration of the barrier layer 14 is relatively low (<5E17cm -3 ), which is likely to introduce a relatively large parasitic resistance. H1 < Hj can reduce the parasitic resistance introduced by the barrier layer 14; the upper isolation layer 6 and the lower isolation layer 5 are not doped. If the upper isolation layer 6 and the lower isolation layer 5 are relatively thick, they will also introduce a relatively large parasitic resistance. Therefore, doping down to the lower doped layer 4 can reduce the parasitic resistance effect of the upper isolation layer 6 and the lower isolation layer 5; Hj < H2 aims to reduce the penetration of impurities into the region below the buffer layer 12 and reduce the leakage current and parasitic capacitance effect of the GaAs substrate 11.

[0092] Some embodiments of the present invention also provide a radio frequency module, including the GaAs-based pHEMT device provided in any of the foregoing embodiments. The radio frequency module is, for example, a low-noise amplifier, a power amplifier, an oscillator, etc. The radio frequency module provided in this embodiment has at least the same effects as the GaAs-based pHEMT, which will not be elaborated here.

[0093] Some embodiments of the present invention further provide a communication device, including the foregoing radio frequency module. The communication device may be, for example, a wireless communication base station, a satellite communication device, a radar system, an optical fiber communication device, etc. It has at least the same effect as the foregoing GaAs-based pHEMT, which will not be elaborated here.

[0094] The above are only the preferred embodiments of the present invention, and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to equivalent embodiments by using the disclosed technical content within the scope of the technical solution of the present invention. However, as long as it does not depart from the content of the technical solution of the present invention, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A GaAs-based semiconductor device, characterized in that: It includes a GaAs substrate and an epitaxial layer. The epitaxial layer is located on the GaAs substrate. The epitaxial layer at least includes a buffer layer, a channel layer, and a barrier layer that are sequentially stacked on the GaAs substrate. The source electrode, drain electrode, and gate electrode are located on the barrier layer, and the gate electrode is located between the source electrode and the drain electrode; in the non-gated region between the source electrode and the drain electrode, there are two ion implantation regions, which are respectively located between the gate electrode and the source electrode and between the gate electrode and the drain electrode. The ion implantation regions extend from the surface of the barrier layer towards the GaAs substrate to the bottom surface of the barrier layer. The doping concentration of the ion implantation region between the gate electrode and the source electrode increases along the direction from the gate electrode to the source electrode, and the doping concentration of the ion implantation region between the gate electrode and the drain electrode increases along the direction from the gate electrode to the drain electrode. The ion implantation region at least forms a first concentration region and an (n + 1)-th concentration region, and the concentration of the (n + 1)-th concentration region is greater than that of the first concentration region, where 1 ≤ n ≤ 4, and the source electrode and the drain electrode are all located on the (n + 1)-th concentration region.

2. The GaAs-based semiconductor device according to claim 1, wherein: The ion implantation region is doped with Si, and the doping concentration range of the first concentration region is 1E16 to 5E17 cm -3 , and the doping concentration range of the n+1th concentration region is 5E17 to 1E19 cm -3 .

3. A GaAs-based semiconductor device according to claim 1, characterized in that: It further includes a lower doping layer, a lower isolation layer, an upper isolation layer, and an upper doping layer. The buffer layer, the lower doping layer, the lower isolation layer, the channel layer, the upper isolation layer, the upper doping layer, and the barrier layer are sequentially stacked. The ion implantation region extends from the barrier layer towards the GaAs substrate. The thickness of the barrier layer is H1, the thickness from the surface of the barrier layer to the bottom surface of the lower doping layer is H2, and the implantation depth of the ion implantation region is Hj, where H1 < Hj < H2.

4. A GaAs-based semiconductor device according to claim 3, characterized in that: The concentration range of the lower doping layer is 1E12 - 1E13 cm -2 , and the concentration of the upper doping layer is 1 - 10 times that of the lower doping layer.

5. A GaAs-based semiconductor device as claimed in claim 1, characterized in that: It further includes a passivation layer, and the passivation layer covers the gate electrode and the surface of the barrier layer not covered by the source electrode and the drain electrode.

6. A GaAs-based semiconductor device according to claim 1, characterized in that: When the gate electrode is a Y-shaped gate, the gate cap width of the Y-shaped gate is L1, the root widths of the source electrode and the drain electrode are the same, the root width of the source electrode is L2, the distance between the source electrode and the drain electrode is L3, and the width of the ion implantation region is L6, and L6 = (L3 + 2L2 - L1) / 2.

7. A GaAs-based semiconductor device according to claim 1, characterized in that: When the gate electrode is a trapezoidal gate, the gate root width of the trapezoidal gate is L4, the root widths of the source electrode and the drain electrode are the same, the root width of the source electrode is L2, the distance between the source electrode and the drain electrode is L3, and the width of the ion implantation region is L6, and L6 = (L3 + 2L2 - L4 - X) / 2, where 0.1 μm ≤ X ≤ 2 μm.

8. A GaAs-based semiconductor device according to claim 1, characterized in that: The root widths of the source electrode and the drain electrode are the same, the root width of the source electrode is L2, the top widths of the source electrode and the drain electrode are the same, which is L8, and L8 = L2 + Y, where Y = 1 - 5 μm.

9. A GaAs-based semiconductor device according to claim 1, characterized in that: The material of the buffer layer is Al x1 Ga 1- x1 In As, the Al component x1 = 0.2 - 0.3, and the material of the channel layer is In x2 Ga 1-x2 As, the In component x2 = 0.2 - 0.4, and the material of the barrier layer is Al x3 Ga 1-x3 As, the Al component x3 = 0.2 - 0.

3.

10. A GaAs-based semiconductor device according to claim 1, characterized in that: The width of the (n + 1)-th concentration region is L5, the root widths of the source electrode and the drain electrode are the same, the root width of the source electrode is L2, and L2 ≤ L5.

11. A GaAs-based semiconductor device according to claim 1, characterized in that: The GaAs-based semiconductor device is a pHEMT or an HFET.

12. A radio frequency module, characterized in that, It includes the GaAs-based semiconductor device according to any one of claims 1 to 11.

13. A communication device, characterized in that, It includes the radio frequency module according to claim 12.

14. A method for fabricating a GaAs-based semiconductor device, characterized in that: It includes the following steps: Step 1, epitaxial layer preparation: Grow an epitaxial layer on the GaAs substrate. The epitaxial layer includes a buffer layer, a channel layer, and a barrier layer that are sequentially stacked on the GaAs substrate; Step 2, gate electrode preparation: Clean the surface of the barrier layer, and perform gate electrode preparation by using a photolithography process and a gate metal deposition process; Step 3, passivation layer preparation: Use plasma-enhanced chemical vapor deposition to deposit a passivation layer on the surface of the gate electrode and the barrier layer; Step 4, Preparation of the non-gated region ion implantation region: Through photolithography and ion implantation processes, the non-gated region between the source and drain is lightly doped, and the doping concentration range is 1E16 to 5E17 cm -3 , at least one concentration region is formed, and the first formed concentration region is the 1st concentration region; Step Five: Preparation of the ion implantation region under the source and drain: Through photolithography and ion implantation processes, the ohmic contact region under the source and drain is heavily doped to form the (n + 1)-th concentration region, where 1 ≤ n ≤ 4, and the doping concentration range is 5E17~1E19 cm -3 , and the activation of the ions is completed; Step Six: Opening the Passivation Layer in the Source and Drain Regions: Through photolithography and passivation layer etching processes, the passivation layer at the deposition positions of the source and drain is etched to expose the metal electrode deposition regions of the source and drain. Step Seven: Preparation of the Source and Drain: Through photolithography and metal thin film deposition processes, metal is deposited in the metal electrode deposition regions to form the source and drain, and alloying is performed. The source and drain are all located on the n+1 concentration region.

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