Conductivity modulation enhanced group III nitride electronic devices and methods of making same

Abstract

The invention discloses a conductivity modulation enhanced III-nitride electronic device and a preparation method thereof. The device comprises a PN junction and a light reflection structure, the PN junction comprises a first conductive characteristic region and a second conductive characteristic region which are in direct contact, the conductive characteristics of the first conductive characteristic region and the second conductive characteristic region are opposite, the first conductive characteristic region is located on a first surface, inclined table surfaces are arranged on the two sides of the first surface, and the normal directions of the inclined table surfaces point to the direction in the PN junction; the light reflection structure comprises a first reflection layer, and the first reflection layer covers the first face and covers the inclined table face in a profiling mode. According to the invention, the inclined mesa is matched with the light reflecting layer, so that escaping photons are reflected back to the semiconductor structure, the conductivity modulation phenomenon is enhanced, and the effects of greatly enhancing the conductivity modulation phenomenon of the device and improving the anti-surge characteristic of the device are realized while the reverse electrical characteristic of the device is not influenced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor electronic technologies, and in particular, to a group-III nitride electronic device with enhanced conductance modulation and a preparation method thereof. Background Art

[0002] Due to advantages such as a wide bandgap, a high critical breakdown field strength, and a high electron saturation drift velocity, the third-generation semiconductor material group-III nitride (such as gallium nitride, GaN) has important application values in power supply fields such as mobile phone fast charging and data centers. Compared with a lateral power device based on an AlGaN / GaN heterojunction, the peak electric field of a vertical power device is located inside the body, and the device has better dynamic characteristics, a large current transport area, good heat dissipation performance, and high reliability.

[0003] As one of the most basic structures of a group-III nitride electronic device, a PN junction has become the basic structure of many devices, such as a vertical PN diode, a junction barrier schottky diode (JBS), a junction transistor, and a lateral high electron mobility transistor (HEMT) and hybrid anode diodes (HADs). When the PN junction is forward-biased, especially under high current injection, the majority carriers in the N-type semiconductor - electrons and the majority carriers in the P-type semiconductor - holes will form a conductance modulation phenomenon, which will significantly reduce the resistance of the device under high current, improve the surge resistance of the device, and improve the current overshoot ability of the device.

[0004] Currently, the main method to improve the conductance modulation effect is to increase the doping concentration of the P or N-type semiconductor, but this will increase the reverse leakage current of the device, affect the reverse breakdown voltage of the device, and reduce the overvoltage impact ability of the device. How to improve the conductance modulation ability of the device without affecting the off-state electrical characteristics of the device and thereby reduce the on-state loss of the device has become an important problem in GaN vertical power devices. Summary of the Invention

[0005] Aiming at the deficiencies of the prior art, the purpose of the present invention is to provide a group-III nitride electronic device with enhanced conductance modulation and a preparation method thereof.

[0006] To achieve the foregoing invention purpose, the technical solutions adopted by the present invention include:

[0007] In a first aspect, the present invention provides a group-III nitride electronic device with enhanced conductance modulation, which includes a PN junction and a light reflection structure;

[0008] The PN junction includes a first conduction characteristic region and a second conduction characteristic region in direct contact. The conduction characteristics of the first conduction characteristic region and the second conduction characteristic region are opposite. The PN junction has a first surface and a second surface disposed opposite to each other. The first conduction characteristic region is located on the first surface, and beveled surfaces are provided on both sides of the first surface, and the normal direction of the beveled surface points in the direction inside the PN junction;

[0009] The optical reflection structure includes a first reflection layer, and the first reflection layer covers the first surface and covers in imitation of the beveled surface.

[0010] In a second aspect, the present invention also provides a method for manufacturing the above-mentioned group III nitride electronic device, which includes:

[0011] Providing a PN junction having a first conduction characteristic region and a second conduction characteristic region;

[0012] Etching the PN junction on the first surface where the first conduction characteristic region is located to form beveled surfaces on both sides of the first surface, and the normal direction of the beveled surface points in the direction inside the PN junction;

[0013] Preparing a first reflection layer, and the first reflection layer covers the first surface and covers in imitation of the beveled surface.

[0014] Based on the above technical solutions, compared with the prior art, the beneficial effects of the present invention at least include:

[0015] In the present invention, an optical reflection layer for enhancing optical reflection is plated near the PN junction, and in cooperation with the shape of the beveled surfaces on both sides, photons that partially escape from the GaN material during forward biasing of the device are reflected back into the semiconductor, generating a continuous photo-generated carrier phenomenon, greatly enhancing the concentration of electrons and holes in the material, and further greatly enhancing the conductance modulation phenomenon of the device, reducing the on-resistance of the device; at the same time, when the device is in the reverse bias state, until avalanche occurs, the PN junction is in the off state, and no obvious photo-generated carriers are generated, that is, it basically has no influence on the off-state electrical properties of the device; ultimately, the effect of greatly enhancing the conductance modulation phenomenon of the device and improving the surge resistance of the device is achieved while not affecting the reverse electrical characteristics of the device.

[0016] The above description is only an overview of the technical solutions of the present invention. In order to enable those skilled in the art to more clearly understand the technical means of the present application and implement it according to the content of the specification, the following is a detailed description with reference to the preferred embodiments of the present invention and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of a semi-finished product structure obtained by etching the group III nitride epitaxial structure into beveled surfaces for a typical embodiment of the present invention;

[0018] Figure 2 Schematic diagram of the semi-finished product structure after fabricating a P-type ohmic contact on the group III nitride epitaxial structure provided by a typical embodiment of the present invention;

[0019] Figure 3 Schematic diagram of the semi-finished product structure after fabricating an optical reflection layer on the group III nitride epitaxial structure provided by a typical embodiment of the present invention;

[0020] Figure 4 Schematic diagram of the semi-finished product structure after fabricating a back electrode and a back optical reflection layer on the group III nitride epitaxial structure provided by a typical embodiment of the present invention;

[0021] Figure 5 Schematic diagram of the semi-finished product structure after fabricating a side optical reflection layer on the group III nitride epitaxial structure provided by a typical embodiment of the present invention;

[0022] Figure 6 Schematic diagram of the device structure of a group III nitride vertical junction barrier Schottky (JBS) diode or a hybrid PIN-Schottky (MPS) diode provided by another typical embodiment of the present invention;

[0023] Figure 7 Schematic diagram of the device structure of a group III nitride vertical junction field effect transistor (JFET) provided by yet another typical embodiment of the present invention;

[0024] Figure 8 Schematic diagram of the device structure of another type of group III nitride vertical junction field effect transistor (JFET) provided by still another typical embodiment of the present invention;

[0025] Figure 9 Schematic diagram of the device structure of a group III nitride vertical current aperture transistor (CAVET) provided by yet another typical embodiment 7 of the present invention;

[0026] Figure 10 Schematic diagram of the device structure of a group III nitride lateral high electron mobility transistor (HEMT) provided by yet another typical embodiment of the present invention;

[0027] Figure 11Schematic diagram of the device structure of a group-III nitride lateral hybrid anode diode (HAD) provided for another typical embodiment of the present invention. Detailed implementation manners

[0028] In view of the deficiencies in the prior art, the inventors of this case have proposed the technical solution of the present invention through long-term research and a large number of practices. The following will further explain the technical solution, its implementation process, principle, etc.

[0029] In the following description, many specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention may be practiced in other ways different from those described herein. Therefore, the scope of protection of the present invention is not limited by the specific embodiments disclosed below.

[0030] Moreover, relational terms such as "first" and "second" are only used to distinguish one component or method step with the same name from another, and do not necessarily require or imply any such actual relationship or order between these components or method steps.

[0031] Due to the presence of parasitic current and inductive load in the circuit, when the PN junction device is just turned on, the energy stored in the inductor will form a relatively high forward surge current. The excessive surge current may cause thermal failure of the device. For group-III nitride electronic devices containing PN junctions, at high currents, their conductance modulation effect will significantly reduce the on-resistance of the device, reduce the Joule heat generation of the device, reduce the junction temperature of the device, and improve the reliability of the device. As described above, the main method currently capable of significantly improving the conductance modulation effect of the device is to increase the doping concentration of the semiconductor and increase the electron and hole densities to enhance the modulation. However, increasing the doping concentration of the semiconductor will reduce the reverse breakdown voltage of the device, reduce the overvoltage impact ability of the device, and reduce the reliability of the device. That is, the current technology is difficult to improve the conductance modulation ability of the device without weakening the off-state characteristics of the device.

[0032] Aiming at the above problems, the main object of the present invention is to provide a structure for improving the conductance modulation ability of group-III nitride electronic devices and its preparation method, and improve the surge resistance characteristics of the device. Based on the above object, the invention proposes a technology and implementation scheme for reducing the enhancement of the conductance modulation ability of light output based on an inclined mesa and an optical reflection layer.

[0033] Specifically, an embodiment of the present invention provides a group III nitride electronic device with enhanced conductance modulation, which includes a PN junction and an optical reflection structure; the PN junction includes a first conduction characteristic region and a second conduction characteristic region in direct contact, the conduction characteristics of the first conduction characteristic region and the second conduction characteristic region are opposite, the PN junction has a first surface and a second surface arranged back to back, the first conduction characteristic region is located on the first surface, and beveled surfaces are arranged on both sides of the first surface, and the normal direction of the beveled surface points in the direction inside the PN junction; the optical reflection structure includes a first reflection layer, the first reflection layer covers the first surface and covers it in imitation of the beveled surface.

[0034] The key point of the above technical solution is to deposit a high-reflectivity optical reflection layer near and around the metal contact of the P-type semiconductor. Generally, there are two types of optical reflection layers used. One is a dielectric reflection layer, such as a stacked dielectric structure composed of SiN x and SiO2, and the other is a metal reflection layer, such as Al or Ag, etc. The metal reflection layer can also be used as a field plate terminal to adjust the electric field distribution when the device is in the off state.

[0035] By plating an optical reflection layer with enhanced optical reflection (including the front, back, and side surfaces of the device) near the PN junction, photons that partially escape from the GaN material during forward biasing of the device are reflected back into the semiconductor, generating a continuous photo-generated carrier phenomenon, greatly enhancing the concentration of electrons and holes in the material, and further greatly enhancing the conductance modulation phenomenon of the device, reducing the on-resistance of the device; at the same time, when the device is in the reverse bias state, until avalanche occurs, the PN is in the off state, and no obvious photo-generated carriers are generated, that is, it has no influence on the off-state electrical properties of the device. Finally, while not affecting the reverse electrical characteristics of the device, the conductance modulation phenomenon of the device is greatly enhanced, and the surge resistance characteristics of the device are improved.

[0036] In some embodiments, the first conduction characteristic region and the second conduction characteristic region are longitudinally stacked along the thickness direction from the first surface to the second surface, and the angle θ between the normal direction of the beveled surface and the first surface is 0° < θ ≤ 80°.

[0037] Or in some embodiments, partial structures of the first conduction characteristic region and the second conduction characteristic region are arranged horizontally along the in-plane direction of the first surface or the second surface, and the angle θ between the normal direction of the beveled surface and the first surface is 0° < θ ≤ 15°.

[0038] In the technical solution provided by the present invention, an optical reflection layer is added near the PN junction of the inclined mesa surface to better improve the light reflectivity. Therefore, in the present invention, the inclined mesa surface is necessary, and the inclination angle (the θ angle shown in the figure) is generally between 0 and 80° (greater than 0). For longitudinal power devices based on a lateral PN junction, such as PN diodes, JBS / MPS, or JFETs, in order to balance the forward and reverse electrical characteristics and the optical reflectivity, the preferred inclination angle is between 0 and 15°.

[0039] In some embodiments, for the longitudinal power device based on a lateral PN junction described above, its specific structural characteristics are as follows: the second conductive characteristic region includes a layered portion and a plurality of protruding portions. The layered portion extends from the second surface to the middle of the PN junction, and the protruding portions extend from the middle of the PN junction to the first surface. The width of the protruding portions is lower than that of the layered portion; the second conductive characteristic region fills the space between the plurality of protruding portions.

[0040] More specifically, the structural characteristics of the PN junction are reflected in: in some embodiments, along the thickness direction, the first conductive characteristic region sequentially includes a highly doped P-type group III nitride layer and a lowly doped P-type group III nitride layer, and the second conductive characteristic region sequentially includes an N-type drift region, a lowly doped P-type group III nitride layer, and a highly doped P-type group III nitride layer.

[0041] Or in some embodiments, along the thickness direction, the first conductive characteristic region includes a P-type group III nitride layer, and the second conductive characteristic region sequentially includes a barrier layer, a channel layer, and a transition layer.

[0042] In addition, regarding some key technical details, in some embodiments, the inclined mesa surface completely covers at least the side surface of the first conductive characteristic region, thereby enabling better optical reflection and conductance modulation effects.

[0043] Moreover, in some embodiments, a dielectric passivation layer is further provided between the first reflection layer and the first surface.

[0044] In some embodiments, in the middle of the first surface, the dielectric passivation layer is provided with a window that exposes the first surface; the group III nitride electronic device further includes a first contact electrode that fills the window and makes an ohmic contact with the first conductive characteristic region.

[0045] In some embodiments, a second contact electrode is further provided on the second surface, the second reflection layer is provided in the middle of the second surface, and the second contact electrode surrounds the second reflection layer and makes an ohmic contact with the second conductive characteristic region.

[0046] In some embodiments, the device further includes a second reflective layer and a third reflective layer, where the second reflective layer covers the second surface, and the third reflective layer covers the sidewall surface of the PN junction.

[0047] The second aspect of the embodiments of the present invention further provides a method for manufacturing the group III nitride electronic device provided in any of the above embodiments, which includes the following steps:

[0048] Provide a PN junction having a first conductive characteristic region and a second conductive characteristic region;

[0049] Etch the PN junction on the first surface where the first conductive characteristic region is located to form inclined mesa surfaces on both sides of the first surface, and the normal direction of the inclined mesa surfaces points in the direction inside the PN junction;

[0050] Prepare a first reflective layer, where the first reflective layer covers the first surface and conformally covers along the inclined mesa surfaces.

[0051] As a typical example of the above technical solution, a method of metal organic chemical vapor deposition (MOCVD) can be used to grow a group III nitride PN power diode structure on a conductive substrate, specifically including an N-type current spreading layer, a lightly doped N-type drift region / breakdown voltage layer, a lightly doped P-type semiconductor layer, and a highly doped P-type semiconductor layer for ohmic contact preparation, as shown in Fig. 1.

[0052] First, based on the method of dry etching, the etching and forming of the inclined mesa surfaces are realized. The etching depth is generally greater than the sum of the thicknesses of the P-type semiconductor layer (i.e., the first conductive characteristic region), as Figure 2 shown. Then, ohmic contacts are prepared on the ohmic contact layer, and then a high-quality passivation layer is deposited. The medium of the passivation layer is subjected to a dielectric windowing process, and then a first reflective layer with a high reflectivity is deposited over the entire surface, as Figure 3 shown. Finally, back ohmic contacts and a second reflective layer are prepared, as Figure 4 shown, and finally a third reflective layer is prepared on the sidewalls, as Figure 5 shown.

[0053] It should be noted that the above solutions may further include more device processing techniques, such as the Mg activation process for the P-type semiconductor, and subsequent field plate or ion implantation processes for electric field homogenization, and subsequent thick metal pad processes for high-current testing.

[0054] The surface of the N-type or P-type semiconductor material can be a relatively flat plane, or a surface with large undulations and a large height difference. Such a surface with large undulations can exist either inside the N-type or P-type semiconductor or between the P-type and N-type semiconductors (which is more common in vertical trench devices), and the height difference is between 0 and 100 μm.

[0055] It should be specifically noted that the doping concentration distribution of the above-mentioned N-type or P-type semiconductor materials can be: i) a graded type: including linear grading and non-linear grading; ii) a step type: including equal-doping steps and non-equal-doping steps. At the same time, for the semiconductor material, it can be a binary alloy such as GaN and AlN, and it may also be a ternary or quaternary alloy composed of Al x Ga y In (1-x-y) N. The component change mode can be: i) a graded type: including linear grading and non-linear grading; ii) a step type: including equal-component steps and non-equal-component steps.

[0056] The technical solutions of the present invention will be further described in detail below through several embodiments in conjunction with the accompanying drawings. However, the selected embodiments are only used to illustrate the present invention and do not limit the scope of the present invention.

[0057] Embodiment 1

[0058] The device of this embodiment is a vertical PN power diode, and the final structure is as Figure 5 shown. The device epitaxial structure mainly consists of a Mg heavily doped p++-GaN layer 105 for ohmic contact preparation, a p-GaN layer 104 with conventional Mg doping, a low-doped n-GaN drift region layer 103, a highly doped n+GaN layer 102, and a GaN substrate 101 at the bottom; the anode 111 and cathode 114 of the device are mainly used to conduct current, the dielectric layer 112 is mainly used to passivate the surface, and the surface reflector layer 113A and the sidewall reflector layer 113B are mainly used to reflect the escaping photons back.

[0059] The preparation process of this embodiment refers to the attached Figures 1-5 . Using the method of metalorganic chemical vapor deposition (MOCVD), on the GaN substrate 101, n+GaN with a thickness of 1 um and a doping concentration of 3×10 18 cm -3 is epitaxially grown in sequence, n+GaN with a thickness of 10 um and a doping concentration of 8×10 15 cm -3 , p+GaN with a thickness of 0.5 um and a Mg doping concentration of 2×10 19 cm -3 , and p++GaN with a thickness of 20 nm and a Mg doping concentration of 2×10 20 cm -3 .

[0060] After cleaning the epitaxial wafer, using photoresist as a mask, based on the ICP etching method, an inclined mesa with a depth of ~600 nm and an inclination angle θ of 5° is etched. Then, Ni / Au (50 / 100 nm) is deposited on p++ GaN as the ohmic contact metal. After the anode metal annealing, then, a high-quality 100 nm PECVD SiO2 is deposited over the entire surface as a passivation layer. Then, based on the RIE method, the window is opened to expose the anode metal. Then, a first reflective layer with a high reflectivity of Al / Cr = 300 / 50 nm is deposited over the entire surface. After the front process is completed, first, a cathode ohmic contact Ti / Al / Ti / Au = 20 / 130 / 50 / 100 nm is deposited on the back, and then a dielectric optical reflective layer with a high reflectivity is deposited. After the processes on the front and bottom surfaces are completed, deep etching isolation is performed on the wafer to form multiple independent devices. Then, a third reflective layer with a high reflectivity is deposited on the sidewalls of the devices in the deeply etched trenches. Finally, a GaN vertical PN power diode is fabricated.

[0061] Comparative Example 1

[0062] This comparative example is generally the same as Example 1, and the main difference lies in:

[0063] The step of forming an inclined mesa by ICP etching is omitted, and instead, the planar state is retained.

[0064] Comparative Example 2

[0065] This comparative example is generally the same as Example 1, and the main difference lies in:

[0066] In the step of forming an inclined mesa by ICP etching, the height of the inclined mesa is insufficient, only covering the p++-GaN layer 105, but not covering the p-GaN layer 104 doped with Mg conventionally.

[0067] The on-state current and cut-off voltage of the devices provided in the above Example 1 and Comparative Examples 1-2 are tested, and it is found that: the breakdown voltage of the device in Comparative Example 1 reaches 700 V, and the differential on-resistance of the device is 1.1 mΩ / cm -2 , while the breakdown voltage of the device in Example 1 reaches 1660 V and the differential on-resistance of the device is 0.2 mΩ / cm -2 .

[0068] The lower differential resistance in Example 1 mainly stems from enhanced photon reflection, which strengthens the conductance modulation phenomenon of the device, thereby significantly reducing the on-resistance of the device. Meanwhile, the inclined mesa structure regulates the electric field distribution at the edge of the PN junction when the device is reverse-biased, improving the reverse breakdown voltage of the device; while the performance of Comparative Example 2 is between that of Example 1 and Comparative Example 1. Since the etching depth of the inclined mesa is insufficient to cover the entire P-type layer, the photon reflection ability is insufficient, making it difficult to fully exert the conductance modulation effect. Moreover, the shallow etching of the inclined mesa (i.e., the p-GaN layer is not completely etched away) will significantly affect the electric field at the edge of the junction when the device is reverse-biased, resulting in a relatively high electric field at the edge of the device junction and a lower breakdown voltage of the device.

[0069] Example 2

[0070] The device of this example is a vertical JBS / MPS power diode, as Figure 6 shown. Its device structure mainly consists of a low-doped n-GaN drift region layer 203, a highly doped n+GaN layer 202, and a support layer 20l at the bottom. The p-GaN layer 204 is Mg-doped p-GaN achieved by selective area. The implementation method can be to directly implant Mg ions on the n-GaN and then activate it, or to etch the n-GaN into a groove and then perform secondary epitaxy to obtain it; the anode 211 and cathode 214 of the device are mainly used to conduct current, the dielectric layer 212 is mainly used to passivate the surface, and the surface reflection layer 213A and sidewall reflection layer 213B are mainly used to reflect the escaping photons back.

[0071] The difference in the preparation process from Example 1 is that in this example, before the inclined mesa etching, deep trench etching is first carried out to form a mesa with a width of 1 um and a depth of 1 um, and then the selective area p-GaN process (using secondary epitaxy or Mg implantation and then activation) is carried out on the whole surface.

[0072] Example 3

[0073] The device of this example is a vertical JFET, as Figure 7 shown. Its device structure is similar to the epitaxial structure of Example 2, except that here it is a transistor rather than a diode. Its basic working principle is as follows: When a positive voltage is applied to the gate 311 and the lateral PN junction between the gate 311 and the source 312 is opened, if a positive voltage is applied to the drain 315 at this time, electrons can be transported from the source 312 to the drain 315, and the device is in the on state; when a negative voltage or zero bias is applied to the gate 311, the lateral PN junction between the gate 311 and the source 312 is turned off. When a positive voltage is applied to the drain 315 at this time, the carriers emitted from the source 312 are difficult to be transported to the drain 315, and the device is in the off state.

[0074] The other structures are: N-type group III nitride 301 with a high doping concentration, N-type group III nitride 302 with the second highest doping concentration, N-type drift region 303, P-type group III nitride 304, dielectric passivation layer 313, first reflection layer 314A, and second optical reflection layer 314B.

[0075] Such as Figure 7 The difference from the epitaxial structures of Specific Embodiments 1 and 2 lies in that there is an n+GaN layer 305 for ohmic contact preparation on the surface layer of the epitaxial structure. Based on Embodiment 2, after the selective p-GaN process is completed, a source metal of Ti / Al / Ti / Au = 20 / 130 / 50 / 100 nm is deposited on the n+GaN layer 305, and a gate metal of Ni / Au = 50 / 100 nm is deposited on the P-type group III nitride 304. The subsequent processes refer to Embodiment 2.

[0076] Compared with Figure 7 , considering the different epitaxial structures, it can also be fabricated into Figure 8 The JFET device shown. Compared with the JFET in Figure 7 , in the JFET device in Figure 8 , the P-type group III nitride 304 is thinner, resulting in the N-type drift region 303 layer being higher than the p-type GaN layer.

[0077] Embodiment 4

[0078] The device of this embodiment is a vertical CAVET, as shown in Figure 9 . Its device structure mainly consists of a first p-GaN layer 404A doped with Mg, a first n-GaN drift region layer 403A with a low doping concentration, a highly doped n+GaN layer 402, and a bottom support layer 401. The manufacturing method is generally as follows: Selective area (p-GaN etching followed by secondary epitaxy or Si ion implantation activation to achieve the second n-GaN drift region layer 403B on p-GaN. Subsequently, the n-GaN is thickened, and then an AlGaN barrier layer 405 and a second p-GaN layer 404B are grown thereon. The basic working principle of the device is: When the gate is at zero bias or negative bias, the p-GaN gate depletes the two-dimensional electron gas between AlGaN and GaN, the channel is turned off, and electrons emitted from the source are difficult to transmit to the drain, and the device is turned off; When the gate is positively biased, when the two-dimensional electron gas between AlGaN and GaN is restored, electrons emitted from the source are smoothly transmitted to the drain, and the device is turned on.

[0079] The specific preparation process of this embodiment can refer to the above Figure 8, and Examples 1, 2 and 3, the main difference is that this structure is used in CAVET devices. First, a N-type group III nitride with a second-highest doping concentration, an N-type drift region, and a P-type group III nitride are directly epitaxially grown on a substrate in sequence. Then, based on a photoresist as a mask, an aperture with a width of 2 μm and a depth of 800 nm is etched. After cleaning, a u-GaN channel layer with a thickness of 800 nm, an Al(Ga)N barrier layer with a thickness of 20 nm and an Al composition of 25%, and a p-GaN layer with a doping concentration of 2E 19 cm- 3 is etched.

[0080] Then, the Al(Ga)N barrier layer is etched through to the u-GaN channel layer, and then an ohmic contact source metal is deposited: Ti / Al / Ti / Au = 6 / 120 / 50 / 100 nm. After metal annealing, a gate metal is deposited on the p-GaN layer: 20 nm thick TiN. The processes of the subsequent dielectric layer, planar reflection layer, and side reflection layer are similar to those in Example 2.

[0081] Example 5

[0082] The device in this example is a lateral HEMT. As shown in Figure 10, its device structure mainly consists of a substrate layer 501, a stress buffer layer 502, a channel layer 503, a barrier layer 504, and a p-GaN gate control layer 505; in addition, it also includes a source 514A, a drain 514B, a gate 511, a passivation layer 512, and an optical reflection layer 513.

[0083] Referring to Figure 10 in this example, as well as Specific Examples 1, 2 and 3. By using the method of metalorganic chemical vapor deposition (MOCVD), a 300 nm AlN / AlGaN transition layer structure, a 550 nm high-quality unintentionally doped GaN layer with a low electron concentration, a 20 nm AlGaN barrier layer, and an 80 nm p-GaN are deposited on a Si<111> substrate.

[0084] Using a photoresist as a mask, after photolithographic patterning, the p-GaN layer in the non-gate region is removed by dry etching, so that the tilt angle θ of the p-GaN mesa is 5°, and the etching stops at the AlGaN barrier layer. A p-GaN gate is fabricated in the gate trench region, and ohmic contacts are fabricated in the AlGaN barrier region as the source (504A) and drain metals.

[0085] Example 6

[0086] The device in this example is a lateral HAD, as Figure 11As shown, its device structure mainly consists of a substrate layer 601, a stress buffer layer 602, a channel layer 603, a barrier layer 604, and a p-GaN gate control layer 605; additionally, it also includes a hybrid anode 611 and a cathode 614, a passivation layer 612, and an optical reflection layer 613.

[0087] In this embodiment, the metal organic chemical vapor deposition (MOCVD) method is used to deposit a 300-nm AlN / AlGaN transition layer structure, a 550-nm high-quality unintentionally doped GaN layer with a low electron concentration, a 20-nm AlGaN barrier layer, and an 80-nm p-GaN on an Si<11l> substrate.

[0088] Using photoresist as a mask, after photolithographic patterning, the p-GaN layer in the non-gate region is removed by dry etching, so that the tilt angle θ of the p-GaN mesa is 5°, and the etching stops at the AlGaN barrier layer. In the AlGaN barrier region, after etching through the AlGaN barrier in the metal electrode region, a Ti / Al / Ti / Au contact electrode is deposited, and then Ni / Au is deposited in the p-GaN region and covered on the AlGaN contact electrode to form a hybrid anode, and the separate electrode on the AlGaN serves as the cathode. The subsequent passivation layer process and the reflective layer process refer to other embodiments.

[0089] In the above-mentioned Embodiments 2-6, the enhanced effect of the inclined mesa combined with the optical reflection layer on the conductance modulation can still be observed, and it has no obvious influence on the electrical characteristics, especially the breakdown voltage value, in the off state.

[0090] Based on the above-mentioned embodiments and the comparative examples, it can be clearly seen that the PN junction structure of the inclined mesa can improve the light reflectivity. By covering a high-reflectivity optical reflection layer near the light-emitting PN junction, it further enhances the reflection of the emitted light back into the semiconductor body, increases the number of photo-generated carriers in the semiconductor material, thereby reducing the internal resistance of the device when it is in the on state and under high bias voltage, improving the over-current capacity of the device, enhancing the anti-surge effect of the device, and this method will not significantly weaken other characteristics of the device, such as the off-state electrical characteristics and dynamic characteristics. The key points and the points to be protected are the inclined plane structure of the semiconductor material at the PN junction (enhancing the light reflectivity into the semiconductor) and the high-reflectivity optical reflection layer.

[0091] Compared with the prior art, the advantages of the present invention are as follows:

[0092] First, by introducing the regulation of the light field to enhance the conductance modulation, this method will not significantly weaken the reverse characteristics and dynamic characteristics of the device. This makes full use of the light emitted during the carrier recombination of the PN junction, changing the conversion from light to joule heat to the conversion from light to current, improving the energy utilization rate, which is the greatest advantage of this patent;

[0093] Second, the manufacturing process of this structure is relatively simple. The equipment required by the process is relatively common, and the equipment cost of the process is low, featuring low cost.

[0094] Third, the process preparation of this method is simple, the process window is large, it can be compatible with a variety of other processes, and it is suitable for group III nitride electronic devices, including vertical and horizontal diodes and transistors.

[0095] It should be understood that the above embodiments are only used to illustrate the technical concept and characteristics of the present invention. The purpose is to enable those familiar with this technology to understand the content of the present invention and implement it accordingly, and it cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit and essence of the present invention should be covered within the protection scope of the present invention.

Claims

1. A group-III nitride electronic device with enhanced conductivity modulation, characterized in that, It includes a PN junction and a light reflection structure; The PN junction includes a first conductivity characteristic region and a second conductivity characteristic region in direct contact. The conductivity characteristics of the first conductivity characteristic region and the second conductivity characteristic region are opposite. The PN junction has a first surface and a second surface arranged back to back with each other. The first conductivity characteristic region is located on the first surface, and inclined mesa surfaces are provided on both sides of the first surface. The normal direction of the inclined mesa surface points in the direction inside the PN junction; The light reflection structure includes a first reflection layer. The first reflection layer covers the first surface and is conformally covered along the inclined mesa surface.

2. The group-III nitride electronic device according to claim 1, wherein The first conductivity characteristic region and the second conductivity characteristic region are longitudinally stacked along the thickness direction from the first surface to the second surface. The included angle θ between the normal direction of the inclined mesa surface and the first surface is 0° < θ ≤ 80°; Or, partial structures of the first conductivity characteristic region and the second conductivity characteristic region are arranged horizontally along the in-plane direction of the first surface or the second surface. The included angle θ between the normal direction of the inclined mesa surface and the first surface is 0° < θ ≤ 15°.

3. The group-III nitride electronic device according to claim 2, wherein, The second conductivity characteristic region includes a layered part and a plurality of protruding parts. The layered part extends from the second surface to the middle of the PN junction. The protruding parts extend from the middle of the PN junction to the first surface. The width of the protruding parts is lower than that of the layered part; The second conductivity characteristic region fills the space between the plurality of protruding parts.

4. The group-III nitride electronic device according to claim 2, characterized in that, Along the thickness direction, the first conductivity characteristic region sequentially includes a highly doped P-type group III nitride layer and a lowly doped P-type group III nitride layer. The second conductivity characteristic region sequentially includes an N-type drift region, a lowly doped P-type group III nitride layer, and a highly doped P-type group III nitride layer; Or, along the thickness direction, the first conductivity characteristic region includes a P-type group III nitride layer, and the second conductivity characteristic region sequentially includes a barrier layer, a channel layer, and a transition layer.

5. The group-III nitride electronic device according to claim 1, wherein, The inclined mesa surface completely covers at least the side surface of the first conductivity characteristic region.

6. The group-III nitride electronic device according to claim 1, wherein, A dielectric passivation layer is further provided between the first reflection layer and the first surface.

7. The group-III nitride electronic device according to claim 6, wherein, In the middle of the first surface, a window is provided in the dielectric passivation layer. The window exposes the first surface. The group III nitride electronic device further includes a first contact electrode. The first contact electrode fills the window and makes an ohmic contact with the first conductivity characteristic region.

8. The group-III nitride electronic device according to claim 1 or 7, characterized in that, A second contact electrode is further provided on the second surface. The second reflection layer is provided in the middle of the second surface. The second contact electrode surrounds the second reflection layer and makes an ohmic contact with the second conductivity characteristic region.

9. The group-III nitride electronic device according to claim 1, wherein It further includes a second reflection layer and a third reflection layer. The second reflection layer covers the second surface. The third reflection layer covers the side wall surface of the PN junction.

10. The method for manufacturing a group-III nitride electronic device according to any one of claims 1-9, characterized in that, It includes: Providing a PN junction having a first conductivity characteristic region and a second conductivity characteristic region; Etching the PN junction on the first surface where the first conductivity characteristic region is located to form inclined mesa surfaces on both sides of the first surface. The normal direction of the inclined mesa surface points in the direction inside the PN junction; Preparing a first reflection layer. The first reflection layer covers the first surface and is conformally covered along the inclined mesa surface.

Images