System and method for displaying signals based on signal characteristics

Abstract

The disclosure relates to systems and methods for displaying signals based on signal characteristics. Systems, methods, and computer program product embodiments are disclosed for displaying signals based on signal characteristics such as late potential or early activation. Embodiments operate by matching, by a first digital signal processor (DSP) of a first signal module, heart rates in a first packet associated with a first cardiac signal to known signal characteristics. The embodiment also searches, by a second DSP of a second signal module, a signal characteristic in a second packet associated with a second cardiac signal in response to the match. Embodiments display a portion of the first cardiac signal through a display module coupled with the first signal module and the second signal module. The embodiment then displays, based on the search, a portion of the second cardiac signal including the signal characteristic, the portion of the second cardiac signal being time synchronized with the displayed portion of the first cardiac signal.

Description

[0001] This application is a divisional application of a Chinese patent application with an international filing date of May 9, 2019, a national application number of 201980046259.0, and an invention title of "Systems and Methods for Displaying Signals Based on Signal Characteristics". Technical Field

[0002] The embodiments included herein generally relate to cardiac electrophysiology (EP) signal acquisition and recording systems. More specifically, embodiments of systems, devices, and methods for transmitting biomedical signals between a patient and monitoring and treatment devices are disclosed. Background Art

[0003] Catheter ablation is a method for treating arrhythmias such as atrial fibrillation, which are myocardial diseases characterized by abnormal conduction. Depending on the severity of the problem, multiple ablation procedures may be required to obtain an effective result. This is because current electrophysiology (EP) techniques have limitations in precisely locating the tissue to be ablated, which is the source of the abnormality.

[0004] The conventional diagnostic process begins with an electrocardiogram (ECG), which is obtained from electrodes attached to the skin surface of a subject (e.g., a patient). The medical team evaluates the ECG signal and determines whether drugs and / or ablation are indicated. If ablation is indicated, an EP study is performed. A catheter is inserted into the heart via the patient's neck or groin, and the electrical activity of the heart is recorded. Based on this EP study, ablation is performed on the (multiple) regions of the heart that the medical team suspects are causing the (multiple) abnormal heart rhythms.

[0005] An ablation catheter is inserted into the patient's blood vessel and guided to the site of the tissue in the heart that causes abnormal electrical propagation. The catheter can use different energy sources (most commonly heat or cold) to scar the tissue, thereby reducing its ability to initiate and / or transmit abnormal electrical impulses, thus eliminating the abnormal heart rhythm. The ECG signal is recorded from surface electrodes on the patient's skin, and intracardiac (IC) signals can be obtained from a catheter inside the patient's heart and recorded as electrograms (EGM). Both the ECG and IC (EGM) signals are small signals that need to be conditioned and amplified to be accurately evaluated.

[0006] In a conventional EP system, in order to confirm whether the ablation treatment of a certain tissue site is successful, the medical team must often stop the ablation procedure and collect physiological signals (e.g., the heart) from a monitoring device (e.g., an ECG monitor). This is because current systems cannot accurately detect, acquire, and isolate small heart signals (with amplitudes in the range of 0.1 - 5 mV and frequencies in the range of DC to 1 KHz) in real time during the application of large ablation signals (about several hundred volts at a frequency of around 450 kHz).

[0007] Specifically, U.S. Patent Application Publication No. US 2006 / 0142753 A1, issued to Francischelli et al., presents systems and methods for ablating and evaluating the integrity or transmurality thereof by monitoring depolarization ECG signals from electrodes adjacent to tissue to be ablated. Francischelli et al. noted that, in order to minimize noise sensing issues during measurement of ECG signals from electrodes on an ablation device, the measurement is preferably made during an interruption in delivery of ablation energy to the ablation electrodes.

[0008] Typically, some current EP recording systems can effectively support the treatment of arrhythmias that manifest as large amplitude, low frequency signals (such as atrial flutter and supraventricular tachycardia). However, more complex and prevalent arrhythmias characterized by low amplitude, high frequency signals (such as atrial fibrillation and ventricular tachycardia) have not been found to have effective evaluation of all relevant signals.

[0009] Line noise and pacing signals can make signal detection, acquisition, and feature extraction more complex. To reduce noise and artifacts from various electrical signal information, current EP recorders use low-pass, high-pass, and notch filters. Unfortunately, conventional filtering techniques may alter the signal and make it difficult or impossible to see low amplitude, high frequency signals inherent in cardiac monitoring, the visualization of which can assist in the treatment of atrial fibrillation and ventricular tachycardia. It has recently been recognized that, due to contamination by artifacts and noise, prior assurance of waveform integrity has not been achieved, such as for low-noise acquisition of IC and ECG signals in an EP environment.

[0010] Specifically, Martinez-Iniesta et al. noted in an article titled "Waveform Integrity in Atrial Fibrillation: The Forgotten Issue of Cardiac Electrophysiology" (Annals of Biomedical Engineering, April 18, 2017) that high frequency and broadband equipment noise is "inevitably recorded" during signal acquisition, and other complications in acquisition also come from various other signals, including 50 Hz or 60 Hz mains power, high frequency patient muscle activity, and low frequency baseline drift (due to respiration or catheter movement or unstable catheter contact). Martinez-Iniesta et al. further noted that conventional filtering can cause significant changes in waveform and spectral properties and that the noise reduction effect is not good. However, active filtering between 30 and 300 Hz remains a conventional EP practice.

[0011] Conventional practices distort the morphological characteristics of the generated signals, resulting in the loss of relevant (of interest) signal information and affecting signal validity. Martinez-Iniesta et al. proposed a software solution that only uses preprocessing and noise reduction methods to reduce mid- and high-frequency noise, but there is no solution that combines the low-frequency noise reduction components in software with those in hardware. The ideal feature of an EP system is the ability to use a combination of hardware and software that can reduce the noise in the signal (or increase the high signal-to-noise ratio) to preserve the integrity of the original signal information while minimizing the hardware filtering that may eliminate the content of the signal of interest.

[0012] Currently, the main method for ablating paroxysmal and persistent atrial fibrillation is pulmonary vein isolation (PVI), in which the medical team uses a cardiac mapping system to reconstruct the cardiac geometry in 3D and perform ablation at anatomical locations (such as the pulmonary veins from which atrial fibrillation originates). The procedure takes 2 - 8 hours, and the physician may not be able to obtain a durable lesion / scar to isolate the problematic tissue from the left atrium. Therefore, patients usually need to return for additional ablation procedures to complete the treatment. However, by being able to clearly observe the cardiac signals during ablation and determine whether the ablation lesions are transmural, additional ablation procedures and possible complications can be minimized.

[0013] Conventional EP systems may suffer from some other limitations. First, users often want to process and display multiple features of the signal nearly in real time. For example, the medical team may want to display various and multiple versions of ECG, IC, and other physiological signals simultaneously nearly in real time to evaluate different signal attributes. However, conventional EP systems usually cannot process and display multiple versions of the signal simultaneously nearly in real time.

[0014] Second, users often want to dynamically apply new digital signal processing functions to the signal without interfering with other digital signal processing functions that have already been applied to the signal. However, conventional solutions do not allow users to dynamically apply new digital signal processing functions to the signal without stopping the signal capture or interfering with other digital signal processing functions that have already been applied to the signal.

[0015] Finally, users often want to synchronize the processing and display of multiple signals nearly in real time. For example, users may want to synchronize the display of multiple processed versions of the same signal. In addition, the medical team may want to synchronize the display of multiple processed versions of ECG, IC, and other physiological signals. This is because the medical team's ability to make an effective clinical diagnosis may depend on comparing multiple signals at the same time point. However, conventional solutions may not be able to process and synchronize the display of multiple processed signals nearly in real time. Summary of the Invention

[0016] Disclosed are devices, systems, and methods for EP signal acquisition and recording that have multiple improvements in noise and artifact reduction for various biomedical applications.

[0017] Embodiments of the disclosed EP systems can record raw (unaltered) cardiac and other physiological signals with multiple display options and with low noise and a large input signal dynamic range. With minimal use of filters in hardware (e.g., hardware filters are only used for AC coupling, anti-aliasing, and RF suppression), the raw signals acquired by the acquisition module are filtered and processed in the accompanying software using the digital processing module. Using software-based digital signal processing algorithms allows the signals to be displayed simultaneously in real time in a single window or multiple windows, either as the raw signals or as a combination of the raw signals and the processed signals. Additionally, the visualization and review capabilities of the disclosed EP systems allow the user to mark features specified in the algorithm during real-time tracking.

[0018] The disclosed EP systems allow the signals to be displayed in the case of applying more than one signal processing algorithm simultaneously, which is a feature not available in conventional systems. For specific reasons, this allows the user to view the signals filtered in multiple ways. In the real-time window, the waveform of interest can be displayed as the raw signal or any combination of the raw signal and the filtered signal, so as to better visualize the signal in the presence of noise and artifacts.

[0019] All displayed signals are time-synchronized. The user can, independent of real-time tracking, choose to open multiple review windows and is able to display the results of various signal processing algorithms.

[0020] From a clinical perspective, the disclosed EP systems can significantly assist the medical team in making decisions for patients undergoing various medical treatments (e.g., ablation), and the benefits include, but are not limited to: suppressing RF energy for a cleaner, more reliable recording of intracardiac signals, reducing baseline drift, and reducing noise; a dynamic range for better visualization, especially for the visualization of very low-amplitude signals temporarily located within large-amplitude signals; real-time digital processing and raw signal recording to facilitate signal filtering and reduce artifacts and noise without affecting the original information; high-quality unipolar signals to assist in determining tissue type and catheter position; improved waveform integrity and reduced artifacts of signal processing by-products, thus allowing the medical team to improve surgical outcomes; and improved signal information, thus allowing the medical team to provide a more accurate catheter tip position for ablation and provide other treatment levels and durations to improve treatment effectiveness.

[0021] In some embodiments of a system for visualizing signals using late potentials, the memory includes: a first signal module including a first digital signal processor (DSP) configured to match beats in a first packet associated with a first cardiac signal to known signal characteristics; and a second signal module including a second DSP configured to search for late potentials in a second packet associated with a second cardiac signal in response to the match. The memory further includes a display module coupled to the first signal module and the second signal module, the display module configured to display a portion of the first cardiac signal based on the search and display a portion of the second cardiac signal including the late potential, the portion of the second cardiac signal being time-synchronized with the displayed portion of the first cardiac signal. The system further includes at least one processor coupled to the memory and configured to execute the first signal module, the second signal module, and the display module. Implementing the system components by a computer system implements various method embodiments for visualizing signals using late potentials. The computer system includes a non-transitory computer-readable device storing instructions that, when executed by at least one computing device, cause the at least one computing device to perform operations implementing method steps.

[0022] In some embodiments of a system for visualizing signals using early activations, the memory includes a first signal module including a first DSP configured to match beats in a first packet associated with a first cardiac signal to known signal characteristics; and a second signal module including a second DSP configured to search for early activations in a second cardiac signal during a period prior to the matched beats. The memory further includes a display module coupled to the first signal module and the second signal module, the display module configured to display a portion of the first cardiac signal based on the search and display a portion of the second cardiac signal including the early activation, the portion of the second cardiac signal being time-synchronized with the displayed portion of the first cardiac signal. The system further includes at least one processor coupled to the memory and configured to execute the first signal module, the second signal module, and the display module. Some method embodiments and non-transitory computer-readable device embodiments for visualizing signals using early activations are also disclosed.

[0023] Some method and non-transitory computer-readable device embodiments implement the steps of: accessing a first cardiac signal associated with a surface lead, matching beats of the first cardiac signal to a known signal pattern, and searching for early activations or late potentials in a second cardiac signal during a period before or after the matched beats.

[0024] Other methods and non-transitory computer-readable device embodiments for filtering noise from an input signal using notch filtering implement the following steps: accessing an input signal having a first harmonic frequency and having noise; determining a silent period in the input signal; storing noise samples of the input signal during the silent period in a buffer; subtracting samples of a single cycle of the noise from the buffer from the input signal to create a filtered signal, wherein the subtraction removes the first harmonic frequency and a second harmonic frequency from the input signal and avoids introducing a transient response in the filtered signal; and repeating the determining, storing, and subtracting to refine the filtered signal.

[0025] Some methods and non-transitory computer-readable device embodiments for filtering noise from an input signal using high-frequency filtering implement the following steps: accessing an input signal including noise and a high-frequency signal of interest; performing high-pass filtering on the input signal to create a filtered signal; isolating artifacts associated with the noise in the filtered signal from the high-frequency signal of interest; optionally selecting a filter based on the isolated artifacts; and

[0026] blanking the filtered signal for a fixed period before and after the isolated artifacts, wherein the blanking optionally uses the selected filter to remove the isolated artifacts and allows the high-frequency signal of interest to pass.

[0027] Some methods and non-transitory computer-readable device embodiments for pattern matching implement the following steps: accessing an input cardiac signal; matching a portion of the input cardiac signal to a known signal pattern; and displaying an indication of the degree of match. Other embodiments for pattern matching match a portion of the input cardiac signal to a known signal pattern based on a detection threshold and display a highlighted portion of the input cardiac signal based on the match.

[0028] System embodiments for generating a pure unipolar signal are also disclosed, the system embodiments including: an electrocardiogram (ECG) circuit board configured to process an ECG signal and a plurality of intracardiac (IC) circuit boards configured to process corresponding IC signals, wherein the ECG circuit board and the plurality of IC circuit boards share substantially the same circuit configuration and components, and the ECG circuit board processes the ECG signal using substantially the same path as each IC circuit board uses to process its corresponding IC signal.

[0029] Other system embodiments for performing electrophysiology (EP) procedures are disclosed. The system embodiments include an ECG circuit board configured to receive an ECG signal, a plurality of IC circuit boards each configured to receive an IC signal, a communication interface communicatively coupled to a remote device, and a processor coupled to the ECG board, the plurality of IC circuit boards, and the communication interface. Such system embodiments can be configured to receive feedback from the remote device via the communication interface and to control the remote device based on the ECG signal, the IC signals, and the feedback from the remote device via the communication interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings, which are incorporated herein and constitute a part of this specification, illustrate the presently disclosed embodiments and, together with the description, further serve to explain the principles of the embodiments and to enable one skilled in the relevant art(s) to make and use the embodiments.

[0031] Figure 1 A block diagram illustrating a conventional electrophysiology (EP) environment with patient connections and sources of interference.

[0032] Figure 2 A hardware system block diagram illustrating the disclosed EP hardware system according to some embodiments.

[0033] Figure 3 A block diagram illustrating multi-channel analog-to-digital input / output of the input stage of an EP hardware system according to some embodiments.

[0034] Figure 4 A block diagram illustrating a single channel of the input stage of an EP hardware system according to some embodiments.

[0035] Figure 5A A block diagram illustrating the entire EP system according to some embodiments.

[0036] Figure 5B A high-level abstraction of the entire EP system hardware and software according to some embodiments.

[0037] Fig. 6A A schematic diagram illustrating the large-signal input protection portion of the input protection circuit of an EP hardware system according to some embodiments.

[0038] Figure 6B A schematic diagram illustrating the electrostatic discharge (ESD) protection portion of the input protection circuit of an EP hardware system according to some embodiments.

[0039] Figure 7 A schematic diagram illustrating the radio frequency (RF) filtering portion of the input protection circuit of an EP hardware system according to some embodiments.

[0040] Figure 8A-8EIllustrates a voltage signal diagram of a typical defibrillation signal at the input of an input protection circuit according to an exemplary embodiment.

[0041] Figure 9A-9E Illustrates a voltage signal diagram of a typical ablation signal at the input of an input protection circuit according to an exemplary embodiment.

[0042] Fig.10 Illustrates a schematic diagram of the instrumentation and gain stages of an EP hardware system according to some embodiments.

[0043] Fig.11 Illustrates a schematic diagram of the large signal detection / quick recovery circuit of an EP hardware system according to some embodiments.

[0044] Fig.12 Illustrates a voltage signal diagram according to an exemplary embodiment, which shows the slow recovery that occurs after a large unwanted signal passes through the input protection, instrumentation, and gain stages of an EP hardware system circuit when the large signal detection / quick recovery circuit is disconnected.

[0045] Figure 13A-13C Illustrates a voltage signal diagram according to an exemplary embodiment, which shows the quick recovery that occurs after a large unwanted signal is applied to the input protection, instrumentation, and gain stages of an EP hardware system circuit when the large signal detection / quick recovery circuit is connected.

[0046] Figures 14A-14D Illustrates a signal diagram of the voltage signals at various internal nodes when the large signal detection / quick recovery circuit is connected according to an exemplary embodiment.

[0047] Figure 15A-15B Illustrates a signal diagram of the current signal on a resistor at the output of the connected large signal detection / quick recovery circuit according to an exemplary embodiment.

[0048] Fig.16 Illustrates a schematic diagram of a low-frequency feedback circuit used as a dynamic current source for an EP hardware system according to some embodiments.

[0049] Figures 17A-17D Illustrates a signal diagram of a typical in-band voltage differential input signal that is affected by 60 Hz common-mode noise entering an EP hardware system according to an exemplary embodiment.

[0050] Figures 18A-18D Illustrates a signal diagram of a typical differential voltage signal that is affected by 60 Hz common-mode noise as it travels through an EP hardware system according to an exemplary embodiment.

[0051] Figures 19A-19D Illustrates a signal diagram of a typical 500 kHz ablation input signal according to an exemplary embodiment, the 500 kHz ablation input signal being in a frequency range that will be attenuated by the RF filter of the EP hardware system.

[0052] Figure 20A-20B Illustrates a signal diagram of a typical 500 kHz ablation input signal at the shielded input according to an exemplary embodiment, the shielded input enabling the RF filter to attenuate the input signal of the EP hardware system.

[0053] Figure 21A-Figure 21D Illustrates a signal diagram of a typical 500 kHz ablation input signal according to an exemplary embodiment, the typical 500 kHz ablation input signal having been attenuated after it travels through the instrumentation amplifier and after it travels through the fully differential operational amplifier of the EP hardware system.

[0054] Fig.22A Illustrates an improvement in the visualization of an ECG or IC signal according to an exemplary embodiment.

[0055] Fig. 22B Illustrates the ability of an EP system according to an exemplary embodiment to reveal micro-components of low-amplitude cardiac signals and artifacts of EP signals in the presence of noise and large-signal processes.

[0056] Fig. 22C Illustrates the ability of an EP system according to an exemplary embodiment to remove 60 Hz noise without saturation or delayed recovery while maintaining the components of the 60 Hz signal that belong to the original waveform.

[0057] Fig.23 Illustrates a schematic diagram of an improved Wilson Central Terminal - Right Leg Drive (WCT - RLD) circuit according to some embodiments.

[0058] Fig.24 Illustrates a schematic diagram of a dual - T feedback network interfacing with the RLD circuit of a WCT - RLD circuit according to some embodiments.

[0059] Fig.25 Illustrates a signal diagram of the output of the dual - T feedback network of a WCT - RLD circuit according to an exemplary embodiment.

[0060] Fig.26 Is a block diagram of a system for processing and displaying multiple signals in near real - time according to some embodiments.

[0061] Fig. 27 Is a block diagram of a queuing module for storing generated packets associated with different base signals according to some embodiments.

[0062] Fig.28 is a block diagram of a configuration path module for generating a processed time alignment signal from a set of base signals at runtime according to some embodiments.

[0063] Fig.29 is a block diagram of a signal module generated by a signal factory module according to some embodiments.

[0064] Fig.30 is a block diagram of a display module for displaying one or more signals according to some embodiments.

[0065] Fig.31 is a block diagram of a monitoring module for performing error checking according to some embodiments.

[0066] Fig.32 Illustrates an example adjustment of the sweep speed for a display module according to some embodiments.

[0067] Fig.33 Illustrates signal management for a display module according to some embodiments.

[0068] Fig.34 Illustrates an example adjustment of the zoom and clip factors for a display module according to some embodiments.

[0069] Fig.35 Illustrates pattern search management for a display module according to some embodiments.

[0070] Fig.36 Illustrates late potential search results highlighted in the display of a display module according to some embodiments.

[0071] Fig.37A Illustrates the use of a display module configured as a waterfall view according to some embodiments.

[0072] Fig.37B Illustrates the correspondence between signals in a conventional display module and a display module configured as a waterfall view according to some embodiments.

[0073] Fig.37C Illustrates the use of a display module configured as a dynamic view according to some embodiments.

[0074] Fig.37D Illustrates the use of a display module configured as a trigger view according to some embodiments.

[0075] Fig.38 Illustrates signal capture in the display of a display module configured as a review window according to some embodiments.

[0076] Fig.39Illustrates amplitude measurements performed in a display of a display module configured as a review window, according to some embodiments.

[0077] Fig.40 Is a flowchart of a method for near real-time processing and display of multiple signals, according to one embodiment.

[0078] Fig.41 Is a flowchart of a method for configuring one or more signal modules, according to some embodiments.

[0079] Fig.42 Is a flowchart of a method for generating signal modules according to signal processing specifications, according to some embodiments.

[0080] Fig.43 Is a flowchart of a method for equalizing processing delays associated with each DSP of one or more signal modules, according to some embodiments.

[0081] Fig.44 Is a flowchart of a method for receiving one or more signal samples for one or more signals using an input module, according to some embodiments.

[0082] Fig.45 Is a flowchart of a method for converting one or more signal samples into one or more packets using a packetizer, according to some embodiments.

[0083] Fig.46 Is a flowchart of a method for distributing packets containing one or more signal samples to a queuing module, according to some embodiments.

[0084] Fig.47 Is a flowchart of a method for distributing packets from a queuing module to signal modules associated with the packets, according to some embodiments.

[0085] Fig.48 Is a flowchart of a method for processing packets using signal modules associated with the packets, according to some embodiments.

[0086] Fig.49 Is a flowchart of a method for displaying processed packets to a display screen using a display module, according to some embodiments.

[0087] Fig.50 Illustrates an example of a signal with superimposed noise, according to some embodiments.

[0088] Fig.51 Illustrates an example of a conventional method for removing noise using a notch filter, according to some embodiments.

[0089] Fig.52Illustrates an application according to some embodiments Fig.51 of the results of a conventional filter.

[0090] Fig.53 Illustrates an example of the 180 Hz harmonic that still exists at Fig.51 the output of a conventional filter.

[0091] Fig.54 Illustrates an example of notch filtering for a signal with 60 Hz and 180 Hz noise according to some embodiments.

[0092] Fig.55 Illustrates an example of a notch filter that uses 100 samples and exactly stores 3 cycles of 60 Hz according to some embodiments.

[0093] Fig.56 Illustrates an example of a notch filter that calculates the silent time according to some embodiments.

[0094] Fig.57 Illustrates an example of a notch filter that accumulates a copy of the noise and subtracts the noise copy from the noise signal according to some embodiments.

[0095] Fig.58 Illustrates an example of the results of a notch filter according to some embodiments.

[0096] Fig.59 Is a flowchart of a process for notch filtering noise from an input signal according to some embodiments.

[0097] Fig.60 Illustrates an example of a conventional high-pass filter according to some embodiments.

[0098] Fig.61 Illustrates an example of a signal according to some embodiments, the signal containing high-frequency signals from the conduction regions of the heart and sharp local spikes from various sources.

[0099] Fig.62 Illustrates an example of using Fig.60 a high-pass filter to Fig.61 filter a signal and output the result according to some embodiments.

[0100] Fig.63 Illustrates an example of using a high-pass filter to Fig.61 filter a signal and output the result according to some embodiments, the high-pass filter allowing the high-frequency signals of interest to pass while removing the pulses.

[0101] Fig.64is a flowchart of a process for high-pass filtering noise from an input signal according to some embodiments.

[0102] Fig.65 Illustrates an example of a review window for selecting a data range using a vertical caliper according to some embodiments.

[0103] Fig.66 Illustrates an example of saving a selected pattern as a reference heartbeat according to some embodiments.

[0104] Fig.67 Illustrates an example of a window of optional patterns to be searched according to some embodiments.

[0105] Fig.68 Illustrates, according to some embodiments, in Fig.65 an example of a summary view of pattern search in a review window of Fig.65 where multiple matching patterns are shown in the review window of

[0106] Fig.69 Illustrates, according to some embodiments, in Fig.68 an example of a summary view of pattern search in a review window of Fig.68 where a single matching pattern is shown and other patterns are hidden in the review window of

[0107] Fig.70 Illustrates, according to some embodiments, Fig.65 an example of a detailed view of a review window of

[0108] Fig.71 Illustrates an example of pattern match confidence values provided by a lead according to some embodiments.

[0109] Fig.72 is a flowchart of a process for pattern matching according to some embodiments.

[0110] Fig.73 is a flowchart of a process for pattern matching according to some embodiments.

[0111] Fig.74 Illustrates an example of a search definition window for creating and managing searches for late potentials and early activations according to some embodiments.

[0112] Fig.75 Illustrates an example of a late potential detection configuration window for defining various search parameters for late potentials according to some embodiments.

[0113] Fig.76 Illustrates an example showing the location of a late potential and its detection confidence according to some embodiments.

[0114] Fig.77 An example of an early activation detection configuration window for defining various search parameters for early activation is illustrated, according to some embodiments.

[0115] Fig.78 An example showing the location of early activation and its detection confidence is illustrated, according to some embodiments.

[0116] Fig.79 An example of a search definition window for managing defined late potential searches and early activation searches is illustrated, according to some embodiments.

[0117] Fig.80 is a flowchart of a process for detecting early activation or late potential, according to some embodiments.

[0118] Fig.81 An example of a waterfall display configuration window is illustrated, according to some embodiments.

[0119] Fig.82 An example of a waterfall view using a time pattern is illustrated, according to some embodiments.

[0120] Fig.83 An example of a waterfall view using a heartbeat pattern is illustrated, according to some embodiments.

[0121] Fig.84 An example of a display parameter window is illustrated, according to some embodiments.

[0122] Fig.85 An example of an exemplary computer system is illustrated, according to some embodiments.

[0123] In conjunction with the accompanying drawings, the features and advantages of the present embodiments will become more apparent from the detailed description set forth below. In the drawings, like reference numerals always identify corresponding elements. In the drawings, like reference numerals generally indicate identical, functionally similar, and / or structurally similar elements. The figure in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference numeral. Detailed Description

[0124] Devices, systems, and methods related to a unique amplifier topology are disclosed for conditioning cardiac (e.g., ECG and IC) and other physiological signals, specifically for clearly defining and recording low-amplitude, low-frequency information that may be obtained during ablation and other similar large-signal perturbations such as pacing and stimulation. During a procedure, the tip of a catheter (or other electrode) can be connected to a pacing, ablation, and stimulator system to allow visualization, pacing, ablation, and stimulation without the need for mode switching. For example, the disclosed devices, systems, and methods can effectively separate ablation signals from cardiac signals during ablation while providing input protection against high voltages such as those from defibrillation signals. Similarly, the disclosed devices, systems, and methods can effectively separate stimulation signals from physiological signals during stimulation.

[0125] Since different system recording requirements cannot be satisfied simultaneously for each signal type, each block or module of the system can be performance-optimized to achieve the various signal conditioning requirements desired by the clinician. Various embodiments can enable the system to simultaneously handle cardiac, pacing, ablation, defibrillation, stimulator, and other physiological signal types by detecting, conditioning, and displaying signals of interest to monitor, for example, the effect of an ongoing procedure on cardiac signals.

[0126] Additionally, in situations where there are many sources of electrical noise and environmental interference in addition to the large signals injected during ablation and stimulation procedures, pacing, or defibrillation, various embodiments can ensure the acquisition of multiple low-amplitude cardiac signals. The cardiac signals of interest can also be displayed in an uncomplicated and clinically relevant manner, processing the signals in real-time or near real-time to show the full causal relationship between physician-initiated procedures and the resulting cardiac signals while identifying signal artifacts and removing unwanted noise. The present disclosure identifies hardware and software embodiments for achieving these purposes.

[0127] The present disclosure relates to "unipolar" and "bipolar" signals, both of which are widely used in EP recording but for complementary purposes. Both unipolar and bipolar signals are the potential differences recorded at two (or more) different, separate electrodes on the patient's body (specifically the patient's limbs and chest), for example, for measuring ECG signals, or the potential differences recorded at two (or more) different, separate catheters placed directly on cardiac tissue, for example, for measuring IC signals.

[0128] It is routine to use a 12 - lead electrocardiogram (ECG) system, which includes connections to each of the following limbs: right arm (RA), left arm (LA), right leg (RL), and left leg (LL), as well as six precordial connections V1 to V6 from six separate electrodes located at different positions on the patient's chest. Separate ECG electrode wires are connected to a cable clamp at the end of the patient bed and routed from there to a data acquisition system. All leads are routinely connected to a protection circuit system to prevent damage to the instrument from defibrillation potentials or static electricity from the environment.

[0129] Bipolar signals are the standard configuration for certain ECG measurements (leads I, II, III), but can also be obtained directly from the heart surface to collect intracardiac (IC) signals. Bipolar signals can be obtained by attaching two (or more) electrodes in close proximity to each other in a specific area of the heart or cardiac tissue and measuring the potential difference between the electrodes, providing information about local electrical activity (such as late potentials caused by damaged myocardium). However, bipolar IC signals do not provide information about the direction of electrical impulse propagation. For example, one of the difficulties with current bipolar mapping is the inability to know whether the signal of interest is from the distal electrode or the proximal electrode. This is important because pacing and energy delivery are provided by the distal electrode.

[0130] By placing one IC electrode on the surface of the patient's heart and keeping another electrode at a distance from the first electrode as a reference signal, unipolar signals are generated from a point source, such as can be obtained from IC potentials. The unipolar leads from the IC electrodes are connected such that one lead acts as the active lead while the other(s) are in an inactive position or as a result of a calculated inactive position (WCT, described below). In this way, current flowing towards the active electrode produces a positive deflection, while current flowing away from the active electrode produces a negative deflection. This provides information about the direction of cardiac signal propagation. Unipolar recording is particularly useful when directional information is needed, such as when determining the depolarization and repolarization pathways of the endocardium and epicardium. A method using the first derivatives of two unipolar signals is disclosed herein.

[0131] Leads can also be connected to the limbs to create an imaginary triangle, called "Einthoven's triangle". In this way, true bipolar leads can be obtained by referring each connection to one of the other two connections (for example, LA referenced to RA is lead I; LL to RA is lead II, and finally LA to LL is lead III). Then, the average of the three limb wires RA, LA, and LL can approximate a zero - potential point to provide a reference electrode (WCT, discussed below). Here, the vector sum of leads I and III is lead II.

[0132] Using the concept of Einthoven's triangle, the Wilson Central Terminal (WCT) is a circuit concept used in the art (and further discussed in this disclosure). The Wilson Central Terminal (WCT) can be used as a neutral electrode, acting as the electrical center of the heart as a reference. When an IC signal is desired to be displayed in a unipolar manner, the WCT can be used. When the WCT is used as a reference for a unipolar signal, the unipolar signal can approximate a widely spaced bipolar signal for consistent unipolar recording. The WCT can prevent the need to use an additional catheter as a reference for unipolar recording of IC signals.

[0133] In this disclosure, "near real-time" refers to the acquisition and visualization of signals by an EP system, from the time the signals appear at the input of the hardware circuitry of the EP system to the time they are first displayed on the EP system display monitor. The signals are displayed in their original (unprocessed) form or after being processed by the EP system's main processing unit (MPU) and one or more digital signal processing (DSP) modules. "Near real-time" for the original signals can be less than about five (5) milliseconds, while "near real-time" for the processed signals can be less than about fifty (50) milliseconds.

[0134] Figure 1 is a block diagram representing a conventional EP environment 100 with patient connections and sources of interference. As will be understood by those of ordinary skill in the art, patient 118 can be connected to diagnostic equipment such as a pulse oximeter 104, one or more ECG units 106, an infusion pump 108, an electroanatomical mapping system 110, a data acquisition system 112 (such as the EP system disclosed herein), an ablation generator 114, a nerve stimulator 128, and other diagnostic equipment (such as an external defibrillator), as well as several IC catheters. Such diagnostic equipment can be connected to and powered by 120 - 240V, 50 / 60Hz AC mains 102. Laboratory diagnostic equipment can be connected to ground 120 via its power connection.

[0135] As the number of connections to patient 118 increases, the leakage current 122 from all patient connections through patient 118 to ground 120 increases, thereby increasing the likelihood of interference and adverse effects. When such devices are connected and operated simultaneously, the total leakage current 122 can safely permit up to several tens of microamps at a fundamental mains frequency of 50Hz or 60Hz, where harmonics extend up to several kilohertz. This leakage current 122 can substantially interfere with the processing of ECG and IC signals. In addition, patient 118 can be capacitively coupled 124 and inductively coupled 126 to the 120 / 240AC mains 102. Patient 118 can additionally pick up RF interference 116 from equipment in the vicinity of the EP environment (e.g., wireless headphones, mobile phones, and wireless monitors).

[0136] For reference, Table 1 outlines the desired and undesired signals found in a conventional medical instrumentation / EP environment, along with their signal characteristics.

[0137] Table 1: Signal Characteristics in a Conventional EP Environment

[0138]

[0139] Due to equipment noise and other EP environmental interferences, in the frequency spectrum range from 50 Hz to several tens of megahertz, the voltage measured on the patient's body can be as high as 1 - 3 V RMS (root mean square). However, the amplitude of the cardiac signal can be measured in the range of 25 microvolts to 5 millivolts. To display these signals in a noisy environment, without losing details (so that, for example, relevant information is not lost) and with very little noise added (so that, for example, the details of the signal are not masked), the cardiac signal is routinely amplified and displayed while, for example, delivering RF ablation energy at a frequency of 500 kHz, about 70 V RMS, or providing cardiac stimulation up to 25 mA.

[0140] To correctly acquire and identify the cardiac signals of interest in such an environment, a very high signal-to-noise ratio (SNR) is desired (about 30 dB), but a very high SNR cannot be achieved if there is no way to minimize or eliminate the electrical interference sources before they must be electrically processed using software methods. Conventional hardware methods for conditioning signals in such a noisy environment include shielded cables, equipment grounding, balanced inputs and outputs, differential amplification, filtering, reducing circuit impedance, electrical isolation, or signal enhancement techniques. These conventional methods have had limited success in obtaining sufficient SNR.

[0141] The disclosed hardware embodiments can reduce interference while applying novel circuit topologies to minimize noise, isolate the IC and ECG signals of interest, condition those signals, and remove unwanted artifacts. This can be done before passing the signals to the processing software, which provides near real-time visualization and comprehensive signal review to the electrophysiologist. The embodiments of the EP systems described herein can achieve a significant SNR improvement.

[0142] Figure 2is a hardware system block diagram showing the disclosed EP hardware system 200 according to some embodiments. The EP hardware system 200 includes, for example, an EP workstation 201 and an EP console 214. The system may include an EP console 214 having an optical interface 216 for EP measurement hardware, from a user input, visualization, and review workstation (referred to herein as the "EP workstation" 201). The EP workstation 201 may include, for example, a conventional laboratory PC 208 having a keyboard / mouse 210 and a monitor allocator 206, which facilitates multiple monitors 202, 204 to provide multi-signal, multi-context display capabilities for EP signal visualization and review software. The EP workstation 201 may also include an additional optical interface 212 for electrically isolated data transmission from the EP console 214, for example, via USB 2.0.

[0143] The EP console 214 may include one or more ECG amplifiers 218, one or more unipolar amplifiers 220 for processing unipolar signals, and one or more bipolar amplifiers 222 for processing bipolar signals from multiple ECG and EGM monitoring units 224. The EP console 214 may also include a dedicated AC input filter 234, an AC / DC power supply 236, and a DC / DC power supply 238 to condition and convert the mains 120 / 240V, 50 / 60Hz source power 240 into DC power for use by the diagnostic equipment. The ECG and EGM electrode inputs 232 may enter the EP console 214 via a deflection coil (yoke) 226, which provides additional input impedance for protection. Junction boxes (1 and 2) 228, 230 may provide a convenient insertion interface for IC catheter inputs (not shown) for subsequent processing by the EGM monitoring units 224.

[0144] Figure 3 is a block diagram showing a multi-channel analog-to-digital input / output module 300 representing the input stage of an EP hardware system according to some embodiments, including an ECG board 302 and an IC board 316. The ECG board 302 and the IC board 316 represent Figure 2 a part of the ECG amplifiers 218, unipolar amplifiers 220, and Figure 2 bipolar amplifiers 222 of. The ECG board 302 and the IC board 316 include multiple channels of the EP hardware system input stage 400 discussed below (see Figure 4 ). Figure 3 Illustrates one (1) 8-channel ECG board and one (1) multi-channel IC board according to an exemplary embodiment. Some embodiments have at least sixteen (16) channels. Other embodiments may include more or fewer channels.

[0145] In Figure 3Among them, the analog inputs V1-V6 304 represent six separate ECG (precordial) electrodes, and the six separate ECG (precordial) electrodes can be placed at various positions on the patient's chest. The analog inputs LL, RA, and LA 306 represent the left leg, right arm, and left arm limb leads, respectively. The analog output RL 308 represents the patient return line for driving the right leg as discussed later in this disclosure. The WCT 314 on the ECG board 302 (also discussed later in this disclosure) represents the Wilson central terminal, and the Wilson central terminal also uses the analog inputs LL, RA, and LA 306. The output of the WCT 314 can then be input into each channel corresponding to the analog inputs V1-V6 304 in the EP hardware system input stage 400. Each of the digital outputs V1-V6 310 represents a conditioned and digitized version of the corresponding analog input V1-V6 304. In an exemplary embodiment, the digital outputs I, II 312 can include LA referenced to RA as lead I and LL referenced to RA as lead II in a conditioned and digitized form. Then, the average value of the three limb leads LL, RA, and LA 306 can be approximated as the zero potential point, thereby providing a reference level for the generation of RL 308.

[0146] In Figure 3 it, the multiple analog inputs of the IC board 316 represent the possible connections and channels from the intracardiac catheter to the EP hardware system input stage 400 (see Figure 4 ). The IC board 316 can accept unipolar or bipolar IC signals. INDIF 318 represents the neutral electrode that provides a reference for multiple unipolar neutral leads. The signals 320 of ICUniWCT1, 2 to N represent the unipolar IC signals referenced to the WCT. The signals 322 of ICUniINDIF1, 2 to N represent the active electrodes of each IC unipolar signal. The signals 324 of ICDiff1, 2 to N represent the multiple bipolar differential signals from the IC catheter. The multiple digital outputs represent the conditioned and digitized versions of the analog inputs, specifically the signals 326 of ICUniWCT1, 2 to N; the signals 328 of ICUniINDIF1, 2 to N; and the signals 330 of ICDiff1, 2 to N.

[0147] Figure 4is a block diagram of a single channel representing the input stage 400 of an EP hardware system according to some embodiments, having circuitry for input protection, signal filtering, detection, feedback, and amplification. The circuitry is represented in the block diagram by blocks numbered 1 through 11, each block representing a part of the hardware functionality. This partitioning and labeling of the blocks is for ease of description and is not intended to limit the scope of protection provided by the appended claims. As described below, the input protection and signal filtering sections of the EP hardware system input stage 400 include symmetric positive and negative circuitry to generate a differential version of each input signal for a differential signal amplification stage 532.

[0148] Figure 5A is a block diagram 500 of the overall EP system disclosed herein according to some embodiments, generally showing the interface of the main system unit (MSU) (hardware component) 504 to the main processing unit (MPU) (software component) 514. Figure 5A will be discussed in more detail later in this disclosure.

[0149] Figure 5B is a block diagram 524 representing the main sections of the EP hardware system input stage 400, where sections 530, 532, 534 are cross-referenced to the sections shown in the EP hardware system input stage 400.

[0150] In Figure 5B , the analog input protection / filter stage 530 includes block 1 - input protection 402a, block 2 - RF filter 404a, block 3 - buffer 406a, block 4 - DC block 408a, block 10 - low-frequency feedback 420a, and block 11 - shield drive 422a. The symmetric negative circuitry includes block 1 - input protection 402b, block 2 - RF filter 404b, block 3 - buffer 406b, block 4 - DC block 408b, block 10 - low-frequency feedback 420b, and block 11 - shield drive 422b. The signal amplification stage 532 includes differential circuitry, which includes block 5 - instrumentation amplifier / filter 410, block 6 - differential amplifier 1 / filter 412, block 7 - differential amplifier 2 / filter 414, and block 9 - large signal detection / quick recovery 418. The A / D converter stage 534 includes block 8 - A / D converter 416. The A / D converter stage 534 also includes a communication module 510 ( Figure 5A shown in), and the communication module 510 can format the signal for transmission over an optical fiber link 512 to a digital processing stage 528 represented by the MPU 514 in some embodiments.

[0151] Figure 4 The functionality of the specific blocks 1 - 11 and the single channel of the EP hardware system input stage 400 are described in the following paragraphs.

[0152] Analog Input Protection / Filtering Stage

[0153] Figure 5B The analog input protection / filtering stage 530 of the EP system shown in FIG. 1 includes block 1—input protection 402a, 402b; block 2—RF filter 404a, 404b; block 3—buffer 406a, 406b; block 4—DC block 408a, 408b; block 10—low frequency feedback 420a,

[0154] 420b; and Block 11 - Shield Drive 422a, 422b. These elements according to some embodiments are described in more detail in the following paragraphs.

[0155] Input protection circuit system

[0156] Fig. 6A , Figure 7 and Figure 6B A circuit comprising an analog input protection / filtering stage 530 of the disclosed EP system is illustrated in accordance with some embodiments. Fig. 6A The overvoltage protection circuit system 600 is shown in FIG. Figure 4 As represented by block 1 (402a, 402b), the overvoltage protection circuit system 600 can protect other EP hardware system input stage 400 circuits from large transient voltages, especially for example, defibrillation pulses. The analog input protection / filtering stage 530 can prevent the input voltage from exceeding the range that the circuit can actually handle.

[0157] Specifically, the analog input protection / filtering stage 530 can reduce high voltage transients at the inputs of the ECG, IC, and other electrode leads connected to the patient's body to less than ten (10) volts, for example, at the input of the EP system buffer. The analog input protection / filtering stage 530 can prevent large signals, such as from a defibrillator, from damaging other parts of the system. Additionally, the analog input protection / filtering stage 530 can perform these functions without absorbing, for example, more than 10% of the energy of an applied defibrillation pulse, without requiring clamping, or without adding nonlinearity when applying ablation signals.

[0158] Fig. 6A An exemplary embodiment of an overvoltage protection circuit system 600 of block 1 is shown, which includes an off-the-shelf gas discharge tube (GDT)

[0159] 608, The gas discharge tube 608 can be fired at a very high voltage (such as a voltage higher than 300V) to provide high voltage surge protection. The GDT 608 is coupled to two stages of diodes 610, 612 (and resistors 602, 604). The diodes are designed to sequentially clip the signal to 18V, for example, removing defibrillation signals such as up to 5000V. Diode 610 represents an off-the-shelf electrostatic discharge (ESD) voltage suppressor device that can assist the GDT 608 until the GDT 608 is fully conducting. Diode 612 represents an off-the-shelf bidirectional ESD protection diode that can limit the In2 input of the RF filter (block 2) to 18V at the node marked (a) in Fig. 6A and Figure 7 the node marked (a).

[0160] Conventionally, a defibrillation signal of approximately 5000V will be clamped to + / - 5V to prevent injury. In the case of the present disclosure, the defibrillation signal can be similarly clamped, but an ablation signal having an ablation voltage of approximately 200V at, for example, 500kHz can be linearly passed through and attenuated by the input resistors RCable, 602, 604 and block 2 ( Figure 4 、404a、404b), RF filter 702.

[0161] Figure 7 Illustrated is the RF filter / shield drive 700. The RF filter / shield drive 700 includes an RF filter 702 and a shield drive 730. The RF filter / shield drive 700 is connected, at the node marked (a), to Fig. 6A the overvoltage protection circuit system 600 for transmitting the signal In12 through the analog input protection / filter stage 530. The RF filter 702 of the RF filter / shield drive 700 is described in more detail below. The shield drive 730 of the RF filter / shield drive 700 is also described below.

[0162] The input overvoltage protection circuit system 600 does not clamp the ablation signal; instead, the ablation signal is linearly attenuated (e.g., proportionally reduced by the input resistors RCable, 602, 604 and the RF filter 702) so that it is not inadvertently altered. For example, if the ablation signal is clamped by the input overvoltage protection circuit system 600, there will be no access to the content of the signal above the clamp. Advantageously, the linear attenuation of the ablation signal by the disclosed EP system can allow recording of small cardiac signals of a few millivolts during ablation. Those of ordinary skill in the art will understand that the devices, systems, and methods disclosed herein are similarly applicable to other high-frequency signals that may need to be passed through a protection circuit (e.g., unclamped) to prevent generation of non-linearity that would affect the signal of interest.

[0163] Figure 6B Represents the ESD input protection circuitry 620 at the last section of the analog input protection / filter stage 530. The ESD input protection circuitry 620 is coupled to the RF filter / shield driver 700 at the node labeled (b) in Figure 7 . The ESD protection chip 622 can provide up to 30 kV of ESD protection for the data lines and can respond to overvoltage conditions within nanoseconds. For this purpose, any number of off-the-shelf ESD protection devices can be used.

[0164] Transient voltage suppressor (TVS) diodes 628, 630 can provide over 16 kV of ESD protection by shunting excess current when the induced voltage exceeds their breakdown voltage. The TVS diodes 628, 630 can act as "clamping" or limiting devices to suppress overvoltages exceeding their breakdown voltage and can automatically reset when the overvoltage subsides. The TVS diodes 622, 630 can also respond to overvoltages faster than other common overvoltage protection components; for example, "clamping" occurs in approximately 1 picosecond. TVS diodes generally have an advantage in preventing very fast and potentially damaging voltage transients.

[0165] Figure 8A-8E and Figure 9A-9E illustrates a sample signal diagram according to an exemplary embodiment, which demonstrates how the front-end input protection circuit processes high-voltage transients and ESD. Fig. 8A illustrates the voltage V(Defib) of a representative defibrillator signal that is applied to the input of the input protection circuit labeled "EP signal" in Fig. 6A . In a laboratory setup, the defibrillator signal can be obtained by applying a 5000-volt voltage to a 32 μF capacitor and then discharging the capacitor to the connected electrodes on the patient. Due to inductance and resistance, the amplitude received at the electrodes is approximately 4500 volts and lasts for tens of milliseconds.

[0166] Figure 8B-Figure 8E illustrates the different voltage levels as the defibrillation signal progresses through the circuit. Figure 8B The V(In) of Fig. 6A is the voltage across the GDT 608 of Figure 8BAs shown by the curve for V(In), one drawback of GDTs is that they may take some time to turn on. The GDTs are supposed to trigger at 230V, but the voltage has to rise to a higher level before they can turn on effectively and start conducting. The turn-on time can be several hundred nanoseconds. Fig. 6A The resistor RCable in limits the current flowing into the GDT 608. This can reduce the power consumed in the system and also ensure that the analog input protection / filter stage 530 does not divert any appreciable power to the patient.

[0167] Fig. 6A The ESD voltage suppressor diodes 610 in can turn on faster (e.g., within a nanosecond), but have a lower power / energy capacity, enabling them to activate quickly. As Figure 8C As shown by the signal diagram for V(P1), when the GDT 608 is fully turned on, they can hold the voltage at P1 to approximately 30V. When the GDT 608 is fully turned on, the ESD voltage suppressor diodes 610 are no longer active.

[0168] Fig. 6A The next stage in is the ESD protection diode bidirectional pair 612, as Fig.8D As shown by the signal diagram for V(In12), it can limit the signal at In12 (the input of the RF filter (block 2)) to approximately 18V. The signal passing through the RF filter will be further described in the following RF filter (block 2) section.

[0169] Finally, as Figure 6B shown, at In13, after the signal has been filtered by the RF filter of block 1, as for the Fig. 8E signal diagram of V(In13), the ESD protection chip 622 can limit the signal at VDD to + / − diode voltage drop (e.g., + / −5.7 volts).

[0170] Those of ordinary skill in the art will understand that Fig. 6A and Figure 6BThe combination of the input protection circuitry shown (including GDT 608, diodes 610, 612, ESD protection chip 622, and TVS diodes 628, 630) protects the circuitry of the EP recording system. However, the circuitry itself may be detrimental to achieving high-quality EP recordings during ablation. For example, if the ablation signal is clipped, the resulting non-linearity can introduce noise and mask the cardiac signals of interest. Since the medical team may wish to view the cardiac signals during ablation, the integration of the RF filter of block 2 with the input protection circuitry is an improvement over conventional solutions. The disclosed embodiments allow unwanted and potentially disruptive or damaging signals to be attenuated while linearly filtering the ablation signal and monitoring the ECG and IC signals.

[0171] For example, 9A to 9E is a signal diagram illustrating the ablation signal traveling through Fig. 6A , Figure 7 and Figure 6B of the input protection circuitry. As shown by the curve V(Defib) in Fig.9A , the ablation input at the sensor electrode is 400 Vpp. As the signal travels through the stages of the input protection circuitry, the signal is attenuated by resistor RCable (as shown by the curve V(In) in Fig. 9B ), resistor 602 (as shown by the curve V(P1) in Fig. 9C ), resistor 604 (as shown by the curve V(In12) in Fig.9D ), and capacitor 716 (as shown by the curve V(In13) in Fig.9E ). The ablation signal voltage level is 100 Vpp at node In in Fig. 6A , 12 Vpp at node In12 in Fig. 6A , and 60 mV at node In13 after the RF filter in Figure 7 . The ablation signal does not trigger the protection device but is linearly attenuated, allowing cardiac signals to be observed and / or recorded during ablation. The ablation signal can be further filtered at each of blocks 5, 6, and 7 of signal amplification stage 532 (see Figure 4 , Figure 5B and Fig.10 ) and at the A / D converter (block 8 in Figure 4 )

[0172] (with a 100 dB low-pass filter at 950 Hz).

[0173] RF filter circuit system with low frequency feedback and shield drive

[0174] In addition to contributing to the input protection circuit to filter and linearly attenuate the ablation signal at the EP system input, RF filter 702 can also work in concert with the low-frequency feedback circuit of block 10 (see Figure 4 , 420a and 420b, and Fig.16 , 1600), so that the entire circuit can continue to linearly attenuate the ablation signal (e.g., having a voltage amplitude of about 200 V in the frequency range of about 300 kHz to about 600 kHz) during cardiac monitoring, while, for example, transmitting small cardiac signals (e.g., having a frequency range of about 0.01 Hz to about 500 Hz).

[0175] RF filter 702 can be designed to, for example, linearly attenuate the amplitude of the ablation signal by at least 75% in some embodiments, or even at least 90% linearly in other embodiments. For example, RF filter 702 can be designed to provide substantially no attenuation to input signals with frequencies less than 5 kHz. This RF filter 702 can also work in concert with the shield drive 730 of block 11 (see Figure 4 , 422a and 422b and Figure 7 ), and the shield drive 730 can work with the input capacitors 706, 714, 716 of RF filter 702 to help maintain a high input impedance for the entire circuit. This high input impedance can help minimize the input loss of cardiac signals of interest. The shield drive 730 is discussed further below.

[0176] Low frequency feedback circuit

[0177] The low-frequency feedback circuit 1600 of block 10 (see Figure 4 , 420a and 420b) can provide positive feedback to the RF filter of block 2 (see Figure 4 , 404a and 404b and Figure 7 , 702) to increase the input impedance of the EP system, thereby reducing signal attenuation. This is beneficial because the input impedance of the EP system in the cardiac signal frequency range may be impaired by RF filter 702.

[0178] Specifically, the high input impedance at the instrumentation amplifier 1001 of Fig.10 can be significantly reduced according to the frequency of the input signal (e.g., 100 times at 60 Hz) due to the presence of the RLC network elements 706, 708, 714, 716 of RF filter 702. Although RF filter 702 is beneficial at the ablation frequency, the reduction in impedance at low frequencies can reduce the amplitude of cardiac signals and affect common-mode rejection. Without mitigating the effects of RF filter 702, the advantages of instrumentation amplifier 1001 will be lost in other ways.

[0179] To mitigate this loss and maintain high common mode rejection (e.g., on the order of 100 dB), it is desirable to maintain a high impedance at the power line frequency so that variations in the source impedance do not convert common mode signals into differential signals. Block 10, Fig.16 The low-frequency feedback circuit 1600 shown in receives a buffered version of the signal of interest as Buf11602 from the buffers 406a, 406b of block 3. The low-frequency feedback circuit 1600 then applies an operational amplifier 1606 to drive Shield1 (shield 1) 728 at the bottom (i.e., the lower plate) of the capacitors 706, 714, 716 in the RF filter 702. Specifically, the operational amplifier 1606 acts as a driver to eliminate the load effect and maintain a high input impedance of the analog input protection / filter stage 530 into the signal amplification stage 532.

[0180] When the low-frequency feedback circuit 1600 of block 10 drives the RF filter 702 at a low frequency, the voltage change across the capacitors 714, 716 is small or none. Thus, at low frequencies, the capacitors 706, 714, 716 act as open circuits and maintain a high input impedance. However, at higher frequencies, due to the low-pass filtering function of block 10, the feedback from the low-frequency feedback circuit 1600 of block 10 is reduced.

[0181] Specifically, the combination of the capacitor 1666 and the resistor 1693 at the inverting input of the operational amplifier 1606 filters high frequencies. The output of this circuit no longer tracks the input and holds Shield1 728 (which is also the reference node of the RF filter 702) at a fixed level with respect to high-frequency signals. This enables the passive RLC network 706, 708, 710, 712, 714, 716 of the RF filter 702 to attenuate high-frequency signals.

[0182] Specifically, the block 10 low-frequency feedback circuit 1600 (see Figure 4 , 420a and 420b) obtains the buffered signal from the block 3 buffer circuit (see Figure 4 , 406a and 406b) and generates a correction signal to Figure 7 's Shield1 728, i.e., the equivalent input is at the capacitors 706, 714, 716 of the RF filter 702 in block 2 (see Figure 4 , 404a and 404b) as a feedback signal. This feedback to the capacitors 706, 714, 716 is provided as a dynamic current source for the circuit.

[0183] The RF filters 702 of blocks 2 404a, 404b are enabled for high-frequency filtering, but are disabled at low frequencies when receiving feedback from the low-frequency feedback circuit 1600 of blocks 10 420a, 420b. At high frequencies, the capacitors 706, 714, 716 in the RF filter 702 act as shunt capacitors that effectively short-circuit the signal at RF frequencies. The impedance of the capacitors 706, 714, 716 linearly decreases as the frequency gets higher. The low-frequency feedback circuit 1600 does not affect the EP system at high frequencies.

[0184] At low frequencies, the low-frequency feedback correction signal Shield1 728 from block 10 (see Fig.16 ) to block 11 ( Figure 7 shield drive 730) drives the lower plates of the capacitors 706, 714, 716 such that these capacitors mimic the input signal. This controls the reference node of the RF filter 702. Specifically, the voltages at the plates of the capacitors 706, 714, 716 change synchronously with each other, and the low-frequency feedback circuit 1600 drives the lower plates of the capacitors 706, 714, 716 of the RF filter 702 to the same voltage as the upper plates, such that the voltage difference between the plates of the capacitors 706, 714, 716 becomes zero, and the capacitors 706, 714, 716 act as open circuits.

[0185] The goal of the low-frequency feedback is to drive the difference between Shield1 728 and Buf1 1602 to zero such that Shield1 728 equals Buf1 1602. When this occurs, the input capacitance can be eliminated. At high frequencies, the positive feedback from the operational amplifier 1606 is reduced to zero. Additionally, at high frequencies, the capacitor 722 (e.g., which is 30 times larger than other capacitors in the circuit) acts as a short circuit between Shield1 728 and ground. This effectively grounds the reference node of the RF filter 702, thereby fully enabling it to attenuate RF frequencies. Thus, the block 10 low-frequency feedback circuit 1600 works in concert with the unique arrangement of the block 2 RF filter 702 components to remove the load effect of the RF filter 702 before passing the signal to the block 5 instrumentation amplifier 1001.

[0186] In this way, the instrumentation amplifier 1001 can condition the cardiac signal without masking the ablation signal. As a result, at low frequencies, the input of the entire circuit still sees a very high input impedance (e.g., on the order of tens of MOhms), which is beneficial for visualizing high-fidelity cardiac signals in an EP environment. Additionally, block 10 is a symmetric (e.g., mirror-image) circuit such that when the signal propagates through the circuit, the common-mode noise is subtracted. Another advantage of the low-frequency feedback circuit 1600 is that its output Shield1 728 can, for example, be at Figure 7At OutS1 of the shield driver 730, it is used to drive the outer shield of the input cable.

[0187] Shield drive circuit

[0188] Block 11 (see Figure 4 , 422a and 422b), specifically Figure 7 the shield driver 730 shown in Figure 4 , receives the output of the low-frequency feedback circuit 1600 of block 10 (see Fig.16 Shield1 728) and provides positive feedback to the cable shield at OutS1, thereby reducing the effective input capacitance of the input cable. Therefore, from the input capacitors 714 in the RF filter 702 of block 2 (see Figure 4 , 404a and 404b),

[0189] the path from the lower plates of 716 to the shield of the input cable further helps to make the input impedance as large as possible. This high input impedance minimizes the input loss of the cardiac signal of interest. In some embodiments, if the shield driver is not desired, the shield driver connection is grounded.

[0190] Signal buffering and DC blocking circuitry

[0191] Block 3 (see Figure 4 , 406a and 406b) is a low-noise unity-gain driver that helps to minimize the input loss of the cardiac signal. Specifically, it can provide a high input impedance to minimize the loading of the input stage on the cardiac signal and drive the signal amplification stage 532. In block 3, two operational amplifiers (circuit not shown) form two buffers, and the two buffers act as unity-gain followers that buffer the input and provide a high input impedance to the input.

[0192] Block 4, the DC block (see Figure 4 , 408a and 408b) is a high-pass module (circuit not shown), and the high-pass module prevents the input offset from the sensor / tissue interface of the patient's body from entering the amplifier gain stage. In block 4, two DC blocking capacitors (not shown) protect the input from large offsets from the catheter.

[0193] Signal amplifier stage

[0194] The signal amplification stage 532 of the EP system (see Figure 5B ) includes a differential circuit system:

[0195] Block 5 - Instrumentation Amplifier / Filter 410, Block 6 - Differential Amplifier 1 / Filter 412, Block 7 - Differential Amplifier 2 / Filter 414, and Block 9 - Large Signal Detection / Fast Recovery Circuit 418. These circuits will be described in more detail in the following paragraphs.

[0196] Instrumentation Amplifier / Filter Circuit

[0197] Block 5 (see Figure 4 , 410) is an instrumentation amplifier / filter that provides amplification for differential signals and performs common-mode rejection on unwanted signals (especially power line noise and related harmonics) from an equipment laboratory or medical environment. Fig.10 Block 5, described in detail in, has a gain stage 1001 with a differential gain of approximately 20 at its output, and it provides additional filtering for RF attenuation through its RC network 1008, 1010, 1012, 1014. Two operational amplifiers 1006, 1016 are, for example, low-noise devices and are designed to receive the cardiac signal at the input of the instrumentation amplifier 1001 before the cardiac signal has been amplified. The differential signal from the instrumentation amplifier 1001 of Block 5 then enters the precision resistor block 1018 of Block 6 Differential Amplifier #1 1017.

[0198] Differential Amplifier / Filter Circuitry

[0199] Block 6 (see Figure 4 , 412) has a differential amplifier 1020 that references a common-mode voltage and produces a fully differential output with unity gain. Block 6 Differential Amplifier #1 1017 can provide additional filtering for RF attenuation. Maintaining a fully differential signal path helps reduce noise entering from the digital part of the system. Such noise mainly appears as common-mode noise and is rejected. This part of the signal amplification stage 532 also shifts the DC bias of the cardiac signal from 0 to up to 2.5V and limits its output from 0 to 5V.

[0200] At the output of Block 6 with the first fully differential amplifier 1020 that references a common-mode, when the signal enters Block 7 Differential Amplifier #2 1021, the common-mode level is set to 2.5V. The circuit continues to low-pass filter the ablation signal to the output of Block 7 (B2OutP, B2OutN). Block 7 with a second fully differential amplifier 1034 similar to the differential amplifier 1020 of Block 6 has a gain of approximately 0.5, where circuit elements 1022, 1024, 1026, 1028, 1030, 1032, 1036, 1038, 1040, 1042 provide additional filtering for RF attenuation. This part of the signal amplification stage 532 maintains a fully differential signal path to continue suppressing noise.

[0201] The gain introduced by block 7 allows the circuit to limit the signal at the input limits of the A / D converter, block 8 (see Figure 4 ,

[0202] 416), and the A / D converter can be, for example, a Δ-Σ converter (not shown). As previously described, block 6 differential amplifier #1 1017 limits each output signal to + / –2.5 volts with respect to a bias level of 2.5 volts. At a gain of 0.5, the output of block 7 differential amplifier #2 1021 produces a signal biased at 2.5 volts, with a range of + / –1.25 volts for each output, or a peak-to-peak difference of 2.5 volts. For example, in some embodiments, this represents the limit of a 24-bit A / D converter 416.

[0203] By limiting and matching the output limits, the input of the A / D converter 416 is prevented from being overdriven. Since a Δ-Σ converter may exhibit irregular behavior when overdriven, which can lead to false results, it is advantageous for the embodiments to allow the entire input range of the A / D converter, but no more.

[0204] The overall gain of the signal amplification stage 532 of the disclosed EP system can be, for example, less than or equal to 20 in some embodiments, or less than or equal to 50 in other embodiments. For example, in some embodiments, a gain of approximately 20 at the output of the instrumentation amplifier 1001, a unity gain at the output of the differential amplifier #1 1017, and a gain of approximately 0.5 at the output of the differential amplifier #2 1021 result in a system gain of approximately 10 at the input of the A / D converter 416. Generally, the signal amplification stage 532 can include an instrumentation amplifier 1001 with a gain greater than one (1) at its output, a differential amplifier #1 1017 with a gain of approximately one (1) at its output, and a differential amplifier #2 1021 with a gain less than one (1) at its output.

[0205] Due to its improved ability to remove noise, the overall low gain of the system provides a further improvement over conventional systems. Conventional systems with 16-bit A / D converters require high gain to visualize small signals that are masked in the presence of high-amplitude signals. Conventional systems can have a gain of up to, for example, 5000, resulting in rapid signal saturation. Additionally, if a lower gain is used with a 16-bit converter, quantization noise can adversely affect the output results. With the disclosed system having a low gain of approximately 10, the system is coupled to a 24-bit A / D converter, saturation can be prevented until, for example, a small signal input of at least 250 mV, and quantization noise is avoided.

[0206] Large signal detection / fast recovery circuit system

[0207] The output from block 6 differential amplifier #1 1017 is passed, in addition to being passed to block 7 differential amplifier #2 1021, to block 9 (see Figure 4 , 418 and Fig.10 ), Fig.11 to the large signal detection / quick recovery circuit 1100. The large signal detection / quick recovery circuit 1100 can remove large signals and quickly recover from large transients. This circuit is called a "quick recovery" circuit because its ability to recover from saturation is much faster than conventionally implemented.

[0208] Specifically, the large signal detection / quick recovery circuit 1100 can detect that the differential input signal has exceeded 100 mV for a duration of, for example, at least 10 milliseconds, which is identified as an abnormal operating range. When this state is detected, the large signal detection / quick recovery circuit 1100 can reduce the time constant after the DC blocking stage in block 4 (see Figure 4 , 408a and 408b) to ensure that the cardiac signal does not remain saturated. However, the effect of the large signal detection / quick recovery circuit 1100 under normal operation can be negligible. For example, the large signal detection / quick recovery circuit 1100 can have no effect on the fast transients generated by pacing, which can be signals of interest to be monitored and recorded in an EP environment and whose transient duration is typically less than 10 milliseconds.

[0209] In one embodiment, the first stage of the large signal detection / quick recovery circuit 1100, for example, has two operational amplifiers 1108, 1112. The gain of operational amplifier 1108 (e.g., approximately 40) determines the activation threshold, i.e., the signal amplitude at which the large signal detection / quick recovery circuit 1100 can operate to limit (or "soft clamp") the signal. The activation threshold determines how large the signal must be before the large signal detection / quick recovery circuit 1100 becomes active and starts pulling the voltages at nodes In14 and In24 towards the common mode level. For example, an operational amplifier 1108 with a gain of approximately 80 can activate the large signal detection / quick recovery circuit 1100 at approximately 50 mV; an operational amplifier 1108 with a gain of approximately 40 can activate the large signal detection / quick recovery circuit 1100 at approximately 100 mV; and an operational amplifier 1108 with a gain of approximately 20 can activate the large signal detection / quick recovery circuit 1100 at approximately 200 mV. When the signal amplitude reaches the set amplitude level determined by the gain, the voltage will be sufficient to overcome the activation threshold of the first pair of diode stages 1114, 1116 for activating the large signal detection / quick recovery circuit 1100.

[0210] The operational amplifier 1112 generates a unity gain to buffer the common mode (CM) signal, which provides a common mode reference for the signal passing through the operational amplifier 1108. The operational amplifier 1108 receives the U4Out1 and U4Out2 signals from block 6 (see Fig.10 ). Thus, the average value of the U4Out1 and U4Out2 signals is referenced to the common mode node ( Fig.11 's CMB). The signal exiting the operational amplifier 1108 passes through the first pair of diode stages 1114, 1116, which limit the charging of the subsequent capacitors 1120, 1124, 1128, 1132. These capacitors 1120, 1124, 1128, 1132 accumulate the charge from the buffered U4Out1 and U4Out2 signals, generating the maximum positive (+) and negative (-) charges for the inverted and non-inverted versions of the signals U4Out1 and U4Out2.

[0211] The capacitors 1120, 1124, 1128, 1132 together with the resistors 1118, 1122, 1126, 1130 form an RC network at nodes C, D, E, and F, and they together serve as a timing network for determining the time constant. The time constant determines the time during which the signal can be at its maximum amplitude before the large signal detection / quick recovery circuit 1100 pulls the voltages at nodes In14 and In24 towards the CM. This RC network is hereinafter referred to as the "timing library" 1158. Some embodiments of the timing library 1158 can be designed to generate a time constant of at least 10 milliseconds, for example, to prevent the activation of the large signal detection / quick recovery circuit 1100 during a pacing signal with a duration, for example, from 2 milliseconds to 10 milliseconds. Other embodiments can be designed to generate a time constant of at least five (5) milliseconds.

[0212] When capacitors 1120, 1124, 1128, 1132 are charged, a difference is detected and the signal is passed through the second pair of diode stages 1146, 1148, which limit (or "soft clamp") the input to approximately, for example, + / - 100 mV. This can prevent the system from saturating for any appreciable amount of time (e.g., less than 100 milliseconds). The second pair of diode stages 1146, 1148 also ensure that there is no interaction between the large signal detection / quick recovery circuit 1100 and the EP system if the magnitude / length of the signal is not sufficient to require a limit. In other words, when it is disadvantageous to activate the large signal detection / quick recovery circuit 1100, the second pair of diode stages 1146, 1148 disconnect the large signal detection / quick recovery circuit 1100. Block 9 large signal detection / quick recovery circuit 1100 ensures that the EP system is not affected by large signal spikes and allows a steady-state response where the difference between the inverting and non-inverting U4Out1 and U4Out2 signals is approximately 100 mV, for example where the operational amplifier 1108 has a gain of approximately 40, for example.

[0213] Block 9 large signal detection / quick recovery circuit 1100 is located at a position in the EP system for removing large signal voltage offsets. Those of ordinary skill in the art will understand that the large signal detection / quick recovery circuit 1100 can be located at other positions in the EP system where potential large signal spikes may occur and are undesirable. Those of ordinary skill in the art will also understand that electronic components (such as capacitors 1120, 1124, 1128, 1132 and resistors 1118, 1122, 1126, 1130 of the timing library 1158) can be replaced in the large signal detection / quick recovery circuit 1100 to change the circuit activation levels and times. As those of ordinary skill in the art will understand, the large signal detection / quick recovery circuit 1100 can be used in various embodiments of other signal acquisition and processing systems to remove large signal voltage offsets from other types of electrical signals.

[0214] In some embodiments, the outputs In14, In24 of block 9 large signal detection / quick recovery circuit 1100 (see Figure 4 , 418) are fed back to block 4, the DC block (see Figure 4 , 408a and 408b). The DC blocking capacitor (not shown) of block 4 adds an additional bias (e.g., a correction bias) back to the input signal. Thus, unless the signal fed into block 9 is large (e.g., has an amplitude on the order of approximately 100 mV or greater), the signal from block 9 large signal detection / quick recovery circuit 1100 is not fed back into the block 4 DC block. In other words, unless a large signal event occurs, the output signal of block 9 is not passed to block 4. Nodes In14 and In24 are typically disconnected.

[0215] Fig.11 An exemplary embodiment of the large-signal detection / quick recovery circuit 1100 will be described in detail with respect to the signal diagrams of Fig.12 , Figure 13A-13C , Figures 14A-14D and Figure 15A-15B . A sample signal is applied at the input to the EP system and is described at various points in the circuit. In this example, the signals shown for demonstrating the large-signal detection / quick recovery circuit 1100 are generated by applying a 20 mVpp signal at the node In12 of Fig. 6A and Figure 7 , and applying a zero input, specifically an input to the RF filter 702, at the node In22 (symmetric negative node, not shown). At time 10 milliseconds, a step of 200 mV is added to the signal at the node In12. As the signal passes through the EP system, it becomes a 200 mV differential signal, which may cause the signal to move out of the display range of most conventional monitoring devices. Such a 200 mV signal typically should be removed so that the signal can be viewed in the EP environment.

[0216] Fig.12 Illustrates what happens to such an input signal if the large-signal detection / quick recovery circuit 1100 is not connected. After the sampled input 20 mVpp signal with the unwanted 200 mV step passes through the analog input protection / filter stage 530, the instrumentation amplifier 1001, and the differential amplifier #1 1017 and reaches the large-signal detection / quick recovery circuit 1100, if the large-signal detection / quick recovery circuit 1100 is not connected, the EP hardware system cannot quickly recover from the 200 mV step signal. Such a slow recovery complicates the identification of the cardiac signal.

[0217] Located Fig.10 before the instrumentation amplifier 1001, the resistors 1002 and 1004 eventually pull the offset signal back to the ground level, but a time constant of about 2.7 seconds is produced by the product of the DC blocking capacitor (not shown) of block 4 and the resistor 1002. This introduced delay is too long to recover an out-of-screen or saturated signal. Fig.12 Illustrates that the signal at the input node In14 does not move significantly downward within about 100 milliseconds and only moves a few millivolts (not shown) within about 400 milliseconds. Without the large-signal detection / quick recovery circuit 1100, such a large transient signal will likely have an adverse effect on the operation of the EP system because the large transient will push the monitored signal to saturation and the waveform details of the signal will be lost.

[0218] Figure 13A-13C Illustrates the same 200 mV large transient signal when the connected large-signal detection / quick recovery circuit 1100 is used. In this example, as Fig.13A and Fig. 13B As shown, the two input nodes In14 and In24 of the large-signal detection / quick recovery circuit 1100 (as Fig.11 shown) are pulled (biased) towards the common-mode signal V(CMB), the amplitude of which is approximately 100 mV (see Fig. 13C ). In14 (the positive input node of the large-signal detection / quick recovery circuit 1100) is pulled down, while In24 (the negative input node of the large-signal detection / quick recovery circuit 1100) is pulled up. V(CMB) is the average of the voltages at nodes In14 and In22 (the symmetric negative input to the entire circuit). The actual common-mode levels of nodes In14 and In24 have no effect, as the required bias levels are applied directly to the differential amplifiers (1020 and 1034 respectively) of blocks 6 and 7, which will set the common-mode voltage at those differential amplifiers 1020, 1034.

[0219] Fig.13A and Fig. 13B The curves in show that the voltages of nodes In14 and In24 are pulled into the monitoring range after approximately 50 milliseconds. The limit or "soft clamp" is thus gradually implemented to avoid discontinuities in signal acquisition and visualization. Other embodiments may allow for a gradual "clamp" within approximately 100 milliseconds.

[0220] FIG. 14A to FIG. 14D demonstrates how a large transient signal is conditioned as it passes through the respective internal nodes of the large-signal detection / quick recovery circuit 1100. Fig.14A The signal curves V(A) of and Fig. 14B V(B) of represent Fig.11 the output of the operational amplifier 1108 of the large-signal detection / quick recovery circuit 1100 in. In this example, the operational amplifier 1108 has a gain of approximately 40 with respect to the input, and produces a differential signal of (40 × 200 mV =) 8 volts across the Fig.11 nodes A and B in.

[0221] As Fig. 14C the curve V(C) of shows, after node B in Fig.11 the negative signal will Fig.11 pull down the voltage at node C in Fig.13A . Here, the signal has been filtered to remove the in-band signal occurring at node B, leaving a low-frequency control voltage at node C. The negative voltage at node C is connected to In14 via resistor 1140, diode 1150, and resistor 1144. This produces a current that pulls In14 towards the common-mode voltage, as Fig.14D shown. Similarly, as Fig.11Node E and J pull In24 towards the common-mode voltage.

[0222] Fig.11 The diode in the large-signal detection / quick recovery circuit 1100 controls the current direction. The first pair of diode stages 1114, 1116 (current-limiting diodes) allow different time constants for charging and discharging nodes C, D, E, and F. They also provide a non-operating range where nodes C, D, E, and F are not charged when the outputs A and B are less than the forward voltage drop of the diodes. The "clamping" diodes 1150, 1152, 1154, 1156 of the second pair of diode stages 1146, 1148 ensure that the input nodes In14 and In24 are pulled in the correct directions.

[0223] Figure 15A-15B Separate signal diagrams show the currents through Fig.11 resistors 1144, 1142 at the outputs In14 and In24 of the large-signal detection / quick recovery circuit 1100. During normal operation, the current is 0 and the instrumentation amplifier / filter 410 circuit is not affected. When the differential level is too high (i.e., when a large signal is detected, for example, exceeding 100 mV within a few milliseconds), the currents in these two resistors 1144, 1142 help pull the signal back to the common-mode voltage V(CMB).

[0224] A / D Converter

[0225] Block 8, the A / D converter 416 (see Figure 4 ) is a fully differential A / D converter designed to accept differential signals from the rest of the circuit. In some embodiments, each in the EP system circuit module is repeated eight times and fed into eight separate channels of the A / D converter 416 as a differential pair. For example, a TI ADS1278 24-bit, 8-channel Δ-Σ converter can be used. Those of ordinary skill in the art can select other A / D converters with similar specifications.

[0226] In some embodiments, the A / D converter 416 is highly linear, which is a characteristic of a Δ-Σ converter. As described below, the high linearity allows accurate digital signal processing to be performed in software. This configuration minimizes hardware filtering, thus facilitating RF attenuation and anti-aliasing, and allows greater flexibility in implementing filtering and signal processing in software. The advantage of selecting a fully differential A / D converter is that it can reject common-mode noise signals (e.g., digital clock signals) from any digital circuit system.

[0227] Wilson Central Terminal - Right Leg Drive (WCT-RLD) Circuit

[0228] Although the input common-mode signal can be at any frequency, the dominant signal is typically at the power line frequency: 60 Hz in the United States, for example. In a conventional EP environment, ECG (and similar) equipment attenuates a large amount of 60 Hz noise, which can be 100 times larger than the signal of interest. Additionally, due to distortion in the power line signal, there is typically a strong third harmonic at 180 Hz, which is usually the noisiest harmonic. Higher order harmonics and other common-mode signals are typically smaller and / or above the frequency band of interest for ECG and IC signals.

[0229] In some embodiments, a Wilson Central Terminal - Right Leg Drive (WCT - RLD) circuit is used to specifically remove 60 Hz and 180 Hz noise through common-mode rejection, i.e., by boosting the fundamental and third harmonic frequencies of the power line signal and selectively feeding these signals back to the patient to cancel the signals. Fig.23 A schematic diagram of an improved WCT - RLD circuit according to some embodiments is illustrated.

[0230] For example, Fig.23 the WCT circuit 2332 provides a virtual ground by summing and averaging two or three limb electrodes (e.g., right arm 2304 and left arm 2306, or right arm 2304, left arm 2306, and left leg 2308) connected to the central terminal 2336 via two or three large resistors 2334 (e.g., 20 kOhms per electrode). One of ordinary skill in the art will understand that the average of the right arm (RA) 2304, left arm (LA) 2306, and left leg 2308 provides a more accurate estimate of the common-mode signal on the patient 2302 compared to the average of the right arm (RA) 2304 and left arm (LA) 2306. As one of ordinary skill in the art will understand, the RA and LA signals are alternative buffered (see buffer 2312) versions of the RL positive (RLP) 2338 and RL negative (RLN) 2340 signals. The WCT is conventionally designed to reduce the overall 60 Hz common-mode noise signal by bringing the net potential difference of these limb leads close to zero.

[0231] Adding an active current to the WCT circuit 2332 via the "Right Leg Drive" (RLD) circuit 2330 through the right leg allows the patient 2302 to be driven to the same voltage as the common amplifier, thereby reducing the common-mode voltage at the inputs (LA, RA, LL, and V1 to V6) of the ECG electrodes. This can be achieved by generating the inversion of the common-mode signal and applying it as an output to the right leg. Specifically, the right leg drive is represented by the limb electrode RL. The patient 2302 receives, via the RL electrode, the sum and the inverted version of the RLD output 2310, other IC catheter signals, or ECG electrode signals to cancel out the interference present within the patient's body. This, combined with the common-mode rejection property of the signal amplification stage 532, can reduce the common-mode low-frequency interference to an acceptable level (e.g., as specified by the standard IEC60601-2-25).

[0232] However, since the 60Hz and 180Hz noises are not equal in all parts of the body, not all of the noise can be removed by common-mode rejection alone. Fig.23 The WCT-RLD circuit 2300 provides a reference signal that is approximately equal to the line frequency entering the system, which further reduces the overall common-mode signal. Thus, the combination of the disclosed WCT-RLD circuit 2300 and conventional common-mode rejection provides a beneficial improvement in the reduction of the common-mode signal.

[0233] In an exemplary embodiment using a WCT, the WCT input within the EP system can provide an optional unipolar input to replace the bipolar positive (+) or negative (-) catheter input to the block 3 buffer circuit (see Figure 4 , 406a, and 406b). Specifically, the WCT-RLD circuit 2300 averages the electrode signals of the right arm 2304, left arm 2306, and left leg 2308. The result is buffered by the operational amplifier 2314, and the output WCTBuf 2316 is sent as an unipolar feedback signal to any location within the EP system where it is needed, particularly in the embodiment when the patient is connected. The WCT-RLD disclosed herein enhances the conventional unipolar WCT solution by utilizing a novel method for generating the RLD signal.

[0234] In some embodiments, the novel method in the WCT-RLD circuit 2300 is to provide an additional filter circuit system called a "Twin-T" feedback network 2440 (see Fig.23 and Fig.24 ), which can generate a stronger RLD at the 60Hz power line frequency or the 180Hz third harmonic frequency. This is particularly useful during ablation. The Twin-T feedback network 2440 resonates at both 60Hz and 180Hz, but advantageously prevents phase oscillation by reducing the feedback at other frequencies.

[0235] Fig.24 FIG. illustrates a schematic diagram of a twin-T feedback network 2440 interfacing with the RLD circuit 2330 of the WCT-RLD circuit 2300, according to some embodiments. Fig.24 The twin-T feedback network 2440 serves as an improved notch filter. Resistors 2406, 2407, 2408, 2409, 2410, 2411 and capacitors 2401, 2402, 2403, 2404 form a single twin-T network that generates a notch at 60 Hz. In the next stage, resistors 2412, 2413, 2414, 2417, 2418, 2419 and capacitors 2415, 2416, 2420, 2421 similarly generate a notch at 180 Hz. However, when the network is in the operational amplifier feedback path, the inverse function is obtained.

[0236] For example, as shown in the curve 2500 of Fig.25 , the RLD output of the twin-T feedback network 2440 at the operational amplifier 2425 produces two peaks, one at 60 Hz 2510 and one at 180 Hz 2520. At higher frequencies (such as 10 kHz or higher), the phase change approaches zero. This prevents phase changes in the RLD circuit 2330 at these higher frequencies that could cause oscillations. The minimal phase change at these higher frequencies can prevent oscillations near the ablation frequency, which would be more difficult to filter out.

[0237] Although twin-T circuit systems have been used in electronic designs, they have not been used in the WCT-RLD circuits disclosed herein. When generating the RLD signal, the twin-T feedback network 2440 removes power line signals that are typically passed by known circuits, such that the power line signals do not affect the phase response at higher frequencies. The twin-T feedback network 2440 thus has a useful application for generating the RLD signal from the electrode leads.

[0238] In Fig.23In an embodiment, the RLD circuit 2330 follows the power line by feeding the RLD output 2310 back to the patient 2302 as a separate signal. In the circuit, the right leg positive (+) (RLP) 2338 and right leg negative (-) (RLN) 2340 differential input signals (which can alternatively be the RA and LA signals) are buffered 2312. Then, the twin-T feedback network 2440 enhances / amplifies the buffered right leg signal at 60 Hz and 180 Hz, and the buffered right leg signal is inverted and buffered again by the RLD circuit 2330. The RLD circuit 2330 includes operational amplifiers 2328, resistors 2320, 2324, 2326, and capacitors 2318, 2322. After passing through the RLD circuit 2330, the signal is output as the RLD output 2310 (RLDrv) at the surface lead of the patient's right leg. The effect is that the entire circuit tracks the power line, and the common mode of the circuit suppresses the power line noise. Additionally, the right leg driven circuit prevents any signal greater than approximately one (1) microampere from returning to the patient.

[0239] In some embodiments, taking the first derivative of two monopolar signals allows the physician to know whether the signal of interest is from a distal electrode or a proximal electrode. The bipolar signal can be displayed in a color-coded format to identify which components in the bipolar signal are from the cathode and which are from the anode. If the main signal of interest is generated there, the physician can then manually move to the proximal electrode. The system can also be automated in combination with a robotic system such that the movement is part of a closed feedback loop.

[0240] Case examples

[0241] The following case illustrates how the disclosed hardware circuit system conditions the signals found in an EP environment, thus allowing for improved cardiac monitoring in the presence of equipment and environmental noise and during the introduction of large, potentially interfering signals into the monitoring environment.

[0242] Signal Example #1 – Common Mode 60Hz and In-Band 500Hz Differential Signal

[0243] Signal Case 1# presents a typical common mode 60 Hz noise signal, as well as an in-band (less than 1000 Hz) differential signal found in a conventional IC lead. In this example, a series of signal plots representing the signals at exemplary nodes of the disclosed circuit are shown. The circuit amplifies the differential signal and suppresses the common mode signal.

[0244] FIG. 17A to FIG. 17B Separate input signals of a 2Vpp 60 Hz sine (power line) signal applied to input node In12 (see Fig. 6A ) and In22 (the negative lower branch of the circuit, not shown) are illustrated. A 0.2Vpp, 500 Hz sine wave signal is superimposed on In12 (see Fig.17A The curve of V(In12)), with a -0.2V, 500Hz sine wave signal superimposed on In22 (see Fig. 17B the curve of V(In22)). This will generate a 2Vpp, 60Hz common-mode signal and a 0.4V, 500Hz differential signal. The frequencies of these signals may be too low to be affected by the RF filter 702 of block 2, so the same signals appear at the output of block 3 (buffer 406a, 406b) and after block 4 (DC blocks 408a, 408b).

[0245] FIG. 17C to FIG. 17D The figure also shows Figures 17A to 17B shielded input signals (Shield1, Shield2) that are the same as the corresponding input signals shown

[0246] (low-frequency feedback circuit 1600) is fed back to the RF filter 702 to eliminate the load from the RF filter 702 (see Figure 7 Shield1, 728. Shield2, the negative lower branch of the circuit is not shown). Figure 7 The voltage variations on the capacitors 714, 716, 706 of the upper branch of the RF filter 702 in

[0247] Figures 18A - 18B The figure shows Out1 and Out2, the output of block 5 ( Figure 10 instrumentation amplifier 1001) with a differential gain of 20. The common-mode signal has a gain of 1, and the differential signal has a gain of 20. At this time, the signals become 2Vpp, 60Hz sine waves at each output, with a 4Vpp, 500Hz signal superimposed on Out1 (see Figure 18A ), and a -4Vpp, 500Hz signal superimposed on Out2 (see Figure 18B ), thus creating an 8Vpp differential signal.

[0248] Figures 18C - 18D The figure shows Figure 10 the outputs B2OutP and B2OutN of Figure 10 the fully differential operational amplifiers (blocks 6 and 7, 1017, 1021) of Figure 18C where the common-mode signal has been eliminated and the output is referenced to the common-mode output voltage VOCM (2.5V bias level). The 0.5 gain at the amplifier 1034 of block 7 results in a 2Vpp, 500Hz signal at B2OutP (see Figure 18C ) and at B2OutN (seeFigure 18D ) the final set of 500 Hz signals at -2 Vpp, which is equivalent to a 4 Vpp differential 500 Hz signal. From input to output,

[0249] the common-mode gain is 0, and the differential gain is 10. The common-mode signal can thus be eliminated by the combined response of the instrumentation amplifier (block 5) and the fully differential operational amplifier (blocks 6 and 7).

[0250] Signal Case #2 – 500kHz Ablation Signal

[0251] Signal Case #2 presents a typical 500 kHz ablation signal applied to the input of the EP system during an ablation procedure while cardiac monitoring continues. Before reaching the A / D converter (see Figure 4 , blocks 8, 416) of the disclosed circuit, the unwanted ablation signal is filtered and attenuated.

[0252] As Figures 19A - 19B shown, the ablation signal input is a 0.2 Vpp, 500 kHz sine wave applied to In12 ( Figure 19A ) and a -0.2 Vpp, 500 kHz sine wave applied to In22 ( Figure 19B ). This produces a 0.4 V, 500 kHz differential signal. This signal is in the frequency range to be attenuated by the RF filter 702 ( Figure 4 , 404a and 404b) of block 2.

[0253] Figures 19C - 19D The figure shows the curves of the output In13 of the RF filter 702 (block 2) (and the symmetric lower branch RF filter output In23) when the circuit receives the ablation signal. Figure 19C The curve of V(In13) and Figure 19D the V(In23) of

[0254] Figure 20A and Figure 20B are shown in the same scale as the input. It can be seen that the signal is attenuated to a few millivolts. Figure 7 The curves of V(Shield1) and V(Shield2) shown in Figure 7 respectively illustrate that the same signal on the shield input (e.g., see Shield1 of

[0255] Figure 21A and Figure 21B is also significantly attenuated, effectively grounding the lower plates of the capacitors 714, 716, 706 of the upper branch of the RF filter 702 inFigure 10 Graphs of the signals V(Out1) and V(Out2) at the output of the instrumentation amplifier 1001). The remaining 500 kHz signal passes through this 20X gain stage, but the filtering on this stage (from capacitors 1010 and 1012) limits the gain of 500 kHz to approximately 1X.

[0256] As Figures 21C to 21D shown, Figure 10 the continuous fully differential operational amplifiers 1017, 1021 (and their negative, lower branch circuit equivalents) in blocks 6 and 7 of Figure 21C continue to filter the 500 kHz signal until it is less than 0.5 mV at B2OutP( Figure 21D ). The remaining signal is removed by the filter on the A / D converter in block 8 (see Figure 4 , 416), which provides 100 dB of attenuation above 1000 Hz. The ablation signal is eliminated by the combined response of the RF filter (block 2), the instrumentation amplifier (block 5), and the fully differential operational amplifiers (blocks 6 and 7).

[0257] Hardware / Software Interface

[0258] Figure 5A illustrates the relationship between the hardware and software of the disclosed EP recording system according to some embodiments. The main system unit (MSU) 504 contains the hardware circuitry of the EP recording system. In Figure 5A , the ECG board 506 with the WCT 507 corresponds to the Figure 3 ECG board 302 and WCT 314 shown in Figure 3 . (For cross-reference, the digital signal outputs of the ECG boards 302, 506 are V1-V6 310 and I-II 312.) Similarly, the IC board 508 corresponds to the

[0259] IC board 316 in . (For cross-reference, the digital signal outputs of the IC boards 316, 508, IC1..ICN are ICUniWCT1-ICUniWCT2 326, ICUniINDIF1-ICUniINDIF2 328, and ICDiff1.ICDiffN 330.) To communicate the digital signal outputs from the ECG board 506 and the IC board 508 to the software 514 of the main processing unit (MPU), a communication module 510 and an optical fiber link 512 are provided.According to some embodiments, the communication module 510 of the MSU 504 transmits independent digital signals from the A / D converters 416, 534 of the ECG board 506 and the IC board 508 to the MPU 514 via the optical fiber link 512 for digital signal processing. The communication module 510 samples the output channels from the A / D converters 416, 534, converts them to a serial format, and transmits the data via the optical fiber link 512. The signal is converted back to a parallel format at the receiving end of the optical fiber link 512 in the MPU 514.

[0260] In this specification, for convenience, the ECG boards 302, 506 and the IC boards 316, 508 are thus named. As will be understood by those of ordinary skill in the art, the circuits of the ECG boards 302, 506 and the IC boards 316, 508 can receive other physiological signals from various types of electrodes other than the ECG and IC electrodes.

[0261] EP Recording System Software Description

[0262] Embodiments of systems, devices, apparatuses, methods, and / or computer program products and / or combinations and sub - combinations thereof for near - real - time processing and display of multiple signals are provided herein. For example, embodiments can relate to near - real - time processing and display of multiple biomedical signals (e.g., EP signals). Before describing these embodiments in further detail, a brief overview of digital signal processing is provided.

[0263] At a high level, digital signal processing is using digital processing to identify specific features in a signal, or to produce a signal of higher quality than the original signal (e.g., by removing noise from the signal). Digital signal processing can be performed on a digitized electrocardiogram (ECG) or intracardiac (IC) signal representing the electrical activity of the heart over a period of time.

[0264] To perform digital signal processing on an analog signal, the analog signal needs to be converted to digital form. As is well known to those of ordinary skill in the art, an analog - to - digital (AD) converter such as the A / D converter 416 can convert an analog signal to digital form.

[0265] Digital signal processing can involve applying digital signal processing functions to one or more signal samples in a sequence of signal samples for a signal. Digital signal processing functions can be sequences of mathematical operations and computational algorithms. For example, digital signal processing functions can measure, filter, compress, or optimize signal samples.

[0266] Depending on the type of analysis and the type of signal to be processed, digital signal processing can use different digital signal processing functions. For example, digital signal processing can use different digital signal processing functions to identify specific words in a voice signal or remove motion blur from a video signal.

[0267] Digital signal processing systems have many applications, such as audio signal processing, audio compression, digital image processing, video compression, speech processing, speech recognition, digital communication, digital synthesis, radar, sonar, financial signal processing, and seismology. However, conventional digital signal processing systems are generally not suitable for certain applications such as biomedical signal processing. This is because conventional digital signal processing systems (including current EP solutions) typically cannot display multiple signals nearly in real time simultaneously. Moreover, conventional solutions do not enable the user to dynamically apply new digital signal processing functions to the underlying signals. Also, conventional solutions generally cannot synchronize the processing and display of multiple signals nearly in real time. This is often problematic in a clinical environment because a physician's ability to make an effective clinical diagnosis may depend on comparing multiple signals at the same point in time. Finally, conventional EP systems using analog filters generally cannot fully utilize the advantages of digital signal processing. This is because when functions are implemented in hardware, the options are severely limited. For example, functions cannot be removed, so the full potential of digital signal processing cannot be achieved.

[0268] The digital signal processing (DSP) system disclosed herein further addresses the problems of these conventional systems. In addition to using multiple DSP filters to process, time-align, and display multiple signals nearly in real time simultaneously, the system also clarifies the operating endpoints for biomedical procedures such as ablation, making the operator more efficient. For example, the present disclosure provides high-fidelity surface ECG signals to automate and create signal-averaged, late potential electrocardiograms. Ablation procedures use intracardiac maps that enable the operator to visualize the heart tissue for ablation. When an intracardiac map is created, the adequacy of the map is judged by a percentage map of the signal-averaged late potential ECG from the surface signals. In other words, if a complete map is created, then when all the intracardiac signals with late potentials are summed, they should reproduce the timing and amplitude of the signal-averaged late potential map from the high-fidelity ECG. A score is displayed to indicate the adequacy of the map. For example, a score of 50% means that the mapping catheter has not reached some locations where late signals are present because they must be present to account for the signal-averaged late potential map data from the high-fidelity signals. After potential ablation, the signal-averaged late potential ECG in real-time high-fidelity determines whether the abnormal late potential has indeed been alleviated. If not, further ablation of the previously marked late potentials can be performed using a late potential filter and a dynamic window for guidance. The disclosed system provides data to guide the operator to the exact late potential regions in the map to reduce the need for further ablation.

[0269] Figure 26 is a block diagram of a system 2600 for processing and displaying multiple signals in near real time according to some embodiments. The system 2600 may represent Figure 5A the MPU (software) 514 in Figure 5B and implement the digital processing stage 528 of Figure 85 . The system 2600 includes a signal path module 2602, a configuration path module 2620, and a monitoring module 2622. The signal path module 2602, the configuration path module 2620, and the monitoring module 2622 may be software modules executable by one or more processors (such as Figure 85 the processors in). Alternatively, multiple processors may be used.

[0270] The signal path module 2602 includes an input module 2604, a timer 2605, a packetizer 2606, a queuing module 2608, a packet distributor 2610, a global signal table 2612, and an output module 2616. The input module 2604, the timer 2605, the packetizer 2606, the queuing module 2608, the packet distributor 2610, the global signal table 2612, and the output module 2616 may be software modules executable by one or more processors such as processor 5004. The signal path module 2602 at least solves the technical problem of how to synchronize the near real-time processing and display of multiple signals. As described below, the signal path module 2602 solves this technical problem using a novel multi-stage process involving packetization, queuing, and processing delay equalization.

[0271] In a first stage, the input module 2604 may receive signal samples for one or more base signals. A base signal may be a signal before any digital signal processing is applied. For example, a base signal may be a biomedical signal such as an ECG or an IC signal. As will be understood by those of ordinary skill in the art, a base signal may be various other types of signals. The input module 2604 may receive signal samples for multiple base signals. For example, the input module 2604 may receive signal samples of an IC signal and signal samples of an ECG signal.

[0272] The input module 2604 may receive signal samples of the base signal from a hardware device associated with the MSU (hardware) 504 in FIG. 5. For example, the input module 2604 may receive signal samples from a hardware device such as Figure 3 the EGG board 302 or the IC board 316 in. The input module 2604 may also receive signal samples from data stored in a computer file. For example, the computer file may contain previously recorded signal samples received from a hardware device.

[0273] The input module 2604 can receive signal samples from a hardware device via the A / D converter stage 534. For example, the input module 2604 can receive signal samples of the underlying signal from the EGG board 302.

[0274] The input module 2604 can receive signal samples of the underlying signal from electrodes attached to the hardware device. For example, the input module 2604 can receive signal samples for each of the eight (8) electrodes attached to the ECG board 302. One of ordinary skill in the art will understand that the input module 2604 can receive more or fewer signal samples depending on the number of hardware devices connected to the input module 2604 and the number of electrodes connected to each hardware device.

[0275] The input module 2604 can store one or more signal samples for each underlying signal in a computer storage device for later analysis by the review module 2624. For example, the input module 2604 can store one or more signal samples in Figure 85 the main memory 8508 or the hard disk drive 8512. This enables a user (e.g., a physician) to review one or more signal samples for each underlying signal after the signal samples have been acquired.

[0276] The input module 2604 can distribute one or more signal samples for each underlying signal to the batcher 2606. The batcher 2606 can perform preprocessing on the received signal samples. The batcher 2606 can perform preprocessing on the received signal samples to ensure that the resulting signals are compatible with subsequent stages in the signal path module 2602. One of ordinary skill in the art will understand that the type of preprocessing performed by the batcher 2606 can depend on the type of the underlying signal. For example, the batcher 2606 can convert the binary values of the received signal samples to their corresponding physical values, e.g., for displaying the underlying signal.

[0277] After preprocessing the received signal samples, the batcher 2606 can store one or more signal samples of the underlying signal into packets. A packet can be a consecutive sequence of N signal samples belonging to the same underlying signal. Storing the signal samples into packets by the batcher 2606 can enable the signal path module 2602 to synchronize the processing and display of multiple signals nearly in real time (especially on a non-real-time operating system). In other words, a packet is a processing unit in the signal path module 2602.

[0278] The batcher 2606 can store one or more signal samples in a packet based on the timer 2605. The timer 2605 can be a high-resolution timer. For example, the timer 2605 can be a High-resolution timer. The timer 2605 can be set to an amount of time associated with receiving a fixed number of signal samples (e.g., N signal samples) from a hardware device or from a computer file. The fixed number of signal samples can correspond to the number of signal samples that can be stored in a packet.

[0279] The packetizer 2606 can use the timer 2605 to ensure that each packet contains the same number of signal samples. Specifically, the packetizer 2606 can set the timer 2605 to an amount of time associated with receiving a given number of signal samples of the underlying signal. In other words, when the timer 2605 is triggered, the packetizer 2606 can expect to receive a certain number of signal samples.

[0280] The packetizer 2606 can start the timer 2605. The packetizer 2606 can then store the signal samples received from the input module 2604 into a packet until the timer 2605 is triggered. The packetizer can then distribute the packet to the queuing module 2608. The packetizer 2606 can then restart the timer 2605. The packetizer 2606 can then store a new set of signal samples received from the input module 2604 into a new packet until the timer 2605 is triggered again.

[0281] The packetizer 2606 can assign a label to each packet. The packetizer 2606 can assign the same label to each packet associated with different underlying signals for the same time period. This assignment can enable the signal path module 2602 to synchronize the processing and display of packets for different underlying signals for the same time period. The assigned label can be used by the display module 2618 to synchronize the output of different signals. In other words, the display module 2618 can work on the same label at any given time.

[0282] The assigned label can correspond to the time period during which the signal samples in the corresponding packet were received. Specifically, the label can correspond to the sample number of the first signal sample in the corresponding packet. For example, the packetizer 2606 can store sixteen (16) signal samples in each packet. In this case, the packetizer 2606 can store the first set of signal samples in a packet labeled 0. The packetizer 2606 can store the second set of signal samples in a packet labeled 15. The packetizer 2606 can store subsequent sets of signal samples in packets labeled 31, 47, 64, etc. Those of ordinary skill in the art will understand that other label assignment conventions can be employed.

[0283] After packetization, the packetizer 2606 can store each generated packet associated with a given underlying signal in the queuing module 2608. The queuing module 2608 is shown in Figure 27 shown.

[0284] Figure 27 is a block diagram of a queuing module 2608 for storing each generated packet associated with different base signals. The queuing module 2608 solves at least the technical problem of how to dynamically apply multiple different digital signal processing functions to the same base signal. The queuing module 2608 solves this technical problem by storing the generated packets associated with each base signal in separate queues that can be dynamically processed by different signal modules 2614. Refer to Figure 26 for discussion Figure 27 .

[0285] The queuing module 2608 includes one or more queues 2702. For example, in Figure 27 , the queuing module 2608 includes queue 2702-1, queue 2702-2, and queue 2702-N. Each queue 2702 can be associated with a given base signal. The queue 2702 can be a queue data structure that stores items in the order in which they are inserted. For example, the first item inserted into the queue 2702 is the first item removed from the queue 2702. In other words, the queue 2702 is a first-in, first-out (FIFO) data structure. As will be understood by those of ordinary skill in the art, the queue 2702 can be implemented using an array, a linked list, or various other data structures.

[0286] The packetizer 2606 can store each generated packet associated with a given base signal in the corresponding queue 2702. For example, the packetizer 2606 can store the generated packets associated with the IC signal in queue 2702-1 and store the generated packets associated with the ECG signal in queue 2702-2.

[0287] The packetizer 2606 can store each packet in the queue 2702 in the order in which it is generated. This can ensure that the signal samples in the generated packets are processed in the order received from the hardware device or computer file.

[0288] Returning Figure 26 , the packet distributor 2610 can distribute the generated packets from Figure 27 the queues 2702 in to one or more signal modules 2614 in the global signal table 2612 for digital signal processing. The packet distributor 2610 solves at least the technical problem of how to dynamically apply multiple different digital signal processing functions to the same base signal. The packet distributor 2610 solves this technical problem by distributing the generated packets associated with each base signal to the appropriate one or more signal modules 2614 for digital signal processing.

[0289] The packet distributor 2610 can continuously scan one or more queues 2702 in the queuing module 2608. Each time the packet distributor 2610 detects a new packet available in a queue 2702 in the queuing module 2608, the packet distributor 2610 can remove the new packet from the queue. The packet distributor 2610 can then distribute the new packet to one or more signal modules 2614 in the global signal table 2612 for digital signal processing. The packet distributor 2610 can distribute the same packet to multiple signal modules 2614 so that the underlying signal can be processed simultaneously using different digital processing functions. Additionally, since the packet distributor 2610 can distribute packets from different queues 2702 to different signal modules 2614, different underlying signals can be processed simultaneously using different digital signal processing functions.

[0290] The packet distributor 2610 can distribute new packets from the queue 2702 to one or more signal modules 2614. The packet distributor 2610 can use the global signal table 2612 to distribute new packets to one or more signal modules 2614. The global signal table 2612 can be a fixed-size array. Each element of the array can be associated with a given underlying signal and thus with a given queue 2702. For example, if there are 100 underlying signals, the global signal table 2612 can be a fixed-size array of 100 elements. Additionally, for each element of the array, there can be one or more signal modules 2614 designed to process the corresponding underlying signal. In some embodiments, each element of the array itself can be a fixed-size array. Each element of this sub-array can be associated with a given signal module 2614. For example, if there are 10 signal modules 2614, the sub-array can contain 10 elements. Thus, by way of example and not limitation, the global signal table 2612 can be a 100×10 array.

[0291] The packet distributor 2610 can distribute a new packet to a signal module 2614 by checking the corresponding element in the sub-array associated with the underlying signal of the new packet. Specifically, the packet distributor 2610 can determine whether the corresponding element in the sub-array indicates that a signal module 2614 is assigned to the underlying signal associated with the packet.

[0292] In some embodiments, the global signal table 2612 can indicate whether a given signal module 2614 is assigned to a given base signal by storing a "0" or a "1" at the corresponding element in the sub-array associated with the given signal module 2614. For example, the global signal table 2612 can indicate that a given signal module 2614 is not assigned to a given base signal by storing a "0" at the corresponding element in the sub-array. In some other embodiments, the global signal table 2612 can indicate whether a given signal module 2614 is assigned to a given base signal by storing a reference to the given signal module 2614 at the corresponding element in the sub-array. As will be understood by those of ordinary skill in the art, the reference can be a memory pointer, a flag, a handle, or other type of identifier.

[0293] The packet distributor 2610 can also use a lookup table to distribute new packets to one or more signal modules 2614. The lookup table can map a given queue 2702 to one or more signal modules 2614. The packet distributor 2610 can use the lookup table to dynamically determine which one or more signal modules 2614 are associated with a given queue 2702. The packet distributor 2610 can then distribute the packet to the determined one or more signal modules 2614 for digital signal processing.

[0294] Before the packet distributor 2610 can begin distributing packets to one or more signal modules 2614 for digital signal processing, the configuration path module 2620 can configure the signal path module 2602. The configuration path module 2620 can perform this configuration during system 2600 initialization or when the user applies a new configuration to the signal path module 2602. The configuration path module 2620 is Figure 28 shown in

[0295] Figure 28 is a block diagram of a configuration path module 2620 for configuring a signal path module 2602 to synchronize the processing and display of multiple signals nearly in real time according to some embodiments. The configuration path module 2620 at least solves the technical problem of how to synchronize the processing and display of multiple signals associated with one or more base signals nearly in real time. The configuration path module 2620 solves this technical problem by equalizing the processing delays of each signal module 2614 such that each signal module 2614 finishes processing the same corresponding packet at approximately the same time. Refer to Figure 26 for discussion Figure 28 of

[0296] The configuration path module 2620 includes a signal configuration module 2802, a signal factory module 2804, a digital signal processor (DSP) equalizer 2806, and a DSP factory module 2808. The configuration path module 2620 is a software module executable by a processor such as processor 5004. The configuration path module 2620 controls the execution of the signal factory module 2804, the DSP equalizer 2806, and the DSP factory module 2808. The signal factory module 2804, the DSP equalizer 2806, and the DSP factory module 2808 may be software modules executable by a processor such as processor 5004.

[0297] During initialization of the system 2600, or in response to a user applying a new configuration to the system 2600, the configuration path module 2620 may generate and configure one or more signal modules 2614 in the global signal table 2612. In some embodiments, the execution of the signal path module 2602 and the monitoring module 2622 may be paused during the execution of the configuration path module 2620.

[0298] The configuration path module 2620 includes a signal configuration module 2802. The signal configuration module 2802 may receive one or more signal processing specifications. The signal processing specifications may be used to generate and configure the signal module 2614. The signal processing specifications may specify the underlying signal to be processed, the lengths of the input and output packet queues for the signal module 2614, and the digital signal processing functions to be used to process the underlying signal. The signal configuration module 2802 may receive one or more signal processing specifications from a computer file. The file may contain one or more signal processing specifications previously specified by the user. The signal configuration module 2802 may also receive signal processing specifications via a graphical user interface (GUI), as will be understood by one of ordinary skill in the art, in which the user manually enters the signal processing specifications using a series of computer mouse, touch, keyboard, and / or voice recognition data input techniques.

[0299] In response to receiving one or more signal processing specifications, the signal configuration module 2802 may forward the one or more signal processing specifications to the signal factory module 2804. The signal factory module 2804 may generate the signal module 2614 based on the signal processing specifications. For example, the signal factory module 2804 may generate the signal module 2614 as Figure 29 shown.

[0300] Figure 29Block diagram of signal module 2614 generated by signal factory module 2804 according to some embodiments. Signal module 2614 may generate a processed signal from a base signal. Signal module 2614 includes an input packet queue 2902, a digital signal processor (DSP) 2904, and an output packet queue 2906. Reference may be made to Figure 26 and Figure 28 for discussion Figure 29 .

[0301] Signal module 2614 includes an input packet queue 2902, DSP 2904, and an output packet queue 2906. Signal factory module 2804 may generate the input packet queue 2902, DSP 2904, and output packet queue 2906 based on signal processing specifications from signal configuration module 2802. The input packet queue 2902 may store one or more packets from packet distributor 2610 for processing by DSP 2904. The input packet queue 2902 may be a queue data structure that stores items in the order in which they are inserted. For example, the first item inserted into the input packet queue 2902 is the first item removed from the input packet queue 2902. In other words, the input packet queue 2902 may be a first-in, first-out (FIFO) data structure. As will be understood by those of ordinary skill in the art, the input packet queue 2902 may be implemented using a linked list, an array, or various other data structures.

[0302] The output packet queue 2906 may store one or more packets processed by DSP 2904. The output packet queue 2906 may be a queue data structure that stores items in the order in which they are inserted. For example, the first item inserted into the output packet queue 2906 is the first item removed from the output packet queue 2906. In other words, the output packet queue 2906 may be a first-in, first-out (FIFO) data structure. As will be understood by those of ordinary skill in the art, the output packet queue 2906 may be implemented using a linked list, an array, or various other data structures.

[0303] Signal factory module 2804 may generate DSP 2904 based on signal processing specifications from signal configuration module 2802. Specifically, signal factory module 2804 may request DSP factory module 2808 to generate DSP 2904. DSP factory module 2808 may generate DSP 2904 based on the digital signal processing functions specified in the signal processing specifications. DSP factory module 2808 may also generate DSP 2904 based on one or more signal processing parameters associated with the digital processing functions. For example, DSP factory module 2808 may generate DSP 2904 based on a low-pass filter function and a cut-off frequency specified in the signal processing specifications.

[0304] The DSP 2904 is a software module that can be executed by a (plurality of) processors such as the processor 8504 in Figure 85 . The DSP 2904 can apply digital processing functions to one or more packets and thus to one or more signal samples. As will be understood by those of ordinary skill in the art, a digital processing function can be a mathematical algorithm that takes one or more signal samples as input, processes them, and produces one or more potentially modified signal samples as output. The digital processing function can be implemented using one or more mathematical operations such as the fast Fourier transform. As will be understood by those of ordinary skill in the art, the DSP 2904 can apply various types of digital processing functions. For example, as will be understood by those of ordinary skill in the art, the DSP 2904 can apply low-pass filters, high-pass filters, band-pass filters, band-stop filters, notch filters, comb filters, all-pass filters, or various other filters.

[0305] The DSP 2904 can also apply digital processing functions that analyze a signal for various characteristics. For example, the DSP2904 can apply digital processing functions that determine whether there are noise anomalies or signal patterns in the signal. The DSP 2904 can also analyze a signal by detecting repeating patterns in the signal. This can involve comparing the signal to previously detected (or recorded or synthesized) signal patterns.

[0306] For example, the DSP 2904 can determine late potentials in a signal. Specifically, the DSP 2904 can determine noise anomalies and then determine subsequent noise anomalies that occur simultaneously with a matched heartbeat. Each subsequent noise anomaly at the same relative position may increase the confidence level at which the late potential lies. The display module 2618 can then display an indication of the late potential.

[0307] For example, the determination of late potentials by the DSP 2904 can be used in a pulmonary vein potential filter. Specifically, the combination of a late p-wave dispersion electrogram and filtering for rapid conduction can be used to identify pulmonary vein potentials that are discrete from adjacent atria and other structures. These signals can serve as endpoints for ablation ports to rapidly identify delays and rejections. The system can be used for other thoracic veins, late electrocardiograms above the semilunar valves, late potentials in patients with cardiomyopathy, and the coronary sinus and the vein of Marshall.

[0308] Similarly, the DSP 2904 can determine early activations in a signal. Specifically, the DSP 2904 can determine the earliest sharp intracardiac signal above a selected threshold that occurs within a predetermined segment before a reference point of a matched heartbeat. The display module 2618 can then display an indication of the early activation.

[0309] The DSP 2904 can use relevant functions to detect patterns in signals. For example, the DSP 2904 can use the mean absolute deviation algorithm to detect patterns. As those of ordinary skill in the art will understand, the DSP 2904 can use various other types of pattern matching algorithms.

[0310] The DSP 2904 can detect patterns (also known as signal patterns) based on various signal characteristics. For example, the DSP 2904 can detect patterns based on shape, amplitude, and time characteristics. As those of ordinary skill in the art will understand, the DSP 2904 can detect patterns based on various other types of signal characteristics.

[0311] The DSP 2904 can also include one or more signal processing parameters. The signal processing parameters can control how the DSP 2904 applies its digital processing functions. For example, the DSP 2904 can include one or more signal processing parameters that specify a threshold frequency or amplitude for filtering. The DSP 2904 can also include one or more signal processing parameters that specify the signal patterns or noise thresholds to be detected.

[0312] The DSP 2904 can apply its digital processing functions to the packets in the input packet queue 2902. In some embodiments, the DSP 2904 can scan the input packet queue 2902 to look for new packets to be processed. In some other embodiments, the DSP 2904 can be notified that there are new packets available in the input packet queue 2902. The DSP 2904 can then retrieve the packets from the input packet queue 2902.

[0313] The DSP 2904 can apply its digital processing functions to the retrieved packets. In other words, the DSP 2904 can apply its digital processing functions to one or more signal samples in the packets. The DSP 2904 can control how to apply its digital processing functions to one or more signal samples in the packets based on its one or more signal processing parameters. After processing the packets, the DSP 2904 can store the packets in the output packet queue 2906 for display by the output module 2616.

[0314] As described below, each DSP 2904 can have an associated processing delay. The processing delay can represent the amount of time it takes to complete the processing of a packet through the digital processing functions of the DSP 2904. The processing delay can vary between different DSP 2904s. As described below, this variation in the processing delay between different DSP 2904s can cause the DSP 2904s to output packets for display at different times.

[0315] After the signal factory module 2804 finishes generating the input packet queue 2902, the DSP 2904, and the output packet queue 2906, the signal factory module 2804 can connect the output of the input packet queue 2902 to the input of the DSP 2904 and connect the output of the DSP 2904 to the input of the output packet queue 2906. Once the signal factory module 2804 finishes the connection, the DSP 2904 can receive packets representing the unprocessed base signal from the input packet queue 2902. The DSP 2904 can then use its digital processing functions to process the packets. The DSP 2904 can output the processed packets to the output packet queue 2906. The signal factory module 2804 can further configure the input packet queue 2902 to receive packets from the base signal specified in the signal processing specification.

[0316] Once the signal module 2614 is created, the signal factory module 2804 can add it to the global signal table 2612. As described above, the global signal table 2612 can be an array of a fixed size. Each element of the array can be associated with a given base signal. In addition, each element of the array itself can be an array of a fixed size. Each element of the sub-array can be associated with a given signal module 2614.

[0317] In some embodiments, the signal factory module 2804 can add the created signal module 2614 to the global signal table 2612 by adding a new array element to each sub-array associated with the base signal. The new array element can correspond to the newly created signal module 2614. For example, if the global signal table 2612 previously contained ten (10) signal modules 2614, then, for example, the newly created signal module 2614 can be added at the element number 11 in each sub-array.

[0318] Once the created signal module 2614 is added to the global signal table 2612, a user (e.g., a physician) can assign the created signal module 2614 to a given base signal. In some embodiments, the global signal table 2612 can indicate whether the created signal module 2614 is assigned to a given base signal by storing a "0" or "1" at the corresponding element in the sub-array associated with the created signal module 2614. In some other embodiments, the global signal table 2612 can indicate whether the created signal module 2614 is assigned to a given base signal by storing a reference to the created signal module 2614 at the corresponding element in the sub-array.

[0319] The signal factory module 2804 can generate multiple signal modules 2614. Each signal module 2614 can have a DSP 2904 that applies different digital signal processing functions. As a result, each signal module 2614 can generate different processed versions of the same base signal. This can enable a user to analyze the same base signal in multiple ways. The user may also wish to analyze the time-aligned outputs of multiple versions of the same base signal. This can enable the user to compare different versions of the same signal at the same or different time points.

[0320] As described above, conventional digital signal processing systems generally cannot synchronize the display of multiple processed signals in near real-time. This may be because different digital signal processing functions have different processing delays. For example, the current EP system can apply two different digital signal processing functions to the same base signal. However, a medical team may wish to synchronize the display of the two processed signals. For example, the medical team may wish to compare an IC signal and an ECG signal at the same time point to determine a clinical diagnosis. In other words, the medical team may wish to align the display of the first processed signal with the display of the second processed signal in near real-time. However, this may not be possible if the two different digital signal processing functions have different processing delays. This is because one of the digital signal processing functions can complete the processing of the base signal faster than the other digital signal processing function. As a result, one processed signal can be displayed before the other processed signal.

[0321] The processing delay associated with a digital processing function may be related to the complexity of the function. For example, a digital processing function that performs low-pass filtering on a signal can have less computational load and use the least amount of memory. As a result, such a digital processing function can have a short processing delay. In contrast, another digital processing function can analyze a signal for specific signal characteristics. This type of digital processing function may require more computational load and use more memory and thus have a longer processing delay.

[0322] Due to different processing delays, one processed signal can be displayed before the other processed signal. Over time, this synchronization gap can become larger. For example, in the case where multiple signals are processed and displayed in near real-time, this synchronization gap can be larger. This is because the difference in processing delays between two digital signal processing functions can propagate to each new signal sample.

[0323] For example, for a given base signal, the first digital signal processing function may have a processing delay of 10 milliseconds. For the same base signal, the second digital signal processing function may have a processing delay of 20 milliseconds. The first digital signal processing function may complete the processing of the first signal sample of the base signal at 10 milliseconds, while the second digital signal processing function may complete the processing of the same first signal sample at 20 milliseconds. Thus, the first signal sample processed by the first digital signal processing function may be displayed at 10 milliseconds, and the first signal sample processed by the second digital signal processing function may be displayed at 20 milliseconds. In other words, the first signal sample processed by the first digital signal processing function may be displayed 10 milliseconds before the first signal sample processed by the second digital signal processing function.

[0324] When the second signal sample is processed, this synchronization gap may increase. For example, the second signal sample may be received at time 10 milliseconds for processing by the first digital signal processing function, and the second signal sample may be received at time 20 milliseconds for processing by the second digital signal processing function. As a result, the second signal sample processed by the first digital signal processing function may be displayed at 20 milliseconds, and the second signal sample processed by the second digital signal processing function may be displayed at 40 milliseconds. In other words, the synchronization gap for the second signal sample may increase by 10 milliseconds; initially, the synchronization gap is 10 milliseconds, and then the synchronization gap is 20 milliseconds.

[0325] In the case where digital signal processing is executed on a non-real-time operating system, this synchronization gap may increase. Unlike a non-real-time operating system, a real-time operating system is a time-limited system with well-defined fixed time constraints. A real-time operating system can guarantee that an application task will be accepted and completed within a certain amount of time. In other words, a real-time operating system can provide a level of consistency regarding the amount of time required to complete a task.

[0326] Conversely, a non-real-time operating system cannot provide any guarantee that an application task will be completed within a certain amount of time. For example, a non-real-time operating system may not be able to guarantee that the execution of a specific digital signal processing function will be completed within a certain amount of time. As a result, there may be a high degree of variability regarding the amount of time taken to complete a task. This can be a problem when attempting to synchronize the processing and display of multiple processed signals. This is because the processing delay associated with a digital processing function may vary with each execution. For example, a digital signal processing function can typically complete execution within 10 milliseconds. However, on a non-real-time operating system, there may be no guarantee that the digital signal processing function will complete execution after 10 milliseconds. For example, the digital signal processing function can complete execution within 30 milliseconds. This variability in processing delay may further increase the synchronization gap.

[0327] In some embodiments, the input packet queue 2902 and the output packet queue 2906 of the signal module 2614 are used, signal samples are stored in packets together with associated tags, and the processing delays among one or more DSPs 2904 are equalized, and the display synchronization problem is solved in a multi-faceted manner.

[0328] The input packet queue 2902 and the output packet queue 2906 can solve the display synchronization problem in three ways. First, they ensure that packets are processed and displayed sequentially and thus ensure that signal samples are processed and displayed sequentially. Second, the output packet queue 2906 can synchronize the display of packets at the same point in time by blocking the processing of more packets until the existing packets are consumed by the output module 2616. In other words, the output packet queue 2906 can provide a feedback mechanism to the DSP 2904 that indicates when the DSP 2904 can stop processing more packets. Finally, the input packet queue 2902 ensures that the DSP 2904 has packets to process. For example, when the input packet queue 2902 is empty, the DSP 2904 can stop processing more packets. In other words, the input packet queue 2902 can provide a feedback mechanism to the DSP 2904 to indicate that there are no more packets to process.

[0329] The DSP delay equalizer 2806 can also solve the display synchronization problem by equalizing the processing delays across one or more DSPs 2904. As described above, different digital signal processing functions have different processing delays, which may cause the processed signals to be displayed asynchronously. Therefore, if the configuration path module 2620 generates multiple signal modules 2614, each signal module including a DSP 2904 with different digital signal processing functions, each signal module 2614 can complete the processing of packets with different processing delays. Due to these different processing delays, the processed signals may be displayed asynchronously by the output module 2616. The DSP delay equalizer 2806 can solve this problem by equalizing the processing delays across the generated signal modules 2614.

[0330] In some embodiments, after the configuration path module 2620 generates one or more signal modules 2614, the signal factory module 2804 may use the DSP delay equalizer 2806 to equalize the processing delays of each of the generated signal modules 2614 such that each signal module 2614 outputs the processed packets to its output packet queue 2906 simultaneously. For example, the DSP delay equalizer 2806 may determine the relative processing delays between two signal modules 2614. The DSP delay equalizer 2806 may then use the determined relative delays to configure the DSP 2904 in the first signal module 2614 to complete the processing of the packets at approximately the same time as the DSP 2904 in the second signal module 2614 is designed to complete the processing of the packets.

[0331] In some embodiments, the DSP delay equalizer 2806 may perform equalization by scanning each of the generated signal modules 2614. During the scan, the DSP delay equalizer 2806 may request the processing delays associated with the DSP 2904 in each signal module 2614. The DSP delay equalizer 2806 may use the application programming interface (API) of each signal module 2614 to request the processing delays. In response, each signal module 2614 may return its associated processing delay.

[0332] The signal module 2614 may store the processing delay associated with its DSP 2904. The processing delay may be a predefined value specified in the signal processing specification used to generate the DSP 2904. In some other embodiments, the DSP factory module 2808 may calculate the processing delay of the DSP 2904 based on various factors including the digital processing functions used by the DSP 2904, the selected signal processing parameters, and hardware characteristics such as the speed of the processor (such as processor 5004), the size of the memory, and the I / O latency.

[0333] After determining the processing delays associated with the DSP 2904 in each signal module 2614, the DSP delay equalizer 2806 may determine the maximum processing delay among the signal modules 2614. For example, the DSP delay equalizer 2806 may determine that the signal module 2614-1 has a processing delay of 10 milliseconds, the signal module 2614-2 has a processing delay of 20 milliseconds, and the signal module 2614-N has a processing delay of 50 milliseconds. Based on this, the DSP delay equalizer 2806 may determine that the maximum processing delay among the signal modules 2614 is 50 milliseconds.

[0334] After determining the maximum processing latency, the DSP latency equalizer 2806 can configure the DSP 2904 of each signal module 2614 to have the maximum processing latency. For example, the DSP latency equalizer 2806 can use an API to set the processing latency of the DSP 2904 of each signal module 2614. In response, each DSP 2904 can be designed to process packets using its digital processing capabilities and output the processed packets to its associated output packet queue 2906 at the end of the maximum processing latency. For example, in some embodiments, if the DSP 2904 finishes processing a packet before the end of the maximum processing latency, it can block its output to its output packet queue 2906. In some other embodiments, the DSP 2904 can insert idle computing cycles during the processing of a packet. As will be understood by those of ordinary skill in the art, various other methods can be used to cause the DSP 2904 to output the processed packets to its output packet queue 2906 at the end of the maximum processing latency.

[0335] Packetization and assigning tags to packets can solve the display synchronization problem. As described above, each generated packet can include a fixed number of signal samples. Each packet can also contain a tag that indicates the relative position of the packet among the packet sequence. To synchronize the display of multiple signals, the display module 2618 can display packets with the same tag. In other words, the display module 2618 can use the tag to synchronize its display.

[0336] As Figure 26 shown, the output module 2616 can include one or more display modules 2618-1 to 2618-N and a review module 2624. The review module 2624 can be a software module executable by a processor (such as the processor 5004). The review module 2624 can display one or more signals processed by one or more signal modules 2614 at a previous time point. Each display module 2618 can be a software module executable by a processor (such as the processor 5004). Each display module 2618 can display one or more real-time signals processed by one or more signal modules 2614. Each display module 2618 can operate independently of the other display modules 2618. In other words, each display module 2618 can simultaneously display one or more signals on one or more display devices (such as Figure 85 the input / output device 8503 in). In some embodiments, each display module 2618 can display its associated one or more signals in a specific GUI window on a given display device.

[0337] Each display module 2618 can display one or more signals. Each display module 2618 can receive packets from an associated output packet queue 2906 in a signal module 2614 in the global signal table 2612. The display module 2618 can display a signal based on the packet.

[0338] Figure 30 is a block diagram of a display module 2618 according to some embodiments. The display module 2618 includes a local signal table 3002, a packet index 3004, and display settings 3006. Refer to Figure 29 for discussion Figure 30 .

[0339] As discussed, the display module 2618 can receive packets from an associated output packet queue 2906 in the signal module 2614. To receive packets, the display module 2618 can maintain a reference to the associated output packet queue 2906 in the signal module 2614. When the display module 2618 is designed to display multiple signals, the display module 2618 can keep references to the output packet queues 2906 associated with each signal being displayed. The display module 2618 can store the references in its local signal table 3002. The local signal table 3002 can contain a list of one or more references to the output packet queues 2906 associated with each signal being displayed. When the associated signal module 2614 is no longer active, the display module 2618 can remove the references from its local signal table 3002.

[0340] In some embodiments, the display module 2618 can continuously scan its one or more associated output packet queues 2906 for new packets. In the case where the display module 2618 is associated with a single output packet queue 2906, whenever the display module 2618 detects a new packet, it can display the packet on the display device. However, in the case where the display module 2618 is associated with multiple output packet queues 2906, the display module 2618 may not immediately display a new packet detected in a particular output packet queue 2906. This is because the display module 2618 may be designed to synchronize the display of multiple signals.

[0341] In some embodiments, where a given display module 2618 is designed to synchronize the display of multiple signals, the display module 2618 may detect new packets in a particular output packet queue 2906. The display module 2618 may then determine a tag associated with the new packet. The display module 2618 may use the determined tag to synchronize the display of new packets from other output packet queues 2906. For example, the display module 2618 may wait to display any packets to a display device until a new packet with the same determined tag is detected at other output packets. Once the display module 2618 detects a new packet with the same tag at its other associated output packet queues 2906, the display module 2618 may display the packets from its associated output packet queues 2906 simultaneously. The display module 2618 may display the multiple signals in a non-overlapping stackable format. Since the display module 2618 may display packets with the same tag, the resulting displayed signals may be time-aligned.

[0342] As previously described, the type of preprocessing that the packetizer 2606 may perform on any of the multiple signals may be related to the type of signal. In some embodiments, the selection of preprocessing of a signal by the packetizer 2606 may be automatic. This allows for the automatic deployment of an appropriate plurality of filters with minimal filtering based on adjacent signals and the ratio of far-field to near-field signals, such as to minimize noise and target signals of interest. As would be understood by one of ordinary skill in the art, for example, this type of automation may effectively minimize the process time for medium and small batch operators. When new packets are detected from the automated process, the display module 2618 may similarly synchronize and display the multiple signals.

[0343] The display module 2618 may maintain the current active tag to be displayed in the packet index 3004. When a new packet is detected in a particular output packet queue 2906, the display module 2618 may determine the tag of the new packet. The display module 2618 may then set the packet index 3004 to the determined tag.

[0344] In some embodiments, a high-frequency rapid conduction signal filter may be applied to multiple electrodes, such as using a basket or balloon catheter, to identify conduction tissue (such as distal Purkinje and circumferential rapid conduction tissue). Such circumferential tissue may be rapidly targeted for ablation due to the prominence of its signals. Based on the dynamic tagging of packets from the packetizer 2606, the display module 2618 may continue to visualize the signals as a reference point for guiding the movement of an ablation catheter and may be used to terminate local energy delivery when the disease-causing signal of interest decays during ablation. As shown in this example, the preprocessing and continued processing of the system may allow a doctor to continue to see signals even during ablation.

[0345] The display module 2618 may include display settings 3006. The display settings 3006 may include one or more parameters that control how the display module 2618 displays one or more of its associated signals. The display settings 3006 may specify colors to display one or more of the associated signals. The display settings 3006 may specify a view format (such as a waterfall view, a dynamic view, or a trigger view as described below). The display settings 3006 may specify a sweep speed for one or more signals. The display settings 3006 may include various other types of display settings as would be understood by one of ordinary skill in the art. As described below, the display settings 3006 may be designed by a user.

[0346] The review module 2624 may display one or more signals processed by one or more signal modules 2614 at a previous time point. This may enable a user (e.g., a physician) to analyze one or more signals long after they have been generated and displayed. In some embodiments, the review module 2624 may capture a display of one or more signals in the display module 2618 in response to a command. For example, a user may click a button in the GUI to capture the current display of the display module 2618. The captured display may include a visualization of a previous display of one or more signals at the time of capture. In some embodiments, the display module 2618 may pause its display of new packets in response to the capture of its current display.

[0347] In some embodiments, the review module 2624 may capture a display of one or more signals in the display module 2618 by determining a capture configuration for the display module 2618. The capture configuration may include one or more active signal modules 2614 for the display module 2618, a capture time, a selected view for the display module 2618, a color scheme for one or more displayed signals, and various other settings as would be understood by one of ordinary skill in the art. After determining the capture configuration, the review module 2624 may apply the capture configuration to previously stored signal samples.

[0348] As described above, the input module 2604 may store one or more signal samples for each base signal in a storage device for later analysis by the review module 2624. The review module 2624 may capture the display of one or more signals in the display module 2618 by applying the determined capture configuration to the stored signal samples. Specifically, the review module 2624 may select the stored signal samples at the capture time in the capture configuration. The review module 2624 may then process the selected signal samples using the active signal module 2614 in the capture configuration. The review module 2624 may also display the selected signal samples using the selected view, color scheme, and various other settings in the capture configuration. Thus, the review module 2624 may enable a user to review one or more processed signals for the display module 2618 at a specific point in time and subject to a specific configuration.

[0349] In some embodiments, the review module 2624 may enable a user to change the review interval for the display module 2618. For example, the user may "rewind" to a different point in the past (e.g., 5 minutes ago). After the capture time is changed, the review module 2624 may display one or more processed signals for the display module 2618 at the new review time index.

[0350] Figure 31 is a block diagram of the monitoring module 2622 according to some embodiments. The monitoring module 2622 includes a queue monitor 3102 and a reporting module 3104. The queue monitor 3102 and the reporting module 3104 may be software modules executable by a processor such as the processor 5004.

[0351] The monitoring module 2622 may be continuously executed while the signal path module 2602 is being executed. For example, the monitoring module 2622 may be executed by the processor as a separate execution thread. The monitoring module 2622 may determine whether there are any problems in the execution of the signal path module 2602.

[0352] In some embodiments, the queue monitor 3102 can periodically scan the queues in the signal path module 2602. For example, the queue monitor 3102 can scan the queue 2702 in the queuing module 2608. The queue monitor 3102 can also scan the input packet queue 2902 and the output packet queue 2906 in one or more signal modules 2614. The queue monitor 3102 can determine the state of each queue during the scan. For example, the queue monitor 3102 can determine the length of each queue during the scan. In some embodiments, if the queue monitor 3102 determines that a queue has an error state, the queue monitor 3102 can request the reporting module 3104 to display the error state on the display device. For example, the queue monitor 3102 can determine that the length of a queue is continuously increasing. In response, the queue monitor 3102 can request the reporting module 3104 to display an error indicating that a particular queue has an incorrect length.

[0353] Figure 32 Illustrates an example adjustment of the sweep speed of the display module 2618 according to some embodiments. Figure 32 Includes a real-time viewing area 3202 and a sweep speed 3204. Refer to Figure 26 for discussion Figure 32 .

[0354] The real-time viewing area 3202 can contain a near real-time display of the display module 2618. In Figure 32 , the real-time viewing area 3202 includes a near real-time display of fourteen (14) different signals (e.g., processed signals or base signals).

[0355] The sweep speed 3204 can be a GUI widget that allows the user to select the sweep speed for the real-time viewing area 3202. The sweep speed can represent the time scale of one or more signals displayed in the real-time viewing area 3202. The range of the sweep speed can be from 10 millimeters per second to 1000 millimeters per second. In Figure 32 , the sweep speed 3204 is shown as being selected to be 50 mm per second. As will be understood by those of ordinary skill in the art, the selection of the sweep speed can affect the level of detail displayed and can therefore be set based on the size of the display screen.

[0356] Figure 33 Illustrates signal management for the display module 2618 according to some embodiments. Figure 33 Includes a signal management window 3302. Refer to Figure 26 for discussion Figure 33 .

[0357] The signal management window 3302 may include available signals 3304 and signal settings 3306. The available signals 3304 may include one or more signals that can be selected by the display module 2618 for display. For example, in Figure 33 the available signals 3304 include fourteen (14) signals that can be selected by the display module 2618 for display. The available signals 3304 may display various information about each signal. For example, the available signals 3304 may display the name of the signal and whether the signal is processed by a particular signal module 2614.

[0358] The signal settings 3306 may display various settings that can be set for each signal. For example, in Figure 33 the signal settings 3306 enable the user to change the name of each signal or assign a specific color to each signal. These settings may be stored in the display settings 3006 in the display module 2618. The signal settings 3306 may also enable the user to change various processing parameters associated with each signal. These processing parameters may be stored in one or more signal processing parameters of the DSP 2904 of the signal module 2614 associated with a given signal.

[0359] Figure 34 Illustrated is an example adjustment of the scaling and clip factors for the display module 2618 according to some embodiments. Figure 34 Includes a real-time viewing area 3402 and a display settings window 3404. Refer to Figure 26 for discussion Figure 34 .

[0360] The real-time viewing area 3402 may include a near real-time display of the display module 2618. In Figure 34 the real-time viewing area 3402 includes a near real-time display of fourteen (14) different signals (e.g., processed signals or base signals).

[0361] The display settings window 3404 may include a scaling factor 3406 and a clip factor 3408. The scaling factor 3406 may be a GUI widget for selecting a scaling factor for a particular signal in the real-time viewing area 3402. The selected scaling factor may increase or decrease the size of a particular signal. For example, the scaling factor 3406 may increase the size of a particular signal from 0.02 times to 40 times.

[0362] The clipping factor 3408 can be a GUI widget, allowing a user to select a clipping factor for a particular signal in the real-time viewing area 3402. The selected clipping factor can control the amount by which a signal overshoots the display screen. For example, a user can adjust the clipping factor to reduce the actual area in which a particular signal is displayed so that if the particular signal is large, it does not extend beyond the entire display screen and thus does not render parts unviewable.

[0363] Figure 35 Illustrated is mode search management for a display module 2618 according to some embodiments. Figure 35 Includes a real-time viewing area 3502 and a mode search window 3504. Refer Figure 26 to discuss Figure 35 .

[0364] The real-time viewing area 3502 can contain a near real-time display of the display module 2618. The mode search window 3504 can be a GUI window that enables a user to load or specify a signal pattern to be searched. For example, in Figure 35 , a user can create or load a search for late potentials or early activations in one or more signals. A user can also specify various parameters for the search, such as, a search interval, a heartbeat detection confidence percentage, a detection confidence percentage, or other parameters that would be understood by one of ordinary skill in the art. The signal pattern to be searched can be stored in one or more signal processing parameters of the DSP 2904 of the signal module 2614 associated with a given signal.

[0365] Figure 36 Illustrated is a late potential search result highlighted in the display of the display module 2618 according to some embodiments. Figure 36 Includes a real-time viewing area 3602. Refer Figure 26 to discuss Figure 36 .

[0366] The real-time viewing area 3602 can contain a near real-time display of the display module 2618 subject to a late potential search. As Figure 35 shown, a user can create or load a search for late potentials. Once the search is initiated, the real-time viewing area 3602 can display late potentials found in one or more signals. The real-time viewing area 3602 can display the late potentials found as well as a detection confidence percentage. For example, in Figure 36 , the late potential 3604 found is displayed with a detection confidence of 83%. The real-time viewing area 3602 can also display the total count of the late potentials found.

[0367] Figure 37A Illustrated is a display module 3618 configured for a waterfall view according to some embodiments.Figure 37A includes a real-time viewing area 3702. Refer to Figure 26 for discussion Figure 37A .

[0368] The real-time viewing area 3702 may include a near real-time display of the display module 2618. The real-time viewing area 3702 may use a waterfall view to display the near real-time display of the display module 2618. In the waterfall view, signals may be displayed side by side and stacked vertically with each other when pattern matching. Specifically, a user may select a pattern (e.g., a specific heartbeat pattern) to match the first signal. When the pattern is detected in the first signal, the display module 2618 may display a portion of the first signal that matches the pattern near the corresponding portion of the second signal (e.g., an IC signal). The user may select the size of the portion of the first signal to be displayed and the size of the portion of the second signal. For example, the user may use a time interval (e.g., 150 milliseconds) to select the size of the portion of the first signal.

[0369] In the waterfall view, whenever the pattern is detected in the first signal, the display module 2618 may vertically display each new portion of the first signal that matches the pattern and the corresponding portion of the second signal. In other words, in the waterfall view, the display module 2618 may display the signals along a vertical time axis.

[0370] In Figure 37A , the real-time viewing area 3702 illustrates a near real-time display of two different signals (e.g., V2[P1] and AB1.d) in the waterfall view. In Figure 37A , the signals V2[P1] and AB1.d are displayed side by side and stacked with each other. For example, at about 10 seconds, the signal portion 3704 is displayed side by side with the signal portion 3706. The signal portion 3704 may represent a portion of the signal V2[P1] that matches a given pattern (e.g., heartbeat P1, lead V2) at about 10 seconds. The signal portion 3706 may represent the corresponding portion of the signal AB1.d when the given pattern matches the signal V2[P1].

[0371] A user (e.g., a physician) may find the waterfall view advantageous. First, the waterfall view enables the user to compare the corresponding portions of two signals side by side. Second, since the signals are stacked vertically, the waterfall view may display the signals on the display screen for a longer time. In contrast, when the signals are displayed from left to right, it is usually difficult for the user to analyze the signals because they are no longer displayed on the display screen after a short time.

[0372] Figure 37B Illustrates the correspondence between signals in a conventional display module 2618 and a display module 2618 configured for a waterfall view according to some embodiments.Figure 37B including a real-time viewing area 3708 and a waterfall view 3710. Refer to Figure 26 for discussion Figure 37B .

[0373] In Figure 37B , the real-time viewing area 3708 illustrates a near real-time display of two different signals (e.g., V2[P1] and AB1.d). The waterfall view 3710 illustrates a near real-time display of the same two signals, except that the signals V2[P1] and AB1.d are displayed side by side to appear stacked on top of each other. In the waterfall view 3710, each time a signal pattern in the signal is detected, the display module 2618 can vertically display the signal portion that matches the signal pattern and the corresponding portion of the second signal.

[0374] For example, in Figure 37B , the signal portion 3712 of the signal V2[P1] contains the signal pattern. The corresponding signal portion 3714 of the signal AB1.d corresponds to the signal portion 3712 at the time of detection. In Figure 37B , each time a signal pattern is detected in the signal V2[P1], the waterfall view 3710 displays the signal portion 3712 and the corresponding signal portion 3714 side by side (e.g., together). In Figure 37B , the waterfall view 3710 displays a portion of the signal V2[P1] that matches the signal pattern from oldest to newest and the corresponding portion in the signal AB1.d. In other words, in Figure 37B , the waterfall view 3710 scrolls up over time to display heartbeats, with the oldest heartbeat at the top and the newest heartbeat at the bottom. As will be understood by those of ordinary skill in the art, the waterfall view 3710 can display heartbeats in various other ways, such as with the newest heartbeat at the top and the oldest heartbeat at the bottom.

[0375] Figure 37C illustrates a display module 2618 configured as a dynamic view according to some embodiments. Figure 37C including a real-time viewing area 3716. Refer to Figure 26 for discussion Figure 37C .

[0376] The real-time viewing area 3716 may include a near-real-time display of the display module 2618. The real-time viewing area 3716 may use a dynamic view to display the near-real-time display of the display module 2618. In the dynamic view, the user may select a trigger for a signal (e.g., related to a stored heartbeat). The user may select a trigger from a variety of trigger types. The trigger type may be a signal characteristic of interest associated with a secondary event of interest. When the trigger occurs, the display module 2618 may dynamically adjust the offset of the signal such that it is fixed to a baseline. This may prevent the signal from advancing and leaving the display screen. For example, this is typically important in a clinical setting where, for example, the height of a signal peak may indicate a particular type of injury and the signal plateau may indicate the effectiveness of an ablation lesion.

[0377] In Figure 37C , the real-time viewing area 3716 illustrates a reference heartbeat measured for a unipolar signal (e.g., Uni1) at a reference time (e.g., reference time 3724). For example, this may occur during ablation. In Figure 37C , since the signal Uni1 is captured at the reference time 3724, signal 3718 may be the initial heartbeat, signal 3720 may be the current heartbeat, and signal 3722 may be the recorded maximum heartbeat. As discussed, in the dynamic view, the user may specify a reference position for determining the signal point that is fixed to the baseline. In Figure 37C , this point is located at the fixed position 3726 (e.g., 0.0 mV) of the signal Uni1 on the screen. This may cause the signal Uni1 to shift such that it is fixed at the fixed position 3726.

[0378] Figure 37D Illustrates a display module 2618 configured to trigger a view according to some embodiments. Figure 37D Includes a real-time viewing area 3728 and a trigger view 3730. Refer to Figure 26 for discussion Figure 37D .

[0379] The real-time viewing area 3728 may include a near-real-time display of the display module 2618. In Figure 37DIn [the figure], the trigger view 3730 illustrates the display of the real-time viewing area 3728 using the trigger view. In the trigger view 3730, the user can select a first signal (e.g., the pacing signal 3732) that triggers the display of other signals (e.g., the II signal 3734, the Uni Dist signal 3736, and the Uni Prox signal 3738). The user can select a specific trigger for the first signal. The user can select a trigger from multiple trigger types. The trigger type can be a signal characteristic of interest associated with a secondary event of interest. For example, the user can select a specific voltage (e.g., 60 millivolts) for the first signal. Those of ordinary skill in the art will understand that other signal characteristics can be selected. When the trigger occurs, the display module 2618 can display the specified one or more signals that are temporally synchronized and vertically stacked in the display. The user (e.g., a physician) may find the trigger view advantageous. This is because it can make it easier for the user to view events that occur relative to an event (e.g., the start of the pacing signal 3732).

[0380] In the trigger view 3730, the user can also specify the time after the trigger occurs when the data is fixed to the baseline. For example, in Figure 37D [the figure], the user sets the time to approximately 70 milliseconds after the trigger occurs. In Figure 37D [the figure], in response to the user setting the time to approximately 70 ms after the trigger occurs, the Uni Dist signal 3736 and the Uni Prox signal 3738 are fixed and always remain in the trigger view 3730. In contrast, in Figure 37D [the figure], the UniDist signal 3736 and the Uni Prox signal 3738 are not seen in the real-time viewing area 3728 because they are not fixed to the baseline.

[0381] Figure 38 Illustrates signal capture in the display of the display module 2618 configured as a review window according to some embodiments. Figure 38 Includes a real-time viewing area 3802 and a review window 3804. Refer to Figure 26 for discussion Figure 38 .

[0382] The real-time viewing area 3802 can contain a nearly real-time display of the display module 2618. The review window 3804 can contain a previous display shown in the real-time viewing area 3802. To capture the display of the real-time viewing area 3802, the user can submit a capture request. For example, in Figure 38In [the system], the user can click on the review button 3806. In response, the review module 2624 can determine the capture configuration of the display module 2618. The capture configuration can include one or more active signal modules 2614 for the display module 2618, the capture time, the selected view of the display module 2618, the color scheme for one or more of the displayed signals, and various other settings that would be understood by a person of ordinary skill in the art. After determining the capture configuration, the review module 2624 can apply the capture configuration to previously stored signal samples and display the output in the review window 3802.

[0383] Figure 39 Illustrated is an amplitude measurement performed in a display of the display module 2618 configured as a review window, according to some embodiments. Figure 39 Includes a real-time viewing area 3902 and a review window 3904. Refer to Figure 26 for discussion Figure 39 .

[0384] The real-time viewing area 3902 can contain a near-real-time display of the display module 2618. The review window 3904 can contain a previously captured display shown in the real-time viewing area 3802. The user can use vertical and horizontal calipers to analyze the previously captured output in the review window 3904. The horizontal caliper can be a GUI selection widget. The user can use the horizontal caliper to measure the amplitude of a specific signal in millivolts (mV). For example, as Figure 39 shown, the user can click on the top and bottom of the V1 signal to generate two horizontal lines (e.g., caliper lines 3908 and 3910). The user can then hover the cursor along the V1 signal to display the amplitude measured at a specific time point (e.g., measurement value 3906). Similarly, the vertical caliper can also be a GUI selection widget. The user can use the vertical caliper to measure time (in milliseconds) or beats per minute (BPM). As Figure 65 shown, the user can click at the left and right points along the signal to generate two vertical lines and display the time or beats per minute measured between the two vertical lines. For example, as shown in the pop-up box 6506, the time between the vertical calipers 6502 and 6504 is 464 milliseconds or 129 BPM.

[0385] For embodiments related to ECG and IC signal visualization, the following method descriptions for near-real-time processing and display of multiple signals are provided. A person of ordinary skill in the art will understand that these methods can be equivalently applied to the visualization of other small physiological signals.

[0386] Figure 40 Is a flowchart of a method 4000 for near-real-time processing and display of multiple signals, according to some embodiments.

[0387] The method 4000 will be described with reference to Figure 26 However, the method 4000 is not limited to this exemplary embodiment.

[0388] In 4002, the configuration path module 2620 configures one or more signal modules 2614. 4002 can be performed by Figure 41 the method 4100 in

[0389] In 4004, the input module 2604 receives one or more signal samples for one or more signals. For example, the input module 2604 can receive one or more signal samples for an IC signal and one or more signal samples for an ECG signal. 4004 can be performed by Figure 44 the method 4400 in

[0390] In 4006, the input module 2604 distributes one or more signal samples to the grouper 2606.

[0391] In 4008, the grouper 2606 converts one or more signal samples into one or more packets. 4008 can be performed by Figure 45 the method 4500 in

[0392] In 4010, the grouper 2606 distributes one or more packets to the queuing module 2608. 4010 can be performed by Figure 46 the method 4600 in

[0393] In 4012, the packet distributor 2610 distributes packets from the queuing module 2608 to the signal module 2614 associated with the packet. 4012 can be performed by Figure 47 the method 4700 in

[0394] In 4014, the signal module 2614 of 4012 processes the packet using the DSP 2904. 4014 can be performed by Figure 48 the method 4800 in

[0395] In 4016, the display module 2618 associated with the signal module 2614 of 4012 displays the processed packet on the display screen. 4016 can be performed by Figure 49 the method 4900 in

[0396] Figure 41 is a flowchart of the method 4100 for configuring one or more signal modules 2614 according to some embodiments.

[0397] The Figure 26To describe method 4100. However, method 4100 is not limited to this example embodiment.

[0398] In 4102, the signal configuration module 2802 may receive one or more signal processing specifications. The signal processing specifications may specify the base signal to be processed, the lengths of the input and output packet queues for the signal module 2614, the digital signal processing functions for processing the base signal, and one or more associated parameters for the digital signal processing functions. In some embodiments, the signal configuration module 2802 may receive the signal processing specifications from a file stored in the memory. In some other embodiments, the signal configuration module 2802 may receive the signal processing specifications from a GUI that enables a user to manually input the signal processing specifications.

[0399] In 4104, the signal configuration module 2802 distributes one or more signal processing specifications to the signal factory module 2804.

[0400] In 4106, the signal factory module 2804 generates the signal module 2614 for each signal processing specification. 4106 may be performed by Figure 42 method 4200 in.

[0401] Figure 42 is a flowchart of method 4200 for generating the signal module 2614 according to signal processing specifications according to some embodiments.

[0402] Reference will be made to Figure 26 to describe method 4200. However, method 4200 is not limited to this example embodiment.

[0403] In 4202, the signal factory module 2804 generates the input packet queue 2902 of the signal module 2614 based on Figure 41 the signal processing specification in 4106 of. For example, the signal factory module 2804 generates the input packet queue 2902 by creating a queue data structure of the length specified in the signal processing specification.

[0404] In 4204, the signal factory module 2804 generates the output packet queue 2906 of the signal module 2614 based on the signal processing specification. For example, the signal factory module 2804 generates the output packet queue 2806 by creating a queue data structure of the length specified in the signal processing specification.

[0405] In 4206, the signal factory module 2804 uses the DSP factory module 2808 to generate the DSP 2904 of the signal module 2614 based on the signal processing specification. Specifically, the signal factory module 2804 may request the DSP factory module 2808 to generate the DSP 2904 based on the digital processing function and one or more signal processing parameters specified in the signal processing specification. For example, the DSP factory module 2808 may generate the DSP 2904 based on the low-pass filter function and a specific cut-off frequency specified in the signal processing specification.

[0406] In 4207, the signal factory module 2804 connects the generated input packet queue 2902, the generated DSP 2904, and the generated output packet queue 2906 in the signal module 2614. Specifically, the signal factory module 2804 connects the output of the input packet queue 2902 to the input of the DSP 2904. The signal factory module 2804 further connects the output of the DSP 2904 to the input of the output packet queue 2906.

[0407] In 4210, the signal factory module 2804 configures the input packet queue 2902 to receive packets distributed from the packet distributor 2610. In some embodiments, the signal factory module 2804 may add rules to the lookup table associated with the packet distributor 2610. The rules may specify that packets associated with a given signal can be processed by a given signal module 2614.

[0408] In 4212, the signal factory module 2804 uses the DSP delay equalizer 2806 to equalize the associated processing delay of each generated signal module 2614, such that each signal module 2614 outputs the processed packets to its output packet queue 2906 simultaneously. 4210 may be performed by Figure 43 the method 4300 in

[0409] Figure 43 is a flowchart of the method 4300 for equalizing the processing delay associated with each DSP 2904 of one or more signal modules 2614 according to some embodiments.

[0410] Reference will be made to Figure 26 to describe the method 4300. However, the method 4300 is not limited to this example embodiment.

[0411] In 4302, the DSP delay equalizer 2806 requests the processing delay associated with each DSP 2904 of one or more signal modules 2614. The DSP delay equalizer 2806 may use the API of the associated signal module 2614 to request the processing delay of the DSP 2904.

[0412] In 4304, the DSP delay equalizer 2806 receives the processing delays of the DSP 2904 from each of one or more signal modules 2614.

[0413] In 4306, the DSP delay equalizer 2806 determines the maximum processing delay among the one or more received processing delays.

[0414] In 4308, the DSP delay equalizer 2806 sets the DSP 2904 of each of the one or more signal modules 2614 to the maximum processing delay. For example, the DSP delay equalizer 2806 can use an API to set the processing delay of the DSP 2904 of each signal module 2614. In response, each DSP 2904 can be designed to process packets using its digital processing function and output the processed packets to the output packet queue 2906 at the end of the maximum processing delay. In some embodiments, if the DSP 2904 finishes processing a packet using its digital processing function before the end of the maximum processing delay, the DSP 2904 can block its output to the output packet queue 2906.

[0415] Figure 44 is a flowchart of a method 4400 for receiving one or more signal samples for one or more signals using an input module 2604 according to some embodiments.

[0416] Reference will be made Figure 26 to describe the method 4400. However, the method 4400 is not limited to this exemplary embodiment.

[0417] In 4402, the input module 2604 receives signal samples for a base signal from a hardware device (e.g., an electrode connected to a patient) or data stored in a computer file. For example, the computer file can contain a previously recorded session of signal samples received from the hardware device. As will be understood by those of ordinary skill in the art, the input module 2604 can receive signal samples for multiple base signals simultaneously.

[0418] In 4404, the input module 2604 distributes the received signal samples to a packetizer 2606.

[0419] Figure 45 is a flowchart of a method 4500 for converting one or more signal samples into one or more packets using a packetizer 2606 according to some embodiments.

[0420] Reference will be made Figure 26 to describe the method 4500. However, the method 4500 is not limited to this exemplary embodiment.

[0421] In 4502, the binner 2606 receives one or more signal samples from the input module 2604.

[0422] In 4504, the binner 2606 may optionally preprocess the one or more signal samples. For example, the binner 2606 may convert the binary values of the one or more signal samples to their corresponding physical values. As will be understood by one of ordinary skill in the art, the binner 2606 may perform various other types of preprocessing.

[0423] In 4506, the binner 2606 generates packets containing one or more signal samples for a given base signal. The binner 2606 may store a predetermined number of signal samples in a packet. In some embodiments, the binner 2606 may use a timer 2605 to ensure that each packet contains the same number of signal samples. Specifically, the binner 2606 may store the signal samples received from the input module 2604 into a packet until the timer 2605 is triggered.

[0424] In 4508, the binner 2606 assigns a label to the generated packet. The label may correspond to the time period during which one or more signal samples in the packet are received. The binner 2606 may assign a new label to each subsequent packet. For example, the binner 2606 may first generate a packet containing sixteen (16) signal samples for a given base signal. In this case, the binner 2606 may store the first set of signal samples in a packet labeled 0. The binner 2606 may store the second set of signal samples in a packet labeled 15. The binner may store subsequent sets of signal samples in packets labeled 31, 47, 64, etc.

[0425] Figure 46 is a flowchart of a method 4600 for distributing packets containing one or more signal samples to a queuing module 2608 according to some embodiments.

[0426] Reference will be made Figure 26 to describe the method 4600. However, the method 4600 is not limited to this exemplary embodiment.

[0427] In 4602, the binner 2606 determines the base signal associated with the newly generated packet.

[0428] In 4604, the binner 2606 determines the queue 2702 in the queuing module 2608 associated with the determined base signal. The binner 2606 may use a lookup table to determine that the queue 2702 is associated with the determined base signal.

[0429] In 4606, the binner 2606 distributes the packet containing one or more signal samples to the determined queue 2702.

[0430] Figure 47 is a flowchart of method 4700 for distributing packets from queuing module 2608 to signal modules 2614 associated with the packets, according to some embodiments.

[0431] Method 4700 will be described with reference to Figure 26 However, method 4700 is not limited to this exemplary embodiment.

[0432] At 4702, packet distributor 2610 continuously scans queue 2702 in queuing module 2608.

[0433] At 4704, packet distributor 2610 detects a new packet in queue 2702.

[0434] At 4706, packet distributor 2610 determines one or more signal modules 2614 in global signal table 2612 that are designed to process the new packet. Since a new packet (e.g., multiple copies or "instances" of the packet) can be distributed to multiple signal modules 2614, the underlying signal associated with the packet can be processed simultaneously using different digital processing functions of signal modules 2614.

[0435] In some embodiments, packet distributor 2610 may use global signal table 2612 to determine one or more signal modules 2614 that are designed to process instances of the new packet. For example, global signal table 2612 can be a fixed-size array. Each element of the array can be associated with a given underlying signal and thus with a given queue 2702. In addition, each element of the array itself can be a fixed-size array. Each element of the sub-array can be associated with a given signal module 2614. Thus, packet distributor 2610 can determine one or more signal modules 2614 that are designed to process the new packet by examining the corresponding elements in the sub-array associated with the underlying signal of the new packet.

[0436] In some other embodiments, packet distributor 2610 may use a lookup table to determine one or more signal modules 2614 that are designed to process the new packet. Specifically, the lookup table can map queue 2702 to one or more signal modules 2614.

[0437] At 4706, packet distributor 2610 distributes the new packet to one or more signal modules 2614 determined in global signal table 2612 for processing. Specifically, packet distributor 2610 inserts the new packet into the input packet queue 2902 of the determined one or more signal modules 2614.

[0438] Figure 48It is a flowchart of method 4800 for processing packets using signal module 2614 associated with a packet according to some embodiments.

[0439] Reference will be made to Figure 26 to describe method 4800. However, method 4800 is not limited to this exemplary embodiment.

[0440] At 4802, DSP 2904 detects whether there is a new available packet in input packet queue 2902 of signal module 2614. In some embodiments, DSP 2904 may scan input packet queue 2902 for new packets to be processed. In some other embodiments, DSP 2904 may obtain a notification that there is a new packet available in input packet queue 2902.

[0441] At 4804, DSP 2904 retrieves the new packet from input packet queue 2902 of signal module 2614.

[0442] At 4806, DSP 2904 processes the new packet using its associated digital signal processing function. Specifically, DSP 2904 may apply its digital processing function to one or more signal samples in the packet. In some embodiments, DSP 2904 may use its digital processing function to control how it processes the packet based on one or more signal processing parameters designed for DSP 2904.

[0443] At 4808, DSP 2904 outputs the processed packet to output packet queue 2906. In some embodiments, DSP 2904 may output the processed packet to output packet queue 2906 based on the maximum processing delay it is designed for.

[0444] Figure 49 It is a flowchart of method 4900 for displaying a processed packet to a display screen using display module 2618 according to some embodiments.

[0445] Reference will be made to Figure 26 to describe method 4900. However, method 4900 is not limited to this exemplary embodiment.

[0446] At 4902, display module 2618 determines from which one or more signal modules 2614 to display the processed packet. In some embodiments, display module 2618 may determine from which one or more signal modules 2614 to display the processed packet by maintaining a reference to output packet queue 2906 of one or more signal modules 2614. Display module 2618 may store the reference in local signal table 3002.

[0447] At 4904, the display module 2618 detects that a new packet is available in the output packet queue 2906 of one of the determined signal modules 2614.

[0448] At 4906, the display module 2618 receives a new packet from the output packet queue 2906 of one of the determined signal modules 2614.

[0449] At 4908, the display module 2618 determines a label associated with the new packet.

[0450] At 4910, the display module 2618 receives new packets that match the determined label from other output packet queues 2906.

[0451] At 4912, the display module 2618 displays the new packets of one or more received signal modules on the display screen. Since the display module 2618 displays new packets with the same label, the display module 2618 synchronizes the display of the signals associated with the new packets.

[0452] The methods 4000, 4100, 4200, 4300, 4400, 4500, 4600, 4700, 4800, 4900 can be executed by processing logic, which may include hardware (e.g., circuits, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions executed on a processing device), or a combination thereof. It should be understood that not all steps may be required to implement the disclosure provided herein. Additionally, as would be understood by one of ordinary skill in the art, some steps may be executed simultaneously or in a different order than Figures 40 to 49 that shown.

[0453] In some embodiments, the DSP 2904 may be based on a notch filter. An electrophysiology laboratory with many devices may tend to have a large amount of line frequency and harmonics (e.g., noise) that interfere with cardiac recordings. In North America, this is mainly 60 Hz plus harmonics. Figure 50 An example of a signal (e.g., triangular spike 5002) with 60 Hz noise 5004 superimposed is illustrated according to some embodiments.

[0454] To obtain an accurate cardiac recording, it is generally desirable to remove the noise while retaining the signal of interest. Conventional methods of removing 60 Hz noise include using a notch filter, which has a transmittance of zero at 60 Hz. Figure 51 An example of a conventional method of removing 60 Hz noise using a notch filter with a transmittance of zero (single notch) at 60 Hz is illustrated according to some embodiments.

[0455] Figure 52 An application according to some embodiments is illustrated Figure 51Example of the result of a conventional filter. As Figure 52 shown, the 60 Hz signal is removed from the input signal 5202 to produce a filtered signal 5204. However, conventional filters may encounter multiple problems. For example, after a large spike 5206, the conventional filter can introduce overshoot and ringing (e.g., transient response) 5208 into the signal. This overshoot and ringing may be an artifact of the filter and not part of the original input signal. This can lead to a reduction in the accuracy of the heart recording.

[0456] Additionally, a conventional 60 Hz notch filter may not reduce any harmonics of 60 Hz. For example, as Figure 53 shown, if the interference in the input signal 5302 is evaluated at both 60 Hz and 180 Hz, the 180 Hz harmonic is still present at the output of the conventional filter. Figure 53 Illustrates an example of the 180 Hz harmonic that is still present in the filtered signal 5304 at the output of a conventional filter according to some embodiments. Figure 51

[0457] Therefore, as Figure 53 shown in, conventional notch filters may suffer from two problems. First, conventional notch filters may introduce overshoot and ringing 5306 in the signal. Second, conventional notch filters may not be able to reduce any higher-order harmonics.

[0458] In some embodiments, the DSP 2904 can apply a notch filter that does not introduce overshoot and ringing in the signal and reduces not only the fundamental harmonic but also higher-order harmonics. The notch filter of the DSP 2904 can solve the above technical problems of conventional notch filters by extracting the interfering noise and subtracting it from the noisy signal. This can remove the interference without creating artifacts (e.g., overshoot and ringing) associated with conventional notch filters. The notch filter of the DSP 2904 can reproduce one cycle of the interfering signal in a separate buffer (also known as a circular buffer, noise buffer, or data buffer) and subtract it from the noisy signal to extract the original data. Since the line frequency noise can be constant or nearly constant, the notch filter of the DSP 2904 can use some variation of averaging to improve the estimate over time. Since the frequency can be known, the size of the buffer can be predetermined. Additionally, a buffer that stores only one cycle can also store integer multiples of higher frequencies that can be subtracted from the noisy data. Figure 54 Illustrates an example of notch filtering by the DSP 2904 for a signal with 60 Hz and 180 Hz noise according to some embodiments. Since the line frequency noise is constant, one cycle of interference 5402 can be reproduced in the input signal and subtracted from each cycle 5404 of the successive cycles.

[0459] At a 60 Hz noise and a sampling rate of 2000 samples per second, 33 1 / 3 samples are stored in the buffer. Since an integer number of samples can be present in the buffer, the notch filter of the DSP 2904 can choose to use 100 samples and accurately store 3 cycles of 60 Hz. Figure 55 Illustrated is an example of the notch filter of the DSP 2904 that uses 100 samples of the input signal 5502 and accurately stores 3 cycles of 60 Hz 5504 according to some embodiments.

[0460] To accumulate steady-state noise in the buffer, data can be collected during the "silent time" of the waveform. As will be understood by those of ordinary skill in the art, the silent time can be a period during which no large spikes or edges are present in the input signal. The silent time can be determined by calculating the slope of the signal. Figure 56 Illustrated is an example of the notch filter of the DSP 2904 calculating the silent time in the input signal 5602 according to some embodiments. Three cycles of noise data (interference) 5604 can be collected in the buffer during the silent time 5606. Subsequent cycles 5608, 5610, 5612 are averaged to build an accurate copy of the interference 5604. Since the cycle time is constant for cycles 5606, 5608, 5610, 5612, only cycles of the fundamental frequency and harmonic frequencies are accumulated. Cycles of other frequencies are averaged to zero.

[0461] For each new point sampled from the incoming data, it can be determined whether it is in the "silent time" of the signal. The silent time can be determined by calculating the slope of the signal. If the slope is above a threshold, the silent time can be determined to have started. If the new point is in the silent time, it can be averaged with the previously stored data at that location in the buffer. Over time, this averaging process can accumulate a copy of the noise that can be subtracted from the noisy signal. For those locations not in the silent time, the buffer may not be updated, but the accumulated signal can still be subtracted. Figure 57 Illustrated is an example of the notch filter of the DSP 2904 accumulating 3 cycles of noise copies in each silent time 5702, 5704, 5706, 5708 in the buffer and subtracting the noise from the noisy signal according to some embodiments. Since the buffer contents 5710, 5712, 5714, 5716 match the noise data in the silent times 5702, 5704, 5706, 5708 respectively, the noise can be more accurately modeled, and when subtracted, the noise content of the displayed signal can be significantly reduced.

[0462] When each sample is added to the buffer, averaging can result in a filter that peaks at the line frequency 5802 and all harmonics (5804, 5806, etc.). This allows for the selective accumulation of the line frequency and all harmonics and the rejection of all other frequencies, such that the notch filter of DSP 2904 subtracts only the additional noise at a fixed frequency. Figure 58 An example of the result of the notch filter or buffer filter of DSP 2904 according to some embodiments is illustrated. To produce Figure 58 the buffer filter shown in, for example, 5% of the new samples are added to 95% of the accumulated values to update the buffer. In implementation-specific cases, other combined percentages of each new sample and the accumulated values can be combined.

[0463] Figure 59 is a flowchart of a method 5900 for notch filtering noise from an input signal according to some embodiments. Method 5900 will be described with reference to Figure 29 However, method 5900 is not limited to this example embodiment.

[0464] In 5902, DSP 2904 accesses an input signal that includes noise having a first harmonic frequency and has noise. The noise frequency in the input signal can be substantially constant.

[0465] In 5904, DSP 2904 determines a silent period in the input signal. DSP 2904 can determine the silent period by calculating the slope of the input signal. DSP 2904 can then determine the presence of the silent period based on the calculated slope being below a threshold.

[0466] In 5906, DSP 2904 stores the noise samples of the input signal during the silent period in a buffer. The size of the buffer can be based on the frequency of the noise in the input signal.

[0467] As part of the storage, DSP 2904 can average the samples of the input signal with the corresponding noise samples in the buffer to create an average sample. DSP 2904 can then use the average sample to replace the corresponding noise sample in the buffer.

[0468] In 5908, DSP 2904 subtracts the samples in a single cycle of the noise in the buffer from the input signal to create a filtered signal. The subtraction can remove the first harmonic frequency and the second harmonic frequency from the input signal while avoiding introducing a transient response (e.g., ringing) in the filtered signal. The first harmonic frequency can be 60 Hz, and the second harmonic frequency can be 120 Hz or 180 Hz.

[0469] In 5910, DSP 2904 repeats 5904 to 5908 to refine the filtered signal. As will be appreciated by those skilled in the art, the samples can be at any position in the loop. Moreover, the samples do not have to constitute a single loop. In other words, DSP 2904 can store multiple noise cycles of the input signal in the buffer.

[0470] In some embodiments, the DSP 2904 may be based on a high pass filter. Certain areas of the heart generate very low amplitude, high frequency signals that may be of interest during cardiac surgery. Physicians often wish to highlight these signals for review in the presence of noise and other larger cardiac signals.

[0471] This can be achieved using a high pass filter. Figure 60 An example of a conventional high pass filter 6002 according to some embodiments is illustrated. In this case, the 3db frequency 6004 of the conventional high pass filter may be approximately 200 Hz to suppress low frequencies. Additionally, since the frequencies of interest are typically above the line frequency (e.g., 60 Hz), the conventional high pass filtering method may include placing a notch 6006 therein to eliminate interference from potential large power line interference.

[0472] However, a typical signal from an intracardiac catheter can contain high frequency signals from the conduction areas of the heart as well as sharp localized spikes from a variety of sources. Figure 61 An example of a signal according to some embodiments is shown, the signal contains high frequency signals from the conductive area of the heart and sharp local spikes from various sources. Figure 61 As shown, there are spikes 6102 similar to local near-field pulses (e.g., QRS, local spikes, transients, etc.) and short bursts of high frequency (e.g., 300 Hz) cardiac signals 6104.

[0473] Figure 62 Illustrated is the use of some embodiments Figure 60 The high-pass filter Figure 61 Example of the output result of filtering the signal. Figure 62 As shown, low frequency components (e.g., baseline wander) are removed and, as desired, the high frequency cardiac signal 6202 is highlighted. However, the transient response of the high pass filter may leave undesired pulses (e.g., artifacts) 6204 and some ringing at the output. In complex and large waveforms, it is easy for physicians to confuse the pulses 6204 with the high frequency cardiac signal 6202. This is problematic for accurate diagnosis and treatment.

[0474] In some embodiments, the DSP 2904 can be a high-pass filter that removes pulses while allowing high-frequency signals of interest to pass through. To remove pulses, the input signal can be monitored for large drifts and high signal slopes (e.g., derivatives). When these conditions exist, the output can be blanked for a fixed period before and after the occurrence of the situation, so that transient conditions are not shown on the displayed waveform. Figure 63 illustrates an example of the resulting output of filtering a Figure 61 signal using a high-pass filter that removes pulses 6302 while allowing high-frequency cardiac signals 6304 of interest to pass through, according to some embodiments.

[0475] Figure 64 is a flowchart of a method 6400 for high-pass filtering noise from an input signal. Method 6400 will be described with reference to Figure 29 However, method 6400 is not limited to this example embodiment.

[0476] In 6402, the DSP 2904 accesses an input signal that includes noise and high-frequency signals of interest. For example, in the application of the DSP2904, rapid-conduction tissue identification filtering can be performed to identify Purkinje fibers, highly isotropic / low anisotropic segments in the myocardial architecture, and preferential conduction pathways in diseased tissue. In such an application, the DSP 2904 can access Purkinje signals in the presence of noise, such as high-frequency signals of interest. The DSP 2904 can use a notch filter to filter the input signal.

[0477] When artifacts are identified in the signal of interest, they can be specifically introduced and characterized, and then direct automation of filtering can be applied so that these diagnosed signals are used as templates to subtract / filter or otherwise process the signal from all retrieved electrograms. For example, the system can record signals with and without flushing through a catheter when the catheter is in contact and stable. The differences can represent artifacts, created templates, and templates for allowing the filtering and summing techniques of the system to remove the artifacts, which can then be automatically characterized. As those of ordinary skill in the art will understand, such a system will be beneficial when used in existing defibrillators and subcutaneous implantable cardioverter defibrillators (ICDs).

[0478] In 6404, the DSP 2904 performs high-pass filtering on the input signal to create a filtered signal.

[0479] In 6406, the DSP 2904 isolates artifacts associated with noise in the filtered signal from the high-frequency signals of interest. For example, the DSP 2904 can isolate the pulse response.

[0480] The DSP 2904 can isolate artifacts by calculating the slope of the filtered input signal. The DSP 2904 can then determine the presence of an artifact based on the calculated slope being higher than a threshold. The DSP can characterize the artifact in an artifact template. The DSP 2904 can select a filter based on the isolated artifact such that the artifact template can be used as the filter.

[0481] In 6408, the DSP 2904 blanks the filtered signal for a fixed period before and after the isolated artifact. The DSP 2904 can optionally use the selected filter to perform the blanking. This blanking can remove the isolated artifact and allow high-frequency signals of interest to pass through. The DSP 2904 can buffer the filtered signal for a fixed period before and after the isolated artifact.

[0482] In some embodiments, the DSP 2904 can perform pattern (or signal characteristic) matching. The pattern matching of the cardiac signal can be based on some kind of correlation. For example, the correlation can be a statistical correlation function or the mean absolute deviation.

[0483] The correlation function (CF) can be specified by Equation 1.

[0484] Equation 1: Correlation function

[0485]

[0486] The mean absolute deviation function (MAD) can be specified by Equation 2.

[0487] Equation 2: Correlation function

[0488]

[0489] For surface ECG, there are typically 12 leads in a set. In a pace matching application, it may be necessary to correlate all 12 leads with all 12 leads of a reference heartbeat. The reference heartbeat can be a heartbeat obtained from a patient when an abnormal heartbeat is exhibited and can be compared with the pacing heartbeat from a catheter during an electrophysiological procedure. In other cases, it may only be necessary for a subset of the leads to be correlated. In the case of the correlation function, a perfect match in shape can be +1, while a directly opposite shape can be -1, and the amplitude similarity cannot be measured. For the MAD function, a perfect match can be 0, a direct opposite can be 1, and the amplitude difference may result in a worse match.

[0490] For multiple lead comparisons, some similarity metric may need to be established. This can be the mean, median, or extension of formula 1 or formula 2 that sums the numerator and denominator for all leads in the set. Additionally, leads with larger amplitudes or specific ranges of heartbeats representing features to be emphasized (e.g., Q waves) can be given greater weight.

[0491] In all comparisons, the leads can be normalized to have a 0 DC offset. This may be because only the shape (and amplitude) is important in the comparison.

[0492] In some embodiments, a pattern (or signal characteristic) can be selected using a vertical caliper. The vertical caliper can be a GUI selection widget. Figure 65 An example of a review window 6500 for selecting a data range (typically a heartbeat) using vertical calipers 6502, 6504 is illustrated according to some embodiments.

[0493] The selected pattern can then be saved as a reference heartbeat (or known signal pattern). Figure 66 An example of saving a selected pattern as a reference heartbeat is illustrated according to some embodiments. Figure 66 The "Save New Pattern" window 6600 shown in may allow the user to view previously saved heartbeats (e.g., known signal patterns) 6602 to decide whether the newly identified heartbeat is unique enough relative to the previously saved heartbeats to be worth saving separately. When a heartbeat is stored, a unique name 6604, color 6606, and / or description (i.e., note) 6608 can be assigned to it.

[0494] When the user wants to initiate a search, the user can open a window of selectable patterns for searching by clicking on the Select Pattern button 6510 in the review window 6500 of Figure 65 An example of a "Select Pattern to Search" window 6700 of selectable patterns is illustrated according to some embodiments. The window 6700 for selecting a pattern to search can display a scrollable list 6710 of all stored patterns. Checkboxes 6720 on the left side of each list item can allow the user to select the associated pattern. The selections can remain active until the user decides to change them. When the user clicks on each pattern in the list 6710, the corresponding signal can be displayed in a window 6730 below the list box. The window 6730 can also display a field allowing the user to enter a confidence factor threshold (also referred to as a pattern detection threshold 6740) that can be used to detect the pattern. For example, the pattern detection threshold 6740 is set to 80% in Figure 67 An example of a "Select Pattern to Search" window 6700 of selectable patterns is illustrated according to some embodiments. The window 6700 for selecting a pattern to search can display a scrollable list 6710 of all stored patterns. Checkboxes 6720 on the left side of each list item can allow the user to select the associated pattern. The selections can remain active until the user decides to change them. When the user clicks on each pattern in the list 6710, the corresponding signal can be displayed in a window 6730 below the list box. The window 6730 can also display a field allowing the user to enter a confidence factor threshold (also referred to as a pattern detection threshold 6740) that can be used to detect the pattern. For example, the pattern detection threshold 6740 is set to 80% in Figure 67 is set to 80%.

[0495] After the user has selected the mode to search for and clicks "OK" 6750, the user can initiate the search by clicking the "Enable / Disable Mode" search button 6512, which can become active in the review window 6500 as shown in Figure 65 . After clicking the button, the mode search can begin, and the heartbeats that match the reference heartbeat (e.g., with a confidence level equal to or greater than the selected confidence factor threshold) are displayed on the review window 6500. The found patterns can be displayed in two different modes (summary view and detailed view) of the review window 6500 as shown in Figure 65 . As shown in the review window 6800 in Figure 68 , the user can use the buttons Summary 6802 and Details 6804 to switch between these two modes.

[0496] In the summary view, the signal segments that match the pattern and are displayed in the review window can be highlighted using the color associated with each pattern. Multiple patterns can overlap on the same segment of the signal. In the summary view, the overlapping segments can be displayed using different colors to make the patterns more clearly visible in each segment.

[0497] Figure 68 Illustrates an example of the summary view of the mode search in the review window in Figure 65 according to some embodiments, where multiple matching patterns are displayed. As shown in Figure 68 , four segments 6806, 6808, 6810, 6812 of the surface ECG signal are highlighted in the review window 6800. In this example, the two segments 6806, 6808 on the left are shown in two colors (or line styles), which means that the patterns of these segments overlap. The two segments 6810, 6812 on the right are shown in the color assigned to pattern P1, which indicates that only pattern P1 is found in these segments.

[0498] Figure 69 Illustrates an example of the summary view 6900 of the mode search in the review window in Figure 68 according to some embodiments, where a single matching pattern is displayed while other patterns are hidden. When the matched pattern segment is displayed, a small window 6910 can be shown on the right. This window can allow the user to show or hide the matching segments associated with each found pattern. In its initial state, all found patterns can be checked. When the user unchecks the checkboxes 6912, 6914 next to each pattern name, the corresponding highlighted segments are hidden. As shown in Figure 69 , the matching segments 6810, 6812 associated with pattern P1 6916 are hidden. Therefore, Figure 68 the monochromatic segments 6810, 6812 inFigure 69 As shown, the monochromatic sections 6810, 6812 are on the right side and match only pattern P1. However, now in Figure 69 the left sections 6806, 6808 where pattern P1 and P4 overlap are shown in the color associated with pattern P4 6918.

[0499] In the detail view, pattern details can be shown one segment at a time. The detail view can be enabled by selecting detail 6804 in the Figure 68 review window 6800. In the detail view, the actual pattern can be shown on top of the matching segments using the color assigned to that pattern. Figure 70 Illustrated is an example of a detail view of a signal in the Figure 65 review window according to some embodiments.

[0500] As Figure 70 shown, the detail view 7000 can show one pattern detail at a time. For each segment, if multiple patterns overlap, the pattern with the highest confidence factor can be shown first. However, the user can select to view other overlapping patterns (e.g., with lower confidence values) by checking their associated checkboxes 7002, 7004 in the detail view list 7006. In this case, the signal shown in the detail view 7000 can be automatically changed to reflect the newly selected pattern. For example, as Figure 70 shown, pattern P1 7008 has the highest confidence value (e.g., 87.0%) and is thus shown first.

[0501] In the detail view, the confidence value for each lead can be shown using a horizontal bar in the "Confidence Factor per Lead" table 7010, and the actual confidence value can be provided on top of those bars as Figure 70 shown. For example, lead I7012 indicates a confidence value of 79.6%. Confidence values above the user-set confidence level (e.g., when a search pattern is selected) can be shown in green, and values below that threshold can be shown in orange, e.g., visually indicating whether the confidence level of each individual lead meets the user's desired threshold. When the user clicks on any lead name in the "Confidence Factor per Lead" table 7010, the matching segments on the corresponding pattern and signal can be shown in the "Pattern and Signal Trace" window 7014 below the "Confidence Factor per Lead" table 7010. Two buttons can be below this window, allowing the user to change the time 7016 and amplitude scale 7018 on the displayed signal to accurately view the shape details of the signal. If the selected time 7016 or amplitude scale 7018 makes part of the signal visible, a scroll bar can be automatically shown to allow the user to access any part of the signal.

[0502] The detail view 7000 can also highlight signal segments and associated matching patterns shown using brackets 7020. This can allow a user to easily identify the signal segments shown in the detail view 7000. A match confidence factor 7022 for the pattern can also be indicated next to one of the brackets.

[0503] Figure 71 An example window 7100 according to some embodiments is illustrated. The example window 7100 has pattern match confidence values provided by leads (confidence factor 7102 for each lead). As Figure 71 shown, leads V1 7104 and V2 7106 are below the confidence threshold and are shown in orange.

[0504] As described for the Figure 64 method, the concept of creating a template for a specific artifact generation event can also be used by the disclosed system for pattern matching. For example, patterns of valve motion artifacts related to unipolar signals collected above and below a valve and within a coronary artery can be used to create a pattern template so that an operator immediately knows whether the catheter is above the valve, below the valve, or within the coronary artery. If the coronary artery profile within the pattern template is met, the system can respond, for example, by not allowing energy delivery during an ablation procedure.

[0505] Figure 72 is a flowchart of a method 7200 for pattern matching according to some embodiments. Method 7200 will be described with reference to Figure 29 However, method 7200 is not limited to this example embodiment.

[0506] At 7202, the DSP 2904 accesses the input cardiac signal.

[0507] At 7204, the DSP 2904 matches a portion of the input cardiac signal to a known signal pattern. The known signal pattern can be captured during a previous patient procedure or the current patient procedure and stored in a pattern template. The known signal pattern can also be stored in a database.

[0508] The DSP 2904 can match a portion of the input cardiac signal to a known signal pattern based on a correlation function. For example, the DSP 2904 can match a portion of the input cardiac signal to a known signal pattern based on the mean absolute deviation (MAD) function. The DSP 2904 can also match a portion of the input cardiac signal to a known signal pattern based on a confidence value.

[0509] At 7206, the display module 2618 displays an indication of the degree of match. The indication of the degree of match can specify the location of cardiac pacing.

[0510] Figure 73 is a flowchart of a method 7300 for pattern matching according to some embodiments. The method 7300 will be described with reference to Figure 29 However, the method 7300 is not limited to this exemplary embodiment.

[0511] At 7302, the DSP 2904 accesses the input cardiac signal.

[0512] At 7304, the DSP 2904 accesses the detection threshold.

[0513] At 7306, the DSP 2906 matches a portion of the input cardiac signal to a known signal pattern based on the detection threshold. The known signal pattern can be captured during a previous patient procedure or the current patient procedure. The known signal pattern can be stored in a database.

[0514] The DSP 2904 can match a portion of the input cardiac signal to a known signal pattern based on a correlation function. For example, the DSP 2904 can match a portion of the input cardiac signal to a known signal pattern based on the mean absolute deviation (MAD) function.

[0515] The DSP 2904 can match a portion of the input cardiac signal to a known signal pattern based on a weighted specific region of the known signal pattern. The DSP 2904 can first match a portion of the input cardiac signal to the known signal pattern. The DSP 2904 can determine a first confidence value based on the first match. The DSP 2904 can then match a portion of a second input signal to the known signal pattern. The DSP 2904 can determine a second confidence value based on the second match. The DSP 2904 can average the first confidence value and the second confidence value to create an average confidence value. The DSP 2904 can then determine that the average confidence value is higher than the detection threshold.

[0516] At 7308, the display module 2618 displays a highlighted portion of the input cardiac signal based on the match. For example, the display module 2618 can display the highlighted portion of the input cardiac signal based on a color associated with the known signal pattern.

[0517] In some embodiments, the DSP 2904 can perform late potential and early activation detection. By interpolating signal data independently displayed using a conventional late potential filter from early sites of activation to late sites of detected activation, the system can infer sites of conduction delay. This site (or region) can be highlighted using any compatible three-dimensional mapping system, which can allow a physician to direct catheter placement, record slow conduction at the site, and perform targeted ablation at the site. These features are difficult or even impossible to accomplish using systems that saturate when gain is applied to small signals and thus sites of slow conduction may otherwise remain invisible to the physician.

[0518] Embodiments herein benefit from the high dynamic range of the system to interpolate data from early sites of activation to late sites of detected activation and to independently display data using a conventional late potential filter. Such embodiments are capable of detecting late potentials and early activations in a main signal display window in real time (e.g., live) and during session playback. By clicking the "Create and Manage Searches" button in the main signal display window, a user can create search criteria, activate searches, and manage existing searches for late potentials or early activations.

[0519] Figure 74 An example of a search definition window 7400 for creating and managing searches for late potentials and early activations, in accordance with some embodiments, is illustrated. To add a late potential search to the main signal display window, a user can click the "Add Late Potential Search" button 7402 within the search definition window (e.g., Figure 74 the search definition window 7400). In response, a late potential detection configuration window can be displayed and various search parameters can be defined by the user. Figure 75 An example of a late potential detection configuration window 7500 for defining various search parameters for late potentials, in accordance with some embodiments, is illustrated.

[0520] A user can create at least one pattern to perform a late potential search. A user can specify various late potential search parameters that allow various types of searches. As Figure 75As shown, the user can define one or more of the following parameters: the name to search for (7502), the selection of the heartbeat pattern for the search (7504), the reference point from which the search starts (7506), which ECG lead to select for heartbeat detection (7508), which intracardiac lead to select for late potential detection (7510), the use of a search interval and length starting from the pattern reference (7512), the heartbeat detection confidence threshold percentage (e.g., 80%) (7514), the selection of the late potential detection confidence threshold percentage (e.g., 80%) (7516), and the selection of the late potential amplitude threshold (e.g., 0.015 mV) (7518). As will be understood by those of ordinary skill in the art, the user can define various other parameters.

[0521] Once all the parameters are defined, the search can be activated. When a late potential is detected, the signal display window can show the location of the late potential and its detection confidence. Figure 76 Illustrated is an example signal display window 7600 showing the locations of late potentials 7602, 7604, 7606, 7606, 7608, 7610 and their detection confidence according to some embodiments. The review window can also show all the late potentials detected under the search results tab. The newly created late potential search can be listed within the search definition window (e.g., Figure 74 the search definition window 7400). The newly created late potential search can be listed under the currently defined search section in the search definition window.

[0522] The user can add an early activation search in a manner similar to the late potential search. The user can specify various early activation search parameters for various types of searches. The parameters can be equivalent to the late potential search parameters. The difference is that the search can occur within the search interval defined before the reference line. Figure 77 Illustrated is an example early activation detection configuration window 7700 for defining various search parameters for early activation (similar to those Figure 75 described for

[0523] Once all the parameters are defined in the early activation detection configuration window 7700, the search can be activated. When an early activation is detected, the signal display window can show the location of the early activation and its detection confidence and length. Figure 78 Illustrated is an example signal display window 7800 according to some embodiments, which shows the locations of early activations 7802, 7804, 7806 and their detection confidence. The review window can also show all the early activations detected under the search results tab. The newly created early activation search can be in the search definition window (e.g., Figure 74Listed within the search definition window 7400). The newly created early activation search can be listed under the currently defined search section in the search definition window.

[0524] The user can use the search definition window to manage the defined late potential and early activation searches. Figure 79 Illustrated is an example of a search definition window 7900 for managing defined late potential searches and early activation searches according to some embodiments.

[0525] In the search definition window 7900, all active searches can be listed in the "Currently Defined Searches" window 7902, and the user can run, stop, delete, or modify the searches. If a search is stopped, the user can resume running the search by clicking the "Run" button 7904. For example, as Figure 79 shown, search EA1 is stopped 7906 and search LP1 is running 7908. In this case, the user can resume running the EA1 search and stop 7910 running the LP1 search or use other options (e.g., delete 7912 and modify 7914).

[0526] Figure 80 is a flowchart of a method 8000 for detecting early activation or late potential according to some embodiments. Method 8000 will be described with reference to Figure 29 However, method 8000 is not limited to this example embodiment.

[0527] At 8002, the first DSP 2904 accesses the first cardiac signal associated with the surface lead.

[0528] At 8004, the first DSP 2904 matches the beats of the first cardiac signal with known signal patterns. The first DSP2904 can match the beats of the first cardiac signal with known signal patterns based on a correlation function. For example, the first DSP2904 can match the beats of the first cardiac signal with known signal patterns based on the mean absolute deviation (MAD) function. The first DSP 2904 can match the beats of the first cardiac signal with known signal patterns based on a confidence value. The confidence value can be user-defined.

[0529] At 8006, the second DSP 2904 searches for early activation or late potential in the second cardiac signal within a period before and after the matched beats. This period can be a user-defined period.

[0530] The second DSP 2904 can search for early activation or late potential in a buffer including a part of the second cardiac signal. The second DSP 2904 can search for early activation based on an amplitude threshold.

[0531] Using early activation or late potentials, the system can interpolate signal data from a catheter at sites of early activation to sites of late potentials. The system can use a conventional late potential filter to display the signal data independently. Using the interpolated signal data, the system can infer sites of conduction delay. The system can also be used in combination with a three-dimensional mapping system with the interpolated signal data at a site to guide further catheter placement, record slow conduction at the site, or perform targeted ablation at the site.

[0532] In some embodiments, the display module 2618 can use a waterfall view (e.g., Figure 37A and 37B the waterfall view in ) to display one or more signals. The waterfall view window can stack cardiac heartbeats that match a selected pattern on a particular ECG lead vertically and can display intracardiac signals selected by the user next to each detected heartbeat. The latter can be shown relative to a user-defined interval of a reference point within the heartbeat pattern.

[0533] To set parameters for the waterfall view, the user can click the "Create Waterfall View Window" button located in the main signal display toolbar. In response, a waterfall display configuration window can be shown. Figure 81 Illustrates an example of a waterfall display configuration window 8100 according to some embodiments.

[0534] As Figure 81 shown, the user can define one or more of the following parameters. The user can select a heartbeat pattern 8102 to be searched (e.g., can be selected from saved heartbeat patterns to be used in the waterfall view). The user can define a reference point 8104 on the heartbeat pattern that will be used to display the interval. If the reference point has not been selected, the user can add a reference point by clicking on the heartbeat pattern display window located below the heartbeat pattern list. Similarly, the position of an existing reference point can be changed by clicking on the heartbeat pattern display window. The user can select a surface ECG lead 8106 for heartbeat detection. The user can define the display interval 8108 of the ECG lead (e.g., the starting point and length relative to the pattern reference point). The user can select an intracardiac channel 8110 for the search. The user can define the display interval 8112 of the intracardiac lead (e.g., the starting point and length relative to the pattern reference point). The user can also select a vertical scroll mode 8114 such as time or heartbeat.

[0535] Figure 82An example of a waterfall view 8200 using a time pattern according to some embodiments is illustrated. When the vertical scroll mode 8114 is set to the time mode, the matching signals can continuously scroll upward over time. Thus, when no heartbeat matching the selected pattern is detected, the time mode can show the gaps 8202 between heartbeats. In the time mode, the last heartbeat timestamp 8204 can be shown at the lower left corner of the window.

[0536] When the vertical scroll mode 8114 is set to the heartbeat mode, the vertical auto-scroll of the waterfall view window can be disabled, and the heartbeats can scroll upward only when a new heartbeat matching the selected pattern is detected. Figure 83 An example of a waterfall view 8300 using a heartbeat pattern according to some embodiments is illustrated. In the heartbeat mode, each individual heartbeat can be timestamped 8302.

[0537] Once all the parameters of the waterfall view are defined by the user, as Figure 82 and Figure 83 shown, the waterfall view window can display two signals side by side. The waterfall view window can display the signals using the time mode or the heartbeat mode. The names of leads 8304, 8306 can be shown at the top of the window. The heartbeat mode name 8208 can also be shown beside the ECG lead name 8206.

[0538] Buttons can exist within the toolbar of the waterfall view window, for example, the waterfall parameter button 8210 and the display parameter button 8212. The waterfall parameter button 8210 can allow the user to adjust the display parameters while opening the waterfall view window. For example, the user can change the display interval, the vertical scroll mode, or any parameter that would be understood by a person of ordinary skill in the art.

[0539] The user can disable this feature. Figure 84 An example of a display parameter window 8400 according to some embodiments is illustrated. The display parameter window 8400 can allow the user to change various display parameters. For example, the user can adjust the scaling 8402, 8404 of each lead using the option to reset 8416, 8418 to the default values. The user can add 8406 or remove 8408 clipping. The user can change the color 8410, 8412 for each lead or subset of leads. The user can disable the fading 8414 of the displayed heartbeats. In some embodiments, the displayed heartbeats may fade as they move toward the upper part of the waterfall view window.

[0540] In some embodiments, according to some embodiments, the EP hardware system can generate a pure unipolar signal. The EP hardware system can generate a pure unipolar signal based on having an ECG circuit board and multiple IC circuit boards that share substantially the same circuit configuration and components, and the ECG circuit board processes the ECG signal using substantially the same path as each IC circuit board uses to process its corresponding IC signal. A single Wilson Central Terminal (WCT) signal can be used for the ECG circuit board and the multiple IC circuit boards.

[0541] In some embodiments, the EP hardware system can act as a central processing system for all other systems. The EP hardware system can include: an ECG circuit board configured to receive an ECG signal; multiple IC circuit boards, each configured to receive an IC signal; a communication interface communicatively coupled to a remote device; and a processor coupled to the ECG circuit board, the multiple IC circuit boards, and the communication interface. The EP hardware system can act as a central processing system by causing its processor to receive feedback from the remote device via the communication interface and to control the remote device via the communication interface based on the ECG signal, the IC signal, and the feedback from the remote device.

[0542] The EP hardware system can receive feedback from and control a remote device, which includes but is not limited to an ultrasound machine, a radio frequency (RF) generator, a stimulator, a three-dimensional imaging device, an intracardiac echocardiogram (ICE) machine, a fluoroscopy machine, and a defibrillator. As will be understood by one of ordinary skill in the art, the remote device can be various other types of devices. The EP hardware system can communicate with the remote device using a communication protocol via a communication interface coupled to the remote device, and the communication protocol includes but is not limited to Digital Imaging and Communications in Medicine (DICOM), Ethernet, Universal Serial Bus (USB), and Institute of Electrical and Electronics Engineers (IEEE) 802.11. As will be understood by one of ordinary skill in the art, the EP hardware system can use various other communication protocols to communicate with the remote device.

[0543] Implementation of the Computer System

[0544] Various embodiments can be implemented, for example, using one or more well-known computer systems (such as Figure 85 the computer system 8500 shown). One or more computer systems 8500 can be used, for example, to implement any of the embodiments discussed herein, as well as their combinations and sub-combinations.

[0545] The computer system 8500 can include one or more processors (also referred to as central processing units or CPUs), such as processor 8504. The processor 8504 can be connected to a communication infrastructure or bus 8506.

[0546] The computer system 8500 may also include one or more user input / output devices 8503, such as monitors, keyboards, pointing devices, etc. The computer system 8500 may communicate with the communication infrastructure 8506 via one or more user input / output interfaces 8502.

[0547] One or more of the processors 8504 may be a graphics processing unit (GPU). In one embodiment, the GPU may be a processor that is a dedicated electronic circuit designed to process math-intensive applications. The GPU may have a parallel architecture that is effective for parallel processing of large data blocks, such as the math-intensive data common in computer graphics applications, images, videos, etc.

[0548] The computer system 8500 may also include a main memory or primary memory 8508, such as random access memory (RAM). The main memory 8508 may include one or more levels of cache. The main memory 8508 may store control logic (e.g., computer software) and / or data therein.

[0549] The computer system 8500 may also include one or more secondary storage devices or memories 8510. The secondary memory 8510 may include, for example, a hard disk drive 8512 or a removable storage device or drive 8514. The removable storage drive 8514 may be a floppy disk drive, a magnetic disk drive, a tape drive, an optical disk drive, an optical storage device, a tape backup device, or any other storage device / drive.

[0550] The removable storage drive 8514 may interact with a removable storage unit 8518. The removable storage unit 8518 may include a computer-usable or readable storage device on which computer software (control logic) or data is stored. The removable storage unit 8518 may be a floppy disk, a magnetic tape, an optical disk, a DVD, an optical storage disk, or any other computer data storage device. The removable storage drive 8514 may read from or write to the removable storage unit 8518.

[0551] The secondary memory 8510 may include other components, devices, assemblies, means, or other methods that allow a computer program or other instructions or data to be accessed by the computer system 8500. Such components, devices, assemblies, means, or other methods may include, for example, removable storage units 8522 and interfaces 8520. Examples of removable storage units 8522 and interfaces 8520 may include program cartridges and cartridge interfaces (such as those found in video game devices), removable memory chips (such as EPROMs or PROMs) and associated sockets, memory sticks and USB ports, memory cards and associated memory card slots, or any other removable storage unit and associated interface.

[0552] The computer system 8500 may further include a communication or network interface 8524. The communication interface 8524 may enable the computer system 8500 to communicate and interact with any combination of external devices, external networks, external entities, etc. (collectively and individually referred to by reference numeral 8528). For example, the communication interface 8524 may allow the computer system 8500 to communicate with external or remote devices 8528 via a communication path 8526, which may be wired or wireless (or a combination thereof) and may include any combination of LAN, WAN, and the Internet. Control logic or data may be transmitted to and from the computer system 8500 via the communication path 8526.

[0553] By way of several non-limiting examples, the computer system 8500 may also be any one of a personal digital assistant (PDA), a desktop workstation, a portable computer or laptop, a netbook, a tablet computer, a smartphone, a smartwatch or other wearable device, a part of the Internet of Things, or an embedded system, or any combination thereof.

[0554] The computer system 8500 may be a client or a server that accesses or hosts any application or data by means of any delivery paradigm, including but not limited to remote or distributed cloud computing solutions; local or in-built software (cloud-based "in-built" solutions); "as-a-service" models (such as content as a service (CaaS), digital content as a service (DCaaS), software as a service (SaaS), managed software as a service (MSaaS), platform as a service (PaaS), desktop as a service (DaaS), framework as a service (FaaS), backend as a service (BaaS), mobile backend as a service (MBaaS), infrastructure as a service (IaaS), etc.); or a hybrid model that includes any combination of the above examples or other services or delivery paradigms.

[0555] Any suitable data structures, file formats, and schemes in the computer system 8500 can be exported according to standards including, but not limited to, JavaScript Object Notation (JSON), Extensible Markup Language (XML), another markup language (YAML), Extensible HyperText Markup Language (XHTML), Wireless Markup Language (WML), MessagePack, XML User Interface Language (XUL), or any other functionally similar representations used alone or in combination. Alternatively, proprietary data structures, formats, or schemes can be used exclusively or in combination with known or open standards.

[0556] In some embodiments, a tangible non-transitory device or article of manufacture including a tangible non-transitory computer-usable or readable medium having control logic (software) stored thereon may also be referred to herein as a computer program product or program storage device. This includes, but is not limited to, the computer system 8500, main memory 8508, secondary memory 8510, and removable storage units 8518 and 8522, and tangible articles embodying any combination of the foregoing. Such control logic, when executed by one or more data processing devices, such as the computer system 8500, can cause such data processing devices to operate as described herein.

[0557] Based on the teachings contained in this disclosure, it will be apparent to those skilled in the relevant art how to make and use embodiments of this disclosure using other means than those Figure 85 data processing devices, computer systems, or computer architectures shown. Specifically, the embodiments can operate with software, hardware, and / or operating system implementations other than those described herein.

[0558] Conclusion

[0559] The EP recording system disclosed herein effectively removes noise and removes or isolates unwanted large signals while preserving the relevant components of the original small signal, i.e., while preserving the integrity of the original information in an EP environment. Conventional EP systems can successfully filter out noise, but can also filter out signal components with noise that a medical team would like to see. Conventional EP systems may also use good software filtering algorithms to generate and introduce additional noise and unwanted artifacts that do not exist in the original noise. Even when conventional EP systems employ the latest noise reduction methods, conventional EP systems are unable to effectively collect pure small signals with high confidence in the presence of large signal processes such as defibrillation and ablation. This is because conventional EP systems do not have a comprehensive signal acquisition and filtering solution across relevant frequency ranges (low (e.g., 0 to 100 Hz), medium (e.g., above 100 Hz to below 300 kHz), and high (e.g., above 300 kHz (including 300 kHz)) and are unable to effectively handle synchronous signals that differ by orders of magnitude of 100s or 1000s. In contrast, the EP recording system disclosed herein integrates and applies novel hardware circuits, software methods, and system topologies to remove unwanted signals, but preserves the original signal waveform of signals found in an EP environment across relevant frequency ranges.

[0560] The disclosed EP system does not have to make the compromises that conventional EP systems have to make. Instead, the disclosed EP system allows aspects of the hardware and software to be performed in series to simultaneously: (1) run an amplifier at high gain to see small signals; (2) prevent clipping and saturation by minimizing destructive large signal filtering in the hardware to see large signals at the same time, (3) process the signals, separate them from each other in separate displays, remove any residual noise and synchronize the separated signals, and finally (4) enable a user to manipulate and analyze both large and small signals such that signal artifacts and events can be precisely time event related.

[0561] Figures 22A - 22B Exemplary signal 2200 illustrates these concepts, which show improvements in the visualization of an ECG or IC cardiac signal in the presence of large transients, ablation signals, defibrillation signals, and EP environmental noise after being acquired, filtered, and processed by the disclosed EP system. Figure 22A Shows the removal of noise from both small and large signals, and the avoidance of clipping when processing large signals. Conventional EP systems can provide a noisy cardiac signal 2203 and artificially clip signal 2202 to limit the amplitude of the displayed signal to avoid the effects of saturation. The disclosed EP system acquires and clearly displays weak signal 2214 and strong signal 2205. With the disclosed EP system, no artificial clipping is required, and strong signal 2204 is fully defined (not clipped).

[0562] Figure 22B It is illustrated that in the presence of noise and large-signal processes, the EP system can reveal the micro-components of low-amplitude cardiac signals and EP-signal-related random artifacts. Window 2216 illustrates a noisy signal 2208 with high-amplitude and low-amplitude micro-components 2206 of the desired signal revealed by the disclosed EP system. In contrast, as shown in window 2218, a conventional EP system may not be able to successfully reveal the low-amplitude and high-amplitude micro-components of the desired signal. In the case of a more noisy signal, the low-amplitude micro-component 2210 of the desired signal can be revealed, but in a conventional EP system, it is more likely to be lost in the noise 2212. The high-amplitude micro-component 2211 of the desired signal may be lost in a conventional EP system through artificial clipping.

[0563] Figure 22C It is illustrated that the disclosed EP system can remove 60 Hz noise 2220 without saturation or delayed recovery, while preserving the component 2222 of the 60 Hz signal that belongs to the original waveform 2224. Specifically, the component 2222 of the original waveform 2224 that occurs simultaneously with the artifact 2220 is not lost. In other words, when a large signal overlaps with a small signal simultaneously, the disclosed EP system can cleanly identify, acquire, and process both.

[0564] It should be understood that the detailed description section, rather than any other section, is intended to interpret the claims. Other sections may set forth one or more but not all exemplary embodiments contemplated by the inventors, and thus are not intended to limit the present disclosure or the appended claims in any way.

[0565] Although the present disclosure describes exemplary embodiments of exemplary fields and applications, it should be understood that the present disclosure is not limited thereto. Other embodiments and their modifications are possible and within the scope and spirit of the present disclosure. For example, and without limiting the generality of this paragraph, the embodiments are not limited to the software, hardware, firmware, or entities illustrated in the figures or described herein. Additionally, the embodiments (whether or not explicitly described herein) have significant utility for fields and applications other than those described by way of example herein.

[0566] The embodiments have been described herein by means of functional building blocks that illustrate the implementation of specific functions and their relationships. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined herein. Alternative boundaries can be defined as long as the specified functions and relationships (or their equivalents) are properly executed. Moreover, alternative embodiments can execute the functional blocks, steps, operations, methods, etc. in a different order than that described herein. The present disclosure also extends to methods associated with using or otherwise implementing the features of the hardware and systems disclosed herein.

[0567] References in this specification to "one embodiment", "an embodiment", "an exemplary embodiment" or similar phrases indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, the incorporation of such feature, structure, or characteristic into other embodiments, whether or not explicitly mentioned or described herein, will be within the knowledge of those skilled in the art. Additionally, some embodiments may use the terms "coupled" and "connected" and their derivatives to describe. These terms are not necessarily synonyms of each other. For example, some embodiments may use the term "connected" or "coupled" to describe to indicate that two or more elements are in direct physical or electrical contact with each other. However, the term "coupled" may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0568] The breadth and scope of the present disclosure should not be limited by any of the above exemplary embodiments, but should be defined only in accordance with the appended claims and their equivalents.

Claims

1. A system for performing electrophysiological (EP) processing, comprising: An electrocardiogram (ECG) circuit board configured to receive an ECG signal, wherein the ECG circuit board includes a large-signal detection circuit and a differential signal amplification stage, wherein the differential signal amplification stage is configured to amplify the ECG signal for outputting an output ECG signal, and the large-signal detection circuit is coupled to the differential signal amplification stage and is configured to remove signal saturation from the output ECG signal based on a time constant, wherein the time constant specifies a length of time that the output ECG signal is at a maximum amplitude; A plurality of intracardiac IC circuit boards, each configured to receive a corresponding IC signal; A communication interface communicatively coupled to a remote device; And A processor coupled to the ECG circuit board, the plurality of IC circuit boards, and the communication interface, the processor being configured to: Receive feedback from the remote device via the communication interface; And Control the remote device via the communication interface based on the ECG signal, the plurality of IC signals, or the feedback from the remote device.

2. The system of claim 1, wherein the remote device is selected from the group consisting of: an ultrasound machine, a radio frequency (RF) generator, a stimulator, a three-dimensional imaging device, an intracardiac echocardiogram (ICE) machine, a fluoroscopy machine, and a defibrillator.

3. The system of claim 1, wherein the communication interface is communicatively coupled to the remote device using a communication protocol selected from the group consisting of: Digital Imaging and Communications in Medicine (DICOM), Ethernet, Universal Serial Bus (USB), and Institute of Electrical and Electronics Engineers (IEEE) 802.

11.

4. The system of claim 1, wherein the ECG circuit board includes an input protection circuit configured to shunt a voltage of the ECG signal that is greater than or equal to 300V.

5. The system of claim 1, wherein the ECG circuit board includes a radio frequency (RF) filter circuit configured to attenuate an amplitude of the ECG signal between approximately 300 kHz and approximately 600 kHz.

6. The system of claim 4, wherein the ECG circuit board further includes a radio frequency (RF) filter circuit configured to attenuate an amplitude of the ECG signal between approximately 300 kHz and approximately 600 kHz.

7. The system of claim 5, wherein the ECG circuit board further includes a low-frequency feedback circuit coupled to the RF filter circuit, wherein the low-frequency feedback circuit is configured to drive a voltage of a reference node of the RF filter circuit to increase an input impedance of a signal frequency of the ECG signal, such that the RF filter circuit is configured as an open circuit at the signal frequency of the ECG signal.

8. The system according to claim 6, wherein the ECG circuit board further includes a low-frequency feedback circuit coupled to the RF filter circuit, and the low-frequency feedback circuit is configured to drive the voltage of the reference node of the RF filter circuit to increase the input impedance of the signal frequency of the ECG signal, so that the RF filter circuit is configured as an open circuit at the signal frequency of the ECG signal.

9. The system according to claim 6, wherein the ECG circuit board further includes a buffer.

10. The system according to claim 9, wherein the differential signal amplification stage includes an instrumentation amplifier, a first differential amplifier, and a second differential amplifier, wherein the output of the instrumentation amplifier has a differential gain of about 20, the output of the first differential amplifier has a differential gain of about 1, and the output of the second differential amplifier has a differential gain of about 0.5.

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