Method for preparing double-layer thick film high-resistance single crystal epitaxial wafer for semiconductor devices

Abstract

The present invention discloses a method for preparing a double-layer thick film high-resistance single crystal epitaxial wafer for semiconductor devices. By comprehensively designing key process parameters such as growth temperature and its fluctuation range, growth rate, temperature rise and fall time, base rotation speed, and acceleration that are different from those of traditional epitaxial processes, the double-layer thick film high-resistance epitaxial process is overcome, which is prone to generate edge polycrystalline particles, slip lines, and even crack-induced defects. The significant effect of batch growing double-layer thick film high-resistance single crystal epitaxial wafers on 6-inch and 8-inch silicon substrates is achieved. By setting the flow rate of hydrogen in the reaction chamber and designing and controlling the radial temperature gradient of the wafer pit in the graphite base, the uniformity of the double-layer thick film high-resistance epitaxial layer is significantly improved. The resistivity non-uniformity of the five-point test reaches <0.8%, and the thickness non-uniformity of the five-point test reaches <0.6%, which meets the use requirements of high-voltage and high-power semiconductor devices and is conducive to large-scale promotion and application.

Description

Technical Field

[0001] The present invention belongs to the preparation of single crystal epitaxial wafers for semiconductor devices, and in particular relates to a method for preparing double-layer thick-film high-resistance single crystal epitaxial wafers for semiconductor devices. Background Art

[0002] With the mature use and reliable performance of semiconductor silicon materials and semiconductor device manufacturing technology, silicon single crystal epitaxial materials are widely used in high-voltage and high-power devices such as 650V, 1200V IGBT, FRED, and are widely used in various fields such as high-voltage DC transmission, high-voltage frequency conversion, AC transmission locomotives / EMUs, urban rail transit, photovoltaic and wind power generation, new energy vehicles, energy storage, data centers, etc.

[0003] Currently, high-voltage, high-power devices fabricated on single-crystal silicon epitaxial wafers are developing with a focus on high reverse withstand voltage and high forward current. Conventional silicon epitaxial wafers are thick, high-resistance single-layer wafers composed of a silicon substrate and a silicon epitaxial layer. This inherently presents compatibility issues between saturation withstand voltage and switching parameters. To address these issues, the industry has developed alternatives using double-layer silicon epitaxial wafers. For example, the 6-inch and 8-inch double-layer silicon epitaxial wafers used in 650V and 1200V IGBT and FRED devices feature a first, thin, low-resistance silicon epitaxial layer, known as the buffer layer, and a second, thicker, high-resistance silicon epitaxial layer, known as the functional layer. The total thickness of the double-layer silicon epitaxial layer with the buffer layer is 90-100 μm, and the resistivity ratio between the first and second silicon epitaxial layers reaches 8-10 times. This offers the advantage of both high reverse withstand voltage and improved forward current characteristics. However, the double-layer silicon epitaxial layer structure is more complex, significantly increasing the difficulty in designing and controlling key process parameters.

[0004] Based on the consistency requirements of key parameters of high-voltage and high-power devices such as saturation withstand voltage (BV) and switch conduction (VF), the resistivity non-uniformity of the double-layer thick-film high-resistance silicon epitaxial layer at five test points must be <0.8%, and the thickness non-uniformity at five test points must be <0.6%. This places very strict process control requirements on epitaxial parameter uniformity and single crystal integrity, requiring the development of an epitaxial growth process suitable for industrial mass production. This significantly increases the difficulty of achieving double-layer thick-film high-resistance silicon epitaxial layers. In terms of parameter uniformity, due to the 6-inch and 8-inch silicon substrates used, the growth process of the double-layer thick-film high-resistance silicon epitaxial layer is affected by the inherent distribution gradients of the growth flow field and thermal field of the original epitaxial layer, as well as the gradual accumulation of impurity effects inherent in the reaction environment. This ultimately leads to the continuous deterioration of the thickness and resistivity uniformity of the thick-film high-resistance silicon epitaxial layer, and even makes it difficult to control. Based on the parameter ranges for thick-film, high-resistance single-crystal epitaxial layers specified in the current national standard GB / T14139-2019, "Silicon Epitaxial Wafers," the resistivity non-uniformity control capability for silicon epitaxial layers is <8% and the thickness non-uniformity control capability is <5%. This falls significantly short of the required resistivity non-uniformity of <0.8% and thickness non-uniformity of <0.6% for silicon epitaxial layers used in high-voltage, high-power devices. In terms of crystal integrity, double-layer thick-film epitaxial growth (90-100μm) is more complex than conventional single-layer thin-film epitaxial growth (less than 30μm). The growth process takes longer, and mechanical and thermal stress control is more challenging. This increases the likelihood of epitaxial-induced defects such as edge polycrystalline grains and slip lines. This requires stricter control of key process parameters in the silicon epitaxial furnace used for silicon epitaxial layer growth, including process temperature, growth rate, cooling time, susceptor rotation speed, and acceleration. Therefore, double-layer thick-film, high-resistance single-crystal epitaxial wafers produced using conventional processes cannot meet these requirements, requiring further design and control of the flow and thermal fields within the reactor chamber.

[0005] Currently, thick-film, high-resistance, and multi-layer silicon epitaxial wafers use a process such as the Chinese patent publication number CN 117626425B, which discloses a method for preparing 8-inch silicon epitaxial wafers for IGBTs: first, rapid growth at high temperature and high flow rate, followed by medium-speed growth at low temperature and high flow rate, and then slow growth at low temperature and low flow rate. This multi-stage growth can effectively release the internal potential energy and lattice distortion accumulated during the medium and high-speed growth stages, reducing the risk of silicon epitaxial wafer cracking. However, this patented process method requires ensuring that the main parameters of odd-numbered wafers are distributed outward and the main parameters of even-numbered wafers are distributed inward during the loading stage. The process is relatively complex to implement and is not suitable for mass industrial production of the present invention.

[0006] Chinese patent publication number CN118241309B discloses a method for preparing ultra-thick silicon epitaxial wafers. By comprehensively designing parameters such as the hydrogen flow rate, growth rate, and growth temperature required for the silicon epitaxial layer, the technical problem of cracking in ultra-thick silicon epitaxial wafers with a thickness of 200-230 μm is reduced. However, the growth rate of ultra-thick silicon epitaxial wafers is 1.5-1.6 μm / min, and the slow growth results in a long process time, making it unsuitable for mass industrial production of the present invention.

[0007] Chinese patent publication number CN103354242B discloses an extremely thick epitaxial wafer for high-voltage power devices and a method for manufacturing the same. The method employs a two-step heating process: the first step involves heating the wafer from room temperature to 950-1000°C at a rate of 80-120°C / min, and the second step involves heating the wafer to the silicon epitaxial layer growth temperature at a rate of 10-20°C / min. This significantly extends the heating time, reduces deformation of the wafer, and enables the preparation of silicon epitaxial wafers with a thickness greater than 100 μm. However, this two-step heating process significantly prolongs the heating time, making it unsuitable for mass industrial production.

[0008] Therefore, high-voltage and high-power devices require a method for preparing double-layer thick-film high-resistance single-crystal epitaxial wafers with good parameter uniformity and stability, simple process and adaptability to industrial continuous production requirements. Summary of the Invention

[0009] In view of the existing technical conditions and existing problems, the present invention provides a method for preparing double-layer thick-film high-resistance single-crystal epitaxial wafers for semiconductor devices. This method solves the problem that the uniformity of the epitaxial layer thickness and resistivity parameters and the integrity of the single crystal are difficult to control well during the growth process of traditional 6-inch and 8-inch double-layer thick-film high-resistance silicon epitaxial wafers in a flat-plate multi-wafer silicon epitaxial furnace. In order to overcome thermal stress, mechanical stress accumulation effect, edge deformation and other reasons, slow growth and two-step heating process methods need to be adopted, which affects industrial continuous production. The present invention adopts the North Huachuang 630 model flat-plate multi-wafer silicon epitaxial furnace, and the comprehensive design is different from the traditional double-layer epitaxial process temperature, growth rate, heating time, cooling time and other key process parameters. The grown double-layer thick-film high-resistance silicon epitaxial wafer achieves the remarkable effect of resistivity non-uniformity <0.8% in five-point test, thickness non-uniformity <0.6% in five-point test, and no polycrystalline particles, slip lines, or crack-induced defects on the edge. It meets the use requirements of high-voltage and high-power semiconductor devices and is conducive to large-scale promotion and application.

[0010] The technical solution adopted by the present invention is: a method for preparing a double-layer thick film high-resistance single crystal epitaxial wafer for semiconductor devices comprises the following steps in sequence:

[0011] S1. Hydrogen chloride gas and hydrogen are introduced into the reaction chamber and the graphite base of the silicon epitaxial furnace for high-temperature etching and cleaning. The deposits and impurity adsorption inside the etching reaction chamber and on the surface of the graphite base are etched to suppress the impurity accumulation effect of the reaction environment. The reaction chamber temperature of the silicon epitaxial furnace is 1130~1160℃, the flow rate of hydrogen chloride gas is 30~35L / min, the flow rate of hydrogen is 5~10L / min, and the etching and cleaning time is 15~16 min. Subsequently, hydrogen is introduced to carry trichlorosilane to grow a polycrystalline silicon coating layer inside the reaction chamber and on the surface of the graphite base. The flow rate of hydrogen is 150~200L / min, the flow rate of trichlorosilane is 13~14g / min, the reaction chamber temperature is 1020~1060℃, and the thickness of the polycrystalline silicon coating layer is 1~2μm.

[0012] S2. Cool the reaction chamber of the silicon epitaxial furnace to 250-300°C, slowly raise the initial temperature of the reaction chamber to 1060-1110°C for 900-1000 seconds, bake the surface of the silicon substrate at high temperature for 1-3 minutes, and then purge the reaction chamber with hydrogen at a flow rate of 250-300 L / min for 1-3 minutes.

[0013] S3. Growing a first silicon epitaxial layer on the polished surface of the silicon substrate at a growth temperature of 1010-1020° C. to form a single crystal silicon epitaxial layer. Using hydrogen to carry trichlorosilane as a silicon growth source, phosphine as a doping gas, the flow rate of trichlorosilane is 10-12 g / min, the flow rate of hydrogen is 165-185 L / min, the flow rate of phosphine is 125-130 sccm, the growth rate of the silicon epitaxial layer is 1.8-2.0 μm / min, the susceptor rotation speed is 5-6 r / min, and the acceleration of the susceptor rotation speed is 0.4-0.5 r / min. 2 The target growth thickness of the first silicon epitaxial layer is 30~35μm, the target resistivity is 2.5~3.5Ω·cm, and the temperature fluctuation during the growth of the silicon epitaxial layer is ≤3℃.

[0014] S4. Growing a second silicon epitaxial layer on the surface of the first silicon epitaxial layer, using hydrogen carrying trichlorosilane as a growth silicon source, phosphine as a doping gas, and a growth temperature of 1020-1040°C to form a single crystal silicon epitaxial layer. The flow rate of trichlorosilane is 13-14 g / min, the flow rate of hydrogen is 165-185 L / min, the flow rate of phosphine is 55-60 sccm, the growth rate of the silicon epitaxial layer is 2.1-2.2 μm / min, the target growth thickness of the second silicon epitaxial layer is 60-65 μm, the target resistivity is 22-26 Ω·cm, and the temperature fluctuation during the growth of the silicon epitaxial layer is ≤3°C.

[0015] S5. Nitrogen is introduced to purge and cool the reaction chamber. The nitrogen flow rate is 100~150L / min. The reaction chamber is slowly cooled from the initial temperature to 250~300℃ for 900~1000sec. The resistivity non-uniformity of the target double-layer thick film high-resistance single crystal epitaxial wafer is <0.8% in a five-point test, and the thickness non-uniformity is <0.6% in a five-point test. The positions of the five-point test are the center point and four points 6mm away from the edge at the top, bottom, left, and right. Finally, a double-layer thick film high-resistance single crystal epitaxial wafer is formed.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] 1. The NAURA 630 flat-plate multi-wafer silicon epitaxial furnace is used. Its comprehensive design differs from the traditional double-layer epitaxial process in terms of key process parameters such as temperature, growth rate, heating time, and cooling time. This overcomes the traditional thick-film epitaxial process, which easily generates polycrystalline particles, slip lines, and crack-induced defects at the edge.

[0018] 2. Achieved good parameter uniformity of single-crystal epitaxial wafers, comprehensively designed the flow field and thermal field for double-layer thick film high-resistance epitaxial growth, and designed a method to suppress the impurity accumulation effect in the reaction environment. The technical advantages of achieving a resistivity non-uniformity of <0.8% in five-point testing of single-crystal epitaxial wafers and a thickness non-uniformity of <0.6% in five-point testing were achieved to meet the needs of high-voltage and high-power devices.

[0019] 3. The traditional process has been simplified, the process is simple, the cost of industrial continuous production has been reduced, and batch epitaxial growth of double-layer thick-film high-resistance single-crystal epitaxial wafers on 6-inch and 8-inch silicon substrates has been achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a schematic diagram of the resistivity distribution of the second silicon epitaxial layer produced in Example 1 of the present invention at five points;

[0021] Figure 2 Schematic diagram of total thickness distribution of a silicon epitaxial layer produced in Example 1 of the present invention after five-point testing;

[0022] Figure 3 A schematic diagram of the resistivity distribution of the second silicon epitaxial layer produced in Example 2 of the present invention at five points during testing;

[0023] Figure 4 Schematic diagram of total thickness distribution of a silicon epitaxial layer produced in Example 2 of the present invention after five-point testing;

[0024] Figure 5 A schematic diagram of the resistivity distribution of the second silicon epitaxial layer produced in Example 3 of the present invention at five points during testing;

[0025] Figure 6Schematic diagram of total thickness distribution of a silicon epitaxial layer produced in Example 3 of the present invention after five-point testing;

[0026] Figure 7 A schematic diagram of the resistivity distribution of the second silicon epitaxial layer produced in Example 4 of the present invention at five points during testing;

[0027] Figure 8 Schematic diagram of total thickness distribution of a silicon epitaxial layer produced in Example 4 of the present invention after five-point testing;

[0028] Figure 9 A schematic diagram of the resistivity distribution of the second silicon epitaxial layer produced in Example 5 of the present invention at five points during testing;

[0029] Figure 10 Schematic diagram of total thickness distribution of a silicon epitaxial layer produced in Example 5 of the present invention after five-point testing;

[0030] Figure 11 A schematic diagram of the resistivity distribution of the second silicon epitaxial layer produced in Comparative Example 2 of the present invention at five points during testing;

[0031] Figure 12 A schematic diagram of the resistivity distribution of the second silicon epitaxial layer produced in Comparative Example 3 of the present invention at five points;

[0032] Figure 13 This is a schematic diagram of the total thickness distribution of the silicon epitaxial layer produced in Comparative Example 6 of the present invention in a five-point test. DETAILED DESCRIPTION

[0033] The technical solution of the present invention is described clearly and completely below in conjunction with the embodiments and drawings.

[0034] A method for preparing a double-layer thick-film high-resistance single-crystal epitaxial wafer for semiconductor devices comprises the following steps in sequence:

[0035] S1. Using the North Huachuang 630 flat-plate multi-wafer silicon epitaxial furnace, hydrogen chloride gas and hydrogen are introduced to perform high-temperature etching and cleaning on the reaction chamber and graphite base of the silicon epitaxial furnace, etching the sediments and impurity adsorption inside the reaction chamber and on the surface of the graphite base, and suppressing the impurity accumulation effect of the reaction environment. The reaction chamber temperature of the silicon epitaxial furnace is 1130~1160℃, the radial temperature gradient of the slice pit in the graphite base is ≤3℃, the flow rate of hydrogen chloride gas is 30~35L / min, the flow rate of hydrogen is 5~10L / min, and the etching and cleaning time is 15~16min. Then, hydrogen is introduced to carry trichlorosilane to grow a polysilicon coating inside the reaction chamber and on the surface of the graphite base. The flow rate of hydrogen is 150~200L / min, and the flow rate of trichlorosilane is 13~14 g / min, the reaction chamber temperature is 1020~1060℃, and the thickness of the polysilicon coating layer is 1~2μm, which further suppresses the impurity accumulation effect in the reaction environment.

[0036] S2. The reaction chamber of the silicon epitaxial furnace is cooled to 250-300°C to reduce the displacement of the subsequent silicon substrate when it is placed in the sheet pit of the graphite base of the reaction chamber. The initial temperature of the reaction chamber is slowly raised to 1060-1110°C for 900-1000 seconds to reduce the accumulation effect of thermal stress on the silicon substrate during the heating process, which leads to edge deformation, slip lines, and crack-induced defects. The surface of the silicon substrate is baked at high temperature for 1-3 minutes, and then the reaction chamber is purged with hydrogen at a flow rate of 250-300 L / min for 1-3 minutes to remove the natural oxide layer on the surface of the silicon substrate to prevent epitaxial growth of polycrystalline particles.

[0037] The silicon substrate is 6-inch or 8-inch silicon substrate with crystal orientation of <100> , the resistivity is 1~4 Ω·cm, the oxygen content is 8~14ppma, the front side of the silicon substrate is polished, and the back side is covered with a 450~550nm thick silicon dioxide backing layer. The removal amount of the edge silicon dioxide backing layer is 0.8~1.0mm, which is used to prevent the epitaxial growth of polycrystalline grains at the edge. The edge chamfer angle is 22°, the chamfer morphology is R-type, and the edge chamfer width is 400~450μm, which is used to reduce the formation of edge cracks.

[0038] S3. Grow the first silicon epitaxial layer on the polished surface of the silicon substrate at a growth temperature of 1010-1020°C to form a single crystal silicon epitaxial layer. Use hydrogen to carry trichlorosilane as the silicon growth source, and phosphine as the doping gas. The flow rate of trichlorosilane is 10-12 g / min, the flow rate of hydrogen is 165-185 L / min, the flow rate of phosphine is 125-130 sccm, the growth rate of the silicon epitaxial layer is 1.8-2.0 μm / min, the susceptor speed is 5-6 r / min, and the acceleration of the susceptor speed is 0.4-0.5 r / min. 2 It is used to reduce the offset of the silicon substrate position in the wafer pit and reduce the mechanical stress accumulation effect of the silicon epitaxial layer. The target growth thickness of the first silicon epitaxial layer is 30~35μm, the target resistivity is 2.5~3.5Ω·cm, and the temperature fluctuation during the growth of the silicon epitaxial layer is ≤3℃. It is used to reduce the accumulation effect of thermal stress during the growth of the silicon epitaxial layer, which leads to edge deformation, slip lines, and crack-induced defects.

[0039] S4. A second silicon epitaxial layer is grown on the surface of the first silicon epitaxial layer, using hydrogen carrying trichlorosilane as a growth silicon source, phosphine as a doping gas, and a growth temperature of 1020-1040°C to form a single crystal silicon epitaxial layer. The flow rate of trichlorosilane is 13-14 g / min, the flow rate of hydrogen is 165-185 L / min, the flow rate of phosphine is 55-60 sccm, and the growth rate of the silicon epitaxial layer is 2.1-2.2 μm / min. The target growth thickness of the second silicon epitaxial layer is 60-65 μm, and the target resistivity is 22-26 Ω·cm. The temperature fluctuation during the growth of the silicon epitaxial layer is ≤3°C, which is used to reduce the accumulation effect of thermal stress during the growth of the silicon epitaxial layer, which leads to edge deformation, slip lines, and crack-induced defects.

[0040] S5. Nitrogen is introduced to purge and cool the reaction chamber. The nitrogen flow rate is 100~150L / min. The reaction chamber is slowly cooled from the initial temperature to 250~300℃ for 900~1000sec to release the thermal stress of the single crystal epitaxial wafer and reduce the edge deformation and the occurrence of slip lines and crack-induced defects. The five-point test resistivity non-uniformity of the target double-layer thick film high-resistance single crystal epitaxial wafer is <0.8%, and the five-point test thickness non-uniformity is <0.6%. The positions of the five-point test are the center point and four points 6mm away from the edge at the top, bottom, left and right, which meet the thickness and resistivity uniformity of the silicon epitaxial layer. There are no polycrystalline particles, slip lines, and crack-induced defects at the edge, and finally a double-layer thick film high-resistance single crystal epitaxial wafer is formed.

[0041] Example 1: A method for preparing a double-layer thick-film high-resistance single-crystal epitaxial wafer for a semiconductor device of this embodiment comprises the following steps in sequence:

[0042] S1. Hydrogen chloride gas and hydrogen are introduced to perform high-temperature etching and cleaning on the reaction chamber and graphite base of the silicon epitaxial furnace, etching the deposits and impurity adsorption inside the reaction chamber and on the surface of the graphite base, and suppressing the impurity accumulation effect of the reaction environment. The reaction chamber temperature of the silicon epitaxial furnace is 1160°C, the radial temperature gradient of the sheet pit in the graphite base is 3°C, the flow rate of hydrogen chloride gas is 35L / min, the flow rate of hydrogen is 5L / min, and the etching and cleaning time is 15min. Subsequently, hydrogen is introduced to carry trichlorosilane to grow a polysilicon coating inside the reaction chamber and on the surface of the graphite base. The flow rate of hydrogen is 150L / min, the flow rate of trichlorosilane is 13g / min, the temperature of the reaction chamber is 1060°C, and the thickness of the polysilicon coating is 2μm, further suppressing the impurity accumulation effect of the reaction environment.

[0043] S2. The reaction chamber of the silicon epitaxial furnace is cooled to 250°C to reduce the displacement of the subsequent silicon substrate when it is placed in the sheet pit of the graphite base of the reaction chamber. The initial temperature of the reaction chamber is slowly raised to 1060°C for 1000 seconds to reduce the accumulation effect of thermal stress on the silicon substrate during the heating process, which leads to edge deformation, slip lines, and crack-induced defects. The surface of the silicon substrate is baked at high temperature for 3 minutes, and then the reaction chamber is purged with hydrogen at a flow rate of 300 L / min for 3 minutes to remove the natural oxide layer on the surface of the silicon substrate to prevent epitaxial growth of polycrystalline particles.

[0044] S3. Grow the first silicon epitaxial layer on the polished surface of the silicon substrate at a growth temperature of 1020°C to form a single crystal silicon epitaxial layer. Use hydrogen to carry trichlorosilane as the silicon growth source, and phosphine as the doping gas. The flow rate of trichlorosilane is 10 g / min, the flow rate of hydrogen is 180 L / min, and the flow rate of phosphine is 125 sccm. The growth rate of the silicon epitaxial layer is 1.9 μm / min, the susceptor speed is 5 r / min, and the acceleration of the susceptor speed is 0.4 r / min. 2 It is used to reduce the offset of the silicon substrate position in the wafer pit and reduce the mechanical stress accumulation effect of the silicon epitaxial layer. The temperature fluctuates by 3°C during the growth of the silicon epitaxial layer. It is used to reduce the accumulation effect of thermal stress during the growth of the silicon epitaxial layer, which leads to edge deformation, slip lines, and crack-induced defects.

[0045] S4. A second silicon epitaxial layer is grown on the surface of the first silicon epitaxial layer. Hydrogen is used to carry trichlorosilane as a growth silicon source, phosphine is used as a doping gas, and the growth temperature is 1040°C to form a single crystal silicon epitaxial layer. The flow rate of trichlorosilane is 13g / min, the flow rate of hydrogen is 180L / min, the flow rate of phosphine is 55sccm, and the growth rate of the silicon epitaxial layer is 2.15μm / min. The temperature fluctuates by 3°C during the growth of the silicon epitaxial layer to reduce the accumulation of thermal stress during the growth of the silicon epitaxial layer, which leads to edge deformation, slip lines, and crack-induced defects.

[0046] S5. Nitrogen is introduced to purge and cool the reaction chamber. The nitrogen flow rate is 100L / min. The reaction chamber is slowly cooled from the initial temperature to 250°C for 1000 seconds to release the thermal stress of the single crystal epitaxial wafer and reduce the edge deformation and the occurrence of slip lines and crack-induced defects. The five-point test positions are the center point and four points 6mm away from the edge: the top, bottom, left, and right points. The thickness and resistivity uniformity of the silicon epitaxial layer are met, and there are no polycrystalline particles, slip lines, and crack-induced defects on the edge. Finally, a double-layer thick film high-resistance single crystal epitaxial wafer is formed.

[0047] The thickness and resistivity of the single crystal epitaxial wafer prepared in Example 1 were measured at five test points, namely the center point and four points 6 mm from the edge, namely the top, bottom, left, and right points. The resistivity distribution diagram of the second silicon epitaxial layer is shown in FIG. Figure 1 As shown, the resistivities of the second silicon epitaxial layer are 23.866Ω·cm, 23.534Ω·cm, 23.523Ω·cm, 23.623Ω·cm, and 23.544Ω·cm, respectively. The resistivity non-uniformity of the five-point test reaches 0.68%. The total thickness distribution diagram of the silicon epitaxial layer is shown in Figure 2 As shown, the thicknesses of the silicon epitaxial layers are 98.592 μm, 97.958 μm, 99.053 μm, 98.454 μm, and 98.562 μm, respectively. The thickness non-uniformity of the five-point test reaches 0.56%, and there are no polycrystalline particles, slip lines, or crack-induced defects on the edges, which meets the requirements of the present invention.

[0048] Example 2: A method for preparing a double-layer thick-film high-resistance single-crystal epitaxial wafer for a semiconductor device of this embodiment comprises the following steps in sequence:

[0049] S1. Hydrogen chloride gas and hydrogen are introduced to perform high-temperature etching and cleaning on the reaction chamber and graphite base of the silicon epitaxial furnace, etching the deposits and impurity adsorption inside the reaction chamber and on the surface of the graphite base, and suppressing the impurity accumulation effect of the reaction environment. The reaction chamber temperature of the silicon epitaxial furnace is 1130°C, the radial temperature gradient of the sheet pit in the graphite base is 2°C, the flow rate of hydrogen chloride gas is 35L / min, the flow rate of hydrogen is 5L / min, and the etching and cleaning time is 15min. Subsequently, hydrogen is introduced to carry trichlorosilane to grow a polycrystalline silicon coating layer inside the reaction chamber and on the surface of the graphite base. The flow rate of hydrogen is 200L / min, the flow rate of trichlorosilane is 14g / min, the temperature of the reaction chamber is 1060°C, and the thickness of the polycrystalline silicon coating is 2μm, further suppressing the impurity accumulation effect of the reaction environment.

[0050] S2. The reaction chamber of the silicon epitaxial furnace is cooled to 250°C to reduce the displacement of the subsequent silicon substrate when it is placed in the sheet pit of the graphite base of the reaction chamber. The initial temperature of the reaction chamber is slowly raised to 1060°C for 900 seconds to reduce the accumulation effect of thermal stress on the silicon substrate during the heating process, which leads to edge deformation, slip lines, and crack-induced defects. The surface of the silicon substrate is baked at high temperature for 1 minute, and then the reaction chamber is purged with hydrogen at a flow rate of 300 L / min for 1 minute to remove the natural oxide layer on the surface of the silicon substrate to prevent epitaxial growth of polycrystalline particles.

[0051] S3. Grow the first silicon epitaxial layer on the polished surface of the silicon substrate at a growth temperature of 1010°C to form a single crystal silicon epitaxial layer. Use hydrogen to carry trichlorosilane as the silicon growth source, phosphine as the doping gas, the flow rate of trichlorosilane is 12 g / min, the flow rate of hydrogen is 185 L / min, the flow rate of phosphine is 125 sccm, the growth rate of the silicon epitaxial layer is 1.94 μm / min, the susceptor speed is 5 r / min, and the acceleration of the susceptor speed is 0.5 r / min. 2 , reduce the offset of the silicon substrate position in the wafer pit, reduce the mechanical stress accumulation effect of the silicon epitaxial layer, and the temperature fluctuates by 3°C during the growth of the silicon epitaxial layer, which is used to reduce the accumulation effect of thermal stress during the growth of the silicon epitaxial layer, resulting in edge deformation, slip lines, and crack-induced defects.

[0052] S4. A second silicon epitaxial layer is grown on the surface of the first silicon epitaxial layer. Hydrogen is used to carry trichlorosilane as a growth silicon source, phosphine is used as a doping gas, and the growth temperature is 1040°C to form a single crystal silicon epitaxial layer. The flow rate of trichlorosilane is 14g / min, the flow rate of hydrogen is 185L / min, and the flow rate of phosphine is 55sccm. The growth rate of the silicon epitaxial layer is 2.18μm / min. The temperature fluctuates by 3°C during the growth of the silicon epitaxial layer to reduce the accumulation effect of thermal stress during the growth of the silicon epitaxial layer, which leads to edge deformation, slip lines, and crack-induced defects.

[0053] S5. Nitrogen is introduced to purge and cool the reaction chamber. The nitrogen flow rate is 100L / min. The reaction chamber is slowly cooled from the initial temperature to 250°C for 900 seconds to release the thermal stress of the single crystal epitaxial wafer and reduce the edge deformation and the occurrence of slip lines and crack-induced defects. The five-point test positions are the center point and four points 6mm away from the edge: the top, bottom, left, and right points. The thickness and resistivity uniformity of the silicon epitaxial layer are met, and there are no polycrystalline particles, slip lines, and crack-induced defects on the edge. Finally, a double-layer thick film high-resistance single crystal epitaxial wafer is formed.

[0054] The thickness and resistivity of the single crystal epitaxial wafer prepared in Example 2 were measured at five test points, namely the center point and four points 6 mm from the edge, namely the top, bottom, left, and right points. The resistivity distribution diagram of the second silicon epitaxial layer is shown in FIG. Figure 3 As shown, the resistivities of the second silicon epitaxial layer are 23.626Ω·cm, 23.432Ω·cm, 23.327Ω·cm, 23.345Ω·cm, and 23.435Ω·cm, respectively. The resistivity non-uniformity of the five-point test reaches 0.64%. The total thickness distribution diagram of the silicon epitaxial layer is shown in FIG. Figure 4As shown, the thicknesses of the silicon epitaxial layers are 98.662 μm, 98.221 μm, 98.986 μm, 98.553 μm, and 98.526 μm, respectively. The thickness non-uniformity of the five-point test reaches 0.39%, and there are no polycrystalline particles, slip lines, or crack-induced defects on the edges, which meets the requirements of the present invention.

[0055] Example 3: A method for preparing a double-layer thick-film high-resistance single-crystal epitaxial wafer for a semiconductor device of this embodiment comprises the following steps in sequence:

[0056] S1. Hydrogen chloride gas and hydrogen are introduced to perform high-temperature etching and cleaning on the reaction chamber and graphite base of the silicon epitaxial furnace, etching the deposits and impurity adsorption inside the reaction chamber and on the surface of the graphite base, and suppressing the impurity accumulation effect of the reaction environment. The reaction chamber temperature of the silicon epitaxial furnace is 1130°C, the radial temperature gradient of the sheet pit in the graphite base is 3°C, the flow rate of hydrogen chloride gas is 30L / min, the flow rate of hydrogen is 10 L / min, and the etching and cleaning time is 16min. Subsequently, hydrogen is introduced to carry trichlorosilane to grow a polycrystalline silicon coating layer inside the reaction chamber and on the surface of the graphite base. The flow rate of hydrogen is 200L / min, the flow rate of trichlorosilane is 13g / min, the temperature of the reaction chamber is 1060°C, and the thickness of the polycrystalline silicon coating is 1μm, further suppressing the impurity accumulation effect of the reaction environment.

[0057] S2. The reaction chamber of the silicon epitaxial furnace is cooled to 250°C to reduce the displacement of the subsequent silicon substrate when it is placed in the sheet pit of the graphite base of the reaction chamber. The initial temperature of the reaction chamber is slowly raised to 1060°C for 900 seconds to reduce the accumulation effect of thermal stress on the silicon substrate during the heating process, which leads to edge deformation, slip lines, and crack-induced defects. The surface of the silicon substrate is baked at high temperature for 1 minute, and then the reaction chamber is purged with hydrogen at a flow rate of 300 L / min for 1 minute to remove the natural oxide layer on the surface of the silicon substrate to prevent epitaxial growth of polycrystalline particles.

[0058] S3. Grow the first silicon epitaxial layer on the polished surface of the silicon substrate at a growth temperature of 1010°C to form a single crystal silicon epitaxial layer. Use hydrogen to carry trichlorosilane as the silicon growth source, and phosphine as the doping gas. The flow rate of trichlorosilane is 10 g / min, the flow rate of hydrogen is 180 L / min, the flow rate of phosphine is 125 sccm, the growth rate of the silicon epitaxial layer is 1.89 μm / min, the susceptor speed is 5 r / min, and the acceleration of the susceptor speed is 0.4 r / min. 2, reduce the offset of the silicon substrate position in the wafer pit, reduce the mechanical stress accumulation effect of the silicon epitaxial layer, and the temperature fluctuates by 2°C during the growth of the silicon epitaxial layer, which is used to reduce the accumulation effect of thermal stress during the growth of the silicon epitaxial layer, resulting in edge deformation, slip lines, and crack-induced defects.

[0059] S4. A second silicon epitaxial layer is grown on the surface of the first silicon epitaxial layer. Hydrogen is used to carry trichlorosilane as a growth silicon source, phosphine is used as a doping gas, and the growth temperature is 1020°C to form a single crystal silicon epitaxial layer. The flow rate of trichlorosilane is 13g / min, the flow rate of hydrogen is 180L / min, and the flow rate of phosphine is 55sccm. The growth rate of the silicon epitaxial layer is 2.12μm / min. The temperature fluctuates by 2°C during the growth of the silicon epitaxial layer to reduce the accumulation effect of thermal stress during the growth of the silicon epitaxial layer, which leads to edge deformation, slip lines, and crack-induced defects.

[0060] S5. Nitrogen is introduced to purge and cool the reaction chamber. The nitrogen flow rate is 150L / min. The reaction chamber is slowly cooled from the initial temperature to 250°C for 1000 seconds to release the thermal stress of the single crystal epitaxial wafer and reduce the edge deformation and the occurrence of slip lines and crack-induced defects. The positions of the five-point test are the center point and four points 6mm away from the edge: the top, bottom, left, and right points. The thickness and resistivity uniformity of the silicon epitaxial layer are met, and there are no polycrystalline particles, slip lines, and crack-induced defects on the edge. Finally, a double-layer thick film high-resistance single crystal epitaxial wafer is formed.

[0061] The thickness and resistivity of the single crystal epitaxial wafer prepared in Example 3 were measured at five test points, namely the center point and four points 6 mm from the edge, namely the top, bottom, left, and right points. The resistivity distribution diagram of the second silicon epitaxial layer is shown in FIG. Figure 5 As shown, the resistivities of the second silicon epitaxial layer are 23.836Ω·cm, 23.654Ω·cm, 23.587Ω·cm, 23.556Ω·cm, and 23.512Ω·cm, respectively. The resistivity non-uniformity of the five-point test reaches 0.68%. The total thickness distribution diagram of the silicon epitaxial layer is shown in Figure 6 As shown, the thicknesses of the silicon epitaxial layers are 98.322 μm, 97.856 μm, 98.854 μm, 98.312 μm, and 98.205 μm, respectively. The thickness non-uniformity of the five-point test reaches 0.51%, and there are no polycrystalline particles, slip lines, or crack-induced defects on the edges, which meets the requirements of the present invention.

[0062] Example 4: A method for preparing a double-layer thick-film high-resistance single-crystal epitaxial wafer for a semiconductor device according to this embodiment comprises the following steps in sequence:

[0063] S1. Hydrogen chloride gas and hydrogen are introduced to perform high-temperature etching and cleaning on the reaction chamber and graphite base of the silicon epitaxial furnace, etching the deposits and impurity adsorption inside the reaction chamber and on the surface of the graphite base, and suppressing the impurity accumulation effect of the reaction environment. The reaction chamber temperature of the silicon epitaxial furnace is 1130°C, the radial temperature gradient of the sheet pit in the graphite base is 3°C, the flow rate of hydrogen chloride gas is 30L / min, the flow rate of hydrogen is 10L / min, and the etching and cleaning time is 16min. Subsequently, hydrogen is introduced to carry trichlorosilane to grow a polysilicon coating inside the reaction chamber and on the surface of the graphite base. The flow rate of hydrogen is 200L / min, the flow rate of trichlorosilane is 14g / min, the temperature of the reaction chamber is 1020°C, and the thickness of the polysilicon coating is 1μm, further suppressing the impurity accumulation effect of the reaction environment.

[0064] S2. The reaction chamber of the silicon epitaxial furnace is cooled to 250°C to reduce the displacement of the subsequent silicon substrate when it is placed in the sheet pit of the graphite base of the reaction chamber. The initial temperature of the reaction chamber is slowly raised to 1060°C for 900 seconds to reduce the accumulation effect of thermal stress on the silicon substrate during the heating process, which leads to edge deformation, slip lines, and crack-induced defects. The surface of the silicon substrate is baked at high temperature for 3 minutes, and then the reaction chamber is purged with hydrogen at a flow rate of 300 L / min for 3 minutes to remove the natural oxide layer on the surface of the silicon substrate to prevent epitaxial growth of polycrystalline particles.

[0065] S3. Grow the first silicon epitaxial layer on the polished surface of the silicon substrate at a growth temperature of 1020°C to form a single crystal silicon epitaxial layer. Use hydrogen to carry trichlorosilane as the silicon growth source, phosphine as the doping gas, the flow rate of trichlorosilane is 12 g / min, the flow rate of hydrogen is 185 L / min, the flow rate of phosphine is 130 sccm, the growth rate of the silicon epitaxial layer is 1.98 μm / min, the susceptor speed is 5 r / min, and the acceleration of the susceptor speed is 0.4 r / min. 2 It is used to reduce the offset of the silicon substrate position in the wafer pit and reduce the mechanical stress accumulation effect of the silicon epitaxial layer. The temperature fluctuates by 3°C during the growth of the silicon epitaxial layer. It is used to reduce the accumulation effect of thermal stress during the growth of the silicon epitaxial layer, which leads to edge deformation, slip lines, and crack-induced defects.

[0066] S4. A second silicon epitaxial layer is grown on the surface of the first silicon epitaxial layer. Hydrogen is used to carry trichlorosilane as a growth silicon source, phosphine is used as a doping gas, and the growth temperature is 1020°C to form a single crystal silicon epitaxial layer. The flow rate of trichlorosilane is 14g / min, the flow rate of hydrogen is 185L / min, and the flow rate of phosphine is 60sccm. The growth rate of the silicon epitaxial layer is 2.18μm / min. The temperature fluctuates by 3°C during the growth of the silicon epitaxial layer to reduce the accumulation effect of thermal stress during the growth of the silicon epitaxial layer, which leads to edge deformation, slip lines, and crack-induced defects.

[0067] S5. Nitrogen is introduced to purge and cool the reaction chamber. The nitrogen flow rate is 100L / min. The reaction chamber is slowly cooled from the initial temperature to 250°C for 900 seconds to release the thermal stress of the single crystal epitaxial wafer and reduce the edge deformation and the occurrence of slip lines and cracks that induce defects. The five-point test positions are the center point and four points 6mm away from the edge: the top, bottom, left, and right points. The thickness and resistivity uniformity of the silicon epitaxial layer are met, and there are no polycrystalline particles, slip lines, cracks and other induced defects on the edge. Finally, a double-layer thick film high-resistance single crystal epitaxial wafer is formed.

[0068] The thickness and resistivity of the single crystal epitaxial wafer prepared in Example 4 were measured at five test points, namely the center point and four points 6 mm from the edge, namely the top, bottom, left, and right points. The resistivity distribution diagram of the second silicon epitaxial layer is shown in FIG. Figure 7 As shown, the resistivities of the second silicon epitaxial layer are 23.487Ω·cm, 23.121Ω·cm, 23.291Ω·cm, 23.279Ω·cm, and 23.354Ω·cm, respectively. The resistivity non-uniformity of the five-point test reaches 0.79%. The total thickness distribution diagram of the silicon epitaxial layer is shown in FIG. Figure 8 As shown, the thicknesses of the silicon epitaxial layers are 98.987 μm, 98.646 μm, 99.653 μm, 98.887 μm, and 98.873 μm, respectively. The thickness non-uniformity of the five-point test reaches 0.51%, and there are no polycrystalline particles, slip lines, or crack-induced defects on the edges, which meets the requirements of the present invention.

[0069] Example 5: A method for preparing a double-layer thick-film high-resistance single-crystal epitaxial wafer for a semiconductor device according to this embodiment comprises the following steps in sequence:

[0070] S1. Hydrogen chloride gas and hydrogen are introduced to perform high-temperature etching and cleaning on the reaction chamber and graphite base of the silicon epitaxial furnace, etching the deposits and impurity adsorption inside the reaction chamber and on the surface of the graphite base, and suppressing the impurity accumulation effect of the reaction environment. The reaction chamber temperature of the silicon epitaxial furnace is 1160°C, the radial temperature gradient of the sheet pit in the graphite base is 2°C, the flow rate of hydrogen chloride gas is 35L / min, the flow rate of hydrogen is 5L / min, and the etching and cleaning time is 15min. Subsequently, hydrogen is introduced to carry trichlorosilane to grow a polycrystalline silicon coating layer inside the reaction chamber and on the surface of the graphite base. The flow rate of hydrogen is 200L / min, the flow rate of trichlorosilane is 13 g / min, the temperature of the reaction chamber is 1020°C, and the thickness of the polycrystalline silicon coating is 1μm, further suppressing the impurity accumulation effect of the reaction environment.

[0071] S2. The reaction chamber of the silicon epitaxial furnace is cooled to 250°C to reduce the displacement of the subsequent silicon substrate when it is placed in the sheet pit of the graphite base of the reaction chamber. The initial temperature of the reaction chamber is slowly raised to 1110°C for 1000 seconds to reduce the accumulation effect of thermal stress on the silicon substrate during the heating process, which leads to edge deformation, slip lines, and crack-induced defects. The surface of the silicon substrate is baked at high temperature for 3 minutes, and then the reaction chamber is purged with hydrogen at a flow rate of 250L / min for 3 minutes to remove the natural oxide layer on the surface of the silicon substrate to prevent epitaxial growth of polycrystalline particles.

[0072] S3. Grow the first silicon epitaxial layer on the polished surface of the silicon substrate at a growth temperature of 1010°C to form a single crystal silicon epitaxial layer. Use hydrogen to carry trichlorosilane as the silicon growth source, and phosphine as the doping gas. The flow rate of trichlorosilane is 10 g / min, the flow rate of hydrogen is 165 L / min, the flow rate of phosphine is 130 sccm, the growth rate of the silicon epitaxial layer is 1.82 μm / min, the susceptor speed is 5 r / min, and the acceleration of the susceptor speed is 0.5 r / min. 2 It is used to reduce the offset of the silicon substrate position in the wafer pit and reduce the mechanical stress accumulation effect of the silicon epitaxial layer. The temperature fluctuates by 3°C during the growth of the silicon epitaxial layer. It is used to reduce the accumulation effect of thermal stress during the growth of the silicon epitaxial layer, which leads to edge deformation, slip lines, and crack-induced defects.

[0073] S4. A second silicon epitaxial layer is grown on the surface of the first silicon epitaxial layer. Hydrogen is used to carry trichlorosilane as a growth silicon source, phosphine is used as a doping gas, and the growth temperature is 1020°C to form a single crystal silicon epitaxial layer. The flow rate of trichlorosilane is 14g / min, the flow rate of hydrogen is 165L / min, and the flow rate of phosphine is 60sccm. The growth rate of the silicon epitaxial layer is 2.13μm / min. The temperature fluctuates by 3°C during the growth of the silicon epitaxial layer to reduce the accumulation effect of thermal stress during the growth of the silicon epitaxial layer, which leads to edge deformation, slip lines, and crack-induced defects.

[0074] S5. Nitrogen is introduced to purge and cool the reaction chamber. The nitrogen flow rate is 100L / min. The reaction chamber is slowly cooled from the initial temperature to 250°C for 900 seconds to release the thermal stress of the single crystal epitaxial wafer and reduce the edge deformation and the occurrence of slip lines and crack-induced defects. The five-point test positions are the center point and four points 6mm away from the edge: the top, bottom, left, and right points. The thickness and resistivity uniformity of the silicon epitaxial layer are met, and there are no polycrystalline particles, slip lines, and crack-induced defects on the edge. Finally, a double-layer thick film high-resistance single crystal epitaxial wafer is formed.

[0075] The thickness and resistivity of the single crystal epitaxial wafer prepared in Example 5 were measured at five test points, namely the center point and four points 6 mm from the edge, namely the top, bottom, left, and right points. The resistivity distribution diagram of the second silicon epitaxial layer is shown in FIG. Figure 9 As shown, the resistivities of the second silicon epitaxial layer are 23.245Ω·cm, 23.087Ω·cm, 23.023Ω·cm, 23.143Ω·cm, and 23.112Ω·cm, respectively. The resistivity non-uniformity of the five-point test reaches 0.77%. The total thickness distribution diagram of the silicon epitaxial layer is shown in FIG. Figure 10 As shown, the thicknesses of the silicon epitaxial layers are 98.172 μm, 97.514 μm, 98.662 μm, 98.024 μm, and 98.016 μm, respectively. The thickness non-uniformity of the five-point test reaches 0.59%. There are no polycrystalline particles, slip lines, or crack-induced defects on the edges, which meets the requirements of the present invention.

[0076] Comparative Example 1: The difference between the preparation method of this comparative example and that of Example 2 is that in step S1, the thickness of the polysilicon coating layer is different. The thickness of the polysilicon coating layer in this comparative example is 4 μm. The remaining steps and parameters are the same as those in Example 2.

[0077] In the single crystal epitaxial wafer prepared in Comparative Example 1, the polysilicon coating layer of the graphite base is too thick. During the growth of the epitaxial layer, the polysilicon coating layer of the graphite base undergoes a mass transfer effect and is transferred to the back and edge of the single crystal silicon epitaxial wafer, causing polycrystalline particles to be adsorbed on the back and edge, which does not meet the requirements of the present invention.

[0078] Comparative Example 2: The difference between the preparation method of this comparative example and that of Example 2 is that in step S1, the thickness of the polysilicon coating layer is different. The thickness of the polysilicon coating layer in this comparative example is 0.5 μm. The remaining steps and parameters are the same as those in Example 2.

[0079] The resistivity distribution diagram of the second silicon epitaxial layer of the single crystal epitaxial wafer prepared in Comparative Example 2 is shown in FIG. Figure 11 As shown, the resistivities of the second silicon epitaxial layer are 23.575Ω·cm, 23.034Ω·cm, 23.121Ω·cm, 23.023Ω·cm, and 23.243Ω·cm, respectively, and the resistivity non-uniformity of the five-point test reaches 1.18%.

[0080] In the single crystal epitaxial wafer prepared in Comparative Example 2, the thickness of the polysilicon coating layer of the graphite base is too thin, the impurity accumulation effect of the reaction environment is insufficiently suppressed, and the edge resistivity value of the prepared single crystal epitaxial wafer drops sharply, thereby causing the resistivity uniformity to deteriorate. Moreover, the back of the silicon substrate is in direct contact with the graphite base. The inconsistency in the thermal expansion coefficients of the silicon substrate and the graphite during the heating and cooling process causes the single crystal epitaxial wafer finally prepared to be prone to slip line defects, which does not meet the requirements of the present invention.

[0081] Comparative Example 3: The difference between the preparation method of this comparative example and that of Example 2 is that in step S1, the radial temperature gradient of the sheet pits in the graphite base is 4°C, and the remaining steps and parameters are the same as those of Example 2.

[0082] The resistivity distribution diagram of the second silicon epitaxial layer of the single crystal epitaxial wafer prepared in Comparative Example 3 is shown in FIG. Figure 12 As shown, the resistivities of the second silicon epitaxial layer are 23.533Ω·cm, 23.324Ω·cm, 23.741Ω·cm, 23.405Ω·cm, and 23.398Ω·cm, respectively, and the resistivity non-uniformity of the five-point test reaches 0.89%.

[0083] The single crystal epitaxial wafer prepared in Comparative Example 3 has an excessively high radial temperature gradient in the pits of the graphite base, which causes the thermal field distribution uniformity to deteriorate during the growth of the silicon epitaxial layer, thereby causing the resistivity uniformity of the silicon epitaxial layer to deteriorate, and is prone to slip line defects, which does not meet the requirements of the present invention.

[0084] Comparative Example 4: The difference between the preparation method of this comparative example and that of Example 2 is that in step S2, the time for the initial temperature of the reaction chamber to slowly rise to 1060°C is 800 seconds, and the remaining steps and parameters are the same as those of Example 2.

[0085] The single crystal epitaxial wafer prepared in Comparative Example 4 has internal thermal stress that is difficult to release due to the continuous accumulation of internal thermal stress caused by the rapid heating rate of the silicon substrate. The edge of the silicon epitaxial layer is easily deformed, and slip lines and crack-induced defects are easily generated, which does not meet the requirements of the present invention.

[0086] Comparative Example 5: The difference between the preparation method of this comparative example and that of Example 2 is that in step S3, the growth temperature of the silicon epitaxial layer is 1000°C, and the remaining steps and parameters are the same as those of Example 2.

[0087] In the single crystal epitaxial wafer prepared in Comparative Example 5, the growth temperature was too low, the crystal integrity of the silicon epitaxial layer deteriorated during the growth process, and polycrystalline grains were formed at the edge of the preparation, which did not meet the requirements of the present invention.

[0088] Comparative Example 6: The difference between the preparation method of this comparative example and that of Example 2 is that in step S3, the acceleration of the base rotation speed is 0.6 r / min 2 The remaining steps and parameters are the same as those in Example 2.

[0089] In the single crystal epitaxial wafer prepared in Example 6, the acceleration of the base rotation speed is set too fast, which easily causes the silicon substrate placed in the graphite base sheet pit to shift in position, resulting in collision or adhesion with the graphite base, causing the flow field and thermal field distribution uniformity during the growth of the silicon epitaxial layer to deteriorate, thereby causing the thickness uniformity of the silicon epitaxial layer to deteriorate. The total thickness distribution diagram is shown in FIG. Figure 13 As shown, the thicknesses of the silicon epitaxial layers are 98.658μm, 98.234μm, 98.876μm, 97.543μm, and 98.432μm, respectively. The thickness non-uniformity of the five-point test not only reaches 0.68%, but the single crystal epitaxial wafer is prone to deformation, and thus slip lines and crack-induced defects are prone to occur, which does not meet the requirements of the present invention.

[0090] Comparative Example 7: The difference between the preparation method of this comparative example and that of Example 2 is that in step S3, the temperature fluctuation during the growth of the silicon epitaxial layer reaches 4°C, and the remaining steps and parameters are the same as those of Example 2.

[0091] The single crystal epitaxial wafer prepared in Comparative Example 7 is prone to deformation due to the continuous accumulation of thermal stress during the growth of the silicon epitaxial layer, and is prone to slip line and crack-induced defects, which does not meet the requirements of the present invention.

[0092] Comparative Example 8: The difference between the preparation method of this comparative example and that of Example 2 is that in step S4, the flow rate of trichlorosilane during the growth of the silicon epitaxial layer is 15 g / min, the growth rate of the silicon epitaxial layer is 2.22 μm / min, and the remaining steps and parameters are the same as those of Example 2.

[0093] The single crystal epitaxial wafer prepared in Comparative Example 8 does not meet the requirements of the present invention because the silicon epitaxial layer grows too fast, resulting in continuous accumulation of thermal stress during the growth of the silicon epitaxial layer, which makes the edge easily deformed and prone to slip line and crack-induced defects.

[0094] Comparative Example 9: The difference between the preparation method of this comparative example and that of Example 2 is that in step S4, the growth temperature of the silicon epitaxial layer during the growth process is 1050°C, and the remaining steps and parameters are the same as those of Example 2.

[0095] The single crystal epitaxial wafer prepared in Comparative Example 9 has an edge that is easily deformed and prone to slip line and crack-induced defects due to the excessively high growth temperature of the silicon epitaxial layer, which causes continuous accumulation of thermal stress during the growth of the silicon epitaxial layer. This does not meet the requirements of the present invention.

[0096] Comparative Example 10: The preparation method of this comparative example differs from that of Example 2 in that in step S5, the reaction chamber is slowly cooled from the initial temperature to 250°C for 800 seconds, and the remaining steps and parameters are the same as those of Example 2.

[0097] The single crystal epitaxial wafer prepared in Comparative Example 10 is prone to edge deformation due to the excessively fast cooling rate of the silicon epitaxial layer, which in turn easily causes slip lines and crack-induced defects, and does not meet the requirements of the present invention.

[0098] The probability of edge polycrystalline grains, slip lines and even crack-induced defects in the single crystal epitaxial wafers prepared in batches in each embodiment and comparative example is calculated below, that is, the ratio of the number of defective single crystal epitaxial wafers to the total number of single crystal epitaxial wafers is shown in Table 1.

[0099] Table 1 Probability of generation of polycrystalline grains, slip lines, and cracks at the edge of double-layer thick film high-resistance single crystal epitaxial wafers

[0100]

[0101] The experimental results in Table 1 indicate that the single-crystal epitaxial wafers grown using the preparation methods of Examples 1-5 of the present invention exhibited resistivity nonuniformity of less than 0.8% and thickness nonuniformity of less than 0.6% in the five-point test of the silicon epitaxial layer, meeting the requirements of the present invention. However, the single-crystal epitaxial wafers grown using the preparation methods of Comparative Examples 1-10 exhibited poor silicon epitaxial layer thickness uniformity, poor resistivity uniformity, and defects such as edge polycrystalline grains, slip lines, and even crack-induced defects, failing to meet the requirements of the present invention.

[0102] Through the above five embodiments and ten comparative examples, it can be verified that, on the one hand, the present invention avoids the problem of positional displacement of the silicon substrate in the sheet pit of the graphite base during the sheet placement and heating process by designing key process parameters such as the rotation speed and acceleration of the graphite base inside the reaction chamber, thereby reducing the edge deformation caused by the mechanical stress accumulation effect generated during the double-layer thick film high-resistance silicon epitaxial process, thereby reducing the probability of slip line and crack-induced defects. On the other hand, by designing key process parameters such as the heating time, cooling time, process temperature and its fluctuation range of the reaction chamber, the thermal stress generated during the heating and cooling stages of the double-layer thick film high-resistance silicon epitaxial process can be released in a timely manner, thereby further reducing the edge deformation caused by the thermal stress accumulation effect, and thus the probability of slip line and crack-induced defects.

[0103] The present invention overcomes the problem that the double-layer thick film high-resistance epitaxial process easily generates edge polycrystalline particles, slip lines and even crack-induced defects by comprehensively designing key process parameters such as growth temperature and its fluctuation range, growth rate, heating and cooling time, base rotation speed and acceleration on the North Huachuang 630 model flat-plate multi-wafer silicon epitaxial furnace that are different from those of traditional epitaxial processes. By setting the flow rate of hydrogen in the reaction chamber and designing and controlling the radial temperature gradient of the slice pit in the graphite base, the uniformity of the double-layer thick film high-resistance epitaxial layer is significantly improved. The resistivity non-uniformity of the five-point test reaches <0.8%, and the thickness non-uniformity of the five-point test reaches <0.6%. The remarkable effect of batch growth of double-layer thick film high-resistance single crystal epitaxial wafers on 6-inch and 8-inch silicon substrates is achieved, which meets the use requirements of high-voltage and high-power semiconductor devices and is conducive to large-scale promotion and application.

Claims

1. A method for preparing a double-layer thick film high-resistance single crystal epitaxial wafer for semiconductor devices, characterized in that: The method includes the following steps: S1. Passing hydrogen chloride gas and hydrogen gas to perform high-temperature etching and cleaning on the reaction chamber and graphite susceptor of the silicon epitaxial furnace, etching the deposits and impurity adsorption inside the reaction chamber and on the surface of the graphite susceptor, and suppressing the impurity accumulation effect of the reaction environment. The reaction chamber temperature of the silicon epitaxial furnace is 1130-1160°C, the radial temperature gradient of the sheet pit in the graphite susceptor is ≤3°C, the flow rate of hydrogen chloride gas is 30-35 L / min, the flow rate of hydrogen is 5-10 L / min, and the etching and cleaning time is 15-16 min. Subsequently, hydrogen gas is passed to carry trichlorosilane to grow a polycrystalline silicon coating layer inside the reaction chamber and on the surface of the graphite susceptor. The flow rate of hydrogen is 150-200 L / min, the flow rate of trichlorosilane is 13-14 g / min, the temperature of the reaction chamber is 1020-1060°C, and the thickness of the polycrystalline silicon coating layer is 1-2 μm. S2. Cooling the reaction chamber of the silicon epitaxial furnace to 250-300° C., slowly raising the initial temperature of the reaction chamber to 1060-1110° C. for 900-1000 seconds, baking the surface of the silicon substrate at high temperature for 1-3 minutes, and then purging the reaction chamber with hydrogen at a flow rate of 250-300 L / min for 1-3 minutes. S3. Growing a first silicon epitaxial layer on the polished surface of the silicon substrate at a growth temperature of 1010-1020° C. to form a single crystal silicon epitaxial layer. Using hydrogen to carry trichlorosilane as a silicon growth source, phosphine as a doping gas, the flow rate of trichlorosilane is 10-12 g / min, the flow rate of hydrogen is 165-185 L / min, the flow rate of phosphine is 125-130 sccm, the growth rate of the silicon epitaxial layer is 1.8-2.0 μm / min, the susceptor rotation speed is 5-6 r / min, and the acceleration of the susceptor rotation speed is 0.4-0.5 r / min. 2 The target growth thickness of the first silicon epitaxial layer is 30-35 μm, the target resistivity is 2.5-3.5 Ω·cm, and the temperature fluctuation during the growth of the silicon epitaxial layer is ≤3°C; S4. Growing a second silicon epitaxial layer on the surface of the first silicon epitaxial layer, using hydrogen carrying trichlorosilane as a growth silicon source, phosphine as a doping gas, and a growth temperature of 1020-1040° C. to form a single crystal silicon epitaxial layer. The trichlorosilane flow rate is 13-14 g / min, the hydrogen flow rate is 165-185 L / min, the phosphine flow rate is 55-60 sccm, and the silicon epitaxial layer growth rate is 2.1-2.2 μm / min. The target growth thickness of the second silicon epitaxial layer is 60-65 μm, the target resistivity is 22-26 Ω·cm, and the temperature fluctuation during the growth of the silicon epitaxial layer is ≤3° C. S5. Nitrogen is introduced to purge and cool the reaction chamber. The nitrogen flow rate is 100~150L / min. The reaction chamber is slowly cooled from the initial temperature to 250~300℃ for 900~1000sec. The resistivity non-uniformity of the target double-layer thick film high-resistance single crystal epitaxial wafer is <0.8% in a five-point test, and the thickness non-uniformity is <0.6% in a five-point test. The positions of the five-point test are the center point and four points 6mm away from the edge at the top, bottom, left, and right. Finally, a double-layer thick film high-resistance single crystal epitaxial wafer is formed.

2. The method for preparing a double-layer thick film high-resistance single crystal epitaxial wafer for semiconductor devices according to claim 1, characterized in that: The silicon epitaxial furnace is a North Huachuang 630 model flat-plate multi-wafer silicon epitaxial furnace.

3. The method for preparing a double-layer thick film high-resistance single crystal epitaxial wafer for semiconductor devices according to claim 1, characterized in that: The silicon substrate is a 6-inch or 8-inch silicon substrate with a crystal orientation of <100> , the resistivity is 1~4Ω·cm, the oxygen content is 8~14ppma, the front side of the silicon substrate is a polished surface, and the back side is covered with a 450~550nm thick silicon dioxide backing layer. The removal amount of the edge silicon dioxide backing layer is 0.8~1.0mm, which is used to prevent the epitaxial growth of polycrystalline particles at the edge. The edge chamfer angle is 22°, the chamfer morphology is R-type, and the edge chamfer width is 400~450μm, which is used to reduce the formation of edge cracks.

Images