Ultra-low voltage constant current source structure

Abstract

The application aims to provide an ultra-low voltage constant current source structure, and belongs to the technical field of analog circuits. The structure adopts a differential pair comparator and a depletion NMOS tube N1. The differential pair comparator outputs a control voltage to adjust an output current. PMOS tubes P4 and P5 are low-opening voltage PMOS tubes. The depletion NMOS tube N1 has an opening voltage of -0.3 V, and the lowest working voltage reaches 0.5 V, and the offset effect is small. The traditional operational amplifier constant current source circuit has limitations in a low-voltage environment. The design complexity is simplified, the chip area is reduced, the static power consumption is reduced, and the application is suitable for the power-sensitive field of Internet of Things sensors, medical implant devices and the like. In addition, the ultra-low voltage constant current source structure can realize wide current range output under ultra-low voltage, meet the demand of large current load scene, such as high-brightness LED driving, and expand the application scene.

Description

Technical Field

[0001] This invention relates to the field of analog circuit technology, and in particular to an ultra-low voltage constant current source structure. Background Technology

[0002] An operational amplifier (op-amp) constant current source circuit is a circuit configuration that utilizes the negative feedback characteristics of an operational amplifier (op-amp) to generate a stable, constant current. This type of circuit has wide applications in hardware circuit design and engineering, especially in applications requiring constant current drive, such as LED lighting, laser driving, electrochemical analysis, and precision measurement.

[0003] like Figure 1 As shown, the design purpose of a traditional operational amplifier constant current source circuit is to provide a stable current output to ensure the stable operation of other circuits. This means that the devices in the output stage must have the volt-ampere characteristic of saturated output current to guarantee a constant output current. Specifically, to achieve this goal, transistors with high output resistance, such as bipolar junction transistors (BJTs) or metal-oxide-semiconductor field-effect transistors (MOSFETs), are typically selected. These transistors can operate in an output current saturation state under certain conditions, thus meeting the requirements of a constant current source.

[0004] For the selection of input stage devices, since they need to act as a constant voltage source to maintain the stability of the input voltage, devices with voltage saturation current-voltage characteristics can be selected. For example, PN junction diodes have an exponentially rising current-voltage characteristic, and the diode formed by shorting the source and drain of an enhancement-mode MOSFET also has a similar parabolic rising current-voltage characteristic. This characteristic makes them suitable as constant voltage sources for the input stage.

[0005] Regarding output stage devices, if a BJT is used, it is necessary to reduce the Evarly effect (base width modulation effect), i.e., to maximize the Evarly voltage to increase the output resistance. If a MOSFET is used, it is necessary to reduce the channel length modulation effect and substrate bias effect to increase the output resistance. Through these measures, it can be ensured that the output resistance of the output transistor is as large as possible, ideally approaching infinity, thereby meeting the requirements of a constant current source.

[0006] However, traditional op-amp constant current source circuits have certain limitations in low-voltage operating environments. Specifically, traditional op-amp constant current source circuits rely on enhancement-mode MOSFETs or BJTs as output stage devices, which have relatively high turn-on voltages (approximately 1V for ordinary NMOS transistors). When the operating voltage is low, ordinary NMOS transistors and BJTs struggle to function properly because they require high turn-on voltages to reach saturation. This limits the operating voltage range of the entire circuit, making it difficult to meet the needs of ultra-low voltage applications (such as low-power IoT devices and wearable electronics). Furthermore, the substrate bias effect of enhancement-mode MOSFETs reduces output resistance, affecting constant current accuracy, especially under low-voltage conditions where performance deteriorates further, making it difficult to maintain constant current characteristics. Therefore, the problem of traditional op-amp constant current source circuits failing to stably provide a constant current under ultra-low operating voltages needs to be addressed.

[0007] To address the aforementioned issues, while existing technologies offer various low-voltage circuit solutions (such as low-power reference sources and bootstrap technologies), their technical approaches primarily focus on power supply voltage suppression or static power consumption optimization. To maintain constant current characteristics, complex bias voltage generation circuits are required, increasing design complexity and chip area. Furthermore, these solutions fail to fundamentally resolve the contradiction between stable output and high precision of constant current sources under ultra-low voltage (<1V) conditions. Summary of the Invention

[0008] The purpose of this invention is to overcome the shortcomings of the prior art and provide an ultra-low voltage constant current source structure. To this end, a depletion-type NMOS transistor is used as the output stage device, and its turn-on voltage can be around -0.3V, so that the operating voltage of the operational amplifier circuit can be reduced to as low as 0.5V. In addition, since the depletion-type NMOS transistor has a small substrate bias effect, it can maintain good performance under low voltage conditions.

[0009] To achieve the above objectives, the present invention provides the following technical solution:

[0010] An ultra-low voltage constant current source structure includes: a differential pair comparator and a depletion-type NMOS transistor N1; the output terminal of the differential pair comparator is connected to the gate of the depletion-type NMOS transistor N1 to provide a control signal, and the turn-on voltage of the depletion-type NMOS transistor N1 is negative; the source of the depletion-type NMOS transistor N1 is grounded through a resistor R2 to form a constant current output terminal, wherein the non-inverting input terminal of the differential pair comparator is connected to a reference voltage Vref, and the inverting input terminal of the differential pair comparator is connected to the source feedback voltage Vfb of the depletion-type NMOS transistor N1, and the negative feedback of the differential pair comparator makes Vfb = Vref, so that the output current I satisfies I = Vref / R2, thereby forming a constant current.

[0011] Furthermore, the differential pair comparator includes a current source I1, PMOS transistors P1, PMOS transistors P2, PMOS transistors P3, PMOS transistors P4, PMOS transistors P5, NMOS transistors N2, NMOS transistors N3, and NMOS transistors N4, and PMOS transistors P4 and PMOS transistors P5 are low turn-on voltage PMOS transistors;

[0012] The gate of PMOS transistor P1 is connected to the gates of PMOS transistor P2 and PMOS transistor P3, the drain of PMOS transistor P1, and the current source I1. The source of PMOS transistor P1 is connected to the power supply voltage. The drain of PMOS transistor P1 is connected to the gates of PMOS transistor P2 and PMOS transistor P3 and the current source I1. The substrate of PMOS transistor P1 is connected to the power supply voltage.

[0013] The gate of PMOS transistor P2 is connected to the gate of PMOS transistor P3 and the current source I1. The source of PMOS transistor P2 is connected to the power supply voltage. The drain of PMOS transistor P2 is connected to the source of PMOS transistor P4, the substrate of PMOS transistor P4, the source of PMOS transistor P5 and the substrate of PMOS transistor P5. The substrate of PMOS transistor P2 is connected to the power supply voltage.

[0014] The gate of the PMOS transistor P3 is connected to the current source I1, the source of the PMOS transistor P3 is connected to the power supply voltage, the drain of the PMOS transistor P3 is connected to the gate of the depletion-type NMOS transistor N1 and the drain of the NMOS transistor N4, and the substrate of the PMOS transistor P3 is connected to the power supply voltage.

[0015] The gate (Vfb) of the PMOS transistor P4 is connected to the source of the depletion-type NMOS transistor N1. The source of the PMOS transistor P4 is connected to the source of the PMOS transistor P5, the substrate of the PMOS transistor P4, and the substrate of the PMOS transistor P5. The drain of the PMOS transistor P4 is connected to the gate of the NMOS transistor N2, the drain of the NMOS transistor N2, and the gate of the NMOS transistor N3. The substrate of the PMOS transistor P4 is connected to the source of the PMOS transistor P5 and the substrate of the PMOS transistor P5.

[0016] The gate (Vref) of the PMOS transistor P5 is connected to the reference voltage, the source of the PMOS transistor P5 is connected to the substrate of the PMOS transistor P5, and the drain of the PMOS transistor P5 is connected to the drain of the NMOS transistor N3 and the gate of the NMOS transistor N4.

[0017] The gate of NMOS transistor N2 is connected to the gate of NMOS transistor N3 and the drain of NMOS transistor N2. The source of NMOS transistor N2 is grounded. The drain of NMOS transistor N2 is connected to the gate of NMOS transistor N3. The substrate of NMOS transistor N2 is grounded.

[0018] The source of NMOS transistor N3 is grounded, the drain of NMOS transistor N3 is connected to the gate of NMOS transistor N4, and the substrate of NMOS transistor N3 is grounded.

[0019] The source of the NMOS transistor N4 is grounded, the drain of the NMOS transistor N4 is connected to the gate of the depletion-type NMOS transistor N1, and the substrate of the NMOS transistor N4 is grounded.

[0020] The drain of the depletion-type NMOS transistor N1 is connected to the power supply voltage, and the substrate of the depletion-type NMOS transistor N1 is grounded.

[0021] One ungrounded end of resistor R2 is connected to the source of NMOS transistor N1 and the gate of PMOS transistor P4.

[0022] Furthermore, the differential comparator also includes a resistor R1 and a capacitor C1, which form a Miller compensation network to improve circuit stability, wherein:

[0023] One end of the resistor R1 is connected to the upper plate of the capacitor C1, and the other end is connected to the gate of the NMOS transistor N4, the drain of the PMOS transistor P5, and the drain of the NMOS transistor N3.

[0024] The lower plate of capacitor C1 is connected to the drain of PMOS transistor P3, the drain of NMOS transistor N4, and the gate of depletion-type NMOS transistor N1.

[0025] Furthermore, in the differential pair comparator: the PSUB terminals of PMOS transistor P1, PMOS transistor P2, PMOS transistor P3, PMOS transistor P4, and PMOS transistor P5 are all grounded.

[0026] Furthermore, the turn-on voltage of the PMOS transistors P4 and P5 is 0.5V.

[0027] Furthermore, the turn-on voltage of the depletion-type NMOS transistor N1 is -0.3V, so that the operating voltage of the constant current source structure is as low as 0.5V.

[0028] Compared with the prior art, the beneficial effects achieved by the present invention are as follows:

[0029] (1) In this invention, the turn-on voltage of the depletion-type NMOS transistor can be as low as -0.3V, and PMOS transistors P4 and P5 are low turn-on voltage PMOS transistors, so that the overall circuit can work stably under a power supply voltage of 0.5V, which is more than 40% lower than the traditional solution that requires a power supply voltage of not less than 1V, and does not require complex compensation circuits.

[0030] (2) The depletion-type NMOS transistor used in this invention has a much smaller substrate bias effect than the enhancement-type device. Combined with the PMOS transistors P1-P3 in the bias circuit, the influence of power supply voltage fluctuation on constant current accuracy is significantly reduced. By suppressing the substrate bias effect, high stability and anti-interference capability are obtained.

[0031] (3) In this invention, resistor R1 and capacitor C1 constitute Miller compensation to compensate the second-stage differential operational amplifier, thereby improving the stability of mass-produced chips.

[0032] (4) The present invention uses the cascade structure of current source I1 and PMOS transistors P1 to P3 to simplify the design complexity without the need to generate an additional precise bias voltage. The chip area is reduced by about 15%, and the simplified circuit structure is easier to integrate into the SoC. The application scenarios are expanded and can meet the requirements of high integration.

[0033] (5) The static power consumption of the present invention is reduced. The static current of the depletion-type NMOS transistor N1 is only in the microampere level, which is suitable for power-sensitive fields such as IoT sensors and medical implantation devices. The power consumption of the present invention is reduced by more than 90% compared with the traditional enhancement-type NMOS solution, while the static current of the traditional solution is in the milliampere level.

[0034] (6) This invention achieves a wide current range (0-80mA) output at ultra-low voltage through the synergistic effect of differential pair comparator and depletion-type NMOS transistor. It can provide a constant current output of up to 80mA at 0.5V voltage, which meets the needs of high current load scenarios, such as high brightness LED driving.

[0035] In summary, this invention addresses the shortcomings of traditional operational amplifier constant current source circuits in low-voltage operating environments by providing a novel ultra-low voltage constant current source structure that can provide stable and reliable constant current source output under low voltage conditions, making it suitable for a wider range of low-voltage application scenarios. Attached Figure Description

[0036] The accompanying drawings, which form part of this specification, illustrate embodiments of the invention and, together with the specification, serve to explain the principles of the invention.

[0037] The invention will be more clearly understood with reference to the accompanying drawings and the following detailed description, wherein:

[0038] Figure 1 This is a traditional operational amplifier constant current source circuit diagram;

[0039] Figure 2 The circuit diagram of the ultra-low voltage constant current source structure provided by the present invention. Detailed Implementation

[0040] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments and specific features in the embodiments are detailed descriptions of the technical solution of the present application, and not limitations thereof. Where there is no conflict, the embodiments and technical features in the embodiments can be combined with each other. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and should not be used to limit the scope of protection of the present invention.

[0041] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0042] Example 1

[0043] Figure 2 This is a circuit diagram of the ultra-low voltage constant current source structure provided by the present invention. This embodiment is a typical implementation of the present invention, providing an ultra-low voltage constant current source structure, including: a differential pair comparator, a depletion-type NMOS transistor N1, and a resistor R2, wherein the PLUS terminal of the resistor R2 is connected to the source of the depletion-type NMOS transistor N1.

[0044] A differential pair comparator and a depletion-type NMOS transistor N1 are used. The output of the differential pair comparator is connected to the gate of the depletion-type NMOS transistor N1 to provide a control signal, and the turn-on voltage of the depletion-type NMOS transistor N1 is negative. The source of the depletion-type NMOS transistor N1 is grounded through resistor R2 to form a constant current output terminal. The non-inverting input of the differential pair comparator is connected to the reference voltage Vref, and the inverting input of the differential pair comparator is connected to the source feedback voltage Vfb of the depletion-type NMOS transistor N1. Through the negative feedback of the differential pair comparator, Vfb tends to Vref, so that the output current I satisfies I = Vref / R2 to form a constant current.

[0045] The differential comparator includes a current source I1, PMOS transistors P1, P2, P3, P4, and P5, NMOS transistors N2, N3, and N4, a resistor R1, and a capacitor C1. PMOS transistors P4 and P5 are low turn-on voltage PMOS transistors. PMOS transistors P1, P2, and P3 form a current mirror to provide symmetrical current. PMOS transistors P4 and P5, together with NMOS transistors N2 and N3, form a differential amplifier that detects the voltage difference between the two input terminals (Vfb and Vref) and outputs the voltage difference signal to the gate of the depletion-type NMOS transistor N1.

[0046] The depletion-type NMOS transistor N1 has its gate connected to the drain of PMOS transistor P3, the drain of NMOS transistor N4, and the lower plate of capacitor C1. Its source is connected to the gate of PMOS transistor P4, its drain is connected to the power supply voltage, its substrate is grounded, and the turn-on voltage of the depletion-type NMOS transistor N1 is negative.

[0047] The PLUS terminal of resistor R2 is also connected to the gate of PMOS transistor P4, and the MINUS terminal of resistor R2 is grounded.

[0048] Furthermore, the gate of PMOS transistor P1 is connected to the gates of PMOS transistors P2 and P3, the drain of PMOS transistor P1, and the current source I1. The source is connected to the power supply voltage, the drain is connected to the gates of PMOS transistors P1, P2, and P3, and the current source I1, and the substrate is connected to the power supply voltage.

[0049] The gate of PMOS transistor P2 is connected to the gate of PMOS transistor P1, the gate of PMOS transistor P3, the drain of PMOS transistor P1, and the current source I1. The source is connected to the power supply voltage, and the drain is connected to the source of PMOS transistor P4 and its substrate, and the source of PMOS transistor P5 and its substrate. The substrate is connected to the power supply voltage.

[0050] The gate of PMOS transistor P3 is connected to the gates of PMOS transistors P1 and P2, the drain of PMOS transistor P1, and the current source I1. The source is connected to the power supply voltage, and the drain is connected to the lower plate of capacitor C1, the gate of depletion-type NMOS transistor N1, and the drain of NMOS transistor N4. The substrate is connected to the power supply voltage.

[0051] The gate of PMOS transistor P4 is connected to the source of depletion-type NMOS transistor N1 and the PLUS terminal of resistor R2. The source is connected to the drain of PMOS transistor P2, the source of PMOS transistor P5, the substrate of PMOS transistor P4, and the substrate of PMOS transistor P5. The drain is connected to the gate of NMOS transistor N2, the gate of NMOS transistor N3, and the drain of NMOS transistor N2. The substrate is connected to the drain of PMOS transistor P2, the source of PMOS transistor P4, the source of PMOS transistor P5, and the substrate of PMOS transistor P5.

[0052] The gate of PMOS transistor P5 is connected to the reference voltage, the source is connected to the drain of PMOS transistor P2, the source of PMOS transistor P4, the substrate of PMOS transistor P4, and the substrate of PMOS transistor P5, the drain is connected to the drain of NMOS transistor N3, the gate of NMOS transistor N4, and the MINUS terminal of resistor R1, and the substrate is connected to the drain of PMOS transistor P2, the source of PMOS transistor P4, the source of PMOS transistor P5, and the substrate of PMOS transistor P4.

[0053] The gate of NMOS transistor N2 is connected to the gate of NMOS transistor N3, the drain of NMOS transistor N2, and the drain of PMOS transistor P4. The source is grounded, and the drain is connected to the gate of NMOS transistor N2, the gate of NMOS transistor N3, and the drain of PMOS transistor P4. The substrate is grounded.

[0054] The gate of NMOS transistor N3 is connected to the gate of NMOS transistor N2, the drain of NMOS transistor N2, and the drain of PMOS transistor P4. The source is grounded. The drain is connected to the drain of PMOS transistor P5, the gate of NMOS transistor N4, and the MINUS terminal of resistor R1. The substrate is grounded.

[0055] The gate of NMOS transistor N4 is connected to the drain of PMOS transistor P5, the drain of NMOS transistor N3, and the MINUS terminal of resistor R1. The source is grounded, and the drain is connected to the lower plate of capacitor C1, the drain of PMOS transistor P3, and the gate of depletion-type NMOS transistor N1. The substrate is grounded.

[0056] In the differential comparator, current source I1, PMOS transistors P1, PMOS transistors P2, PMOS transistors P4, PMOS transistors P5, NMOS transistors N2, and NMOS transistors N3 together form a first-stage differential operational amplifier. PMOS transistors P3 and P4, capacitor C1, and resistor R1 together form a second-stage differential operational amplifier. The second-stage differential operational amplifier can increase the dynamic range of the first-stage differential operational amplifier output, which can approach the power supply voltage at its highest and 0V at its lowest. Optionally, one or more secondary differential operational amplifiers can be inserted between the second-stage differential operational amplifier and the depletion-mode NMOS transistor N1. The secondary differential operational amplifiers use the same components as the second-stage differential operational amplifier.

[0057] Specifically, the PSUB terminals of PMOS transistors P1, P2, P3, P4, and P5 are all grounded.

[0058] Specifically, the PLUS terminal of resistor R1 is connected to the upper plate of capacitor C1, and the MINUS terminal is connected to the gate of NMOS transistor N4, the drain of PMOS transistor P5, and the drain of NMOS transistor N3.

[0059] The upper plate of capacitor C1 is connected to the PLUS terminal of resistor R1, and the lower plate is connected to the drain of PMOS transistor P3, the drain of NMOS transistor N4, and the gate of depletion-mode NMOS transistor N1. NMOS transistor N4, together with resistor R1 and capacitor C1, forms a compensation network to help improve the stability of the circuit.

[0060] Specifically, the turn-on voltage of PMOS transistors P4 and P5 is 0.5V.

[0061] Specifically, the turn-on voltage of the depletion-type NMOS transistor N1 is -0.3V, so that the operating voltage of the constant current source structure is as low as 0.5V.

[0062] The output stage of the circuit of this invention includes an NMOS transistor N4 and resistors R1 and R2. The NMOS transistor N4 serves as a common-source output stage to convert the differential signal into a single-ended output. Resistors R1 and R2 form a load network, which determines the output gain.

[0063] Specifically, the turn-on voltage of the depletion-type NMOS transistor N1 is -0.3V, which makes the minimum operating voltage of the constant current source structure 0.5V, so that it can be used to provide a constant current source of about 0 to 80mA in low operating voltage environments.

[0064] Since N1 uses a depletion-type NMOS transistor, and the turn-on voltage of the depletion-type NMOS transistor N1 is negative, it can still work normally at lower power supply voltages. That is, N1 can work normally as long as it is above 0V, while the normal operating voltage of a normal NMOS transistor is about 1V. In addition, the bias effect of the depletion-type NMOS transistor is significantly reduced compared to that of a normal NMOS transistor. Specifically, the turn-on voltage of the depletion-type NMOS transistor N1 is -0.3V, which means that even when the power supply voltage is lower than 1V, the depletion-type NMOS transistor N1 can still remain on, thereby ensuring the normal operation of the constant current source. Furthermore, PMOS transistors P4 and P5 are low turn-on voltage PMOS transistors. Ordinary PMOS transistors turn on at about 0.7V, while low-voltage turn-on PMOS transistors turn on at 0.5V. This allows the constant current source structure of the present invention to operate at a voltage as low as about 0.5V under conventional processes.

[0065] The depletion-type NMOS transistor N1 has a negative turn-on voltage, which allows it to operate normally even at lower supply voltages. Specifically, N1 has a turn-on voltage of -0.3V, meaning that N1 will remain on even when the supply voltage is below 1V, thus ensuring the normal operation of the constant current source.

[0066] The value of resistor R2 needs to be selected according to the required output current range. By adjusting the value of R2, precise control of the output current can be achieved.

[0067] The function of capacitor C1 is to stabilize the output of the differential pair comparator, prevent oscillation, and improve the stability of the entire constant current source structure.

[0068] In practical use, the power supply voltage is connected to the power supply voltage terminal (Vcc), the reference voltage (Vref) is connected to the gate of PMOS transistor P5, the input signal is input through the input terminal of the differential pair comparator, and the output current I is output through the source of the depletion-type NMOS transistor N1. Precise control of the output current can be achieved by adjusting the parameters of the current source I1 and resistors R1 and R2 in the bias circuit. Furthermore, the dimensions of PMOS transistors P1, P2, and P3 in the bias circuit, as well as the value of the current source I1, need to be designed according to the specific application to ensure a stable reference current. The dimensions of PMOS transistors P4 and P5 in the differential pair comparator also need to be selected based on the range of the input signal and the comparator's gain.

[0069] In summary, this embodiment provides a constant current source structure that can operate in ultra-low voltage environments, featuring low power consumption, high stability, and a wide range of current regulation capabilities. It is suitable for various low-voltage applications, such as portable devices and low-power sensors, where power supply voltage requirements are relatively low.

[0070] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A structure for an ultra-low voltage constant current source, characterized in that, include: The system comprises a differential pair comparator and a depletion-type NMOS transistor N1. The output of the differential pair comparator is connected to the depletion-type NMOS transistor N1 to provide a control signal, and the turn-on voltage of the depletion-type NMOS transistor N1 is negative. The depletion-type NMOS transistor N1 is grounded through resistor R2 to form a constant current output terminal. The non-inverting input of the differential pair comparator is connected to a reference voltage Vref, and the inverting input is connected to the source feedback voltage Vfb of the depletion-type NMOS transistor N1. Through the negative feedback of the differential pair comparator, Vfb tends to Vref, so that the output current I satisfies I=Vref / R2 to form a constant current. The differential pair comparator includes a current source I1, PMOS transistors P1, P2, P3, P4, and P5, and NMOS transistors N2, N3, and N4, wherein PMOS transistors P4 and P5 are low turn-on voltage PMOS transistors. The source of PMOS transistor P1, the substrate of PMOS transistor P1, the source of PMOS transistor P2, the substrate of PMOS transistor P2, the source of PMOS transistor P3, the substrate of PMOS transistor P3, and the gate of depletion-type NMOS transistor N1 are connected to the power supply voltage Vcc. The gate of PMOS transistor P1, the drain of PMOS transistor P1, the gate of PMOS transistor P2, the gate of PMOS transistor P3, and the drain of PMOS transistor P1 are connected to the current source I1. The drain of PMOS transistor P2 is connected to the source of PMOS transistor P4, the substrate of PMOS transistor P4, the source of PMOS transistor P5, and the substrate of PMOS transistor P5. The drain of the PMOS transistor P3 is connected to the gate of the depletion-type NMOS transistor N1 and the drain of the NMOS transistor N4; The drain of the PMOS transistor P4, the drain of the NMOS transistor N2, the gate of the NMOS transistor N2, and the gate of the NMOS transistor N3 are connected together. The gate of the PMOS transistor P5 is connected to the reference voltage Vref, and the drain of the PMOS transistor P5 is connected to the drain of the NMOS transistor N3 and the gate of the NMOS transistor N4. The source of NMOS transistor N2, the substrate of NMOS transistor N2, the source of NMOS transistor N3, the substrate of NMOS transistor N3, the source of NMOS transistor N4, and the substrate of NMOS transistor N4 are all grounded. The source of the depletion-type NMOS transistor N1 is connected to the gate of the PMOS transistor P4 and grounded through the resistor R2.

2. The ultra-low voltage constant current source structure according to claim 1, characterized in that, The differential pair comparator also includes a resistor R1 and a capacitor C1: One end of the resistor R1 is connected to the upper plate of the capacitor C1, and the other end is connected to the gate of the NMOS transistor N4. The lower plate of capacitor C1 is connected to the drain of NMOS transistor N4.

3. The ultra-low voltage constant current source structure according to claim 1, characterized in that, In the differential pair comparator: the PSUB terminals of PMOS transistors P1, P2, P3, P4, and P5 are all grounded.

4. The ultra-low voltage constant current source structure according to claim 1, characterized in that, The turn-on voltage of PMOS transistors P4 and P5 is 0.5V.

5. The ultra-low voltage constant current source structure according to claim 1, characterized in that, The turn-on voltage of the depletion-type NMOS transistor N1 is -0.3V, so that the operating voltage of the constant current source structure is as low as 0.5V.

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