Embedded RDMA system and method for multi-source sensor access scenarios

Abstract

The present invention relates to an embedded RDMA system and method for multi-source sensor access scenarios. This system encapsulates transmitted data into an RDMA message format and correctly implements hardware adaptation for RDMA in multi-source sensor access scenarios. The system provides a software communication interface and software message parsing and response processing on the software side, a sensor communication interface and DDR read / write management on the sensor side, and transmission control offload for the RDMA message processing logic module. This system addresses technical issues such as standard compatibility, software-hardware collaboration, and reliable transmission associated with RDMA in multi-source sensor access scenarios. Furthermore, it provides high-performance network transmission for sensor data transmission with high bandwidth, low latency, and low CPU overhead.

Description

Technical Field

[0001] The present invention belongs to the field of computer technology and relates to an embedded RDMA system and method for multi-source sensor access scenarios. Background Art

[0002] RDMA (Remote Direct Memory Access), leveraging its zero-copy, kernel bypass, and CPU offload design principles, enables reliable network communication with high bandwidth, low latency, and low CPU overhead by offloading the protocol stack to the hardware network interface card (NIC). It has been widely adopted in high-performance computing and data centers. With the rapid development of technologies such as autonomous driving and the Industrial Internet of Things, unmanned vehicles require comprehensive environmental perception and rapid response using multiple sensors, placing higher demands on the performance of data acquisition and transmission. Current data acquisition and communication methods include point-to-point communication methods like MIPI and USB3 Vision, which lack scalability and have limited bandwidth. Bus-based communication methods like CAN and MOST have low bandwidth. Software network protocol stacks using Ethernet-based communication methods like RTP / GigE Vision have high overhead, resulting in high processing latency and significant CPU resource consumption. Extending RDMA to multi-sensor access scenarios will help meet the requirements for reliable communication with high bandwidth and low latency while minimizing CPU resource consumption.

[0003] However, existing RDMA solutions require general-purpose CPUs to support the RDMA protocol stack, making them inadequate for the computationally intensive needs of embedded scenarios requiring multi-source sensor access. Regarding standard compatibility, current embedded RDMA technology approaches rely on the InfiniBand Trade Association (IBTA)-developed IB protocol standard, with custom protocol modifications for acquisition and integration. This makes interoperability with commercial RDMA network cards like the NVIDIA ConnectX series difficult, hindering practical deployment and application. Regarding hardware-software collaboration, RDMA protocol stack deployments for multi-source sensor access often utilize embedded CPU cores with relatively weak computing power. Given the high operating frequency and processing speed of hardware, these weak CPU cores must participate in the initiation control before each data transfer and the CQE (Completion Queue Entry) processing after the transfer completes, significantly impacting RDMA transmission performance. Current technology approaches for multi-source sensor access have not been optimized to address this issue. Regarding reliability, most current technology approaches utilize the RDMA UD (Unreliable Datagram) transmission method to simplify hardware implementation. However, this UD transmission method can only transmit a maximum of 4KB of data per transmission, making it unsuitable for large-scale sensor data transmission and unable to guarantee transmission reliability.

[0004] Furthermore, in scenarios with multi-source sensor access, the sensor data has different traffic characteristics. Temperature and humidity sensors with smaller data volumes may package periodically collected data and transmit it in fixed-size blocks, while audio and video stream data from cameras are often streamed as continuous byte streams. To ensure reliable transmission, embedded RDMA architectures and systems for multi-source sensor access scenarios need to resolve the contradiction between the continuous writing of sensor data and the need for reliable RDMA reading. Currently, there is no mature technology that can effectively guarantee RDMA transmission reliability in streaming scenarios. This is especially difficult to ensure data integrity and real-time requirements when dealing with special situations such as RDMA retransmissions and when the streaming data storage space is full and overwritten. Summary of the Invention

[0005] In response to the problems existing in the above-mentioned traditional technologies, the present invention proposes an embedded RDMA system for multi-source sensor access scenarios and an embedded RDMA method for multi-source sensor access scenarios, which can provide high-performance network transmission with high bandwidth, low latency and low CPU overhead for sensor data transmission.

[0006] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0007] On the one hand, an embedded RDMA system for multi-source sensor access scenarios is provided, including a sensor communication interface, an RDMA peer communication interface, a software communication interface, a DDR controller, a software configuration message parsing and response module, an RDMA message processing logic module, an RDMA transmission control offload module, and a DDR read and write management module;

[0008] The DDR read and write management module is respectively connected to the sensor communication interface, the DDR controller and the RDMA transmission control offload module; the RDMA message processing logic module is respectively connected to the RDMA transmission control offload module, the RDMA peer communication interface, the software communication interface, the software configuration message parsing response module and the DDR controller; the software configuration message parsing response module is respectively connected to the software communication interface and the RDMA transmission control offload module; the software communication interface is used to connect to the embedded RDMA software end;

[0009] The sensor communication interface is used to obtain sensor data. The RDMA peer communication interface is used to exchange RDMA messages, two-end link establishment messages, and communication control messages with the RDMA communication peer. The software communication interface is used to transmit software configuration messages, link establishment messages, and ARP request response messages. The DDR controller is used to control the peripheral DDR memory. The software configuration message parsing and response module is used to parse, process, and forward software message types, and to configure the RDMA message processing logic module and the RDMA transmission control offload module. The RDMA message processing logic module is used to encapsulate RDMA messages, parse RDMA messages, and implement packet retransmission. The RDMA transmission control offload module is used to offload the RDMA transmission startup and completion processing corresponding to the standard RDMA protocol stack to hardware execution. The DDR read and write management module is used to maintain and update the DDR read and write pointers based on the sensor data writing and the reading of the RDMA message processing logic module.

[0010] On the other hand, an embedded RDMA method for multi-source sensor access scenarios is also provided, which is applied to an embedded RDMA system for multi-source sensor access scenarios. The embedded RDMA system includes a sensor communication interface, an RDMA peer communication interface, a software communication interface, a DDR controller, a software configuration message parsing and response module, an RDMA message processing logic module, an RDMA transmission control offload module, and a DDR read and write management module.

[0011] The DDR read and write management module is respectively connected to the sensor communication interface, the DDR controller and the RDMA transmission control offload module; the RDMA message processing logic module is respectively connected to the RDMA transmission control offload module, the RDMA peer communication interface, the software communication interface, the software configuration message parsing response module and the DDR controller; the software configuration message parsing response module is respectively connected to the software communication interface and the RDMA transmission control offload module; the software communication interface is used to connect to the embedded RDMA software end;

[0012] The sensor communication interface is used to obtain sensor data. The RDMA peer communication interface is used to exchange RDMA messages, two-end link establishment messages, and communication control messages with the RDMA communication peer. The software communication interface is used to transmit software configuration messages, link establishment messages, and ARP request response messages. The DDR controller is used to control the peripheral DDR memory. The software configuration message parsing and response module is used to parse, process, and forward software message types, and to configure the RDMA message processing logic module and the RDMA transmission control offload module. The RDMA message processing logic module is used to encapsulate RDMA messages, parse RDMA messages, and implement packet retransmission. The RDMA transmission control offload module is used to offload the RDMA transmission startup and completion processing corresponding to the standard RDMA protocol stack to hardware execution. The DDR read and write management module is used to maintain and update the DDR read and write pointers based on the sensor data writing and the reading of the RDMA message processing logic module.

[0013] The embedded RDMA method includes the following steps:

[0014] When the system is powered on, the hardware network port negotiates the physical link and sequentially receives ARP request messages, metadata configuration messages, link establishment messages, and transmission control messages from the software communication interface. The software configuration message parsing and response module performs preliminary message parsing, forwarding, or configuration, and constructs and aggregates response messages corresponding to each request and provides them to the embedded RDMA software.

[0015] The RDMA transmission control offload module parses the transmission control message and configures it according to the parsed transmission control parameters;

[0016] After receiving the software acquisition startup configuration, the sensor data is imported through the sensor communication interface, and the DDR read and write management module converts the sensor data into an AXIS stream and writes it into the DDR memory through the DDR controller;

[0017] The RDMA transmission control offload module constructs a WQE and writes it to the on-chip cache SQ based on the software configuration parameters and the pre-read pointer information provided by the DDR read and write management module. The RDMA transmission control offload module sends the SQ doorbell information to the RDMA message processing logic module based on the software configuration parameters and the number of WQEs.

[0018] The RDMA message processing logic module reads the corresponding WQE in the on-chip cache based on the SQ Doorbell information, obtains the sensor data through the DDR controller, and constructs and sends the RDMA write request message;

[0019] After all the response messages corresponding to the request messages are received, the RDMA message processing logic module constructs a CQE and stores it in the on-chip cache CQ;

[0020] The RDMA transmission control offload module monitors the CQE write signal of the RDMA message processing logic module, reads the CQE, parses it, and provides the CQN information to the DDR read and write management module to update the read pointer; at the same time, the RDMA transmission control offload module sends the CQ Doorbell to the RDMA message processing logic module to update the CQ status.

[0021] One of the above technical solutions has the following advantages and beneficial effects:

[0022] The embedded RDMA system and method for multi-source sensor access scenarios can encapsulate transmitted data into RDMA message formats and correctly implement RDMA hardware adaptation in multi-source sensor access scenarios. By providing a software communication interface and software message parsing and response processing on the software side, a sensor communication interface and DDR read / write management on the sensor side, and transmission control offload for the RDMA message processing logic module, this system addresses technical issues such as standard compatibility, software-hardware collaboration, and reliable transmission in RDMA applications in multi-source sensor access scenarios. It can provide high-performance network transmission with high bandwidth, low latency, and low CPU overhead for sensor data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 Schematic diagram of the architecture of an embedded RDMA system for multi-source sensor access scenarios in one embodiment;

[0025] Figure 2 A schematic diagram of the internal design of a message parsing submodule in one embodiment;

[0026] Figure 3 A schematic diagram of the internal design of a CQE polling submodule in one embodiment;

[0027] Figure 4 A schematic diagram of the internal design of a DDR read / write management module in one embodiment;

[0028] Figure 5 The figure is a flowchart of an embedded RDMA method for a multi-source sensor access scenario in one embodiment. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing the specific embodiments and are not intended to limit the present invention.

[0030] It should be noted that, when referred to in this document as an "embodiment", it means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be understood by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in this document refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0031] The following describes the implementation of the present invention in detail with reference to the accompanying drawings in the embodiments of the present invention.

[0032] As can be understood, to address existing issues in the background technology, the present invention provides an embedded RDMA system for multi-source sensor access scenarios. This system addresses issues related to standard compatibility, software-hardware collaboration, and reliable transmission (especially for streaming transmission) in RDMA applications in these scenarios. This system meets the high-performance network transmission requirements of multi-source sensor access scenarios, including high bandwidth, low latency, and low CPU overhead. This embedded RDMA architecture and system is compatible with the standard RDMA protocol and utilizes software-configurable transmission parameters to provide flexible access for sensor data acquisition. Through transmission control hardware offload and DDR hardware storage management, it achieves high-performance, low-network processing overhead embedded RDMA reliable transmission services.

[0033] In one embodiment, Figure 1As shown, an embedded RDMA system for multi-source sensor access scenarios includes a sensor communication interface 10, an RDMA peer communication interface 20, a software communication interface 30, a DDR controller 40, a software configuration message parsing and response module 50, an RDMA message processing logic module 60, an RDMA transmission control offload module 70, and a DDR read / write management module 80. The DDR read / write management module 80 is connected to the sensor communication interface 10, the DDR controller 40, and the RDMA transmission control offload module 70. The RDMA message processing logic module 60 is connected to the RDMA transmission control offload module 70, the RDMA peer communication interface 20, the software communication interface 30, the software configuration message parsing and response module 50, and the DDR controller 40. The software configuration message parsing and response module 50 is connected to the software communication interface 30 and the RDMA transmission control offload module 70. The software communication interface 30 is used to connect to the embedded RDMA software (end).

[0034] The sensor communication interface 10 is used to acquire sensor data and can be deserialized and decoded using Xilinx SDI-related IP cores. The RDMA peer communication interface 20 exchanges RDMA messages, two-way link establishment messages, and communication control messages (such as RDMA messages, ARP messages, and UDP messages) with the RDMA communication peer. It can utilize the Xilinx UltraScale (FPGA) + 100GEthernet Subsystem IP core. The software communication interface 30 transmits software configuration messages, link establishment messages, and ARP request and response messages, and can utilize the Xilinx AXI 1G Ethernet Subsystem IP core.

[0035] The DDR controller 40 controls peripheral DDR memory (such as DDR4) and can directly call upon the relevant Xilinx IP core. The software configuration message parsing response module 50 parses and processes software message types, forwards them, and configures the RDMA message processing logic module 60 and the RDMA transmission control offload module 70. The RDMA message processing logic module 60 encapsulates and parses RDMA messages, and implements packet retransmission to ensure transmission reliability. The specific design of this module can refer to the relevant processing logic of the Xilinx ERNIC IP core. The RDMA transmission control offload module 70 constructs a WQE and the corresponding SQ Doorbell before RDMA transmission begins, and sends it to the RDMA message processing logic module 60. It also processes the CQE constructed by the RDMA message processing logic module 60 after the transmission is complete, and sends it to the CQ Doorbell. The DDR read / write management module 80 maintains and updates the DDR read / write pointers.

[0036] It can be understood that the embedded RDMA system for multi-source sensor access scenarios provided in this embodiment has an overall system architecture consisting of peripheral interfaces, software configuration message parsing and response, RDMA message processing logic, RDMA transfer control offload module, and DDR read / write management module. Its main functions are to hardware offload RDMA transfer initiation and completion processing while being compatible with the standard RDMA protocol, and to ensure data integrity and reliable RDMA transmission through collected data storage management. This embedded RDMA architecture and system can be deployed using a Xilinx UltraScale (FPGA) + VCU118 development board. Its PCIe interface is disabled, and it also includes a 10 / 100 / 1000Mbps SGMII Ethernet interface and two QSFP28 interfaces (100Gbps). In terms of memory resources, it provides 4MB of on-chip cache and two 2.5GB DDR4 memory sticks.

[0037] Peripheral interfaces include sensor communication, peer communication, and software communication, respectively connecting acquisition sensors (i.e., sensing devices), RDMA communication peers, embedded RDMA software, and DDR memory. For acquisition sensors, such as the SDI interface of a camera input (other acquisition interfaces can be substituted without affecting the overall mechanism), signals are connected to the GTX / GTH transceiver on the VCU118 development board via the FMC HPC interface on the ALINX FH12219. These signals are then converted into AXI4-Stream video streams using the relevant Xilinx IP cores and fed into the embedded RDMA system. High-bandwidth sensor data communication with the RDMA communication peer is achieved via a 100G optical port. Custom configuration messages, such as those exchanged with the embedded RDMA software, are communicated via a 1000Mbps network port. For DDR memory, a DDR controller is used to read and write DDR storage space.

[0038] The RDMA message processing logic module is used to complete RDMA request message encapsulation and receive message parsing, and ensures transmission reliability through the Go-back-N (policy) retransmission mechanism. This embodiment mainly uses the existing RDMA message processing logic module to implement an embedded integrated design for multi-source sensor access scenarios. In addition, the VCU118 development board's on-chip cache is used to store RDMA QPs (Queue Pairs, which are the basic units for managing and controlling data transmission). This allows the RDMA message processing logic module to quickly read SQ (Send Queue) WQEs (Work Queue Entry) and write corresponding CQ (Completion Queue) CQEs (Completion Queue Entry).

[0039] The software configuration message parsing and response module parses messages received from the embedded RDMA software and sends back responses to ensure reliable hardware-software interaction. For various message types sent by the software, including UDP link establishment messages, transmission start and stop control messages, metadata configuration messages, and ARP request response messages, the software configuration message parsing and response module identifies the different message types and provides corresponding response messages. Furthermore, the software configuration message parsing and response module forwards relevant information based on the message type to other hardware modules for further processing.

[0040] The RDMA transmission control offload module offloads the RDMA transmission initiation and completion processing corresponding to the standard RDMA protocol stack to hardware (such as Xilinx UltraScale) for execution. This prevents weak CPU cores from participating in transmission start and stop, which could affect hardware transmission performance. Transmission control offload specifically offloads WQE construction, SQ Doorbell delivery, CQE processing, and CQ Doorbell delivery to hardware implementation. This ensures that the RDMA message processing logic module can normally obtain Doorbells and WQEs, and that related CQEs can be correctly processed at the hardware level.

[0041] The DDR read / write management module is used to maintain and update the DDR read / write pointers based on the sensor data writes and reads from the RDMA message processing logic module. Taking video streaming as an example, to ensure correct system operation under abnormal conditions such as DDR full writes and RDMA retransmissions (to avoid DDR data overwriting and the inability to obtain the expected retransmitted data), the DDR read / write pointer updates are designed to correspond one-to-one with the RDMA QP processing status. Specifically, the DDR write pointer is updated based on the sensor data write status and triggers WQE construction. The DDR pre-read pointer is updated based on the WQE construction status, and the DDR read pointer is updated based on the CQE completion status. This allows the pre-read and read pointers to lock the DDR space in the SQ where the WQE has been constructed but the CQE has not yet been received, thus avoiding incorrect retransmitted data.

[0042] In one embodiment, the software configuration message parsing response module 50 further includes a message parsing submodule and a message response submodule. The message parsing submodule first performs message assembly to combine 8-bit data into 512-bit data blocks after receiving data from the gigabit network port, and then classifies different types of messages by message diversion. The message response submodule caches the Ethernet message, metadata configuration response message, and transmission parameter configuration response message from the RDMA peer separately and arbitrates them according to the design priority. Then, the data decomposition submodule decompositions and assembles the 520-bit FIFO data into the 8-bit data format supported by AXI4-Stream.

[0043] Specifically, the data received by the message parsing submodule from the gigabit network port is first assembled into 512-bit data blocks by message assembly (Assemble) 501, and then classified into different types of messages by message decomposition (Type_Dec) 502. The internal design diagram is shown in the figure below. Figure 2 As shown. Ethernet message processing 503, including link establishment and acquisition control responses, sent by the software, sends them to the RDMA message processing logic module 60 for forwarding to the RDMA communication peer. Token bucket configuration message processing 504 completes configuration via the configuration register path provided by the RDMA message processing logic module 60. Mbox configuration message processing 505 performs metadata configuration via the Mbox interaction mechanism of the RDMA message processing logic module 60, and Mbox response message aggregation 506 constructs a corresponding response message and sends it to the message response submodule. Transmission parameter configuration message processing 507 passes it to the RDMA transmission control offload module 70 for further processing. Accordingly, the message response submodule caches the Ethernet messages, metadata configuration response messages, and transmission parameter configuration response messages from the RDMA peer, arbitrates them based on design priorities, and then uses data disassembly to disassemble the 520-bit FIFO data into the 8-bit data format supported by AXI4-Stream. Among them, ETH_Pkt_Data represents Ethernet message data, Token_Data represents token data, MboxW / MboxR represents write / read data of the message queue, ACK_Pkt_Data represents response message data, and Reg_Pkt_Data represents transmission parameter configuration message.

[0044] In one embodiment, the RDMA transmission control offload module 70 further includes a Reg_Ctrl submodule, a WQE construction submodule, a communication parameter configuration submodule, an SQ Doorbell construction submodule, a CQE polling submodule, and a CQDoorbell construction submodule. The Reg_Ctrl submodule is used to parse the software transmission parameter configuration message obtained from the software configuration message parsing response module and configure it to the corresponding module, while also constructing the corresponding response message based on the parsed message field parameters. The WQE construction submodule is used to construct a WQE and write it to the on-chip cache based on the transmission parameters provided by the communication parameter configuration submodule and the write pointer information provided by the DDR read / write management module, while also outputting the PI pointer required by the SQ Doorbell construction submodule. The communication parameter configuration submodule is also used to provide acquisition start and stop control information. The SQ Doorbell construction submodule is used to notify the RDMA message processing logic module of new WQEs to be processed, count WQEs based on the doorbell_rate parameter provided by the transmission parameter configuration message processing, and construct and issue an SQ Doorbell when the WQE count reaches the value of the doorbell_rate parameter. The CQE polling submodule monitors the RDMA message processing logic module's AXI write operations to the on-chip cache, determines whether they are CQEs based on the write address range, and outputs the CQE pointer and CI pointer. The CQ Doorbell construction submodule notifies the RDMA message processing logic module that the constructed CQE has been processed.

[0045] Specifically, within the Reg_Ctrl submodule, the transmission parameter processing module Reg_Dec parses the software transmission parameter configuration message received from the software configuration message parsing and response module 50 and assigns it to the corresponding functional module. Simultaneously, the Reg_Ack_Con (transmission acknowledgment response module) constructs the corresponding response message based on the parsed message field parameters. The transmission parameters used are shown in Table 1. The WQE construction submodule constructs a WQE based on the transmission parameters provided by the communication parameter configuration submodule and the write pointer information provided by the DDR read / write management module 80, writes it to the on-chip cache, and outputs information such as the PI pointer required for the SQ Doorbell construction submodule. Furthermore, the acquisition start / stop control information provided by the communication parameter configuration submodule is used to control whether the WQE construction submodule can continue or pause WQE construction. The interface signals of the WQE construction submodule are shown in Table 2.

[0046] The SQ Doorbell construction submodule is used to inform the RDMA message processing logic module 60 that a new WQE is pending. This submodule counts WQEs based on the doorbell_rate parameter provided by the transmission parameter configuration message processing 507. Once the WQE count reaches this parameter value, it constructs and sends an SQ Doorbell. In the CQE polling submodule, CQE_Record (completion queue entry write unit) 701 monitors the AXI write operations of the RDMA message processing logic module 60 to the on-chip cache and determines whether it is a CQE based on the write address range. CQE_Read (completion queue entry read unit) 702 reads the CQE data and sends it to Ctrl_Gen (control signal generation) logic 703. Ctrl_Gen logic 703 parses the CQE content and outputs information such as the CQE pointer and CI pointer for use by the CQ Doorbell construction submodule and the DDR read / write management module 80. The internal design diagram of the CQE polling submodule is shown in Figure 2. Figure 3 The CQ Doorbell construction submodule is used to inform the RDMA message processing logic module 60 that the CQE it has constructed has been processed. The SQ / CQ Doorbell data structure is shown in Table 3.

[0047]

[0048] Specifically, the internal design diagram of the DDR read / write management module 80 is as follows: Figure 4 As shown in the figure, RGBtoAXIS (RGB to AXIS unit) 801 converts the RGB video signal (for the camera) into an AXIS stream for FPGA processing. Data buffer (FIFO_64to512) 802 temporarily stores the input sensor data. AXI_WR (AXI read / write unit) 803 polls the FIFO (first-in, first-out) status. When the data volume meets the AXI burst write condition, the data is written to the DDR memory. Simultaneously, the write pointer is dynamically adjusted to skip overwritable areas where a WQE has been sent but a corresponding CQE has not yet been received (by comparing the write pointer, read pointer, and read-ahead pointer). AXIS, short for AXI4-Stream, belongs to the Xilinx AXI (Advanced eXtensible Interface) protocol family and is specifically designed for high-speed streaming data (such as video and audio streaming). Raddr and Waddr represent reading from and writing to DDR memory, respectively, and WQE_Len represents the WQE length.

[0049] Based on the write pointer information provided by AXI_WR 803 and the pre-read pointer and read pointer information it maintains, Addr_Ctrl (the address control unit) 804 determines the unsent area in the DDR memory that has been written but for which a CQE has not yet been constructed. (Under normal circumstances, this area is between the pre-read pointer and the write pointer; if the DDR memory wraps around after a full write, this area is between the pre-read pointer and the end of the DDR memory and between the beginning of the DDR memory and the write pointer.) If the unsent area exceeds the Message_Size parameter provided by the Reg_Ctrl submodule, it triggers a valid signal from the WQE construction submodule and updates the pre-read pointer. It also updates the read pointer after receiving a completion signal from the CQE polling submodule. Furthermore, upon receiving an acquisition pause signal, the pre-read pointer pauses updates, while the write and read pointers continue to update.

[0050] In some embodiments, to make the technical method of the present invention more clear and understandable, the following further describes the detailed operation process of the above-mentioned embedded RDMA system for multi-source sensor access scenarios with reference to the accompanying drawings and combined with operation examples:

[0051] When the system is powered on, the hardware network port negotiates the physical link and sequentially receives ARP (Address Resolution Protocol) request messages, metadata configuration messages, link establishment messages, and transmission control messages from the software communication interface 30. The message parsing submodule in the software configuration message parsing and response module 50 performs preliminary message parsing and further forwarding (or configuration). The message response submodule then constructs and aggregates response messages corresponding to each request and provides them to the embedded RDMA software. The communication parameter configuration submodule in the RDMA transmission control offload module 70 parses the transmission control messages and sends the transmission control parameters to submodules such as the WQE configuration and SQ Doorbell configuration for configuration.

[0052] After receiving the software acquisition startup configuration, the sensor data imported by the sensor device is imported through the sensor communication interface, converted into an AXIS stream by the RGBtoAXIS submodule of the DDR read and write management module 80, and then written into the DDR4 memory by the AXI_WR submodule through the DDR controller 40.

[0053] The WQE construction submodule in the RDMA transmission control offload module 70 constructs a WQE based on the software configuration parameters and the pre-read pointer information provided by the Addr_Ctrl (address control) submodule in the DDR read and write management module 80 and writes it into the on-chip cache SQ. The SQ Doorbell construction submodule sends the SQ Doorbell information to the RDMA message processing logic module 60 based on the software configuration parameters and the number of WQEs.

[0054] The RDMA message processing logic module 60 reads the corresponding WQE in the on-chip cache according to the SQ Doorbell information, obtains the sensor data through the DDR controller 40, constructs and sends an RDMA WRITE (or WRITE with imm, that is, using the immediate number imm as the operand to perform a write operation) request message.

[0055] One WQE may correspond to multiple request messages. After all the response messages corresponding to the request messages are received, the RDMA message processing logic module 60 constructs a CQE and stores it in the on-chip cache CQ.

[0056] The CQE polling submodule in the RDMA transmission control offload module 70 monitors the CQE write signal of the RDMA message processing logic module 60, reads the CQE, parses it, and provides information such as the CQN to the Addr_Ctrl submodule to update the read pointer. At the same time, it triggers the CQ Doorbell construction submodule to send the CQ Doorbell to the RDMA message processing logic module 60 to update the CQ status.

[0057] After that, the sensor data can continue to be imported from the sensor device into the DDR memory, and the DDR write pointer update operation starts the next RDMA transmission process in a loop until the acquisition pause configuration is received or the system transmission task is completed.

[0058] Each module in the aforementioned embedded RDMA system for multi-source sensor access scenarios can be implemented in whole or in part through software, hardware, or a combination thereof. These components can be embedded in or independent of a device with radar data processing capabilities in hardware form, or stored in the memory of the aforementioned device in software form, allowing the processor to call and execute the corresponding operations of each module. The aforementioned device can be, but is not limited to, various types of computers known in the art.

[0059] In one embodiment, an embedded RDMA method for multi-source sensor access scenarios is also provided, which is applied to an embedded RDMA system for multi-source sensor access scenarios. The embedded RDMA system includes a sensor communication interface, an RDMA peer communication interface, a software communication interface, a DDR controller, a software configuration message parsing and response module, an RDMA message processing logic module, an RDMA transmission control offload module, and a DDR read / write management module. The DDR read / write management module is respectively connected to the sensor communication interface, the DDR controller, and the RDMA transmission control offload module. The RDMA message processing logic module is respectively connected to the RDMA transmission control offload module, the RDMA peer communication interface, the software communication interface, the software configuration message parsing and response module, and the DDR controller. The software configuration message parsing and response module is respectively connected to the software communication interface and the RDMA transmission control offload module. The software communication interface is used to connect to the embedded RDMA software end. The sensor communication interface is used to obtain sensor data. The RDMA peer communication interface is used to exchange RDMA messages, two-end link establishment messages, and communication control messages with the RDMA communication peer. The software communication interface is used to transmit software configuration messages, link establishment messages, and ARP request response messages. The DDR controller is used to control the peripheral DDR memory. The software configuration message parsing and response module is used to parse, process, and forward software message types, and to configure the RDMA message processing logic module and the RDMA transmission control offload module. The RDMA message processing logic module is used to encapsulate RDMA messages, parse RDMA messages, and implement packet retransmission. The RDMA transmission control offload module is used to offload the RDMA transmission startup and completion processing corresponding to the standard RDMA protocol stack to hardware execution. The DDR read and write management module is used to maintain and update the DDR read and write pointers based on the sensor data writing and the reading of the RDMA message processing logic module.

[0060] like Figure 5 As shown, the above embedded RDMA method may include the following steps:

[0061] S10: The system is powered on, the hardware network port negotiates the physical link, and receives ARP request messages, metadata configuration messages, link establishment messages, and transmission control messages from the software communication interface in sequence. The software configuration message parsing and response module performs preliminary message parsing, forwarding, or configuration, and constructs and aggregates response messages corresponding to each request and provides them to the embedded RDMA software.

[0062] S12, the RDMA transmission control offload module parses the transmission control message and configures according to the parsed transmission control parameters;

[0063] S14, after receiving the software acquisition startup configuration, the sensor data is imported through the sensor communication interface, and the DDR read and write management module converts the sensor data into an AXIS stream and writes it into the DDR memory through the DDR controller;

[0064] S16: The RDMA transmission control offload module constructs a WQE and writes it into the on-chip cache SQ based on the software configuration parameters and the pre-read pointer information provided by the DDR read / write management module. The RDMA transmission control offload module sends the SQ Doorbell information to the RDMA message processing logic module based on the software configuration parameters and the number of WQEs.

[0065] S18, the RDMA message processing logic module reads the corresponding WQE in the on-chip cache according to the SQ Doorbell information, obtains the sensor data through the DDR controller, constructs and sends an RDMA write request message;

[0066] S20, after all the response messages corresponding to the request messages are received, the RDMA message processing logic module constructs a CQE and stores it in the on-chip cache CQ;

[0067] S22, the RDMA transmission control offload module monitors the CQE write signal of the RDMA message processing logic module, reads the CQE, parses it, and provides the CQN information to the DDR read and write management module to update the read pointer; at the same time, the RDMA transmission control offload module sends the CQ Doorbell to the RDMA message processing logic module to update the CQ status.

[0068] Afterwards, the remaining sensor data transmission operations may be continued from step S14.

[0069] This embedded RDMA approach for multi-source sensor access scenarios encapsulates transmitted data into the RDMA message format and correctly implements RDMA hardware adaptation for multi-source sensor access scenarios. By providing a software communication interface and software message parsing and response processing on the software side, a sensor communication interface and DDR read / write management on the sensor side, and transmission control offload for the RDMA message processing logic module, it addresses technical challenges associated with applying RDMA in multi-source sensor access scenarios, such as standard compatibility, software-hardware collaboration, and reliable transmission. This approach provides high-performance network transmission with high bandwidth, low latency, and low CPU overhead for sensor data transmission.

[0070] In one embodiment, the software configuration message parsing response module includes a message parsing submodule and a message response submodule. The message parsing submodule first performs message assembly to combine 8-bit data into 512-bit data blocks after receiving data from the gigabit network port. Message diversion then classifies and processes different types of messages. The message response submodule caches the Ethernet message, metadata configuration response message, and transmission parameter configuration response message from the RDMA peer separately and arbitrates them based on design priorities. The data decomposition and assembly process then decompresses the 520-bit FIFO data into the 8-bit data format supported by AXI4-Stream.

[0071] In one embodiment, the RDMA transmission control offload module includes a Reg_Ctrl submodule, a WQE construction submodule, a communication parameter configuration submodule, an SQ Doorbell construction submodule, a CQE polling submodule, and a CQ Doorbell construction submodule. The Reg_Ctrl submodule is responsible for parsing the software transmission parameter configuration message received from the software configuration message parsing response module and configuring it to the corresponding module. It also constructs the corresponding response message based on the parsed message field parameters. The WQE construction submodule is responsible for constructing a WQE and writing it to the on-chip cache based on the transmission parameters provided by the communication parameter configuration submodule and the write pointer information provided by the DDR read / write management module. It also outputs the PI pointer required by the SQ Doorbell construction submodule. The communication parameter configuration submodule is also responsible for providing acquisition start and stop control information. The SQ Doorbell construction submodule is responsible for notifying the RDMA message processing logic module of new WQEs to be processed, counting WQEs based on the doorbell_rate parameter provided by the transmission parameter configuration message processing, and constructing and issuing an SQ Doorbell when the WQE count reaches the value of the doorbell_rate parameter. The CQE polling submodule monitors the RDMA message processing logic module's AXI write operations to the on-chip cache, determines whether they are CQEs based on the write address range, and outputs the CQE pointer and CI pointer. The CQ Doorbell construction submodule notifies the RDMA message processing logic module that the constructed CQE has been processed.

[0072] It should be understood that although the above process Figure 5 The steps in the flowchart are shown in the order indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Figure 5At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0073] All of the above optional technical solutions can be combined in any way to form optional embodiments of the present application, and will not be described in detail here.

[0074] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the above-described method embodiments. Any reference to memory, storage, database, or other media used in the various embodiments provided herein may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus DRAM (RDRAM), and DDR DRAM.

[0075] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0076] The above embodiments merely illustrate several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of the present invention.

Claims

1. An embedded RDMA system for multi-source sensor access scenarios, characterized by: It includes sensor communication interface, RDMA peer communication interface, software communication interface, DDR controller, software configuration message parsing response module, RDMA message processing logic module, RDMA transmission control offload module and DDR read and write management module; The DDR read and write management module is respectively connected to the sensor communication interface, the DDR controller and the RDMA transmission control offload module; the RDMA message processing logic module is respectively connected to the RDMA transmission control offload module, the RDMA peer communication interface, the software communication interface, the software configuration message parsing response module and the DDR controller; the software configuration message parsing response module is respectively connected to the software communication interface and the RDMA transmission control offload module; the software communication interface is used to connect to the embedded RDMA software end; The sensor communication interface is used to obtain sensor data. The RDMA peer communication interface is used to exchange RDMA messages, two-end link establishment messages, and communication control messages with the RDMA communication peer. The software communication interface is used to transmit software configuration messages, link establishment messages, and ARP request response messages. The DDR controller is used to control the peripheral DDR memory. The software configuration message parsing response module is used to parse and forward software message types, as well as to configure the RDMA message processing logic module and the RDMA transmission control offload module. The RDMA message processing logic module is used to encapsulate RDMA messages, parse RDMA messages, and implement packet retransmission. The RDMA transmission control offload module is used to offload the RDMA transmission startup and completion processing corresponding to the standard RDMA protocol stack to hardware execution. The DDR read and write management module is used to maintain and update the DDR read and write pointers based on the sensor data writing and the reading of the RDMA message processing logic module. The software configuration message parsing response module includes a message parsing submodule and a message response submodule. The message parsing submodule first assembles the data received from the gigabit network port into 512-bit data blocks through message assembly, and then classifies different types of messages through message diversion. The message response submodule caches the Ethernet message, metadata configuration response message, and transmission parameter configuration response message of the RDMA peer and arbitrates them according to the design priority. Then, the data decompression and assembly process decomposes the 520-bit FIFO data into the 8-bit data format supported by AXI4-Stream.

2. The embedded RDMA system for multi-source sensor access scenarios according to claim 1 is characterized in that: The RDMA transmission control offload module includes the Reg_Ctrl submodule, the WQE construction submodule, the communication parameter configuration submodule, the SQDoorbell construction submodule, the CQE polling submodule and the CQ Doorbell construction submodule; The Reg_Ctrl submodule is used to parse the software transmission parameter configuration message obtained from the software configuration message parsing response module and configure it to the corresponding module, and construct the corresponding response message according to the parsed message field parameters; The WQE construction submodule is used to construct the WQE and write it into the on-chip cache based on the transmission parameters provided by the communication parameter configuration submodule and the write pointer information provided by the DDR read and write management module. At the same time, it outputs the PI pointer required by the SQ Doorbell construction submodule. The communication parameter configuration submodule is also used to provide acquisition start and stop control information; The SQ Doorbell construction submodule is used to inform the RDMA message processing logic module that there are new WQEs to be processed, and to count WQEs according to the doorbell_rate parameter provided by the transmission parameter configuration message processing. After the WQE count value reaches the value of the doorbell_rate parameter, the SQ Doorbell is constructed and issued. The CQE polling submodule is used to monitor the AXI write operations of the RDMA message processing logic module to the on-chip cache and determine whether it is CQE based on the write address range, and is used to output the CQE pointer and CI pointer; The CQ Doorbell construction submodule is used to inform the RDMA message processing logic module that the CQE constructed has been processed.

3. An embedded RDMA method for multi-source sensor access scenarios, characterized in that: Applied to the embedded RDMA system for multi-source sensor access scenarios described in claim 1 or 2, the embedded RDMA method comprises the steps of: When the system is powered on, the hardware network port negotiates the physical link and sequentially receives ARP request messages, metadata configuration messages, link establishment messages, and transmission control messages from the software communication interface. The software configuration message parsing and response module performs preliminary message parsing, forwarding, or configuration, and constructs and aggregates response messages corresponding to each request and provides them to the embedded RDMA software. The RDMA transmission control offload module parses the transmission control message and configures it according to the parsed transmission control parameters; After receiving the software acquisition startup configuration, the sensor data is imported through the sensor communication interface, and the DDR read and write management module converts the sensor data into an AXIS stream and writes it into the DDR memory through the DDR controller; The RDMA transmission control offload module constructs a WQE and writes it to the on-chip cache SQ based on the software configuration parameters and the pre-read pointer information provided by the DDR read and write management module. The RDMA transmission control offload module sends the SQ doorbell information to the RDMA message processing logic module based on the software configuration parameters and the number of WQEs. The RDMA message processing logic module reads the corresponding WQE in the on-chip cache based on the SQ Doorbell information, obtains the sensor data through the DDR controller, and constructs and sends the RDMA write request message; After all the response messages corresponding to the request messages are received, the RDMA message processing logic module constructs a CQE and stores it in the on-chip cache CQ; The RDMA transmission control offload module monitors the CQE write signal of the RDMA message processing logic module, reads the CQE, parses it, and provides the CQN information to the DDR read and write management module to update the read pointer; at the same time, the RDMA transmission control offload module sends the CQ Doorbell to the RDMA message processing logic module to update the CQ status.

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