A CPU micro-architecture parameter exploration method based on bayesian optimization

Abstract

The application provides a CPU micro-architecture parameter exploration scheme based on Bayesian optimization, which aims to realize end-to-end CPU design space exploration and optimization by constructing a CPU micro-architecture parameter exploration device with multiple confidence levels. The scheme combines the advantages of different confidence level simulation tools, not only realizes accurate calibration of low-cost low-confidence simulation, but also provides more accurate feedback information for the multi-confidence Bayesian optimization device. In addition, the scheme selects appropriate confidence level simulation tools according to the real-time distribution characteristics of data samples, thereby achieving the best balance between accuracy and efficiency of CPU design parameter exploration. Overall, the scheme effectively coordinates the contradiction between accuracy and time consumption of different confidence level simulation tools, and significantly improves the exploration efficiency of CPU micro-architecture design parameters.

Description

TECHNICAL FIELD

[0001] The present application relates to a general-purpose processor micro-architecture design parameter exploration method, in particular to the field of central processor design, more particularly to a CPU micro-architecture parameter exploration method based on Bayesian optimization. BACKGROUND

[0002] In CPU micro-architecture design, core parameters such as register file size, cache capacity, and operation unit configuration are key factors affecting the performance and energy efficiency of the CPU. Due to the high cost of tape-out, simulation tools are usually used to evaluate the performance and power consumption of specific CPU design parameters during the CPU design phase to guide the design and production of the CPU.

[0003] In the prior art, low-confidence simulation tools or high-confidence simulation tools are usually used for CPU design parameter simulation. Low-confidence simulation tools achieve efficient performance evaluation through high-level abstraction. For example, the Gem5 architecture simulator is a low-confidence simulation tool for simulating processor behavior. It is written in a high-level and abstract programming language (such as C / C++, Python) and can run on a normal computer. Generally speaking, the simulator focuses on simulating the behavior of CPU components at most, but not at the register transfer level. In addition, since the mainstream X86 and ARM instruction set chips are not open source, researchers cannot obtain the hardware description language code of these chips, and it is impossible to perform register transfer level and gate level simulation. Therefore, most CPU micro-architecture design space exploration is carried out in the architecture level using low-confidence simulation tools or prediction models. In addition, low-confidence simulation usually achieves higher simulation efficiency than high-confidence simulation by ignoring more circuit details. High-confidence simulation tools mainly focus on register transfer level or gate level, or even circuit level simulation. With the development of open source chips, researchers can more easily obtain chip design code to facilitate micro-architecture exploration using high-confidence simulation. However, high-confidence simulation takes a long time and can only be used to explore and evaluate within a limited design space. In addition, the time-consuming problem of high-confidence simulation becomes more serious with the increase of CPU design scale. Therefore, micro-architecture design parameter exploration of large-scale processor cores becomes more challenging.

[0004] The existing CPU micro-architecture parameter exploration scheme mainly focuses on the use and improvement of a single simulation tool, ignoring the attempt to combine different confidence simulation tools. Using a single simulation tool cannot effectively balance the efficiency and accuracy of simulation. Specifically, high-accuracy simulation has high computational cost and is difficult to apply on a large scale, while low-accuracy simulation has high efficiency but insufficient accuracy, making it difficult to meet the needs of design optimization. In addition, due to the low accuracy of the prediction results of low-accuracy simulation tools, how to improve the accuracy of low-accuracy simulation data has become a key problem faced by current technology. In recent years, although some schemes involve combining two or more simulation tools, they often collect data through high-accuracy simulation in advance and train models based on the collected data, and still use low-accuracy simulation tools for simulation in the later stage. This approach takes advantage of the high-precision simulation results of high-accuracy simulation, but still relies on low-accuracy simulation tools in the subsequent optimization process, failing to fully leverage the advantages of both simulation tools. For schemes that combine multiple simulation tools, how to effectively combine simulation tools of different confidence levels and achieve the best balance between efficiency and accuracy in the optimization process is also a problem that needs to be solved by current technology.

[0005] In summary, the existing CPU design parameter exploration scheme mostly focuses on the use and improvement of a single simulation tool, while ignoring the potential of combining different confidence simulation tools. Although some studies attempt to integrate multiple simulation tools, these studies usually only use high-accuracy simulation to collect data for model training in the early stage, and still rely on the simulation results of low-accuracy simulation tools in the subsequent optimization process, failing to fully exploit the synergistic advantages of both simulation tools. In summary, the existing CPU design parameter exploration scheme is difficult to achieve a balance between efficiency and accuracy, especially in improving the accuracy of low-accuracy simulation data. Therefore, there is an urgent need for a CPU micro-architecture design parameter exploration scheme that can integrate the advantages of low-accuracy and high-accuracy simulation tools and achieve a precise balance between efficiency and accuracy.

[0006] It should be noted that the background art is only used to introduce the relevant information of the present application, so as to facilitate the understanding of the technical solutions of the present application, but does not mean that the relevant information must be prior art. In the absence of evidence that the relevant information has been disclosed before the filing date of the present application, the relevant information should not be considered as prior art. SUMMARY

[0007] Therefore, the purpose of the present application is to overcome the defects of the prior art and provide a CPU micro-architecture parameter exploration scheme based on Bayesian optimization

[0008] The purpose of the present application is achieved by the following technical solutions:

[0009] According to a first aspect of the present application, a CPU micro-architecture parameter exploration method based on Bayesian optimization is provided for exploring a plurality of CPU design parameters meeting performance requirements from a preset CPU design parameter space, the method comprising multiple rounds of iterations, wherein each round of iteration comprises: step S1, selecting a CPU design parameter sample with an optimal performance index from the CPU design parameter space according to the performance indexes of all CPU design parameters in the CPU design space by using a pre-constructed Bayesian optimization device; step S2, simulating the CPU design parameter sample selected in step S1 by using a preset low-confidence simulation tool to obtain a low-confidence performance index and micro-architecture events of the CPU design parameter sample; step S3, predicting the simulation error of the CPU design parameter sample selected in step S1 by using a preset error prediction model and outputting the uncertainty of the predicted simulation error, wherein the simulation error is the difference between the performance indexes obtained by simulating the same CPU design parameter sample by using a preset high-confidence simulation tool and a preset low-confidence simulation tool; step S4, obtaining the final performance index of the CPU design parameter sample selected in step S1 and updating the Bayesian optimization device and the preset error prediction model according to the uncertainty of the simulation error obtained in step S3 in a preset manner, and retaining the design parameters in the CPU design parameter sample obtained in the current iteration when the final performance index meets the required performance requirements.

[0010] Preferably, the pre-constructed Bayesian optimization device comprises a surrogate model and a collection function, wherein the surrogate model is a random forest model constructed based on the prior distribution of the objective function and used to fit the posterior distribution of the objective function, wherein the surrogate model is updated based on the CPU design parameter sample and the final performance index of each round of iteration, and the objective function is a mapping of the CPU design parameter sample and the performance index constructed based on prior knowledge; the collection function selects a CPU design parameter sample with the optimal performance from the CPU design space based on the posterior distribution of the objective function fitted by the updated surrogate model in each round.

[0011] Preferably, the collection function is an expected Pareto hyper volume improvement function.

[0012] Preferably, the preset error prediction model is a prediction model constructed based on a random forest model or a Gaussian process probability model, which is configured to predict the simulation error of the CPU design parameter sample based on the CPU design parameter sample to be predicted, the micro-architecture events of the CPU design parameter sample, and the performance index derived features derived by using a preset method, and output the uncertainty of the predicted simulation error.

[0013] Preferably, the preset method comprises: step T1, selecting a plurality of CPU design parameter samples from a preset CPU design space in advance, and performing simulation on all selected CPU design parameter samples by using a preset low-confidence simulation tool to obtain a low-confidence performance index of each CPU design parameter sample; step T2, calculating the maximum value, the minimum value, and the average of all obtained low-confidence performance indexes; step T3, calculating the difference between the low-confidence performance index of the CPU design parameter sample to be predicted and the maximum value, the minimum value, and the average obtained in step T2, and taking the calculated difference as the performance index derived feature of the CPU design parameter sample.

[0014] Preferably, the preset manner is: when the uncertainty satisfies the constraint condition, correcting the low-confidence performance index obtained in step S2 based on the simulation error predicted in step S3, taking the corrected low-confidence performance index as the final performance index of the CPU design parameter sample selected in step S1, and updating the Bayesian optimization device based on the CPU design parameter sample and the final performance index thereof; when the uncertainty does not satisfy the constraint condition, performing simulation on the CPU design parameter sample selected in step S1 by using a preset high-confidence simulation tool to obtain a high-confidence performance index of the CPU design parameter sample, taking the high-confidence performance index as the final performance index of the CPU design parameter sample, updating the Bayesian optimization device based on the CPU design parameter sample and the final performance index thereof, and updating the error prediction model by taking the CPU design parameter sample as feature data, and taking the difference between the high-confidence performance index of the CPU design parameter sample and the low-confidence performance index obtained in step S2 as a label.

[0015] Preferably, the constraint condition is that the uncertainty output by the error prediction model in the current iteration round is less than the uncertainty threshold configured in the current iteration round.

[0016] Preferably, the uncertainty threshold of each iteration round is configured in any of the following manners: manner one, the uncertainty threshold in each iteration round is preset to a fixed value; manner two, the uncertainty threshold of each iteration round is configured in the following manner:

[0017] ,

[0018] wherein, denotes the uncertainty threshold of the i th iteration round, denotes an initial uncertainty threshold, denotes the uncertainty threshold of the i th iteration round, denotes an initial uncertainty threshold, a proportion parameter of each iteration, wherein, the initial uncertainty threshold is reduced by a first preset value after each time a preset number of loop iterations are executed, and the proportion parameter is increased by a second preset value if the uncertainty output by the error prediction model shows an upward trend in a continuous preset number of iteration rounds, or the proportion parameter is increased by the second preset value if the uncertainty output by the error prediction model shows a downward trend.

[0019] Preferably, the method comprises: randomly collecting a plurality of CPU design parameter samples from historical loop iterations as feature data and taking the difference between the final performance index of each collected CPU design parameter sample and the low-confidence performance index as the label of the CPU design parameter sample to train the preset error prediction model after each time a preset number of loop iterations are executed.

[0020] Preferably, the performance index comprises the power consumption and the number of instructions per clock cycle of the CPU.

[0021] Compared with the prior art, the present application has the following advantages:

[0022] The present application realizes low-cost and accurate calibration of low-confidence simulation by integrating the advantages of different confidence simulation tools, thereby providing more accurate feedback information for the multi-confidence Bayesian optimization device. In addition, the present application intelligently selects appropriate confidence simulation according to the real-time distribution characteristics of the data sample, thereby achieving an optimal balance between accuracy and efficiency in the optimization process. Overall, the present application effectively coordinates the contradiction between accuracy and time consumption of different confidence simulation tools, and significantly improves the exploration efficiency of CPU micro-architecture design parameters. BRIEF DESCRIPTION OF DRAWINGS

[0023] The embodiments of the present application will be further described below with reference to the accompanying drawings, in which:

[0024] Figure 1 A schematic diagram of a CPU micro-architecture parameter exploration method based on Bayesian optimization according to an embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application will be further described in detail below through specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0026] As mentioned in the background section, in summary, existing CPU design parameter exploration schemes mostly focus on the use and improvement of a single simulation tool, ignoring the potential of combining different confidence simulation tools. In addition, although some schemes attempt to integrate multiple simulation tools, they usually only use high-confidence simulation at the initial stage to collect data to train the model, and the subsequent optimization process still relies on the simulation results of low-confidence simulation tools, failing to fully exploit the synergistic advantages of both simulation tools. Existing CPU design parameter exploration schemes are difficult to achieve a balance between efficiency and accuracy, especially in improving the accuracy of low-confidence simulation data.

[0027] To solve the above problems, the present application proposes a CPU micro-architecture parameter exploration scheme based on Bayesian optimization, which is used to screen CPU design parameters that meet performance requirements from a pre-set CPU design space during the CPU design phase, to guide the design of CPU micro-architecture, and thus reduce the cost of CPU tape-out phase. Specifically, the scheme constructs a multi-confidence CPU micro-architecture parameter exploration device based on a Bayesian optimization device to realize end-to-end CPU design space exploration. The device combines the advantages of different confidence simulation tools, realizes low-cost and accurate calibration of low-confidence simulation, and thus provides more accurate feedback information for the multi-confidence Bayesian optimization device. In addition, the present scheme intelligently selects appropriate confidence simulation according to the real-time distribution characteristics of data samples, thus achieving the best balance between accuracy and efficiency in the optimization process. In general, the present scheme can effectively balance the contradiction between the accuracy and time-consuming of different confidence simulation tools, and efficiently explore CPU design parameters.

[0028] In order to better understand the present application, the present application will be described in detail below in conjunction with specific embodiments.

[0029] According to an embodiment of the present application, the present application proposes a CPU micro-architecture parameter exploration method based on Bayesian optimization, which explores CPU design parameters that meet performance requirements from a pre-set CPU design parameter space in a multi-round iteration manner, wherein the steps of each round of iteration are as follows Figure 1As shown, the steps shown in the figure include: step S1, using a pre-constructed Bayesian optimization device, selecting a CPU design parameter sample with the optimal performance index from the CPU design space according to the performance index of all CPU design parameters in the CPU design space; step S2, using a preset low-confidence simulation tool to simulate the CPU design parameter sample selected in step S1 to obtain the low-confidence performance index and micro-architecture events of the CPU design parameter sample; step S3, using a preset error prediction model to predict the simulation error of the CPU design parameter sample selected in step S1 and output the uncertainty of the predicted simulation error, wherein the simulation error is the difference between the performance indexes obtained by using the preset high-confidence simulation tool and the preset low-confidence simulation tool when simulating the same CPU design parameter sample; step S4, based on the uncertainty of the simulation error obtained in step S3, obtaining the final performance index of the CPU design parameter sample selected in step S1 in a preset manner, updating the Bayesian optimization device and the preset error prediction model, and retaining the design parameters in the CPU design parameter sample obtained in the current iteration when the final performance index meets the required performance requirement. It should be noted that the performance index in the present application includes the power consumption and the number of instructions per clock cycle of the CPU. When the uncertainty satisfies the constraint condition, the low-confidence performance index obtained in step S2 is corrected based on the predicted simulation error in step S3 to obtain the final performance index of the CPU design parameter sample selected in step S1. Otherwise, when the uncertainty does not satisfy the constraint condition, the preset high-confidence simulation tool is used to simulate the CPU design parameter sample selected in step S1 to obtain the high-confidence performance index of the CPU design parameter sample.

[0030] According to one embodiment of the application, in the present application, the preset CPU design parameter space is pre-configured by the user according to the requirements, which includes a plurality of CPU micro-architecture design parameters and a plurality of optional values of each CPU micro-architecture design parameter, wherein the types of CPU micro-architecture design parameters include but are not limited to the number of registers of the register file, the size of the cache, and the configuration number of the operation unit. In step S1 of the present application, the Bayesian optimization device collects one optional value of each CPU micro-architecture design parameter in the preset CPU design parameter space to construct a CPU design parameter sample. It should be understood that the CPU micro-architecture design parameters in the preset CPU design parameter space are not limited to the three types listed above, and other micro-architecture parameters of CPU design can also be configured in the preset CPU design parameter space.

[0031] It should be understood that the Bayesian optimization apparatus is an apparatus for optimizing a target function with long evaluation time, which comprises a surrogate model and an acquisition function. For complex problems, the required analysis target function is usually unknown, and Bayesian optimization regards it as a black box function, i.e., a surrogate model, and gives it a prior distribution. After the target function is evaluated, new data is used to form the posterior distribution of the target function, and the posterior distribution is used to build an acquisition function, which determines the next point to be evaluated.

[0032] According to an embodiment of the present application, in the present application, the surrogate model in the preset Bayesian optimization apparatus is a random forest model for fitting the posterior distribution of the target function, which is constructed based on the prior distribution of the target function, the surrogate model is updated based on the CPU design parameter sample and its final performance index of each round of iteration, and the target function is a mapping function of the CPU design parameter sample and its performance index, which is constructed based on prior knowledge, wherein the prior knowledge is simulation results obtained by pre-simulation using a preset low-confidence simulation tool or a preset high-confidence simulation tool, or simulation results obtained from other existing data sets; the acquisition function selects a CPU design parameter sample with the best performance from the preset CPU design space based on the posterior distribution of the target function fitted by the updated surrogate model of each round, and the present application uses the expected improvement in Pareto hypervolume (EIPV) as the acquisition function in the Bayesian optimization apparatus. It should be noted that the expected improvement in Pareto hypervolume is a known technology to those skilled in the art, and will not be described in detail here.

[0033] It should be understood that in the Bayesian optimization apparatus, the acquisition function uses the output of the surrogate model to calculate the score of each candidate point and selects a candidate point with the highest score as a data sample for the next round of iteration. According to an embodiment of the present application, in step S1 of the present application, the acquisition function selects a CPU design parameter sample with the best performance index from the preset CPU design space based on the posterior distribution of the target function fitted by the updated surrogate model of each round, i.e., the performance index corresponding to each parameter sample.

[0034] According to one embodiment of the present application, in step S2 of the present application, the CPU design parameter sample selected in step S1 is simulated by using a low-confidence simulation tool to obtain a low-confidence performance index of the CPU design parameter sample, and the low-confidence performance index is taken as a reference. It should be understood that, since the low-confidence simulation tool focuses on simulating the behavior of components of the CPU without being accurate to the register transfer level, the low-confidence simulation tool is used to quickly obtain the low-confidence performance index of the CPU design parameter sample by taking advantage of the high simulation efficiency of the low-confidence simulation tool. However, since the low-confidence simulation tool cannot ensure the fidelity of the simulation result, the obtained low-confidence performance index can only be taken as a reference of the performance index of the CPU design parameter sample and cannot be taken as the final performance index of the CPU design parameter sample.

[0035] According to one embodiment of the present application, in step S4 of the present application, whether the uncertainty of the simulation error predicted according to the preset error model satisfies a constraint condition is used to select a way to obtain the final performance parameter of the CPU design parameter sample. Specifically, when the uncertainty satisfies the constraint condition, it indicates that the predicted simulation error has high reliability, and the predicted simulation error can be used to correct the low-confidence performance parameter. Therefore, the low-confidence performance index obtained in step S2 is corrected based on the predicted simulation error in step S3, and the corrected low-confidence performance index is taken as the final performance index of the CPU design parameter sample selected in step S1. The Bayesian optimization device is updated based on the CPU design parameter sample and the final performance index thereof. When the uncertainty does not satisfy the constraint condition, it indicates that the predicted simulation error has low reliability, and the predicted error cannot be used to correct the low-confidence performance parameter. Therefore, a preset high-confidence simulation tool is used to simulate the CPU design parameter sample selected in step S1 to obtain a high-confidence performance index of the CPU design parameter sample, and the high-confidence performance index is taken as the final performance index of the CPU design parameter sample. The Bayesian optimization device is updated based on the CPU design parameter sample and the final performance index thereof. The error prediction model is updated by taking the CPU design parameter sample as feature data and taking the difference between the high-confidence performance index of the CPU design parameter sample and the low-confidence performance index obtained in step S2 as a label. According to the uncertainty of the simulation error, the error correction method is flexibly selected or the high-confidence simulation is called to accurately obtain the final performance index of the CPU design parameter, so that the accuracy of the simulation result is significantly improved on the premise of ensuring the simulation efficiency.

[0036] According to one embodiment of the present application, in the present application, the preset error prediction model is constructed based on a random forest, a Gaussian process or other probability models, therefore, the preset error prediction model not only predicts the simulation error, but also outputs the uncertainty of the predicted simulation error, wherein the predicted simulation error can be the difference between the high-confidence simulation and the low-confidence simulation, or the numerical ratio of the high-confidence simulation and the low-confidence simulation, it should be understood that the uncertainty output by the error prediction model represents the fidelity of the predicted simulation error, according to which the reliability of the predicted simulation error can be judged, and then it can be judged whether the simulation error can be used to calibrate the low-confidence performance index.

[0037] According to one embodiment of the present application, in the present application, the input features of the error prediction model include: (1) CPU design parameter samples, i.e. CPU design parameter samples selected by the collection function; (2) microarchitectural events generated during low-confidence simulation, microarchitectural events refer to various operations and state changes at the processor microarchitecture level, these events are usually closely related to the internal components and operations of the processor, and are key factors for evaluating and optimizing the performance of the processor. For example, the CPU calls a floating-point multiplication operation unit once when executing an instruction, which is a microarchitectural event; when a certain instruction is fetched, the I Cache is not hit (the instruction is not cached in the I Cache, and needs to be found in the next level of storage), which is also a microarchitectural event. According to the experience of designers, selecting representative microarchitectural events as features reflects the dynamic behavior of the CPU, which is closely related to performance and power. (3) a set of derived features are derived based on global statistical information of performance and power, specifically, the derived features are derived by the following method: step T1, a plurality of CPU design parameter samples are selected in advance from the preset CPU design space, and a preset low-confidence simulation tool is used to simulate all collected CPU design parameter samples to obtain the low-confidence performance index of each CPU design parameter sample; step T2, the maximum value, the minimum value and the average of all obtained low-confidence performance indexes are calculated; step T3, the difference between the performance index of the CPU design parameter sample to be predicted and the maximum value, the minimum value and the average obtained in step T2 is calculated, and the calculated difference is taken as the performance index derived feature of the CPU design parameter sample. It should be understood that the derived features aim to establish the numerical relationship between the performance index of the current CPU design parameter sample and the performance indexes of other CPU parameter design samples, so as to provide a global perspective for the error prediction model, therefore, when deriving the derived features, other numerical operation methods can also be used to construct the numerical relationship between the performance index of the CPU design parameter sample and the performance indexes of other CPU parameter design samples.

[0038] According to one embodiment of the present invention, the constraint condition is that the uncertainty is less than the uncertainty threshold configured in the current iteration. There are two ways to configure the uncertainty threshold, including: (1) configuring the threshold to be the same in each iteration and fixed during the iteration; (2) configuring the uncertainty threshold in each iteration in the following manner: ,in, Indicates the The uncertainty threshold of the round iteration, Represents the initial uncertainty threshold, and each time a preset number of loop iterations is executed, preferably, the preset number is 200. It should be understood that the preset number can be configured by the user according to needs, and the initial uncertainty threshold is reduced by a first preset value to reduce the number of calls of high-confidence simulation. Preferably, the first preset value is configured as 10% by default. It should be understood that the first preset value can also be customized by the user according to needs. Indicates the The proportional parameter of the round iteration is adjusted based on the changing trend of the uncertainty. Specifically, in consecutive preset iteration rounds, if the uncertainty is on an upward trend, the proportional parameter is increased by a second preset value; if the uncertainty is on a downward trend, the proportional parameter is increased by the second preset value. Preferably, assuming that the simulation error is Gaussian distributed, the desired running frequency is obtained based on the running time, number of rounds and expected total time of a single high-confidence simulation tool, and the second preset value is configured according to the percentile of the Gaussian distribution. For example, assuming that 5-10 high-confidence simulations are desired to be run in 200 iterations, 2 standard deviations of the Gaussian distribution, i.e., the 95% percentile, are selected as the second preset value. It should be understood that the second preset value is more of an empirical choice, and the user can configure it according to needs. In the present invention, based on the uncertainty output by the error prediction model and the number of iterations, the uncertainty threshold is adjusted in real time to adjust the high-confidence simulation frequency, thereby achieving the best balance between accuracy and efficiency in the CPU design parameter exploration process.

[0039] According to one embodiment of the present application, if the uncertainty of the simulation error output by the error prediction model in the current iteration meets the constraint condition, i.e., the uncertainty is less than the uncertainty threshold of the current iteration, the low-confidence performance index obtained in step S2 is corrected based on the predicted simulation error in step S3. Specifically, when the predicted simulation error is the difference between the high-confidence simulation and the low-confidence simulation, the result of adding the difference to the low-confidence performance index is taken as the final performance index of the CPU design parameter sample to complete the correction of the low-confidence performance index. When the predicted simulation error is the ratio of the difference between the high-confidence simulation and the low-confidence simulation, the product of the low-confidence performance index and the ratio is taken as the final performance index of the CPU design parameter sample to complete the correction of the low-confidence performance index. In order to update the parameters of the surrogate model in the Bayesian optimization device so that the surrogate model is closer to the target function, the present application takes the CPU design parameter sample as the feature data and takes the final performance parameter of the CPU design parameter sample as the label to update the surrogate model in the Bayesian optimization device.

[0040] According to one embodiment of the present application, if the uncertainty of the simulation error output by the error prediction model in the current iteration does not meet the constraint condition, i.e., the uncertainty is greater than the uncertainty threshold of the current iteration, the CPU design parameter sample is simulated by using the simulation tool with high confidence to obtain the final performance index of the CPU design parameter sample, and then the Bayesian optimization device and the error prediction model are updated based on the obtained final performance index. Specifically, the CPU design parameter sample is taken as the feature data and the final performance parameter of the CPU design parameter sample is taken as the label to update the surrogate model in the Bayesian optimization device, and the CPU design parameter sample is taken as the feature data and the difference between the final performance parameter of the CPU design parameter sample and the low-confidence performance index of the CPU design parameter sample is taken as the label to update the error prediction model.

[0041] In the multi-confidence Bayesian optimization adopted in the present application, the accuracy of calibration of the optimal CPU design parameter sample selected by each round of the acquisition function is higher, while the calibration of other less optimal CPU design parameter samples is less important, which means that only the calibration accuracy of the CPU design parameter sample in the historical iteration round is concerned in the iteration process. According to an embodiment of the present application, in the present application, every time a preset number of iterations is performed, preferably, the preset number is 200, it should be understood that the preset number can be configured by the user according to the demand, a plurality of CPU design parameter samples are randomly sampled from the historical cyclic iteration as feature input, and the difference between the final performance index of each sampled CPU design parameter sample and the low-confidence performance index is taken as a label for training the preset error prediction model. Compared with the existing main consideration of the diversity and representativeness of the samples in the global space and the exploration of the CPU design parameters, the simulation frequency of the CPU design parameters is reduced, thereby significantly saving the simulation cost of the exploration of the CPU design parameters.

[0042] According to an embodiment of the present application, in the present application, the preset low-confidence simulation tool is any one of Gem5, ZSim, GPGPU-SIM, SESC, RTSim and Simics, and the preset high-confidence simulation tool is an EDA simulation tool. It should be understood that the above-mentioned low-confidence simulation tools and high-confidence simulation tools are well-known technologies to those skilled in the art, and will not be described here. In addition, the present application aims to combine the efficient characteristics of the low-confidence simulation tool and the high accuracy characteristics of the high-confidence simulation tool to provide a method for effectively solving the contradiction between the accuracy and time consumption of different confidence simulation tools and efficiently exploring the CPU design parameters. The high-confidence simulation tool and the low-confidence simulation tool adopted are not limited, and other CPU simulation tools that can realize low-confidence simulation and high-confidence simulation can also be used.

[0043] For the long-standing efficiency and accuracy trade-off problem in the micro-architecture design space exploration process, the present application proposes a multi-confidence Bayesian optimization device based on iterative path sampling calibration. The device focuses on improving the calibration accuracy of the sample points on the search path. The iterative path sampling method effectively reduces the complexity of the problem, realizes low-cost and high-precision calibration of low-confidence simulation, and at the same time, adopts an accurate threshold calibration mechanism to dynamically adjust the threshold value of calling high-confidence simulation. In addition, the present application combines the advantages of different confidence simulation tools to realize efficient multi-confidence Bayesian optimization, which significantly improves the efficiency and accuracy of micro-architecture design space exploration.

[0044] It should be noted that although the above describes the various steps in a specific order, it does not mean that the steps must be performed in the above specific order. In fact, some of these steps can be executed concurrently or even in a different order as long as the required functions can be achieved.

[0045] The present invention may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present invention.

[0046] A computer-readable storage medium may be a tangible device that holds and stores instructions used by an instruction execution device. Computer-readable storage media may include, for example, but is not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove having instructions stored thereon, and any suitable combination thereof.

[0047] While various embodiments of the present invention have been described above, the above descriptions are intended to be illustrative, non-exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or technological improvements in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A CPU microarchitecture parameter exploration method based on Bayesian optimization, used to explore multiple CPU design parameters that meet performance requirements from a preset CPU design parameter space, characterized in that: The method comprises multiple rounds of iterations, wherein each round of iteration comprises: Step S1, using a pre-built Bayesian optimization device, selecting a CPU design parameter sample with an optimal performance index from the CPU design space according to the performance indexes of all CPU design parameters in the CPU design space; Step S2, using a preset low-confidence simulation tool to simulate the CPU design parameter sample selected in step S1 to obtain a low-confidence performance index and microarchitecture event of the CPU design parameter sample; Step S3, using a preset error prediction model to predict the simulation error of the CPU design parameter sample selected in step S1 and outputting the uncertainty of the predicted simulation error, wherein the simulation error is the difference between the performance index obtained when simulating the same CPU design parameter sample using a preset high-confidence simulation tool and a preset low-confidence simulation tool; Step S4, based on the uncertainty of the simulation error obtained in step S3, obtain the final performance index of the CPU design parameter sample selected in step S1 in a preset manner, and update the Bayesian optimization device and the preset error prediction model, and retain the design parameters in the CPU design parameter sample obtained in the current iteration when the final performance index meets the required performance requirements.

2. The method according to claim 1, characterized in that The pre-built Bayesian optimization device includes a proxy model and an acquisition function, wherein: The surrogate model is a random forest model constructed based on a prior distribution of the objective function and used to fit the posterior distribution of the objective function, wherein the surrogate model is updated based on the CPU design parameter samples and their final performance index in each iteration, and the objective function is a mapping between the CPU design parameter samples and the performance index constructed based on prior knowledge; The acquisition function selects a CPU design parameter sample with optimal performance from the CPU design space based on the posterior distribution of the objective function fitted by the proxy model after each round of update.

3. The method according to claim 2, characterized in that The acquisition function is an expected Pareto hypervolume improvement function.

4. The method according to claim 1, wherein The preset error prediction model is a prediction model constructed based on a random forest model or a Gaussian process probability model, which is configured to: predict the simulation error of the CPU design parameter sample based on the CPU design parameter sample to be predicted, the microarchitecture event of the CPU design parameter sample, and the performance index derived characteristics derived using a preset method, and output the uncertainty of the predicted simulation error.

5. The method according to claim 4, characterized in that The preset method includes: Step T1: Pre-select multiple CPU design parameter samples from a preset CPU design space, and simulate all the selected CPU design parameter samples using a preset low-confidence simulation tool to obtain a low-confidence performance index for each CPU design parameter sample; Step T2, calculating the maximum value, minimum value, and average value of all low confidence performance indices obtained; Step T3, calculate the difference between the low confidence performance index of the CPU design parameter sample to be predicted and the maximum value, minimum value, and average value obtained in step T2, and use the calculated difference as the performance index derived feature of the CPU design parameter sample.

6. The method according to claim 1, characterized in that The preset method is: When the uncertainty satisfies the constraint condition, the low-confidence performance index obtained in step S2 is corrected based on the simulation error predicted in step S3, and the corrected low-confidence performance index is used as the final performance index of the CPU design parameter sample selected in step S1, and the Bayesian optimization device is updated based on the CPU design parameter sample and its final performance index; When the uncertainty does not meet the constraint conditions, the CPU design parameter sample selected in step S1 is simulated using a preset high-confidence simulation tool to obtain a high-confidence performance index of the CPU design parameter sample, and this is used as the final performance index of the CPU design parameter sample. The Bayesian optimization device is updated based on the CPU design parameter sample and its final performance index, and the error prediction model is updated using the CPU design parameter sample as feature data and the difference between the high-confidence performance index of the CPU design parameter sample and the low-confidence performance index obtained in step S2 as a label.

7. The method according to claim 6, characterized in that The constraint condition is that the uncertainty of the error prediction model output in the current iteration round is less than the uncertainty threshold configured for the current iteration round.

8. The method according to claim 7, characterized in that The uncertainty threshold for each iteration is configured in one of the following ways: Method 1: Pre-configure the uncertainty threshold in each iteration to a fixed value; Method 2: The uncertainty threshold for each iteration is configured as follows: ， in, Indicates the The uncertainty threshold of the round iteration, represents the initial uncertainty threshold, Indicates the A proportional parameter for each round of iteration, wherein each time a preset number of loop iterations is performed, the initial uncertainty threshold is reduced by a first preset value, and in consecutive preset rounds of iterations, if the uncertainty output by the error prediction model shows an upward trend, the proportional parameter is increased by a second preset value, and if the uncertainty output by the error prediction model shows a downward trend, the proportional parameter is increased by the second preset value.

9. The method according to claim 1, characterized in that The method comprises: Each time a preset number of loop iterations are executed, multiple CPU design parameter samples are randomly collected from historical loop iterations as feature data, and the difference between the final performance index and the low-confidence performance index of each collected CPU design parameter sample is used as the label of the CPU design parameter sample to train the preset error prediction model.

10. The method according to any one of claims 1, 2, 4, 5, 6, and 9, characterized in that: The performance index includes the power consumption and the number of instructions per clock cycle of the CPU.

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