Semiconductor laser chip with current modulation and method of manufacture

Abstract

The application provides a semiconductor laser chip with current modulation and a preparation method, and relates to the field of semiconductor laser chips.The semiconductor laser chip comprises, from bottom to top, a substrate layer, an n-type confinement layer, an n-type waveguide layer, a quantum well active region, a p-type waveguide layer, a first p-type confinement layer, a second p-type confinement layer and a contact layer.The anti-reflection cavity surface and the high-reflection cavity surface are arranged on the opposite sides of the second p-type confinement layer.The functional area is arranged between the anti-reflection cavity surface and the high-reflection cavity surface.The functional area comprises a current injection sub-area and a current blocking sub-area.The current injection sub-area has a plurality of injection tips.The current blocking sub-area has a plurality of blocking tips.The injection tips are arranged between any two adjacent blocking tips.Two grooves are formed in the first p-type confinement layer and penetrate the second p-type confinement layer and the contact layer.The two grooves are located on the opposite sides of the current injection sub-area and the current blocking sub-area.The application helps to improve the light output power and the beam quality of the semiconductor laser chip.

Description

Technical Field

[0001] This invention relates to the field of semiconductor laser chips, and more particularly to a semiconductor laser chip with current modulation and its fabrication method. Background Technology

[0002] High-power semiconductor laser chips are key components in modern laser technology, serving as pump sources for both solid-state and fiber laser chips. They are primarily used in industrial processing and advanced manufacturing, such as laser cutting, laser welding, laser drilling, laser cladding, and 3D printing. They can also be used as direct semiconductors in high-power processing systems. Continuously increasing output power and brightness are crucial for improving laser system performance and enabling new applications. Commercially available high-power semiconductor laser chips typically employ a wide stripe structure. Due to thermal lensing effects and factors such as longitudinal spatial temperature and current non-uniformity, the power of the semiconductor laser chip will reach saturation, while the product of transverse optical parameters increases rapidly with increasing current.

[0003] Chinese patent application CN116316054B discloses a laser chip with a current-non-injection layer and its fabrication method. The laser chip has a recessed step formed at the contact point between the ridge waveguide layer and the front end face, with a current-non-injection layer on the step, and a third electrode grown above the current-non-injection layer. This invention utilizes current-non-injection layer technology to fabricate a current-non-injection layer on the emitter cavity surface of the laser chip and grow a third electrode above it. However, the above approach struggles to fully control the displacement of charge carriers from the p-type semiconductor depletion layer towards the active region. High carrier diffusion and aggregation still exist locally at the cavity surface, resulting in thermal lensing distortion and the emergence of higher-order modes. This fails to effectively suppress light absorption at the cavity surface, leading to a reduction in the output power of the semiconductor laser chip. Therefore, it is essential to provide a semiconductor laser chip with a small horizontal divergence angle and its fabrication method to improve the output power and beam quality of the semiconductor laser chip. Summary of the Invention

[0004] In view of this, the present invention proposes a semiconductor laser chip with current modulation and its fabrication method. By creating two trenches in the first p-type confinement layer that penetrate the second p-type confinement layer and the contact layer, the modulated current is injected gradually from the high-reflectivity cavity surface to the anti-reflectivity cavity surface along the cavity length direction, reducing the carrier density and spread amplitude at the edge of the front cavity surface, thereby correspondingly reducing the gain of higher-order side modes and improving the output power and beam quality.

[0005] This invention provides a semiconductor laser chip with current modulation, comprising, from bottom to top, a substrate layer, an n-type confinement layer, an n-type waveguide layer, a quantum well active region, a p-type waveguide layer, a first p-type confinement layer, a second p-type confinement layer, and a contact layer, wherein,

[0006] The contact layer includes an anti-reflective cavity surface, a functional region, and a high-reflective cavity surface. The anti-reflective cavity surface and the high-reflective cavity surface are disposed on opposite sides of the second p-type confinement layer. The functional region is disposed between the anti-reflective cavity surface and the high-reflective cavity surface. The functional region includes a current injection sub-region and a current blocking sub-region. The current injection sub-region has multiple injection tips, and the current blocking sub-region has multiple blocking tips. The injection tips are disposed between any two adjacent blocking tips, and the injection tips and blocking tips are arranged alternately. The projections of the current blocking sub-region and the current injection sub-region are located on the same horizontal plane, and the current blocking sub-region is higher than the current injection sub-region.

[0007] The first p-type limiting layer has two trenches that penetrate the second p-type limiting layer and the contact layer, and the two trenches are located on opposite sides of the current injection sub-region and the current blocking sub-region, and the trenches are filled with an insulating medium.

[0008] Based on the above technical solutions, preferably, a first blocking groove along the width direction of the semiconductor laser chip is formed between the anti-reflection cavity surface and the functional area, and a second blocking groove along the width direction of the semiconductor laser chip is formed between the high-reflection cavity surface and the functional area.

[0009] Based on the above technical solutions, preferably, the trench penetrates the first p-type confinement layer, the second p-type confinement layer, and the contact layer, and the trench extends along the length direction of the semiconductor laser chip to the anti-reflection cavity surface and the high-reflection cavity surface, respectively.

[0010] More preferably, both the injection tip and the blocking tip are isosceles triangles, and the apex angles of the injection tip and the blocking tip satisfy the following:

[0011] 0.1 ≤ tan(θ / 2) ≤ 0.2

[0012] Wherein, θ represents the apex angle of the injection tip or the blocking tip.

[0013] More preferably, the second p-type confinement layer and the contact layer stacked in sequence form a ridge waveguide structure, which is used to regulate the current injection from the high-reflectivity cavity surface to the anti-reflectivity cavity surface in the cavity length direction, thereby suppressing the thermal lensing effect.

[0014] More preferably, the ratio of the ridge width of the ridge waveguide structure to the number of injection tips in the current injection sub-region satisfies:

[0015] 8≤L / n≤12

[0016] Where L represents the ridge width of the ridge waveguide structure, and n represents the number of injection tips in the current injection sub-region.

[0017] More preferably, the height of the ridge waveguide structure is 500–800 nm.

[0018] More preferably, the width of the trench is 0.5μm to 1μm, and the distance between the trench and the edge of the ridge waveguide structure is at least 5μm.

[0019] More preferably, the substrate layer includes an n-type substrate and an n-type buffer layer, wherein the n-type substrate and the n-type buffer layer both include any one of GaAs, InP, GaSb and GaN.

[0020] A second aspect of this application provides a method for fabricating a semiconductor laser chip with current modulation, comprising:

[0021] An epitaxial wafer is fabricated, the epitaxial wafer comprising sequentially epitaxially growing an n-type confinement layer, an n-type waveguide layer, a quantum well active region, a p-type waveguide layer, a first p-type confinement layer, a second p-type confinement layer, and a contact layer on a substrate layer;

[0022] The epitaxial wafer is removed from the MOCVD reaction chamber, and the contact layer located on the topmost layer of the epitaxial wafer is etched to remove the second p-type confinement layer and part of the conductive medium in the contact layer, so as to expose the ridge waveguide structure formed by the second p-type confinement layer and the contact layer.

[0023] The ridge waveguide structure is etched with a double-striped pattern to form trenches penetrating the first p-type confinement layer, the second p-type confinement layer, and the contact layer, and the trenches are filled with SiO2 or SiN dielectric.

[0024] A current injection region is etched in the contact layer, and P-side electrodes and N-side electrodes are sequentially fabricated on opposite sides of the epitaxial wafer to complete the fabrication of the semiconductor laser.

[0025] The semiconductor laser chip with current modulation and its fabrication method provided by this invention have the following advantages over the prior art:

[0026] (1) By setting alternating injection tips and blocking tips in the contact layer, the injection position and distribution of current can be effectively controlled, reducing local current density or leakage problems, thereby reducing the risk of local overheating and laser threshold. Furthermore, the design of anti-reflection cavity surface, functional area and high reflection cavity surface in the contact layer provides clear optical partitioning for the entire cavity. The reasonable configuration of current injection and blocking functional area makes the coupling between injected carriers and optical field more matched, which is conducive to suppressing the lasing of non-target optical modes and improving the beam quality and spectral purity of laser output. The two grooves opened in the first p-type confinement layer that penetrate the second p-type confinement layer and the contact layer realize the gradual injection of the current from the high reflection cavity surface to the anti-reflection cavity surface in the cavity length direction, reducing the carrier density at the edge of the front cavity surface and reducing the temperature gradient in the cavity length direction, thereby suppressing the thermal lensing effect, which reduces the gain of higher-order side modes accordingly and increases the output power. At the same time, by introducing a double stripe structure in the side, higher-order modes can be effectively suppressed, thereby effectively suppressing the broadening of the lateral divergence angle and improving the beam quality.

[0027] (2) The trenches clearly isolate the preset current injection sub-region and current blocking sub-region in the first p-type confinement layer, which helps to confine the charge carriers to the predetermined area. By extending along the chip length to the anti-reflection and high-reflection cavity surface, a precise current path across multiple layers is realized, so that the injected current can be concentrated in the optimized lasing region, avoiding edge diffusion, thereby reducing local overheating and threshold current. At the same time, the trenches not only penetrate the first and second p-type confinement layers and contact layers, but also directly act on the interface with the cavity surface. The filling insulating medium plays an effective electric field shielding role. This multi-layer insulation design effectively prevents leakage and short circuits from other areas, and improves the overall device's anti-interference capability under high-frequency or pulsed operating conditions. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 A schematic diagram of the cavity surface of the semiconductor laser chip provided by the present invention;

[0030] Figure 2 A schematic diagram of the ridge waveguide cross-section of the semiconductor laser chip provided by the present invention.

[0031] Explanation of reference numerals in the attached figures: 1. Substrate layer; 2. n-type confinement layer; 3. n-type waveguide layer; 4. Quantum well active region; 5. p-type waveguide layer; 6. First p-type confinement layer; 7. Second p-type confinement layer; 8. Contact layer; 81. Anti-reflection cavity surface; 82. Functional region; 821. Current injection sub-region; 822. Current blocking sub-region; 823. Trench; 83. High-reflection cavity surface. Detailed Implementation

[0032] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0033] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms "an" or "a" and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms "connected" or "linked" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up," "down," "left," "right," etc., are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship also changes accordingly.

[0034] refer to Figure 1 This invention provides a semiconductor laser chip with current modulation, characterized in that it comprises, from bottom to top, a substrate layer 1, an n-type confinement layer 2, an n-type waveguide layer 3, a quantum well active region 4, a p-type waveguide layer 5, a first p-type confinement layer 6, a second p-type confinement layer 7, and a contact layer 8, stacked sequentially.

[0035] Substrate layer 1 includes an n-type substrate and an n-type buffer layer, both of which include any one of GaAs, InP, GaSb, and GaN.

[0036] n-type semiconductor materials are prepared by adding appropriate impurities (such as silicon, antimony, germanium, etc.) to make their main charge carriers free electrons. These materials have the characteristics of high electron concentration and high electron mobility, and are widely used in electronic and optoelectronic devices. GaAs, InP, GaSb, and GaN are all important III-V compound semiconductor materials that can be doped into n-type structures and used as substrate materials in various heterostructure devices. In the fabrication of heterostructure devices, an n-type buffer layer is usually located between the substrate and the device layer structure. It plays a role in alleviating lattice mismatch between the substrate and the epitaxial layer, reducing dislocation density, providing good crystal quality for the subsequent growth of device layers, providing conductive channels, and reducing the parasitic resistance of the device.

[0037] like Figure 2 As shown, the contact layer 8 includes an anti-reflective cavity surface 81, a functional region 82, and a high-reflective cavity surface 83. The anti-reflective cavity surface 81 and the high-reflective cavity surface 83 are disposed on opposite sides of the second p-type confinement layer 7. The functional region 82 is disposed between the anti-reflective cavity surface 81 and the high-reflective cavity surface 83. The functional region 82 includes a current injection sub-region 821 and a current blocking sub-region 822. The current injection sub-region 821 has multiple injection tips, and the current blocking sub-region 822 has multiple blocking tips. The injection tips are disposed between any two adjacent blocking tips, and the injection tips and blocking tips are arranged alternately. The projections of the current blocking sub-region 822 and the current injection sub-region 821 are located on the same horizontal plane, and the current blocking sub-region 822 is higher than the current injection sub-region 821.

[0038] In this embodiment, the injection sub-region and the blocking sub-region are arranged alternately, and the injection tips are uniformly distributed among the blocking tips. The anti-reflection cavity surface 81 and the high-reflection cavity surface 83 are positioned on opposite sides of the second p-type confinement layer 7, forming an effective cavity feedback structure that suppresses unnecessary lasing while ensuring stable output of favorable modes, further improving the beam quality and efficiency of the device. The design of the functional region 82 integrates current injection and current blocking functions in the same area. By precisely controlling the geometry of the current-carrying region and the current-blocking region, the current flow direction within the device can be better controlled, achieving precise control of the current distribution.

[0039] Both the injection tip and the blocking tip are isosceles triangles, and the vertex angles of the injection tip and the blocking tip satisfy the following:

[0040] 0.1 ≤ tan(θ / 2) ≤ 0.2

[0041] Where θ represents the apex angle of the injection tip or the blocking tip.

[0042] A first blocking groove along the width direction of the semiconductor laser chip is formed between the anti-reflection cavity surface 81 and the functional area 82, and a second blocking groove along the width direction of the semiconductor laser chip is formed between the high-reflection cavity surface 83 and the functional area 82.

[0043] In this embodiment, the blocking groove effectively isolates current transmission between different regions, preventing current from spreading to unwanted areas, thereby achieving more precise current injection and blocking, and improving the device's operational stability. The blocking groove helps define the transmission path of optical modes, avoiding unnecessary mode coupling and light scattering, and improving the quality and stability of the intracavity optical field. Effective isolation of current and optical fields helps reduce interference and coupling between adjacent regions, thereby reducing energy loss within the device and improving overall efficiency.

[0044] Two trenches 823 formed in the first p-type confinement layer 6 penetrate the second p-type confinement layer 7 and the contact layer 8, and the two trenches 823 are located on opposite sides of the current injection sub-region 821 and the current blocking sub-region 822. The trenches 823 are filled with an insulating medium. The trenches 823 penetrate the first p-type confinement layer 6, the second p-type confinement layer 7, and the contact layer 8, and extend along the length of the semiconductor laser chip to the anti-reflection cavity surface 81 and the high-reflection cavity surface 83, respectively. The width of the trenches 823 is 0.5 μm to 1 μm, and the distance between the trenches 823 and the edge of the ridge waveguide structure is at least 5 μm.

[0045] In this embodiment, the trench 823 clearly isolates the preset current injection sub-region 821 and current blocking sub-region 822 in the first p-type confinement layer 6, which helps to confine the charge carriers to a predetermined area. For example, by extending along the chip length direction to the anti-reflection and high-reflection cavity surface 83, a precise current path across multiple layers is achieved, allowing the injected current to be concentrated in the optimized lasing region, avoiding diffusion and accumulation towards the cavity surface, thereby reducing local overheating and threshold current. The trench 823 not only penetrates the first and second p-type confinement layers 7 and the contact layer 8, but also directly acts on the interface with the cavity surface, and the filling insulating medium plays an effective role in electric field shielding. This multi-layered insulation design effectively prevents leakage and short circuits from other areas, improving the overall device's anti-interference capability under high-frequency or pulsed operating conditions.

[0046] Furthermore, the trench 823 design extends along the chip length to the anti-reflection and high-reflection cavity surface 83, ensuring that the current is strictly limited within a preset area while also influencing the optical field distribution inside the cavity to a certain extent. By matching the current with the optical field distribution, the stability and output efficiency of the laser oscillation mode can be improved, while reducing the possibility of lasing in non-target modes. The width of the trench 823 is strictly controlled within the range of 0.5μm to 1μm, maintaining a distance of at least 5μm from the edge of the ridge waveguide structure. This size and spacing design not only meets the precision requirements of current semiconductor micro / nano fabrication but also provides sufficient process margin, reducing the negative impact of processing errors on device performance and ensuring consistency and reliability during mass production.

[0047] The second p-type confinement layer 7 and the contact layer 8, stacked sequentially, form a ridge waveguide structure. The ridge waveguide structure is used to control the gradual injection of current from the high-reflectivity cavity surface 83 to the anti-reflectivity cavity surface 81 along the cavity length, thereby suppressing the thermal lensing effect. The height of the ridge waveguide structure is 500–800 nm.

[0048] In this embodiment, a ridge waveguide structure is formed by stacking the second p-type confinement layer 7 and the contact layer 8. This allows for the gradual injection of current along the cavity length from the high-reflectivity cavity surface 83 to the anti-reflectivity cavity surface 81, effectively avoiding current concentration or uneven transition and ensuring uniform carrier distribution within the laser. The gradual current injection results in a more uniform local heat distribution, thereby reducing the temperature gradient and significantly suppressing the thermal lensing effect caused by local overheating. This is particularly crucial for maintaining laser beam quality and frequency stability. The height of the ridge waveguide structure, controlled within the range of 500–800 nm, not only contributes to achieving good optical waveguide effects but also provides effective current confinement, helping to improve the matching between the optical field and electronic states, and enhancing the efficiency and stability of the laser operation.

[0049] The ratio of the ridge width of the ridge waveguide structure to the number of injection tips in the current injection sub-region 821 satisfies:

[0050] 8≤L / n≤12

[0051] Where L represents the ridge width of the ridge waveguide structure, and n represents the number of injection tips in the current injection sub-region 821. By modulating the ratio of the ridge width of the ridge waveguide structure to the number of injection tips in the current injection sub-region 821, the ridge width occupied by each injection tip is ensured to be within a suitable range, guaranteeing that each tip can obtain a similar injection current area. This results in a more uniform current distribution, effectively avoiding current leakage imbalance caused by local current density, and reducing the risk of hot spots and local overheating. Furthermore, the balanced injection structure ensures the symmetry of the carrier distribution within the cavity, which helps stabilize the optical resonant mode and better suppresses the lasing of lateral higher-order modes, thereby achieving stable single-mode or multi-mode operation and improving the purity of the device beam and signal quality.

[0052] In this embodiment, by setting alternating injection tips and blocking tips within the contact layer 8, the injection position and distribution of current can be effectively controlled, reducing local current density or leakage problems, thereby lowering the risk of local overheating and the laser threshold. Furthermore, the design of the anti-reflective cavity surface 81, functional region 82, and high-reflective cavity surface 83 within the contact layer 8 provides clear optical partitioning for the entire cavity. The rational configuration of the current injection and blocking functional region 82 makes the coupling between the injected carriers and the optical field more matched, which is beneficial for suppressing the lasing of non-target optical modes and improving the beam quality and spectral purity of the laser output. Two trenches 823 in the first p-type confinement layer 6, penetrating the second p-type confinement layer 7 and the contact layer 8, enable the controlled current to be injected gradually from the high-reflective cavity surface 83 towards the anti-reflective cavity surface 81 along the cavity length direction. This reduces the carrier density at the edge of the front cavity surface and lowers the temperature gradient along the cavity length direction, thereby suppressing the thermal lensing effect. This results in a corresponding reduction in the gain of higher-order side modes and an increase in output power. Simultaneously, the introduction of a double-striped structure in the lateral direction effectively suppresses higher-order modes while enhancing lower-order modes. This can effectively suppress the broadening of the lateral divergence angle and improve beam quality.

[0053] This embodiment also provides a method for fabricating a semiconductor laser chip with current modulation, the method comprising:

[0054] An epitaxial wafer is prepared, comprising the sequential epitaxial growth of an n-type confinement layer 2, an n-type waveguide layer 3, a quantum well active region 4, a p-type waveguide layer 5, a first p-type confinement layer 6, a second p-type confinement layer 7, and a contact layer 8 on a substrate layer 1.

[0055] In this step, a suitable substrate material (such as GaAs or InP) is selected, and after chemical cleaning and surface treatment, the substrate is loaded into an MOCVD reactor. First, an n-type confinement layer 2 is grown on the substrate. By precisely controlling the gas flow rate, temperature, and pressure, an appropriate amount of n-type dopant (such as silicon) is incorporated to form a uniform confinement layer. Next, an n-type waveguide layer 3 is grown on the n-type confinement layer 2. This layer is mainly used for current transmission and optical waveguide functions. Finally, a quantum well structure is formed on the n-type waveguide layer 3 using low-temperature growth techniques. The layer is the light-emitting or lasing active region of the device, and controlling its layer thickness and interface quality is usually very critical. A p-type waveguide layer 5 is grown on the active region 4 of the quantum well. This layer ensures both current transmission and symmetrical optical waveguide. A first p-type confinement layer 6 is grown on the p-type waveguide layer 5 to confine the vertical diffusion of charge carriers and optimize the overall charge carrier distribution. Then, a second p-type confinement layer 7 is grown to further ensure the confinement and isolation of the injected current. Finally, a contact layer 8 is grown on the outermost layer to provide excellent metal contact and low contact resistance.

[0056] The epitaxial wafer is removed from the MOCVD reaction chamber, and the contact layer 8 located on the topmost layer of the epitaxial wafer is etched to remove part of the conductive dielectric in the second p-type confinement layer 7 and the contact layer 8, so as to expose the ridge waveguide structure formed by the second p-type confinement layer 7 and the contact layer 8.

[0057] In this step, after epitaxial growth is completed, the temperature inside the reaction chamber is reduced to a safe range, and the epitaxial wafer is then removed from the MOCVD reactor. At this point, it is crucial to ensure the epitaxial wafer is free from environmental contamination; subsequent processing is typically performed in a cleanroom environment. The surface of the epitaxial wafer is cleaned to remove any residues or organic contaminants. A suitable photoresist layer is coated and soft-dried to ensure uniform coverage of the contact layer 8. The contact layer 8 area on the epitaxial wafer is exposed using a mask to form the predetermined ridge waveguide structure pattern. Selective etching (either wet etching or dry etching such as reactive ion etching) is used, starting from the uppermost contact layer 8. The etching depth is controlled to remove some of the conductive dielectric material located in the second p-type confinement layer 7 and the contact layer 8, exposing the well-functioning ridge waveguide structure composed of these two layers. After etching, residual photoresist is removed, and the epitaxial wafer is then cleaned and surface-trimmed as necessary to ensure the exposed ridge waveguide structure is flat and undamaged.

[0058] The ridge waveguide structure is etched with a double-striped pattern to form a trench 823 penetrating the first p-type confinement layer 6, the second p-type confinement layer 7, and the contact layer 8, and the trench 823 is filled with SiO2 dielectric; and

[0059] In this step, a high-quality photoresist layer is uniformly coated onto the epitaxial wafer with the formed ridge waveguide structure. A high-resolution mask is used to expose a predefined double-striped pattern on the ridge waveguide region. After exposure, development is performed to form the photoresist pattern for etching. Dry etching processes such as reactive ion etching (RIE) or deep reactive ion etching (DRIE) are employed, with precise adjustments to the etching gas composition, power, pressure, and temperature to ensure the etching process occurs within the ridge waveguide structure and simultaneously penetrates the first p-type confinement layer 6, the second p-type confinement layer 7, and the contact layer 8. After etching, two parallel trenches 823 (double-striped structure) are formed within the ridge waveguide region, clearly exposing the inner layer area. After etching, residual photoresist and etching products are removed using appropriate methods (such as wet cleaning or plasma cleaning) to ensure that the edges of the trenches 823 are smooth and free of harmful residues. SiO2 is uniformly deposited onto the entire sample using methods such as chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD) in a processing environment. After SiO2 filling is complete, excess SiO2 on the surface can be removed using chemical mechanical planarization (CMP) or wet etching, leaving only the filler within the trench 823. This ensures the insulating function of the trench 823 without affecting the subsequent design of the current injection region.

[0060] A current injection region is etched in the contact layer 8, and P-side electrodes and N-side electrodes are sequentially fabricated on opposite sides of the epitaxial wafer to complete the fabrication of the semiconductor laser.

[0061] In this step, before etching, the epitaxial wafer surface is thoroughly cleaned to remove particles and residues. A high-resolution photoresist layer is then uniformly coated and pre-baked to ensure uniform coverage of the contact layer 8. A mask with a current injection region pattern is fabricated, defining the size and location of the current injection area. The mask is aligned with the photoresist on the epitaxial wafer, and the predefined pattern is transferred onto the photoresist through UV exposure. After exposure, the sample is immersed in a developer to remove the unexposed portions of the photoresist, forming the pattern mask for the current injection region. Using wet or dry etching (e.g., reactive ion etching, RIE), a portion of the conductive dielectric in the contact layer 8 outside the protected area of ​​the developed pattern is etched away to form the desired current injection region. The etching depth must be strictly controlled to ensure that only a portion of the material within the contact layer 8 is removed without damaging the underlying structure (such as the second p-type confinement layer 7) to form an optimized injection region. After etching, a suitable stripper is used to remove residual photoresist, resulting in a clearly defined current injection region.

[0062] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A semiconductor laser chip with current modulation, characterized in that, The structure comprises, from bottom to top, a substrate layer (1), an n-type confinement layer (2), an n-type waveguide layer (3), a quantum well active region (4), a p-type waveguide layer (5), a first p-type confinement layer (6), a second p-type confinement layer (7), and a contact layer (8), wherein, The contact layer (8) includes an anti-reflective cavity surface (81), a functional area (82), and a high-reflective cavity surface (83). The anti-reflective cavity surface (81) and the high-reflective cavity surface (83) are disposed on opposite sides of the second p-type confinement layer (7). The functional area (82) is disposed between the anti-reflective cavity surface (81) and the high-reflective cavity surface (83). The functional area (82) includes a current injection sub-region (821) and a current blocking sub-region (822). The current injection sub-region (821) has multiple injection tips, and the current blocking sub-region (822) has multiple blocking tips. The injection tips are disposed between any two adjacent blocking tips, and the injection tips and blocking tips are arranged alternately. The projections of the current blocking sub-region (822) and the current injection sub-region (821) are located on the same horizontal plane, and the current blocking sub-region (822) is higher than the current injection sub-region (821). The two trenches (823) formed by the first p-type limiting layer (6) penetrate the second p-type limiting layer (7) and the contact layer (8), and the two trenches (823) are located on opposite sides of the current injection sub-region (821) and the current blocking sub-region (822), and the trenches (823) are filled with an insulating medium. The trench (823) penetrates the first p-type confinement layer (6), the second p-type confinement layer (7), and the contact layer (8), and the trench (823) extends along the length of the semiconductor laser chip to the anti-reflection cavity surface (81) and the high-reflection cavity surface (83), respectively. The second p-type confinement layer (7) and the contact layer (8) are stacked sequentially to form a ridge waveguide structure. The ridge waveguide structure is used to control the current to be injected gradually from the high-reflectivity cavity surface (83) to the anti-reflectivity cavity surface (81) in the cavity length direction, thereby suppressing the thermal lensing effect. The width of the trench (823) is 0.5μm~1μm, and the distance between the trench (823) and the edge of the ridge waveguide structure is at least 5μm. The ridge waveguide structure is etched with a double stripe structure to form the trench (823), and the trench (823) is filled with SiO2 or SiN dielectric.

2. The semiconductor laser chip with current modulation as described in claim 1, characterized in that, A first blocking groove along the width direction of the semiconductor laser chip is formed between the anti-reflection cavity surface (81) and the functional area (82), and a second blocking groove along the width direction of the semiconductor laser chip is formed between the high-reflection cavity surface (83) and the functional area (82).

3. The semiconductor laser chip with current modulation as described in claim 1, characterized in that, Both the injection tip and the blocking tip are isosceles triangles, and the apex angles of the injection tip and the blocking tip satisfy the following: 0.1 ≤ tan(θ / 2) ≤ 0.2 Wherein, θ represents the apex angle of the injection tip or the blocking tip.

4. The semiconductor laser chip with current modulation as described in claim 1, characterized in that, The ratio of the ridge width of the ridge waveguide structure to the number of injection tips in the current injection sub-region (821) satisfies: 8≤L / n≤12 Where L represents the ridge width of the ridge waveguide structure, and n represents the number of injection tips in the current injection sub-region (821).

5. The semiconductor laser chip with current modulation as described in claim 1, characterized in that, The height of the ridge waveguide structure is 500~800nm.

6. The semiconductor laser chip with current modulation as described in claim 1, characterized in that, The substrate layer (1) includes an n-type substrate and an n-type buffer layer, wherein the n-type substrate and the n-type buffer layer are each of GaAs, InP, GaSb and GaN.

7. A method for fabricating a semiconductor laser chip with current modulation, used to fabricate a semiconductor laser chip with current modulation as described in any one of claims 1-6, characterized in that, include: An epitaxial wafer is prepared, the epitaxial wafer comprising sequentially growing an n-type confinement layer (2), an n-type waveguide layer (3), a quantum well active region (4), a p-type waveguide layer (5), a first p-type confinement layer (6), a second p-type confinement layer (7), and a contact layer (8) on a substrate layer (1); The epitaxial wafer is removed from the MOCVD reaction chamber, and the contact layer (8) located on the topmost layer of the epitaxial wafer is etched to remove part of the conductive medium in the second p-type confinement layer (7) and the contact layer (8) to expose the ridge waveguide structure formed by the second p-type confinement layer (7) and the contact layer (8); The ridge waveguide structure is etched with a double-striped structure to form a trench (823) penetrating the first p-type confinement layer (6), the second p-type confinement layer (7), and the contact layer (8), and the trench (823) is filled with SiO2 or SiN dielectric; and A current injection region is etched in the contact layer (8), and P-side electrodes and N-side electrodes are sequentially fabricated on opposite sides of the epitaxial wafer to complete the fabrication of the semiconductor laser.

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