Sectional data transmission circuit, control method thereof and image sensor

Abstract

The invention provides a sectional type data transmission circuit, a control method thereof and an image sensor, and the sectional type data transmission circuit is characterized in that a selection switch circuit is connected with a plurality of counters, and the counters are conducted with a buffer circuit under the control of a selection control signal; the buffer circuit receives and prestores a counting signal output by the counter, and transmits the counting signal to the data transmission circuit under the control of the gating enable signal; and the data transmission circuit outputs the counting signals in sequence under the control of the clock signal and the gating enable signal. By adding the buffer circuit, the counting signal output by the counter can be pre-stored, so that the counting signal can be completely established at the buffer circuit, the counting signal can be quickly transmitted to the data transmission circuit and is fully established during data transmission, and the data transmission rate is improved; meanwhile, the buffer circuit corresponds to the plurality of counters, so that the area of the buffer circuit is small, and the problem of how to improve the data transmission rate without increasing the area of an image sensor chip is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit design, and particularly to a segmented data transmission circuit, a control method thereof, and an image sensor. Background Art

[0002] CMOS image sensors (CIS) are widely used in imaging fields such as video, surveillance, industrial manufacturing, automobiles, and household appliances. With the continuous improvement of various application requirements, the requirements for parameters such as the resolution and frame rate of CIS are also continuously increasing, the amount of data to be transmitted is larger, and the data transmission rate per unit time is required to be higher.

[0003] The current mainstream CIS readout circuit is an architecture mainly based on column-parallel ADCs (analog-to-digital converters), and it is necessary to transmit all ADC quantization results to the digital module within the line frequency period. Due to the layout limitation of the CIS chip layout, usually a single bus runs through the entire array, connecting the same bit (bit) together, and a sense amplifier is used to drive and transmit the data of each column in sequence. The rate of this transmission method is usually about 100 Mbps. However, in this way, since a single bus runs through the entire array and there are multiple parallel ADCs on the array, the RC delay of the bus is relatively large.

[0004] In order to reduce the RC delay, currently a segmented transmission method is usually adopted, that is, a whole bus is split into several segments, so that the RC delay of each segment of the bus can be greatly reduced. However, due to the layout limitation of the CIS chip layout, it is impossible to configure a sense amplifier for each segment of the bus to achieve driving. Therefore, the signals on each segment of the bus must be fully established to ensure accurate data transmission. However, in existing CIS chips, the latch for temporarily storing data in each column has a very weak driving ability for the segmented bus, making it the bottleneck restricting the transmission rate. If the transmission rate in the segmented transmission method is to be increased, the driving ability of the latch for each column and each bit needs to be enhanced, which will significantly increase the power consumption and area cost of the CIS chip; or, increase the number of segments and reduce the capacitive load of each segment, but more dense segmentation results in more inter-stage transmission circuits, which will also increase the power consumption and area cost of the CIS chip. Therefore, the current segmented transmission method has a rate of about 200 Mbps and still cannot meet the application requirements of CIS chips in high-rate scenarios. Summary of the Invention

[0005] The purpose of the present invention is to provide a segmented data transmission circuit, a control method thereof, and an image sensor, so as to solve the problem of how to improve the data transmission rate without increasing the area of the image sensor chip.

[0006] To solve the above technical problem, the present invention provides a segmented data transmission circuit, including a selection switch circuit, a buffer circuit, and a data transmission circuit; The selection switch circuit is connected to a plurality of counters and is configured to conduct the output end of the selected counter to the input end of the buffer circuit under the control of a selection control signal; The buffer circuit is configured to receive the counting signal output by the counter and perform pre-storage, and transmit the pre-stored counting signal to the data transmission circuit under the control of a strobe enable signal; The data transmission circuit is configured to output the received counting signal in sequence under the control of a clock signal and the strobe enable signal.

[0007] Optionally, in the segmented data transmission circuit, the total number of the counters is N; the selection switch circuit includes M selection switches, and each selection switch is connected to N / M counters; the buffer circuit includes M buffers, and the input ends of the buffers are connected to the selection switches in one-to-one correspondence; where N and M are both positive integers, and N is greater than M; All the selection switches connect the output end of the selected counter to the input end of the buffer connected thereto under the control of the same selection control signal.

[0008] Optionally, in the segmented data transmission circuit, the buffer is a tri-state gate.

[0009] Optionally, in the segmented data transmission circuit, the data transmission circuit includes M data transmission units, and the M data transmission units are cascaded in sequence, and the data transmission units are connected to the output ends of the buffers in one-to-one correspondence.

[0010] Optionally, in the segmented data transmission circuit, the data transmission unit includes a segmented bus, a flip-flop, and a tri-state gate; one end of the segmented bus is connected to the output end of the tri-state gate of the previous-stage data transmission unit to receive the counting signal transmitted by the previous-stage data transmission unit; the segmented bus is further configured to receive the counting signal output by the buffer; the other end of the segmented bus is connected to the input end of the flip-flop; the clock terminal of the flip-flop receives the clock signal, and the output terminal is connected to the input end of the tri-state gate; the tri-state gate is configured to transmit the counting signal output by the flip-flop under the control of the strobe enable signal.

[0011] Optionally, in the segmented data transmission circuit, the data transmission unit further includes a buffer; the input end of the buffer receives the clock signal, and the output end is connected to the clock terminal of the flip-flop.

[0012] Optionally, in the segmented data transmission circuit, the flip-flop is a D flip-flop.

[0013] To solve the above technical problems, the present invention also provides a control method for a segmented data transmission circuit, which is used to control the segmented data transmission circuit described in any one of the above. The control method includes: Under the control of a selection control signal, control the selection switch circuit to transmit the counting signal output by the selected counter to the buffer circuit for pre-storage; Under the control of a strobe enable signal, the buffer circuit transmits the pre-stored counting signal to the data transmission circuit; Under the control of a clock signal and a strobe enable signal, the data transmission circuit outputs the received counting signal in sequence.

[0014] Optionally, in the control method of the segmented data transmission circuit, the control method includes: When the strobe enable signal is valid, all the buffers in the buffer circuit transmit the pre-stored counting signal to the corresponding segmented bus in the data transmission circuit; When the clock signal is valid and the strobe enable signal is invalid, the cascaded multiple flip-flops in the data transmission circuit transmit the counting signal received from the segmented bus to the tri-state gate in the data transmission circuit and output it in sequence.

[0015] To solve the above technical problems, the present invention also provides an image sensor, which includes the segmented data transmission circuit described in any one of the above.

[0016] The segmented data transmission circuit, its control method, and the image sensor provided by the present invention include a selection switch circuit, a buffer circuit, and a data transmission circuit; the selection switch circuit is connected to multiple counters, and is used to conduct the output end of the selected counter to the input end of the buffer circuit under the control of a selection control signal; the buffer circuit is used to receive the counting signal output by the counter and pre-store it, and under the control of a strobe enable signal, transmit the pre-stored counting signal to the data transmission circuit; the data transmission circuit is used to output the received counting signal in sequence under the control of a clock signal and the strobe enable signal. By adding a buffer circuit between the selection switch circuit and the data transmission circuit, the counting signal output by the counter can be stored in the buffer circuit in advance, so as to ensure that the counting signal can be fully established at the buffer circuit, and then the counting signal can be quickly transmitted to the data transmission circuit and fully established during data transmission, improving the data transmission rate; at the same time, since the buffer circuit corresponds to multiple counters, the area of the buffer circuit is small, solving the problem of how to improve the data transmission rate without increasing the area of the image sensor chip. Description of the Drawings

[0017] Figure 1 It is a structural block diagram of the segmented data transmission circuit provided in this embodiment; Figure 2 Schematic diagram of a partial circuit of the segmented data transmission circuit provided in this embodiment; Figure 3 Schematic diagram of a partial circuit of a preferred segmented data transmission circuit provided in this embodiment; Figure 4 Flowchart of the control method for the segmented data transmission circuit provided in this embodiment; Figure 5 Timing diagram of the segmented data transmission circuit provided in this embodiment; Figure 6 Schematic diagram of the structure of the image sensor provided in this embodiment. Detailed implementation manners

[0018] The following further elaborates on the segmented data transmission circuit, its control method, and the image sensor proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention. In addition, the structures shown in the accompanying drawings are often part of the actual structures. Specifically, the accompanying drawings need to show different focuses and sometimes use different scales.

[0019] It should be noted that the "first", "second", etc. in the description, claims, and drawings of the present invention are used to distinguish similar objects in order to describe the embodiments of the present invention, rather than to describe a specific order or sequence. It should be understood that such structures can be interchanged under appropriate circumstances. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0020] This embodiment provides a segmented data transmission circuit, as Figure 1 shown, including a selection switch circuit, a buffer circuit, and a data transmission circuit; The selection switch circuit is connected to a plurality of counters and is used to conduct the output end of the selected counter to the input end of the buffer circuit under the control of a selection control signal; The buffer circuit is used to receive the counting signal output by the counter and pre-store it, and under the control of a strobe enable signal, transmit the pre-stored counting signal to the data transmission circuit; The data transmission circuit is used to sequentially output the received counting signal under the control of a clock signal and the strobe enable signal.

[0021] The high-speed data transmission circuit provided in this embodiment can store the count signal output by the counter in the buffer circuit in advance by adding a buffer circuit between the selection switch circuit and the data transmission circuit, so as to ensure that the count signal can be fully established at the buffer circuit, and then can quickly transmit the count signal to the data transmission circuit and be fully established during data transmission, improving the data transmission rate. At the same time, since the buffer circuit corresponds to multiple counters, the area of the buffer circuit is small, solving the problem of how to improve the data transmission rate without increasing the area of the image sensor chip.

[0022] Specifically, in this embodiment, the total number of the counters is N; the selection switch circuit includes M selection switches, and each of the selection switches is connected to N / M counters; the buffer circuit includes M buffers, and the input ends of the buffers are connected to the selection switches in one-to-one correspondence; where N and M are both positive integers, and N is greater than M.

[0023] That is to say, as Figure 2 shown, every m (N / M) counters form a counter group and are connected to a selection switch. Each selection switch includes m branches, and each branch is connected to a counter, so as to realize the on-off control of each counter by the selection switch. At the same time, each buffer B is connected to a selection switch, so as to correspondingly receive the count signals transmitted by the m counters connected to the selection switch.

[0024] In practical applications, all the selection switches are controlled by the same selection control signal COL_SEL to connect the output ends of the selected counters to the input ends of the buffers connected thereto. For example, as Figure 2 shown, when the selection control signal COL_SEL selects the branch corresponding to the first counter (counter (0)) in counter group 1 to conduct, the branch corresponding to the first counter (counter (m)) in counter group 2 conducts, and the first counters in other counter groups all conduct; similarly, when the selection control signal COL_SEL selects the kth counter in counter group 1 to conduct, the kth counters in other counter groups all conduct, which is beneficial to the sequential reading of subsequent count signals and subsequent signal processing.

[0025] In addition, in this embodiment, the buffer can complete the establishment of the count signal output by the counter under the control of the strobe enable signal EN_SEL and determine whether to transmit the count signal output by the counter to the data transmission circuit.

[0026] In practical applications, the buffer can be a tri-state gate. Preferably, a tri-state gate with strong driving force can be selected as the buffer, so as to significantly improve the establishment speed of the signal at the segmented bus and effectively improve the data transmission efficiency.

[0027] Specifically, as Figure 2 shown, when the strobe enable signal EN_SEL is invalid (low level), the tri-state gates B1 and B2 are in a high-impedance state, disconnecting the selection switch circuit from the data transmission circuit, so that the counting signal output by the counter is pre-stored at the OUT_SW node of the buffer, realizing the establishment of the signal; when the counting signal is fully established, the strobe enable signal EN_SEL becomes valid (high level), at this time the tri-state gates B1 and B2 are turned on, enabling the counting signal to be quickly transmitted to the data transmission signal and fully established.

[0028] In practical applications, the control circuit can establish the counting signal output by the counter in advance at the buffer. In this way, even if the driving ability of the latch is very weak, as long as the advance time is sufficient to ensure sufficient signal establishment time at the buffer, the counting signal can be fully established at the OUT_SW node of the buffer, and then can quickly transmit the counting signal to the data transmission signal after the buffer is turned on, improving the data transmission efficiency.

[0029] In addition, since the buffer of this embodiment corresponds to m counters, the circuit cost of improving the driving ability of the latch for each counter is saved, thus greatly saving the circuit area. Moreover, when using tri-state gates to implement the buffer function, due to the simple circuit structure, extremely small occupied area and low power consumption of the tri-state gate circuit, the circuit area and power consumption of the image sensor chip can be hardly increased additionally.

[0030] Further, in this embodiment, corresponding to the number of buffers, the data transmission circuit includes M data transmission units, and the M data transmission units are cascaded in sequence, and the data transmission units are connected to the output ends of the buffers in a one-to-one correspondence.

[0031] Specifically, as Figure 2 shown, the data transmission unit includes a segmented bus BUS-LINE, a flip-flop DFF, and a tri-state gate T. One end of the segmented bus is connected to the output end of the tri-state gate of the previous-level data transmission unit to receive the counting signal transmitted by the previous-level data transmission unit; the segmented bus is also used to receive the counting signal output by the buffer; the other end of the segmented bus is connected to the input end of the flip-flop; the clock terminal of the flip-flop receives the clock signal CLK, and the output end is connected to the input end of the tri-state gate; the tri-state gate is used to transmit the counting signal output by the flip-flop under the control of the strobe enable signal EN_SEL.

[0032] Taking Figure 2Taking the shown example, the data transmission unit 1 includes a segmented bus BUS-LINE1, a flip-flop DFF1, and a tri-state gate T1, and the data transmission unit 2 includes a segmented bus BUS-LINE2, a flip-flop DFF2, and a tri-state gate T2. One end of the segmented bus BUS-LINE1 is connected to the output end of the tri-state gate T2, so as to receive the counting signal transmitted by the counter group 2 received by the data transmission unit 2; at the same time, the segmented bus BUS-LINE1 is also connected to the buffer B1 to receive the counting signal transmitted by the counter group 1; and the other end of the segmented bus BUS-LINE1 is connected to the input end of the flip-flop DFF1; the output end of the flip-flop DFF1 is connected to the input end of the tri-state gate T1. Since the data transmission unit 1 is the last stage on the transmission route, the output end of the tri-state gate T1 outputs the counting signal in sequence.

[0033] In this embodiment, the flip-flop can be a D flip-flop. Of course, in other embodiments, it can also be set to other flip-flops, and the present application does not limit this.

[0034] It should be noted that this embodiment only takes Figure 2 the shown two sets of structures as examples to illustrate the connection relationship between each device. Of course, in actual applications, those skilled in the art can refer to Figure 2 the connection method to know the connection relationship between each device under more sets of structures, and the present application will not elaborate.

[0035] In actual application, as Figure 2 shown, when the strobe enable signal EN_SEL is at a high level (valid), the buffers B1 and B2 are turned on, and at the same time the tri-state gates T1 and T2 are in a high-impedance state, so that the transmission chain between the data transmission unit 1 and the data transmission unit 2 is disconnected. At this time, the segmented buses BUS-LINE1 and BUS-LINE2 respectively receive the counting signals fully established by the buffers B1 and B2 and transmit them to the flip-flops DFF1 and DFF2; when the strobe enable signal EN_SEL is at a low level (invalid), the buffers B1 and B2 are in a high-impedance state and are disconnected from the data transmission circuit. At the same time, the tri-state gates T1 and T2 are turned on, so that the transmission chain is closed, and the counting signals in the flip-flops are normally output in sequence under the control of the clock signal.

[0036] Preferably, in order to ensure that each data transmission unit has sufficient driving ability to ensure that the time interval of the output counting signal meets the data reading requirements, in this embodiment, as Figure 3As shown, the data transmission unit further includes a buffer; the input end of the buffer receives the clock signal CLK, and the output end is connected to the clock end of the flip-flop. Specifically, the clock signal CLK is input to the flip-flop DFF1 through the buffer B3, and then input to the flip-flop DFF2 through the buffer B4, so as to accurately control the output signals between the flip-flops DFF1 and DFF2 by using the buffers B3 and B4.

[0037] This embodiment also provides a control method for a segmented data transmission circuit, which is used to control the segmented data transmission circuit as described above, such as Figure 4 As shown, the control method includes: S1. Under the control of the selection control signal, control the conduction of the path in the selection switch circuit to transmit the counting signal output by the selected counter to the buffer circuit for pre-storage; S2. Under the control of the strobe enable signal, the buffer circuit transmits the pre-stored counting signal to the data transmission circuit; S3. Under the control of the clock signal and the strobe enable signal, the data transmission circuit outputs the received counting signals in sequence.

[0038] Next, in combination with Figure 2 and Figure 5 , the control method for the segmented data transmission circuit provided in this embodiment will be described in detail, where SEL <x>Indicates the counter strobe signal in the counter group. For example, SEL = 0 indicates that the first counter in each counter group is strobed, SEL = 1 indicates that the second counter in each counter group is strobed, and so on. When the counter strobe signal SEL <x>After selecting the counter for the counting signal to be transmitted, select the control signal COL_SEL to control the selection switch to conduct the selected counter to the input terminal of the buffer, so that the counting signal of the selected counter can be fully established at OUT_SW of the buffer. As Figure 5 shown, where the red curve describes the establishment process of the counting signal.

[0039] When the counting signal is fully established, control the strobe enable signal EN_SEL to be at a high level (valid). At this time, the pre-stored counting signal at the buffer is transmitted to the segmented bus and then to the D flip-flop. At this time, the tri-state gate in the digital transmission unit is in a high-impedance state, isolating the data transmission between each data transmission unit.

[0040] When the strobe enable signal EN_SEL is at a low level (invalid), the buffer is in a high-impedance state and isolated from the segmented bus; at the same time, the tri-state gate in the digital transmission unit conducts, and then when the clock signal CLK is valid, it triggers the D flip-flop to work, transmits the counting signal to the tri-state gate, and outputs it in sequence.

[0041] And so on, until the output of the counting signals in all counters is completed, thus completing the readout process of a working cycle.

[0042] In this way, even if the establishment speed of the counting signal at OUT_SW of the buffer is very slow, as long as the selection control signal COL_SEL is selected in advance of the strobe enable signal EN_SEL long enough, it can ensure that the counting signal is fully established at OUT_SW of the buffer. For example, the selection control signal COL_SEL can be advanced to the end moment of the previous strobe enable signal EN_SEL pulse at most. According to each counter group having N / M (m) counters and each small cycle duration being m×T, the selection control signal COL_SEL can be stretched to (m - 1)×T at most.

[0043] In addition, this embodiment also provides an image sensor, including the segmented data transmission circuit as described above.

[0044] In practical applications, as Figure 6 shown, the image sensor further includes a pixel array, an analog-to-digital converter, a row selection decoder driver, a ramp generator, a timing controller, a data processor, etc. Among them, the analog-to-digital converter includes analog-to-digital conversion units corresponding one-to-one to the columns of the pixel array, and each analog-to-digital conversion unit includes a comparator and a counter, so as to use the comparator to compare the pixel signal output by the pixel array with the ramp signal output by the ramp generator, and then use the counter to count the comparison signal output by the comparator, so as to complete the quantization of the pixel signal and output a counting signal.

[0045] The data transmission circuit of the image sensor adopts the segmented data transmission circuit provided in this embodiment, so that the counting signal output by the counter can be transmitted to the data processor at a high speed for subsequent processing, realizing high-speed data transmission.

[0046] The segmented data transmission circuit and the image sensor provided in this embodiment can achieve a transmission rate of about 500 Mbps. And since only a few buffers are added, the chip area and power consumption are hardly increased.

[0047] The specific circuit connection manners of the pixel array, analog-to-digital converter, row selection decoder driver, ramp generator, timing controller, data processor, etc. in the image sensor are well known to those skilled in the art, and will not be elaborated in this application.

[0048] It should be noted that the various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other. In addition, the different parts among the embodiments can also be combined and used with each other, and the present invention does not limit this.

[0049] The segmented data transmission circuit and its control method, and the image sensor provided in this embodiment include a selection switch circuit, a buffer circuit, and a data transmission circuit. The selection switch circuit is connected to multiple counters and is used to conduct the output end of the selected counter to the input end of the buffer circuit under the control of a selection control signal. The buffer circuit is used to receive the counting signal output by the counter and pre-store it, and under the control of a strobe enable signal, transmit the pre-stored counting signal to the data transmission circuit. The data transmission circuit is used to sequentially output the received counting signal under the control of a clock signal and a strobe enable signal. By adding a buffer circuit between the selection switch circuit and the data transmission circuit, the counting signal output by the counter can be pre-stored in the buffer circuit, so as to ensure that the counting signal can be fully established at the buffer circuit, and then the counting signal can be quickly transmitted to the data transmission circuit and fully established during data transmission, improving the data transmission rate. At the same time, since the buffer circuit corresponds to multiple counters, the area of the buffer circuit is small, solving the problem of how to improve the data transmission rate without increasing the area of the image sensor chip.

[0050] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure fall within the protection scope of the claims.< / x> < / x>

Claims

1. A segmented data transmission circuit, characterized in that It includes a selection switch circuit, a buffer circuit, and a data transmission circuit; The selection switch circuit is connected to a plurality of counters and is used to conduct the output end of the selected counter to the input end of the buffer circuit under the control of a selection control signal; The buffer circuit is used to receive the count signal output by the counter and perform pre-storage, and under the control of a strobe enable signal, transmit the pre-stored count signal to the data transmission circuit; The data transmission circuit is used to sequentially output the received count signal under the control of a clock signal and the strobe enable signal.

2. The segmented data transmission circuit according to claim 1, wherein The total number of the counters is N; the selection switch circuit includes M selection switches, and each selection switch is connected to N / M counters; the buffer circuit includes M buffers, and the input ends of the buffers are connected to the selection switches in one-to-one correspondence; where N and M are both positive integers, and N is greater than M; All the selection switches connect the output end of the selected counter to the input end of the buffer connected thereto under the control of the same selection control signal.

3. The segmented data transmission circuit according to claim 2, wherein, The buffer is a tri-state gate.

4. The segmented data transmission circuit according to claim 2, wherein The data transmission circuit includes M data transmission units, and the M data transmission units are cascaded in sequence, and the data transmission units are connected to the output ends of the buffers in one-to-one correspondence.

5. The segmented data transmission circuit according to claim 4, wherein The data transmission unit includes a segmented bus, a flip-flop, and a tri-state gate; one end of the segmented bus is connected to the output end of the tri-state gate of the upper-level data transmission unit to receive the count signal transmitted by the upper-level data transmission unit; the segmented bus is also used to receive the count signal output by the buffer; the other end of the segmented bus is connected to the input end of the flip-flop; the clock terminal of the flip-flop receives the clock signal, and the output terminal is connected to the input end of the tri-state gate; the tri-state gate is used to transmit the count signal output by the flip-flop under the control of the strobe enable signal.

6. The segmented data transmission circuit according to claim 5, wherein, The data transmission unit further includes a buffer; the input end of the buffer receives the clock signal, and the output end is connected to the clock terminal of the flip-flop.

7. The segmented data transmission circuit according to claim 5, wherein The flip-flop is a D flip-flop.

8. A control method for a segmented data transmission circuit, used to control the segmented data transmission circuit according to any one of claims 1 to 7, characterized in that, The control method includes: Under the control of a selection control signal, controlling the selection switch circuit to transmit the count signal output by the selected counter to the buffer circuit for pre-storage; Under the control of a strobe enable signal, the buffer circuit transmits the pre-stored count signal to the data transmission circuit; Under the control of a clock signal and a strobe enable signal, the data transmission circuit sequentially outputs the received count signal.

9. The control method of the segmented data transmission circuit according to claim 8, characterized in that, The control method includes: When the strobe enable signal is valid, all the buffers in the buffer circuit transmit the pre-stored count signal to the corresponding segmented bus in the data transmission circuit; When the clock signal is valid and the strobe enable signal is invalid, the cascaded multiple flip-flops in the data transmission circuit transmit the count signal received from the segmented bus to the tri-state gate in the data transmission circuit and output it in sequence.

10. An image sensor, characterized in that, It includes the segmented data transmission circuit according to any one of claims 1 to 7.

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