Semiconductor structure and preparation method thereof

Abstract

The embodiment of the invention relates to a semiconductor structure and a preparation method thereof, and the semiconductor structure comprises a plurality of active groups which are arranged in an array, and each active group comprises two semiconductor columns which are arranged at an interval along a first direction; the body region control line and the two word lines correspond to an active group and are arranged at intervals in the first direction, the body region control line is located on the first side walls, close to each other, of the two semiconductor columns, and the two word lines are located on the second side walls, away from the body region control line, of the two semiconductor columns respectively; the body region control line and the word line are partially opposite in the first direction. The semiconductor structure provided by the embodiment of the invention at least can improve the floating body effect and the coupling effect of the semiconductor structure at the same time.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and particularly to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] As the integration density of dynamic memories develops towards a higher level, higher requirements are imposed on the arrangement of transistors and the transistor size in a dynamic memory array structure.

[0003] The further reduction of the transistor size inevitably leads to the deterioration of the performance of the memory device. For example, problems such as an increase in the off-state leakage current due to the floating body effect, and the problem that coupling effects are likely to occur between adjacent word lines due to the too small size (too small pitch). In order to ensure excellent performance while increasing the integration degree of the memory device, how to solve the floating body effect and the coupling effect has become an urgent problem to be solved at present. Summary of the Invention

[0004] Embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which can at least simultaneously improve the floating body effect and the coupling effect of the semiconductor structure.

[0005] Embodiments of the present disclosure provide a semiconductor structure, including: a plurality of active groups arranged in an array, each active group including two semiconductor pillars spaced apart along a first direction; a body region control line and two word lines spaced apart along the first direction corresponding to one of the active groups, the body region control line being located on a first side wall of the two semiconductor pillars close to each other, and the two word lines being respectively located on a second side wall of the two semiconductor pillars facing away from the body region control line, and the body region control line and the word line being partially opposite to each other in the first direction.

[0006] In some embodiments, the semiconductor pillar includes a first source / drain region, a second source / drain region, and a channel region and a body region located between the first source / drain region and the second source / drain region, the channel region and the body region being arranged along the first direction, wherein the word line is directly opposite to the channel region, and the body region control line is directly opposite to a part of the body region arranged close to the first source / drain region.

[0007] In some embodiments, the body region control line has a first surface and a second surface opposite to each other, the word line has a third surface and a fourth surface opposite to each other, the direction from the first surface to the second surface and the direction from the third surface to the fourth surface are both the same as the direction from the first source / drain region to the second source / drain region, wherein the third surface is flush with the first surface, or the orthographic projection of the third surface in the first direction is located on the surface of the body region control line.

[0008] In some embodiments, the ratio of the dimension of the body region control line in the extending direction of the semiconductor column to the dimension of the word line in the extending direction of the semiconductor column is 0.1 to 0.5.

[0009] In some embodiments, the semiconductor structure further includes: a bit line, and the bit line is coupled to the first source / drain region.

[0010] In some embodiments, the semiconductor structure further includes: a capacitor structure, and the capacitor structure is coupled to the second source / drain region.

[0011] In some embodiments, the semiconductor structure further includes: a first gate dielectric layer, the first gate dielectric layer is located between the semiconductor column and the body region control line, covering the body region; a second gate dielectric layer, the second gate dielectric layer is located between the semiconductor column and the word line, covering the channel region, and in the first direction, the ratio of the thickness of the first gate dielectric layer to the thickness of the second gate dielectric layer is 0.5 to 1.5.

[0012] In some embodiments, a plurality of active groups are arranged in an array along the first direction and the second direction, the body region control line and the word line extend along the second direction, and one body region control line and two word lines are correspondingly provided for any column of active groups arranged along the second direction, and the first direction intersects with the second direction.

[0013] In some embodiments, the semiconductor structure further includes: a substrate, and the plurality of active groups are located on the substrate, wherein the semiconductor column extends in a direction perpendicular to the substrate, and both the first direction and the second direction are parallel to the substrate.

[0014] In some embodiments, the semiconductor structure further includes: a substrate, and the plurality of active groups are located on the substrate, wherein the semiconductor column extends in a direction parallel to the substrate, the first direction is parallel to the substrate, and the second direction is perpendicular to the substrate.

[0015] In some embodiments, the semiconductor structure further includes: an air gap structure, the air gap structure is located between the two semiconductor columns of the active group, and the air gap structure is also partially opposite to the word line in the first direction.

[0016] Correspondingly, an embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure, including: forming a plurality of active groups arranged in an array, where each active group includes two semiconductor pillars spaced apart along a first direction; forming a body region control line and two word lines corresponding to one of the active groups and spaced apart along the first direction, the body region control line is located on a first sidewall of the two semiconductor pillars close to each other, the two word lines are respectively located on a second sidewall of the two semiconductor pillars facing away from the body region control line, and the body region control line and the word lines are partially opposite to each other along the first direction.

[0017] In some embodiments, the semiconductor pillar includes a first source / drain region, a second source / drain region, and a channel region and a body region located between the first source / drain region and the second source / drain region. The two semiconductor pillars of the active group are separated by a first isolation groove. Before forming the body region control line and the word lines, it further includes: forming a first gate dielectric layer on a sidewall of the semiconductor pillar facing the first isolation groove, the first gate dielectric layer covering the body region; forming a second gate dielectric layer on a sidewall of the semiconductor pillar away from the first isolation groove, the second gate dielectric layer covering the channel region.

[0018] In some embodiments, the method for forming the body region control line includes: forming an initial body region control line filling the first isolation groove, the initial body region control line covering the surface of the first gate dielectric layer; etching a part of the initial body region control line in the first isolation groove to make the remaining initial body region control line face the part of the body region, and the remaining initial body region control line serves as the body region control line.

[0019] In some embodiments, after forming the body region control line, it further includes: forming an air gap structure, the air gap structure is located between the two semiconductor pillars of the active group, and the air gap structure is also opposite to a part of the word lines in the first direction.

[0020] In some embodiments, the method for forming the air gap structure includes: forming an isolation layer in the first isolation groove, the isolation layer is spaced apart from the body region control line along the extending direction of the semiconductor pillar, and the gap between the isolation layer and the body region control line constitutes the air gap structure.

[0021] In some embodiments, after forming the air gap structure, forming the word lines, the method for forming the word lines includes: forming an initial word line layer covering the surface of the second gate dielectric layer; performing an etching process on a part of the initial word line layer to make the remaining part of the initial word line layer face the channel region, and the remaining part of the initial word line layer serves as the word line.

[0022] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages:

[0023] In the semiconductor structure provided by an embodiment of the present disclosure, an active group corresponds to one body region control line and two word lines. The body region control line is located on the first side walls of two semiconductor pillars that are close to each other. That is, the body region control line can serve as a back gate, and the two semiconductor pillars can share the same body region control line. When a fixed voltage is applied to the body region control line, the body region control line can respectively form discharge channels on the two semiconductor pillars, thereby discharging the accumulated charges and improving the floating body effect. In addition, since the body region control line and the word lines are partially opposite in the first direction, the body region control line can play a partial shielding role between the two opposite word lines, weakening the coupling effect between the two word lines. And because the body region control line is only partially opposite to the word lines, it can prevent the problem that the parasitic capacitance between the body region control line and the word lines increases due to the complete alignment of the body region control line and the word lines. Description of the Drawings

[0024] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplary illustrations do not limit the embodiments unless otherwise stated. The figures in the drawings do not constitute a proportional limitation; in order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the following described drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0025] Figure 1 It is a schematic structural diagram of the first semiconductor structure provided by an embodiment of the present disclosure;

[0026] Figure 2 It is a schematic structural diagram of the second semiconductor structure provided by an embodiment of the present disclosure;

[0027] Figure 3 It is a schematic structural diagram of the third semiconductor structure provided by an embodiment of the present disclosure;

[0028] Figure 4 It is a three-dimensional structural diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0029] Figure 5 It is a three-dimensional structural diagram of another semiconductor structure provided by an embodiment of the present disclosure;

[0030] Figure 6 It is a schematic structural diagram of the fourth semiconductor structure provided by an embodiment of the present disclosure;

[0031] Figure 7 It is a schematic structural diagram of the fifth semiconductor structure provided by an embodiment of the present disclosure;

[0032] Figure 8 Schematic diagram of the structure of the sixth semiconductor structure provided by an embodiment of the present disclosure;

[0033] Figure 9 Schematic three-dimensional structure diagram corresponding to the step of forming a semiconductor pillar in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0034] Figure 10 Top view structure diagram corresponding to the steps of forming a semiconductor layer and a sacrificial layer in another method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0035] Figure 11 is Figure 10 Cross-sectional structure diagram in the aa' direction of;

[0036] Figure 12 Top view structure diagram corresponding to the steps of forming a first isolation groove and a second isolation groove in another method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0037] Figure 13 is Figure 12 Cross-sectional structure diagram in the bb' direction of;

[0038] Figure 14 Schematic three-dimensional structure diagram corresponding to the step of forming a first isolation structure in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0039] Figure 15 Schematic three-dimensional structure diagram corresponding to the step of etching the first isolation structure in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0040] Figure 16 Schematic three-dimensional structure diagram corresponding to the steps of forming a first gate dielectric layer and a second gate dielectric layer in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0041] Figure 17 Top view structure diagram corresponding to the step of forming a first isolation structure in another method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0042] Figure 18 is Figure 17 Cross-sectional structure diagram in the bb' direction of;

[0043] Figure 19 Top view structure diagram corresponding to the step of etching the first isolation structure in another method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0044] Figure 20Schematic top view structure corresponding to the steps of forming a first gate dielectric layer and a second gate dielectric layer in another semiconductor structure manufacturing method provided by embodiments of the present disclosure;

[0045] Figure 21 For Figure 20 Schematic cross-sectional structure in the bb' direction in;

[0046] Figure 22 Schematic three-dimensional structure corresponding to the step of forming a body region control line in a semiconductor structure manufacturing method provided by embodiments of the present disclosure;

[0047] Figure 23 Schematic top view structure corresponding to the step of forming an initial body region control line in another semiconductor structure manufacturing method provided by embodiments of the present disclosure;

[0048] Figure 24 For Figure 23 Schematic cross-sectional structure in the bb' direction in;

[0049] Figure 25 Schematic top view structure corresponding to the step of forming a body region control line in another semiconductor structure manufacturing method provided by embodiments of the present disclosure;

[0050] Figure 26 For Figure 25 Schematic cross-sectional structure in the cc' direction in;

[0051] Figure 27 Schematic three-dimensional structure corresponding to the step of forming an air gap structure in a semiconductor structure manufacturing method provided by embodiments of the present disclosure;

[0052] Figure 28 Schematic top view structure corresponding to the step of forming an initial isolation layer in another semiconductor structure manufacturing method provided by embodiments of the present disclosure;

[0053] Figure 29 For Figure 28 Schematic cross-sectional structure in the bb' direction in;

[0054] Figure 30 Schematic top view structure corresponding to the step of forming an air gap structure in another semiconductor structure manufacturing method provided by embodiments of the present disclosure;

[0055] Figure 31 Schematic three-dimensional structure corresponding to the step of forming an initial word line layer in a semiconductor structure manufacturing method provided by embodiments of the present disclosure;

[0056] Figure 32 Schematic three-dimensional structure corresponding to the step of forming a second isolation structure in a semiconductor structure manufacturing method provided by embodiments of the present disclosure;

[0057] Figure 33 Schematic three-dimensional structure diagram corresponding to the step of forming a word line in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0058] Figure 34 Top-view structure diagram corresponding to the step of forming a second isolation structure in another method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0059] Figure 35 Top-view structure diagram corresponding to the step of forming a word line in another method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure. Detailed implementation manners

[0060] As can be seen from the background art, currently, due to the reduction in size of semiconductor structures, floating body effects and coupling effects are likely to occur, thereby affecting the performance of semiconductor structures. Among them, the floating body effect is caused by the accumulation of charges in the body region, resulting in leakage current and causing higher current consumption. The coupling effect usually occurs between adjacent word lines. When a control voltage is applied to one of the word lines, it will interfere with the other word line, resulting in a large leakage current in the transistor controlled by the other word line.

[0061] An embodiment of the present disclosure provides a semiconductor structure. A body region control line is provided on the first side walls of two semiconductor pillars close to each other. The body region control line can serve as a common back gate for the two semiconductor pillars. When a fixed voltage is applied to the body region control line, discharge channels can be formed on the two semiconductor pillars respectively, thereby discharging the accumulated charges and improving the floating body effect. The body region control line is partially opposite to the word line in the first direction, which not only enables the body region control line to play a partial shielding role between two opposite word lines, weakening the coupling effect between the two word lines, but also can prevent the body region control line from being completely opposite to the word line, so that the coupling effect between the body region control line and the word line will not be too large, avoiding the problem of an increase in the parasitic capacitance between the body region control line and the word line.

[0062] The following will elaborate on each embodiment of the present disclosure with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present disclosure, many technical details are proposed for the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions required to be protected by the present disclosure can still be implemented.

[0063] Figure 1 Schematic structure diagram of the first semiconductor structure provided by an embodiment of the present disclosure; Figure 2 Schematic structure diagram of the second semiconductor structure provided by an embodiment of the present disclosure; Figure 3Schematic diagram of the third semiconductor structure provided by an embodiment of the present disclosure; Figure 4 Schematic three-dimensional structure diagram of a semiconductor structure provided by an embodiment of the present disclosure; Figure 5 Schematic three-dimensional structure diagram of another semiconductor structure provided by an embodiment of the present disclosure; Figure 6 Schematic diagram of the fourth semiconductor structure provided by an embodiment of the present disclosure; Figure 7 Schematic diagram of the fifth semiconductor structure provided by an embodiment of the present disclosure; Figure 8 Schematic diagram of the sixth semiconductor structure provided by an embodiment of the present disclosure.

[0064] Refer to Figure 1 , the semiconductor structure includes: a plurality of active groups 10 arranged in an array, and each active group 10 includes two semiconductor columns 101 arranged at intervals along the first direction X. The semiconductor structure further includes: a body region control line 102 and two word lines 103 corresponding to one active group 10 and arranged at intervals along the first direction X. The body region control line 102 is located on the first side walls of the two semiconductor columns 101 close to each other, and the two word lines 103 are respectively located on the second side walls of the two semiconductor columns 101 facing away from the body region control line 102. The body region control line 102 and the word lines 103 are partially opposite to each other along the first direction X.

[0065] Each semiconductor column 101 can be used to form a transistor, and the two word lines 103 are respectively used to form the gates of the two transistors; one body region control line 102 corresponds to the two semiconductor columns 101 of one active group 10 and can be used to form a common "back gate" of the two transistors. It should be noted that in the present disclosure, the "back gate" may not be turned on simultaneously with the gate, that is, the gate independently controls the conduction of the transistor.

[0066] The word line 103 is used to control the conduction of the transistor to complete the access of data. During the conduction process of the transistor, a part of the channel close to the gate (such as Figure 2 shown by the channel region 113 in) is depleted; while another part of the channel away from the gate (such as Figure 2 shown by the body region 114 in) is not depleted, that is, in an electrically floating state, and holes can accumulate in the floating body, thereby generating a floating body effect and having an adverse impact on the transistor performance.

[0067] Specifically in the semiconductor structure, charges will accumulate on the side of the semiconductor column 101 away from the word line 103. Based on this, a body region control line 102 is provided on the side of the semiconductor column 101 away from the word line 103. After applying a fixed voltage to the body region control line 102, a charge discharge channel can be formed on the side of the semiconductor column 101 with more accumulated holes, and then the accumulated holes are discharged through the discharge channel, thereby reducing or eliminating the floating body effect.

[0068] Two word lines 103 corresponding to an active group 10 are opposite to each other. When a control voltage is applied to one of the word lines 103, due to the coupling effect, interference will be generated on the other word line 103, resulting in a large leakage current in the transistor controlled by the other word line 103. The body region control line 102 is also partially opposite to the word line 103 in the first direction X, so that the body region control line 102 can play a role in shielding part of the electric field between the two opposite word lines 103, thereby weakening the coupling effect between the two word lines 103 and reducing the generation of leakage current. It should be noted that the body region control line 102 is only partially opposite to the word line 103. This is because if the body region control line 102 is opposite to the whole word line 103, although the coupling effect between the two word lines 103 will be alleviated to a great extent, however, since the body region control line 102 is a conductor, a coupling effect will be generated between itself and the word line 103. Therefore, in the embodiments of the present disclosure, the body region control line 102 is set to be only partially opposite to the word line 103, which can not only improve the floating body effect, but also play a role in weakening the coupling effect between two adjacent word lines 103.

[0069] In some embodiments, the material of the semiconductor column 101 can be silicon. In some embodiments, the material of the semiconductor column 101 can also be germanium, silicon germanium, silicon on insulator, etc.

[0070] In some embodiments, the material of the word line 103 can be a metal-based material. For example, it can include metal, metal nitride, metal silicide, or a combination thereof. Among them, the metal can be at least one of aluminum, tungsten, silver, copper, gold, cobalt, nickel, titanium, etc.

[0071] In some embodiments, the material of the body region control line 102 can be a conductor. For example, it can be a metal-based material, including metal, metal nitride, metal silicide, or a combination thereof. The metal can be at least one of aluminum, tungsten, silver, copper, gold, cobalt, nickel, titanium, etc. The material of the body region control line 102 can also be other materials capable of conducting electricity.

[0072] Reference Figure 2 and Figure 3 In some embodiments, the semiconductor column 101 includes a first source / drain region 111, a second source / drain region 112, and a channel region 113 and a body region 114 located between the first source / drain region 111 and the second source / drain region 112. The channel region 113 and the body region 114 are arranged along the first direction X. Among them, the word line 103 is opposite to the channel region 113, and the body region control line 102 is opposite to a part of the body region 114 arranged close to the first source / drain region 111. For example, the first source / drain regions 111 in two semiconductor columns 101 of the same active group 10 are integrally formed (i.e., in contact with each other and serving as a common first source / drain region 111).

[0073] The first source / drain region 111, the second source / drain region 112, and the channel region 113 can be used to form a transistor. In some embodiments, the first source / drain region 111 can be used to form the source of the transistor, and the second source / drain region 112 is used to form the drain of the transistor.

[0074] In some embodiments, the doping ion type of the first source / drain region 111 is the same as that of the second source / drain region 112. For example, it can be an N-type doping ion. The doping ion type of the channel region 113 is the same as that of the body region 114. For example, it can be a P-type doping ion, and the formed transistor has an N-type conductivity type.

[0075] It should be noted that in the embodiments of the present disclosure, the region between the first source / drain region 111 and the second source / drain region 112 is divided into the channel region 113 and the body region 114, which does not mean that there is a boundary line between the channel region 113 and the body region 114. The channel region 113 and the body region 114 are an integrated structure and have the same doping ion type. In the embodiments of the present disclosure, both the channel region 113 and the body region 114 can be used to form the channel of the transistor, but are divided into the channel region 113 and the body region 114 according to the region where charges accumulate. That is, charges mainly accumulate in the body region 114.

[0076] The body region control line 102 faces the part of the body region 114 disposed near the first source / drain region 111, so that after applying a fixed voltage to the body region control line 102, a discharge channel can be formed between the first source / drain region (such as the source) of the transistor and the channel (body region 114), which is beneficial to the discharge of the charges accumulated in the body region 114 through this discharge channel, thereby reducing or eliminating the floating body effect.

[0077] The word line 103 faces the channel region 113 and can control the conduction of the transistor.

[0078] Reference Figure 4 and Figure 5 , in some embodiments, a plurality of active groups 10 are arranged in an array along the first direction X and the second direction Y. The body region control line 102 and the word line 103 extend along the second direction Y. One body region control line 102 and two word lines 103 are correspondingly provided for each column of active groups 10 arranged along the second direction Y. The first direction X intersects with the second direction Y.

[0079] One column of active groups 10 includes: two columns of semiconductor pillars 101, and the plurality of semiconductor pillars 101 in each column of semiconductor pillars 101 are spaced apart along the second direction Y. One body region control line 102 is located between the two columns of semiconductor pillars 101. The two word lines 103 are respectively located on the second sidewalls of the two columns of semiconductor pillars 101, and each word line 103 is electrically connected to each channel region 113 in one column of semiconductor pillars 101.

[0080] In some embodiments, the semiconductor structure further includes: a substrate 100, and a plurality of active groups 10 located on the substrate 100.

[0081] In some embodiments, the material of the substrate 100 may be a semiconductor material. In some embodiments, the material of the substrate 100 may be silicon. In some embodiments, the substrate 100 may also be germanium, silicon germanium, or silicon on insulator.

[0082] Reference Figure 4 , in some embodiments, the semiconductor pillar 101 may extend in a direction perpendicular to the substrate 100, and the first direction X and the second direction Y are both parallel to the substrate 100. The plurality of active groups 10 are arranged in an array along a direction parallel to the substrate 100, and the body region control line 102 and the word line 103 both extend along a direction parallel to the substrate 100. The plurality of active groups 10 form a vertical-channel array transistor. In this way, the transistor area can be reduced as much as possible, and the integration degree of the semiconductor structure can be improved.

[0083] Reference Figure 5 , in some embodiments, the semiconductor pillar 101 may also extend in a direction parallel to the substrate 100, the first direction X is parallel to the substrate 100, and the second direction Y is perpendicular to the substrate 100. For example, each row of active groups 10 is arranged at intervals along a direction parallel to the substrate 100, and each column of active groups 10 is vertically stacked along a direction perpendicular to the substrate 100. The body region control line 102 and the word line 103 both extend vertically along a direction perpendicular to the substrate 100.

[0084] Reference Figure 2 , Figure 3 and Figure 5 , in some embodiments, the body region control line 102 has opposite first and second surfaces 121 and 122, the word line 103 has opposite third and fourth surfaces 123 and 124, the direction in which the first surface 121 points to the second surface 122 and the direction in which the third surface 123 points to the fourth surface 124 are both the same as the direction in which the first source-drain region 111 points to the second source-drain region 112. Among them, the third surface 123 is flush with the first surface 121 (as shown in Figure 2 ), or the positive projection of the third surface 123 in the first direction X is located on the surface of the body region control line 102 (that is, the plane where the third surface 123 is located is between the plane where the first surface 121 is located and the plane where the second surface 122 is located, as shown in Figure 3 ). That is to say, along the first direction X, the positive projection of the body region control line 102 on the word line 103 is located on the surface of a part of the word line 103. In this way, both the floating body effect can be improved, and the coupling effect between two adjacent word lines 103 can be weakened.

[0085] It can be understood that the word line 103 is opposite to the channel region 113, and the third surface 123 of the word line 103 is closer to the first source / drain region 111 than the fourth surface 124. Therefore, by setting the third surface 123 flush with the first surface 121, it can be ensured that the body region control line 102 is opposite to the part of the body region 114 arranged close to the first source / drain region 111, and thus an efficient discharge channel is formed between the first source / drain region 111 and the body region 114, improving the charge discharge efficiency and further improving the floating body effect.

[0086] The positive projection of the third surface 123 in the first direction X is located on the surface of the body region control line 102, that is, the third surface 123 is closer to the plane where the fourth surface 124 is located than the first surface 121. In other words, the relative distance from the third surface 123 to the plane where the fourth surface 124 is located is less than the relative distance from the first surface 121 to the plane where the fourth surface 124 is located. In this way, it can be further ensured that the body region control line 102 is opposite to the part of the body region 114 arranged close to the first source / drain region 111, and even opposite to part of the first source / drain region 111. For example, if the third surface 123 of the word line 103 is exactly opposite to the boundary line between the first source / drain region 111 and the channel region 113, since the positive projection of the third surface 123 is located on the surface of the body region control line 102, the fourth surface 124 of the body region control line 102 will exceed the boundary line between the first source / drain region 111 and the channel region 113, making the body region control line 102 opposite to part of the first source / drain region 111, and thus ensuring the formation of an efficient discharge channel.

[0087] Reference Figure 1 , in some embodiments, the ratio of the size h1 of the body region control line 102 in the extending direction of the semiconductor column 101 to the size h2 of the word line 103 in the extending direction of the semiconductor column 101 is 0.1 - 0.5. Within this range, the size of the body region control line 102 in the semiconductor extending direction is not too large compared to the size of the word line 103 in the semiconductor extending direction, enabling the body region control line 102 to shield part of the electric field between two opposite word lines 103, weakening the coupling effect between the two word lines 103. At the same time, it can also reduce the coupling effect generated between itself and the word line 103.

[0088] Reference Figure 6 , in some embodiments, the semiconductor structure further includes: a first gate dielectric layer 104, the first gate dielectric layer 104 is located between the semiconductor column 101 and the body region control line 102 and covers the body region 114; a second gate dielectric layer 105, the second gate dielectric layer 105 is located between the semiconductor column 101 and the word line 103 and covers the channel region 113. In the first direction X, the ratio of the thickness of the first gate dielectric layer 104 to the thickness of the second gate dielectric layer 105 is 0.5 - 1.5.

[0089] On the first sidewalls of the two semiconductor pillars 101 of an active group 10, a first gate dielectric layer 104 is covered, and a body region control line 102 is covered on the surface of the first gate dielectric layer 104 away from the first sidewall. On the second sidewalls of the two semiconductor pillars 101, a second gate dielectric layer 105 is covered, and a word line 103 is covered on the surface of the second dielectric layer away from the second sidewall.

[0090] Set the ratio of the thickness of the first gate dielectric layer 104 to the thickness of the second gate dielectric layer 105 to be 0.5 - 1.5. For example, it can be 0.5 - 0.8, 0.8 - 1, 1 - 1.2, 1.2 - 1.3, or 1.3 - 1.5. Within the above range, the thickness of the first gate dielectric layer 104 is not too large compared to the second gate dielectric layer 105, avoiding the problem that a too large fixed voltage needs to be applied to the body region control line 102 to form a discharge channel between the first source-drain region 111 and the body region 114. Additionally, within the above range, the thickness of the first gate dielectric layer 104 is not too small compared to the second gate dielectric layer 105, avoiding the problem of a large leakage current generated during the conduction of the discharge channel.

[0091] In some embodiments, the material of the first gate dielectric layer 104 may include silicon oxide, and the material of the second gate dielectric layer 105 may include silicon oxide.

[0092] Reference Figure 7 , in some embodiments, the semiconductor structure further includes: an air gap structure 106. The air gap structure 106 is located between the two semiconductor pillars 101 of the active group 10, and the air gap structure 106 is also partially opposite to the word line 103 in the first direction X. The air gap structure 106 and the body region control line 102 are arranged adjacent to each other in the first direction X. The inside of the air gap structure 106 is air, and air has a small dielectric constant, which can weaken the coupling effect between adjacent word lines 103.

[0093] In some embodiments, along the first direction X, the overall structure formed by the air gap structure 106 and the body region control line 102 substantially coincides with the orthographic projection of the word line 103. In other words, the orthographic projection of the air gap structure 106 in the first direction X covers a partial surface of the word line 103 facing the semiconductor pillar 101, and the orthographic projection of the body region control line 102 in the first direction X covers the remaining surface of the word line 103 facing the semiconductor pillar 101. In this way, the overall formed by the body region control line 102 and the air gap structure 106 is opposite to the word line 103, weakening the coupling effect between adjacent word lines 103 to the greatest extent. At the same time, the body region control line 102 can improve the floating body effect, thereby improving the performance of the semiconductor structure.

[0094] In some embodiments, the first gate dielectric layer 104 covers the entire first sidewall of the semiconductor pillar 101, and the second gate dielectric layer 105 covers the entire second sidewall of the semiconductor pillar 101. The semiconductor structure further includes: an isolation layer 107, which is located between two semiconductor pillars 101 of the active group 10, is arranged at an interval from the body region control line 102 along the first direction X, and the isolation layer 107 is opposite to the second source / drain region 112. The two opposite sidewalls of the isolation layer 107 in the first direction X are respectively in contact with the first gate dielectric layer 104, thereby forming an air gap structure 106 between the isolation layer 107 and the body region control line 102.

[0095] In some embodiments, the material of the isolation layer 107 can be an insulating material such as silicon oxide or silicon nitride.

[0096] Reference Figure 8 , in some embodiments, the semiconductor structure further includes: a bit line 108, and the bit line 108 is coupled to the first source / drain region 111.

[0097] The bit line 108 is located at the end of the semiconductor pillar 101 and is in contact with the first source / drain region 111.

[0098] In some embodiments, the number of bit lines 108 is multiple. The multiple bit lines 108 are arranged at intervals along the second direction Y, and each bit line 108 extends along the first direction X. Each bit line 108 is coupled to the first source / drain region 111 of the semiconductor pillars 101 in each row of the active group 10 arranged at intervals along the first direction X.

[0099] In some embodiments, the material of the bit line 108 can include a metal-based material. For example, it can include a metal, a metal nitride, a metal silicide, or a combination thereof. In some embodiments, the material of the bit line 108 can also be the same as the material of the semiconductor pillar 101. For example, it is a semiconductor material, and by doping the semiconductor material to make it conductive, the bit line 108 is formed.

[0100] Reference Figure 8 , in some embodiments, the semiconductor structure further includes: a capacitor structure 109, and the capacitor structure 109 is coupled to the second source / drain region 112. The capacitor structure 109 can be located on the side of the semiconductor pillar 101 away from the bit line 108. The number of capacitor structures 109 is multiple, and each capacitor structure 109 corresponds to a semiconductor pillar 101.

[0101] In the semiconductor structure provided by the above embodiments, a body region control line 102 is disposed on the first sidewalls of two semiconductor pillars 101 close to each other. The body region control line 102 can serve as a common "back gate" for the two semiconductor pillars 101. When a fixed voltage is applied to the body region control line 102, discharge channels can be respectively formed on the two semiconductor pillars 101, and then the accumulated charges can be discharged, thereby improving the floating body effect. The body region control line 102 is partially opposite to the word line 103 in the first direction X. This not only enables the body region control line 102 to play a partial shielding role between two opposite word lines 103, weakening the coupling effect between the two word lines 103, but also can prevent the body region control line 102 from being completely opposite to the word line 103, so that the coupling effect between the body region control line 102 and the word line 103 will not be too large, avoiding the problem of an increase in the parasitic capacitance between the body region control line and the word line.

[0102] Correspondingly, an embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure. The method for manufacturing the semiconductor structure can be used to manufacture the semiconductor structure provided by the above embodiments. Hereinafter, a semiconductor structure provided by an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0103] The method for manufacturing the semiconductor structure includes:

[0104] Referring to Figures 9 to 13 , a plurality of active groups arranged in an array are formed. Each active group includes two semiconductor pillars 101 spaced apart along the first direction X.

[0105] In some embodiments, the plurality of active groups are arranged in an array along the first direction X and the second direction Y. Among them, each row of active groups is spaced apart along the first direction X, and each column of active groups is spaced apart along the second direction Y. The first direction X intersects the second direction Y.

[0106] In some embodiments, the active groups arranged in an array are formed on a substrate 100.

[0107] In one example, the semiconductor pillar 101 can extend in a direction perpendicular to the substrate 100, and both the first direction X and the second direction Y are parallel to the substrate 100. That is, the plurality of active groups are arranged in an array along a direction parallel to the substrate 100 to form a vertical channel array transistor.

[0108] In another example, the semiconductor pillar 101 can also extend in a direction parallel to the substrate 100, the first direction X is parallel to the substrate 100, and the second direction Y is perpendicular to the substrate 100. For example, each row of active groups is spaced apart along a direction parallel to the substrate 100, and each column of active groups is vertically stacked along a direction perpendicular to the substrate 100.

[0109] It should be noted that in the present disclosure, the concepts of "row" and "column" can be interchanged.

[0110] The formation method of the active group will be described below for the above two different semiconductor structures.

[0111] Figure 9 It is a schematic three-dimensional structure diagram corresponding to the step of forming a semiconductor column in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure.

[0112] Refer to Figure 9 , the semiconductor column 101 extends in a direction perpendicular to the substrate 100, and both the first direction X and the second direction Y are parallel to the substrate 100. The method for forming a plurality of active groups arranged in an array includes:

[0113] First, a substrate is provided. In some embodiments, the material of the substrate may be a semiconductor material. In some embodiments, the material of the substrate may be silicon. In some embodiments, the substrate may also be germanium, germanium-silicon, or silicon-on-insulator.

[0114] After that, the surface of the substrate is patterned to define the positions of the semiconductor columns. In some embodiments, any one of the SADP (Self-aligned Double Patterning) process or the SAQP (Self-Aligned Quadruple Patterning) process may be used to pattern the surface of the substrate.

[0115] For example, a patterned hard mask layer (not shown) may be first formed on the substrate, and then the substrate is etched based on the patterned hard mask layer to etch a part of the thickness of the substrate to form an active group array arranged in an array, and the remaining substrate serves as the substrate 100. Each active group includes discrete semiconductor columns 101. The two semiconductor columns 101 in the active group are separated by a first isolation groove 21. The two adjacent active groups along the first direction X are separated by a second isolation groove 22.

[0116] The depth of the first isolation groove 21 is less than the depth of the second isolation groove 22, and the width dimension of the first isolation groove 21 along the first direction X is less than the width dimension of the second isolation groove 22 along the first direction X.

[0117] Figure 10 It is a schematic top view structure diagram corresponding to the steps of forming a semiconductor layer and a sacrificial layer in another method for preparing a semiconductor structure provided by an embodiment of the present disclosure; Figure 11 For Figure 10 the cross-sectional structure diagram in the aa' direction of Figure 12 It is a schematic top view structure diagram corresponding to the steps of forming the first isolation groove and the second isolation groove in another method for preparing a semiconductor structure provided by an embodiment of the present disclosure;Figure 13 is Figure 12 a schematic cross-sectional structure diagram in the bb' direction in

[0118] Referring to Figures 10 to 13 , the semiconductor column 101 extends in a direction parallel to the substrate 100, and the first direction X is parallel to the substrate 100, and the second direction Y is perpendicular to the substrate 100. A method for forming a plurality of active groups arranged in an array includes:

[0119] Referring to Figure 10 and Figure 11 , providing a substrate 100. In some embodiments, the material of the substrate 100 may be a semiconductor material. In some embodiments, the material of the substrate 100 may be silicon. In some embodiments, the substrate 100 may also be germanium, silicon germanium, or silicon on insulator.

[0120] Forming a plurality of sacrificial layers 31 and a plurality of semiconductor layers 32 stacked alternately in a direction perpendicular to the substrate 100 on the substrate 100, that is, the plurality of sacrificial layers 31 and the plurality of semiconductor layers 32 are stacked alternately in the second direction Y, and each semiconductor layer 32 is used to form a semiconductor column 101. Among them, the material of the sacrificial layer 31 may be silicon germanide, and the material of the semiconductor layer 32 may be a semiconductor material, such as silicon, germanium, silicon germanium, or silicon on insulator.

[0121] Referring to Figure 12 and Figure 13 , performing a patterning process on the alternately stacked plurality of sacrificial layers 31 and the plurality of semiconductor layers 32 to define the positions of the semiconductor columns 101. In some embodiments, the patterning process may include any one of the SADP process or the SAQP process.

[0122] For example, a patterned hard mask layer (not shown) may be first formed on the alternately stacked plurality of sacrificial layers 31 and the plurality of semiconductor layers 32, and then the plurality of sacrificial layers 31 and the plurality of semiconductor layers 32 are etched based on the patterned hard mask layer to form first isolation grooves 21 and second isolation grooves 22 arranged alternately in the first direction X. In the first direction X, the width of the first isolation groove 21 is smaller than the width of the second isolation groove 22. For example, each semiconductor layer 32 and each sacrificial layer 31 are etched until the substrate 100 is exposed, forming a stacked structure separated from each other in the first direction X. The semiconductor layers 32 in each stacked structure form semiconductor columns 101, thereby forming a plurality of semiconductor columns 101 stacked in the second direction Y. Among them, adjacent stacked structures are separated by the first isolation grooves 21 and the second isolation grooves 22, and the semiconductor columns 101 in adjacent stacked structures separated by the first isolation grooves 21 constitute an active group, and the semiconductor columns 101 in adjacent stacked structures separated by the second isolation grooves 22 belong to different active groups respectively.

[0123] Figure 14 A schematic three-dimensional structure diagram corresponding to the step of forming a first isolation structure in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure; Figure 15 A schematic three-dimensional structure diagram corresponding to the step of etching the first isolation structure in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure; Figure 16 A schematic three-dimensional structure diagram corresponding to the step of forming a first gate dielectric layer and a second gate dielectric layer in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure; Figure 17 A schematic top-view structure diagram corresponding to the step of forming a first isolation structure in another method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure; Figure 18 is Figure 17 a schematic cross-sectional structure diagram in the bb' direction; Figure 19 A schematic top-view structure diagram corresponding to the step of etching the first isolation structure in another method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure; Figure 20 A schematic top-view structure diagram corresponding to the step of forming a first gate dielectric layer and a second gate dielectric layer in another method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure; Figure 21 is Figure 20 a schematic cross-sectional structure diagram in the bb' direction.

[0124] Referring to Figures 14 to 21 , in some embodiments, the semiconductor pillar 101 includes a first source / drain region 111, a second source / drain region 112, a channel region 113 and a body region 114 located between the first source / drain region 111 and the second source / drain region 112. The two semiconductor pillars 101 of the active group are separated by a first isolation groove 21. The method for manufacturing the semiconductor structure further includes: forming a first gate dielectric layer 104 on the sidewall of the semiconductor pillar 101 facing the first isolation groove 21, and the first gate dielectric layer 104 covers the body region 114; forming a second gate dielectric layer 105 on the sidewall of the semiconductor pillar 101 away from the first isolation groove 21, and the second gate dielectric layer 105 covers the channel region 113.

[0125] In some embodiments, the doping ion type of the first source / drain region 111 is the same as that of the second source / drain region 112. For example, it can be an N-type doping ion. The doping ion type of the channel region 113 is the same as that of the body region 114. For example, it can be a P-type doping ion, and the formed transistor has an N-type conduction type.

[0126] In some embodiments, after the semiconductor pillar 101 is etched and formed, different parts of the semiconductor pillar 101 may be doped to respectively form a first source / drain region 111, a second source / drain region 112, and a channel region 113 and a body region 114 located between the first source / drain region 111 and the second source / drain region 112. In some embodiments, the doping process may be an ion implantation process.

[0127] In some embodiments, the first isolation trench 21 exposes the body region 114 and the second source / drain region 112 of the semiconductor pillar 101, and the second isolation layer exposes the channel region 114 and the second source / drain region 112 of the semiconductor pillar 101.

[0128] In some embodiments, the material of the first gate dielectric layer 104 may be silicon oxide, and the material of the second gate dielectric layer 105 may be silicon oxide.

[0129] The formation methods of the first gate dielectric layer 104 and the second gate dielectric layer 105 will be described below for the semiconductor structures in the above two different embodiments.

[0130] Refer to Figures 14 to 16 , the semiconductor pillar 101 extends in a direction perpendicular to the substrate 100, and both the first direction X and the second direction Y are parallel to the substrate 100. The methods for forming the first gate dielectric layer 104 and the second gate dielectric layer 105 include:

[0131] As Figure 14 shown, after the active group is formed, a first isolation structure 11 that fills the first isolation trench 21 and the second isolation trench 22 is formed. In some embodiments, the material of the first isolation structure 11 may be silicon oxide, silicon nitride, etc. Since the depth of the first isolation trench 21 is less than the depth of the second isolation trench 22, the depth of the first isolation structure 11 located in the first isolation trench 21 is less than the depth of the first isolation structure 11 located in the second isolation trench 22.

[0132] Refer to Figure 15 , the first isolation structure 11 in the first isolation trench 21 and the second isolation trench 22 is etched back to remove the first isolation structure 11 in the first isolation trench 21. Since the depth of the first isolation structure 11 located in the first isolation trench 21 is less than the depth of the first isolation structure 11 located in the second isolation trench 22, a part of the first isolation structure 11 still remains in the second isolation trench 22. Also, since the width of the first isolation trench 21 is less than the width of the second isolation trench 22, the etching load effect of the second isolation trench 22 is less than the etching load effect of the first isolation trench 21. Therefore, the etching rate of the first isolation structure 11 in the second isolation trench 22 is greater than the etching rate of the first isolation structure 11 in the first isolation trench 21, such that the top surface of the remaining first isolation structure 11 in the second isolation trench 22 is lower than the bottom surface of the first isolation trench 21.

[0133] In some embodiments, in order to make the top surface of the remaining first isolation structure 11 in the second isolation groove 22 flush with the bottom surface of the first isolation groove 21, so that the bottom surfaces of the subsequent formed word lines 103 and body region control lines 102 are flush or approximately flush, referring to Figure 16 , a filling layer 23 can be formed on the top surface of the remaining first isolation structure 11 in the second isolation groove 22, and the top surface of the filling layer 23 is flush with the bottom surface of the first isolation groove 21. In some embodiments, the filling layer 23 can be formed by a deposition process, and the material of the filling layer 23 can be the same as that of the first isolation structure 11, for example, both are silicon oxide or silicon nitride, etc.

[0134] Referring to Figure 16 , a first gate dielectric layer 104 can be formed on the sidewall of the first isolation groove 21 by a deposition process, and a second gate dielectric layer 105 can be formed on the sidewall of the second isolation groove 22. The first gate dielectric layer 104 located on the sidewall of the first isolation groove 21 covers the first sidewalls of the two semiconductor pillars 101 close to each other, and the first gate dielectric layer 104 located on the sidewall of the second isolation groove 22 covers the second sidewalls of the two semiconductor pillars 101 far from each other. And the first gate dielectric layer 104 and the second gate dielectric layer 105 are also located on the top surface of the semiconductor pillar 101. The deposition process can include: a chemical vapor deposition (CVD) process, plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition processes.

[0135] Referring to Figures 17 to 21 , the semiconductor pillar 101 extends in a direction parallel to the substrate 100, and the first direction X is parallel to the substrate 100, and the second direction Y is perpendicular to the substrate 100. The method for forming the first gate dielectric layer 104 and the second gate dielectric layer 105 includes:

[0136] As Figure 17 and Figure 18 shown, after forming the active group, a first isolation structure 11 that fills the first isolation groove 21 and the second isolation groove 22 is formed. Among them, the first isolation groove 21 can include a first side 1 and a second side 2 opposite to each other along the extending direction of the semiconductor pillar 101. The first side 1 is close to the first source / drain region 111, and the second side 2 is close to the second source / drain region 112. The second isolation groove 22 can include a third side 3 and a fourth side 4 opposite to each other along the extending direction of the semiconductor pillar 101. The third side 3 is close to the first source / drain region 111, and the fourth side 4 is close to the second source / drain region 112. Among them, the first side 1 is closer to the plane where the second side 2 is located than the third side 3. That is to say, in the extending direction of the semiconductor pillar 101, the width of the first isolation structure 11 located in the first isolation groove 21 is smaller than the width of the first isolation structure 11 located in the second isolation groove 22.

[0137] AsFigure 19 As shown, the first isolation structure 11 in the first isolation groove 21 and the second isolation groove 22 is etched to remove the first isolation structure 11 in the first isolation groove 21 and part of the first isolation structure 11 in contact with the fourth side 4 in the second isolation groove 22 until the surface of the substrate 100 is exposed. The remaining part of the first isolation structure 11 is located on the third side 3 of the second isolation groove 22. The surface of the remaining part of the first isolation structure 11 in the second isolation groove 22 away from the third side 3 is flush or substantially flush with the first side 1 of the first isolation groove 21. In this way, it can be ensured that the body region control line 102 formed in the first isolation groove 21 and the word line 103 formed in the second isolation groove 22 are flush or substantially flush.

[0138] Reference Figure 20 and Figure 21 , a first gate dielectric layer 104 is formed on the opposite sidewalls of the first isolation groove 21 along the first direction X by a deposition process, and a second gate dielectric layer 105 is formed on the opposite sidewalls of the second isolation groove 22 along the first direction X. The first gate dielectric layer 104 on the sidewalls of the first isolation groove 21 covers the first sidewalls of the two semiconductor pillars 101 close to each other, and the first gate dielectric layer 104 on the sidewalls of the second isolation groove 22 covers the second sidewalls of the two semiconductor pillars 101 away from each other. The deposition process may include: a chemical vapor deposition (CVD) process, plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition processes.

[0139] Reference Figures 22 to 35 , after the first gate dielectric layer 104 and the second gate dielectric layer 105 are formed, a body region control line 102 and two word lines 103 corresponding to an active group and arranged at intervals along the first direction X are formed. The body region control line 102 is located on the first sidewalls of the two semiconductor pillars 101 close to each other, and the two word lines 103 are respectively located on the second sidewalls of the two semiconductor pillars 101 facing away from the body region control line 102. The body region control line 102 and the word lines 103 are partially opposite in the first direction X.

[0140] When a fixed voltage is applied to the body region control line 102, discharge channels can be respectively formed on the two semiconductor pillars 101, and then the accumulated charges can be discharged to improve the floating body effect. Setting the body region control line 102 and the word lines 103 to be partially opposite in the first direction X not only enables the body region control line 102 to play a partial shielding role between the two opposite word lines 103, weakening the coupling effect between the two word lines 103, but also can prevent the problem of increased parasitic capacitance between the body region control line 102 and the word lines 103 due to the complete alignment of the body region control line 102 and the word lines 103.

[0141] Figure 22Schematic three-dimensional structure diagram corresponding to the step of forming the body region control line in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure; Figure 23 Top view structure diagram corresponding to the step of forming the initial body region control line in another method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure; Figure 24 is Figure 23 Cross-sectional structure diagram in the bb' direction in Figure 25 Top view structure diagram corresponding to the step of forming the body region control line in another method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure; Figure 26 is Figure 25 Cross-sectional structure diagram in the cc' direction in

[0142] Referring to Figures 22 to 26 , in some embodiments, the method for forming the body region control line 102 includes:

[0143] First, an initial body region control line filling the first isolation groove 21 is formed, and the initial body region control line covers the surface of the first gate dielectric layer 104.

[0144] Next, a part of the initial body region control line in the first isolation groove 21 is etched so that the remaining initial body region control line is aligned with a part of the main body region 114, and the remaining initial body region control line 102 serves as the body region control line 102.

[0145] Hereinafter, for the above two different semiconductor structures, the method for forming the body region control line 102 will be described.

[0146] Referring to Figure 22 , the semiconductor pillar 101 extends in a direction perpendicular to the substrate 100, and both the first direction X and the second direction Y are parallel to the substrate 100. The method for forming the body region control line 102 includes:

[0147] First, an initial body region control line filling the first isolation groove 21 is formed by a deposition process. Before depositing the initial body region control line, a sacrificial structure (not shown) filling the second isolation groove 22 can be formed in the second isolation groove 22. In this way, it can be avoided that the initial body region control line is formed in the second isolation groove 22. The sacrificial structure can be removed in subsequent steps.

[0148] Referring to Figure 22 , after the initial body region control line is formed, the initial body region control line is etched back to remove a part of the initial body region control line in the first isolation groove 21 so that the remaining initial body region control line at the bottom of the first isolation groove 21 is aligned with a part of the main body region 114 in the semiconductor pillar 101 close to the first source / drain region 111, and the remaining initial body region control line serves as the body region control line 102.

[0149] Referring to Figures 23 to 26, the semiconductor pillar 101 extends in a direction parallel to the substrate 100, the first direction X is parallel to the substrate 100, and the second direction Y is perpendicular to the substrate 100. The method for forming the body region control line 102 includes:

[0150] Reference Figures 23 to 24 , an initial body region control line 33 filling the first isolation groove 21 is formed by a deposition process. The body region control line 102 is aligned with the main body region 114 and the second source / drain region 112. Before depositing the initial body region control line 33, a sacrificial structure filling the second isolation groove 22 can be formed in the second isolation groove 22. In this way, it can be avoided that the initial body region control line 33 is formed in the second isolation groove 22. The sacrificial structure can be removed in subsequent steps.

[0151] After that, a first mask layer is formed on the top surface of the initial body region control line 33 along the second direction Y. The first mask layer has a first opening, and the first opening exposes the top surface of the initial body region control line 33 aligned with the first source / drain region 111 and a part of the main body region 114.

[0152] Reference Figures 25 to 26 , the initial body region control line 33 is etched along the first opening, and the remaining initial body region control line 33 is aligned with a part of the main body region 114 close to the first source / drain region 111. The remaining initial body region control line 33 serves as the body region control line 102.

[0153] After forming the body region control line 102, the first mask layer is removed.

[0154] Figure 27 It is a schematic three-dimensional structure diagram corresponding to the step of forming the air gap structure in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure; Figure 28 It is a schematic top view structure diagram corresponding to the step of forming an initial isolation layer in another method for preparing a semiconductor structure provided by an embodiment of the present disclosure; Figure 29 It is Figure 28 The cross-sectional structure diagram in the bb' direction in Figure 30 It is a schematic top view structure diagram corresponding to the step of forming the air gap structure in another method for preparing a semiconductor structure provided by an embodiment of the present disclosure.

[0155] Reference Figures 27 to 30 , in some embodiments, after forming the body region control line 102, it further includes: forming an air gap structure 106. The air gap structure 106 is located between two semiconductor pillars 101 of the active group, and the air gap structure 106 is also opposite to a part of the word line 103 in the first direction X.

[0156] The air gap structure 106 contains air, and air has a small dielectric constant, which can weaken the coupling effect between adjacent word lines 103.

[0157] In some embodiments, the whole formed by the body region control line 102 and the air gap structure 106 is directly opposite to the word line 103, which can weaken the coupling effect between adjacent word lines 103 to the greatest extent. At the same time, the body region control line 102 can also improve the floating body effect and the performance of the semiconductor structure.

[0158] In some embodiments, the method of forming the air gap structure 106 includes: forming an isolation layer 107 in the first isolation groove 21. The isolation layer 107 and the body region control line 102 are arranged at intervals along the extending direction of the semiconductor column 101. The gap between the isolation layer 107 and the body region control line 102 constitutes the air gap structure 106.

[0159] The method of forming the air gap structure 106 will be described below for the above two different semiconductor structures.

[0160] Reference Figure 27 , the semiconductor column 101 extends in a direction perpendicular to the substrate 100, and both the first direction X and the second direction Y are parallel to the substrate 100. The method of forming the air gap structure 106 includes:

[0161] Reference Figure 27 , perform a deposition process in the first isolation groove 21 to form an isolation layer 107 that seals the opening of the first isolation groove 21. The formed isolation layer 107 is located above the body region control line 102 and forms a spatial gap with the body region control line 102 to form the air gap structure 106. It can be understood that, by using the relatively large aspect ratio of the first isolation groove 21 and controlling the parameters of the deposition process at the same time, the step coverage ability of the isolation layer 107 material can be reduced, so that the isolation layer 107 is formed above the body region control line 102 without contacting the top of the body region control line 102, thereby forming the air gap structure 106.

[0162] It should be noted that, in some embodiments, before performing the deposition process in the first isolation groove 21, the sacrificial structure located in the second isolation groove 22 can be retained to prevent the formed isolation layer 107 from also being formed in the second isolation groove 22. After forming the air gap structure 106, the sacrificial structure is removed.

[0163] Reference Figures 28 to 30 , the semiconductor column 101 extends in a direction parallel to the substrate 100, the first direction X is parallel to the substrate 100, and the second direction Y is perpendicular to the substrate 100. The method of forming the air gap structure 106 includes:

[0164] Reference Figures 28 to 29 , form an initial isolation layer 34 filled in the remaining part of the isolation groove. The initial isolation layer 34 contacts the surface of the first side 1 of the body region control line 102 far from the first isolation groove 21 and contacts the second side 2 of the first isolation groove 21.

[0165] It should be noted that, in some embodiments, before the deposition process is performed in the first isolation groove 21, the sacrificial structure located in the second isolation groove 22 can be retained to prevent the initially formed isolation layer 34 from also being formed in the second isolation groove 22. After the air gap structure 106 is formed, the sacrificial structure is removed.

[0166] After the initial isolation layer 34 is formed, a second mask layer is formed on the top surface of the first isolation groove 21. The second mask layer has a second opening that exposes a part of the initial isolation layer 34 and is used to define the position of the air gap structure 106.

[0167] Reference Figure 30 , the initial isolation layer 34 is etched along the second opening until the substrate 100 is exposed, and the part of the initial isolation layer 34 in contact with the body region control line 102 is removed. The remaining part of the initial isolation layer 34 forms the isolation layer 107, and there is a gap between the isolation layer 107 and the body region control line 102.

[0168] In some embodiments, after the isolation layer 107 is formed, a sealing layer (not shown) is formed to seal the top opening of the first isolation groove, so as to form the air gap structure 106 between the body region control line 102 and the isolation layer 107. In some embodiments, the material of the sealing layer can be silicon oxide or the like.

[0169] After the air gap structure 106 is formed, the second mask layer is removed.

[0170] Figure 31 Schematic three-dimensional structure diagram corresponding to the step of forming the initial word line layer in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure; Figure 32 Schematic three-dimensional structure diagram corresponding to the step of forming the second isolation structure in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure; Figure 33 Schematic three-dimensional structure diagram corresponding to the step of forming the word line in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure; Figure 34 Schematic top view structure diagram corresponding to the step of forming the second isolation structure in another method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure; Figure 35 Schematic top view structure diagram corresponding to the step of forming the word line in another method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.

[0171] Reference Figures 31 to 35 , in some embodiments, after the air gap structure 106 is formed, the word line 103 is formed. The method for forming the word line 103 includes:

[0172] First, an initial word line layer 35 is formed covering the surface of the second gate dielectric layer 105.

[0173] After that, an etching process is performed on a part of the initial word line layer 35 so that the remaining part of the initial word line layer 35 is directly opposite to the channel region 113, and the remaining part of the initial word line layer 35 serves as the word line 103.

[0174] Hereinafter, a method for forming the word line 103 will be described for the above two different semiconductor structures.

[0175] Refer to Figures 31 to 33 , the semiconductor pillar 101 extends in a direction perpendicular to the substrate 100, and both the first direction X and the second direction Y are parallel to the substrate 100. The method for forming the word line 103 includes:

[0176] Refer to Figure 31 , an initial word line layer 35 that conformally covers the surface of the second gate dielectric layer 105 and the top surface of the filling layer 23 is formed in the second isolation groove 22. The initial word line layer 35 also extends above the opening of the second isolation groove 22 and covers the first gate dielectric layer 104 on the top surface of the semiconductor pillar 101, the second gate dielectric layer 105, and the top surface of the isolation layer 107 that seals the opening of the first isolation groove 21.

[0177] Refer to Figure 32 , the initial word line layer 35 above the opening of the second isolation groove 22 and the initial word line layer 35 on the top surface of the filling layer 23 are removed so that the remaining initial word line layer 35 is flush with the opening of the second isolation groove 22, and the remaining initial word line layer 35 only covers the surface of the second gate dielectric layer 105 in the second isolation groove 22. After that, a second isolation structure 12 is formed in the second isolation groove 22. The top surface of the second isolation structure 12 is lower than the opening of the second isolation groove 22, and the second isolation structure 12 is directly opposite to the channel region 113 of the semiconductor pillar 101. The second isolation structure 12 is located between the opposite initial word line layers 35 in the second isolation groove 22 and can be used to isolate the opposite initial word line layers 35. The material of the second isolation structure 12 can be silicon oxide.

[0178] Refer to Figure 33 , an etch-back process is performed on the initial word line layer 35 to remove the initial word line layer 35 above the top surface of the second isolation structure 12 so that the remaining part of the initial word line layer 35 is directly opposite to the channel region 113, and the remaining part of the initial word line layer 35 serves as the word line 103.

[0179] Refer to Figures 34 to 35 , the semiconductor pillar 101 extends in a direction parallel to the substrate 100, the first direction X is parallel to the substrate 100, and the second direction Y is perpendicular to the substrate 100. The method for forming the word line 103 includes:

[0180] Refer to Figure 34, a second isolation structure 12 with a "T"-shaped cross-section is formed in the second isolation groove 22. The second isolation structure 12 is used to define a word line groove 24 in the second isolation groove 22. The word line groove 24 is aligned with the channel region 113 and is used to define the shape of the word line. Subsequently, the word line formed in the word line groove 24 is aligned with the channel region 113. The material of the second isolation structure 12 can be silicon oxide.

[0181] In some embodiments, the method of forming the second isolation structure 12 may include: First, form an initial second isolation structure that fills the second isolation groove 22. Then, perform a patterning process on the initial second isolation structure to etch part of the initial second isolation structure to form a word line groove 24 in the second isolation groove, and the remaining part of the initial second isolation structure constitutes the second isolation structure 12.

[0182] Reference Figure 35 , form a word line 103 that fills the word line groove 24 (reference Figure 34 ). The second isolation structure 12 is located between the opposite word lines 103 in the second isolation groove 22 and can be used to isolate the opposite word lines 103.

[0183] Reference Figure 4 And Figure 5 , in some embodiments, the method of manufacturing the semiconductor structure further includes: forming bit lines 108, and the bit lines 108 are coupled to the first source / drain regions 111.

[0184] In some embodiments, the number of bit lines 108 is multiple. The multiple bit lines 108 are arranged at intervals along the second direction Y, and each bit line 108 extends along the first direction X. Each bit line 108 is coupled to the first source / drain region 111 of a semiconductor pillar 101 in a row of active groups arranged at intervals along the first direction X.

[0185] In some embodiments, the bit lines 108 may be formed after the semiconductor pillars 101 are formed.

[0186] In some embodiments, for a semiconductor structure in which the semiconductor pillar 101 extends in a direction perpendicular to the substrate 100, and the first direction X and the second direction Y are both parallel to the substrate 100, the method of forming the bit line 108 may be as follows: The substrate includes opposite first and second surfaces. The semiconductor pillar 101 is located on the first surface. The substrate 100 is thinned from the second surface of the substrate 100. Then, a doping process is performed on the substrate 100 from the bottoms of the first isolation groove 21 and the second isolation groove 22 to convert a portion of the substrate 100 opposite to the semiconductor pillar 101 into a conductive bit line 108. In other embodiments, the substrate 100 may be doped by an ion implantation process. The implantation depth and angle of the ion implantation process can be controlled to convert the substrate 100 opposite to the semiconductor pillar 101 into the bit line 108, such that the formed bit line 108 extends along the first direction X.

[0187] In some embodiments, for a semiconductor structure in which the semiconductor pillar 101 extends in a direction parallel to the substrate 100, the first direction X is parallel to the substrate 100, and the second direction Y is perpendicular to the substrate 100, the method of forming the bit line 108 may be as follows: A doping process is performed on the semiconductor pillar 101 on the side of the first source / drain region 111 away from the channel region 113 from the first side 1 of the first isolation groove 21 and the third side 3 of the second isolation groove 22 to convert this portion into a conductive bit line 108.

[0188] Those of ordinary skill in the art can understand that the above-described embodiments are specific examples for implementing the present disclosure. In practical applications, various changes may be made to them in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make their respective changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure should be determined by the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A plurality of active groups arranged in an array, each active group including two semiconductor columns spaced apart along a first direction; A body region control line and two word lines corresponding to one of the active groups and spaced apart along the first direction, the body region control line being located on the first side walls of the two semiconductor columns close to each other, and the two word lines being respectively located on the second side walls of the two semiconductor columns facing away from the body region control line, and the body region control line and the word lines being partially opposite to each other along the first direction.

2. The semiconductor structure according to claim 1, wherein The semiconductor column includes a first source / drain region, a second source / drain region, and a channel region and a body region located between the first source / drain region and the second source / drain region, the channel region and the body region being arranged along the first direction, wherein the word line is opposite to the channel region, and the body region control line is opposite to a part of the body region arranged close to the first source / drain region.

3. The semiconductor structure according to claim 2, wherein, The body region control line has a first surface and a second surface opposite to each other, and the word line has a third surface and a fourth surface opposite to each other. The direction in which the first surface points to the second surface and the direction in which the third surface points to the fourth surface are both the same as the direction in which the first source / drain region points to the second source / drain region. Wherein, the third surface is flush with the first surface, or the positive projection of the third surface in the first direction is located on the surface of the body region control line.

4. The semiconductor structure according to claim 3, wherein, The ratio of the dimension of the body region control line in the extending direction of the semiconductor column to the dimension of the word line in the extending direction of the semiconductor column is 0.1 - 0.

5.

5. The semiconductor structure according to any one of claims 2-4, wherein, Further comprising: A bit line, the bit line being coupled to the first source / drain region.

6. The semiconductor structure according to any one of claims 2-5, characterized in that, Further comprising: A capacitive structure, the capacitive structure being coupled to the second source / drain region.

7. The semiconductor structure according to any one of claims 2-6, characterized in that, The semiconductor structure further includes: A first gate dielectric layer, the first gate dielectric layer being located between the semiconductor column and the body region control line and covering the body region; A second gate dielectric layer, the second gate dielectric layer being located between the semiconductor column and the word line and covering the channel region. In the first direction, the ratio of the thickness of the first gate dielectric layer to the thickness of the second gate dielectric layer is 0.5 - 1.

5.

8. The semiconductor structure according to any one of claims 1 to 7, characterized in that, The plurality of active groups are arranged in an array along the first direction and a second direction, the body region control line and the word lines extend along the second direction, and one body region control line and two word lines are correspondingly arranged for any column of active groups arranged along the second direction, and the first direction intersects with the second direction.

9. The semiconductor structure according to claim 8, wherein Further comprising: A substrate, the plurality of active groups being located on the substrate, wherein the semiconductor column extends in a direction perpendicular to the substrate, and both the first direction and the second direction are parallel to the substrate.

10. The semiconductor structure according to claim 8, characterized in that, Further comprising: A substrate, the plurality of active groups being located on the substrate, wherein the semiconductor column extends in a direction parallel to the substrate, the first direction is parallel to the substrate, and the second direction is perpendicular to the substrate.

11. The semiconductor structure according to any one of claims 1-10, characterized in that, The semiconductor structure further includes: An air gap structure, the air gap structure being located between the two semiconductor columns of the active group, and the air gap structure is also partially opposite to the word line in the first direction.

12. A method for preparing a semiconductor structure, characterized in that, Comprising: Form a plurality of active groups arranged in an array, where each active group includes two semiconductor pillars spaced apart in a first direction; Form a body region control line and two word lines corresponding to one of the active groups and spaced apart in the first direction. The body region control line is located on the first side walls of the two semiconductor pillars close to each other, and the two word lines are respectively located on the second side walls of the two semiconductor pillars facing away from the body region control line. The body region control line and the word lines are partially opposite in the first direction.

13. The method for manufacturing a semiconductor structure according to claim 12, characterized in that, The semiconductor pillar includes a first source / drain region, a second source / drain region, a channel region and a body region located between the first source / drain region and the second source / drain region. The two semiconductor pillars of the active group are separated by a first isolation groove. Before forming the body region control line and the word lines, it further includes: Form a first gate dielectric layer on the side wall of the semiconductor pillar facing the first isolation groove, and the first gate dielectric layer covers the body region; Form a second gate dielectric layer on the side wall of the semiconductor pillar away from the first isolation groove, and the second gate dielectric layer covers the channel region.

14. The method for manufacturing a semiconductor structure according to claim 13, wherein, The method for forming the body region control line includes: Form an initial body region control line that fills the first isolation groove, and the initial body region control line covers the surface of the first gate dielectric layer; Etch a part of the initial body region control line in the first isolation groove so that the remaining initial body region control line is aligned with a part of the body region, and the remaining initial body region control line serves as the body region control line.

15. The method for preparing a semiconductor structure according to claim 14, characterized in that, After forming the body region control line, it further includes: forming an air gap structure, the air gap structure is located between the two semiconductor pillars of the active group, and the air gap structure is also opposite to a part of the word lines in the first direction.

16. The method for manufacturing a semiconductor structure according to claim 15, characterized in that, The method for forming the air gap structure includes: forming an isolation layer in the first isolation groove, the isolation layer is spaced apart from the body region control line along the extending direction of the semiconductor pillar, and the gap between the isolation layer and the body region control line forms the air gap structure.

17. The method for preparing a semiconductor structure according to claim 15 or 16, characterized in that, After forming the air gap structure, form the word lines. The method for forming the word lines includes: Form an initial word line layer covering the surface of the second gate dielectric layer; Perform an etching process on a part of the initial word line layer so that the remaining part of the initial word line layer is aligned with the channel region, and the remaining part of the initial word line layer serves as the word line.

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