Vertical fin field effect transistor and memory device

Abstract

Embodiments of the present disclosure provide a memory device and a vertical fin field effect transistor. The memory device includes a memory cell, wherein the memory cell includes a bit line, a word line over the bit line, a plurality of semiconductor fins on the bit line and embedded in the word line, a body line physically contacting one sidewall of each semiconductor fin, and an insulating layer covering the body line. The body line is grounded to direct accumulated charge out of the semiconductor fins, thereby reducing floating body effects in the memory cell.

Description

Technical Field

[0001] This disclosure relates to memory devices, and more particularly to memory devices including vertical fin field-effect transistors. Background Technology

[0002] A gate-around transistor (SGT) is an option for dynamic random access memory (DRAM) designs. Typically, a SGT consists of a columnar channel and a gate surrounding the channel, with the source / drain regions located at the top and bottom of the columnar structure. However, charge can accumulate in the columnar structure, causing a floating body effect in the SGT. Summary of the Invention

[0003] According to some embodiments of this disclosure, a vertical-fin field-effect transistor includes bit lines, word lines located above the bit lines, and semiconductor fins located on the bit lines. The semiconductor fins include a channel region surrounded by the word lines, a top source / drain region located on the top surface of the channel region, and a bottom source / drain region located below the bottom surface of the channel region. The vertical-fin field-effect transistor also includes a body line physically contacting one of the sidewalls of the channel region and an insulating layer covering the body line, wherein the body line is grounded.

[0004] In some implementations, the semiconductor fins and the body wires are formed of the same material.

[0005] In some implementations, the semiconductor fins and the body wires are integrally formed.

[0006] In some implementations, the conductivity of the body wire is higher than that of the semiconductor fin.

[0007] In some implementations, the top surface of the main body line is lower than or flush with the top surface of the channel region.

[0008] In some implementations, the bottom surface of the main body line is flush with the bottom surface of the channel area.

[0009] In some implementations, the character lines physically contact the sidewalls of the channel area.

[0010] In some implementations, the sidewall of the main line extends beyond one of the sidewalls of the channel region.

[0011] In some implementations, the sidewall of the main line is flush with the other sidewall of the channel area.

[0012] In some implementations, the insulating layer separates the body line and the character line.

[0013] According to some embodiments of this disclosure, a memory device includes a first memory cell. The first memory cell includes a first bit line, a first word line located above the first bit line, a plurality of first semiconductor fins located on the first bit line and embedded in the first word line, a first body line physically contacting one of the sidewalls of each of the first semiconductor fins, and an insulating layer covering the first body line.

[0014] In some embodiments, the first memory cell further includes a memory node contact covering the top surface of the first semiconductor fin and a capacitor located on the memory node contact, wherein the bottom surface of the first semiconductor fin contacts the first memory line.

[0015] In some implementations, the first main line is separated from the storage node contact.

[0016] In some embodiments, the storage node contact includes a polysilicon liner that contacts the top surface of the first semiconductor fin, and a metal layer located between the polysilicon liner and the capacitor.

[0017] In some implementations, the first character line and the first semiconductor fin extend along a first direction, and the first character line and the first body line extend along a second direction different from the first direction.

[0018] In some embodiments, the memory device further includes a second memory cell. The second memory cell includes a second bit line adjacent to the first bit line, a first word line above the second bit line, a plurality of second semiconductor fins located on the second bit line and embedded in the first word line, and a first body line physically contacting one of the sidewalls of each of the second semiconductor fins, wherein the first body line connects the first semiconductor fin and the second semiconductor fin.

[0019] In some embodiments, the memory device further includes a second memory cell. The second memory cell includes a first word line, a second word line adjacent to and above the first word line, a plurality of second semiconductor fins located on the first word line and embedded in the second word line, and a second body line physically contacting one of the sidewalls of each of the second semiconductor fins.

[0020] In some embodiments, the memory device further includes a second memory cell, a third memory cell, and a fourth memory cell, wherein the second memory cell includes a plurality of second semiconductor fins located on a second bit line and embedded in a first word line, the third memory cell includes a plurality of third semiconductor fins located on a first bit line and embedded in a second word line, and the fourth memory cell includes a plurality of fourth semiconductor fins located on a second bit line and embedded in a second word line. A first body line connects the first semiconductor fins and the second semiconductor fins. A second body line connects the third semiconductor fins and the fourth semiconductor fins. The first memory cell, the second memory cell, the third memory cell, and the fourth memory cell are arranged in a 2×2 array.

[0021] In some embodiments, the memory device further includes a word line contact connected to a first word line and a body line contact connecting a first body line and a ground point, wherein the word line contact and the body line contact are disposed on opposite sides of the first memory cell.

[0022] In some embodiments, the memory device further includes a word line contact connected to a first word line and a body line contact connecting a first body line and a ground point, wherein the word line contact and the body line contact are disposed on the same side of the first memory cell.

[0023] According to the above embodiments, a memory device includes a memory cell, the memory cell including bit lines, word lines, a plurality of semiconductor fins embedded in the word lines, a main line that physically contacts the sidewalls of the semiconductor fins, and an insulating layer covering the main line, wherein the main line is grounded to reduce the floating body effect in the memory cell. Attached Figure Description

[0024] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial methods, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0025] Figure 1 A three-dimensional schematic diagram of a memory device is shown according to one embodiment of the present disclosure.

[0026] Figure 2 Draw Figure 1 An enlarged top view of the memory device.

[0027] Figure 3 Draw Figure 2 A cross-sectional view of the memory device in the image.

[0028] Figure 4 A cross-sectional view of a memory device is shown according to another embodiment of the present disclosure.

[0029] Figure 5 A cross-sectional view of a memory device is shown according to another embodiment of the present disclosure.

[0030] Figure 6 A cross-sectional view of a memory device is shown according to another embodiment of the present disclosure. Detailed Implementation

[0031] To achieve the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0032] Furthermore, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to facilitate the description of the relationship between one element or feature and another element or feature as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptive symbols used herein may be interpreted accordingly.

[0033] According to some embodiments of this disclosure, a memory device includes a memory cell, wherein the memory cell includes bit lines, word lines, a plurality of semiconductor fins located on the bit lines and embedded in the word lines, a body line physically contacting the sidewalls of the semiconductor fins, and an insulating layer covering the body line. The bit lines, word lines, and semiconductor fins can be used as vertical fin field-effect transistors in the memory cell, wherein the body line is grounded to reduce the floating body effect of the vertical fin field-effect transistors.

[0034] According to one embodiment of this disclosure Figure 1 A three-dimensional schematic diagram of a memory device 100 is shown. The memory device 100 includes a plurality of memory cells 200 arranged in a two-dimensional array. For simplicity, Figure 1The diagram illustrates nine memory cells 200 arranged in a 3×3 array in the memory device 100. However, this is not intended to limit the number of memory cells 200 that the memory device 100 may include. To clearly illustrate the details of the memory cells 200, Figure 2 Draw Figure 1 An enlarged top view of the three memory cells 200 of the memory device 100, and Figure 3 Memory device 100 along Figure 2 The cross-sectional view of line AA′ in the diagram.

[0035] refer to Figures 1 to 3 The memory cell 200 includes a bit line 210, a word line 220 located above the bit line 210, and a plurality of semiconductor fins 230 located on the bit line 210. The bit line 210 extends along the y-axis, while the word line 220 extends along the x-axis. The word line 220 is separated from the bit line 210 along the z-axis. The plurality of semiconductor fins 230 extend along the y-axis and are separated from each other along the x-axis. The semiconductor fins 230 are electrically connected to the bit line 210 and are surrounded by the word line 220. For example, the bottom surface of the semiconductor fin 230 may contact the top surface of the bit line 210, and the sidewalls of the semiconductor fin 230 may be surrounded by the word line 220. Therefore, the bit line 210, the word line 220, and the plurality of semiconductor fins 230 can be used as a plurality of vertical fin field-effect transistors 300 in the memory cell 200.

[0036] Specifically, for each semiconductor fin 230, the middle portion of the semiconductor fin 230 is embedded in the word line 220. Since the word line 220 serves as the gate of the vertical fin field-effect transistor 300, the middle portion of the semiconductor fin 230 surrounded by the word line 220 can be referred to as the channel region 232 of the vertical fin field-effect transistor 300. In some embodiments, the word line 220 can be considered as a surrounding gate by physically contacting multiple sidewalls of the channel region 232.

[0037] In addition to the channel region 232, the semiconductor fin 230 includes a top protruding along the z-axis above the word line 220, which becomes a top source / drain region 234 located on the top surface of the channel region 232. The semiconductor fin 230 also includes a bottom protruding along the z-axis below the word line 220, which becomes a bottom source / drain region 236 located below the bottom surface of the channel region 232. Therefore, the semiconductor fin 230 can be used as both the channel and the source / drain region of a vertical fin field-effect transistor 300.

[0038] In some embodiments, bit lines 210, word lines 220, and semiconductor fins 230 may be formed of suitable materials to fabricate vertical fin field-effect transistors 300 in memory cell 200. For example, bit lines 210 may include conductive materials, such as tungsten, copper, or other metals, buried in a substrate (not shown). Word lines 220 may include layers of oxides, polysilicon, high-dielectric-constant materials, metal gate materials, or combinations thereof. Semiconductor fins 230 may include silicon, polysilicon, compound semiconductors, or other semiconductor materials.

[0039] The memory cell 200 further includes a memory node contact 240 and a capacitor 250 located above the semiconductor fins 230 along the z-axis direction. The memory node contact 240 covers the top surface of the plurality of semiconductor fins 230, such that the memory node contact 240 is connected to the top source / drain regions 234 of the plurality of vertical fin field-effect transistors 300. The capacitor 250 is disposed on the top surface of the memory node contact 240. To clearly illustrate the configuration of other components in the memory cell 200, Figure 2 Storage node contact 240 and capacitor 250 are omitted.

[0040] Since multiple semiconductor fins 230 of a memory cell 200 are sandwiched between a bit line 210 and a capacitor 250, the multiple semiconductor fins 230 of the memory cell 200 can be regarded as channel regions 232 of multiple vertical fin field-effect transistors 300, wherein these vertical fin field-effect transistors 300 are connected in parallel in the memory cell 200. In other words, the number of semiconductor fins 230 sandwiched between a bit line 210 and a capacitor 250 corresponds to the number of vertical fin field-effect transistors 300 in a memory cell 200. The multiple semiconductor fins 230 in the memory cell 200 can reduce the critical size of the vertical fin field-effect transistors 300, thereby improving the cell integration in the memory device 100. Since the fin width and fin height of the semiconductor fins 230 are related to the channel width and channel length of the vertical fin field-effect transistors 300, the thinned semiconductor fins 230 in the memory cell 200 can also increase the driving current of the vertical fin field-effect transistors 300.

[0041] In some embodiments, the storage node contact 240 may include a polysilicon liner adjacent to the semiconductor fins 230 and a metal layer located between the polysilicon liner and the capacitor 250 to reduce junction leakage between the storage node contact 240 and the semiconductor fins 230 and to reduce contact resistance between the storage node contact 240 and the capacitor 250. For example, the storage node contact 240 may include a polysilicon liner contacting the top surface of a plurality of semiconductor fins 230, a metal silicide layer on the polysilicon liner, and a metal layer on the metal silicide layer.

[0042] The memory cell 200 further includes a body line 260 extending along the x-axis and adjacent to the word line 220. The body line 260 serves as a conductive path for the vertical-fin field-effect transistor 300 to discharge excess charge in the semiconductor fins 230. Specifically, the body line 260 physically contacts one of the multiple sidewalls of each semiconductor fin 230, particularly the sidewall of the channel region 232 of each semiconductor fin 230. In other words, the body line 260 connects the multiple semiconductor fins 230 together in the memory cell 200. When charge accumulates in the channel region 232 during operation of the vertical-fin field-effect transistor 300, the body line 260 can be grounded to guide the accumulated charge out of the channel region 232, thereby reducing the floating body effect of the vertical-fin field-effect transistor 300.

[0043] In some embodiments, the body line 260 and the semiconductor fin 230 can be formed of the same material, such as silicon or polysilicon, to increase the charge release efficiency of the body line 260. The body line 260 and the semiconductor fin 230 can be formed simultaneously of the same material, thereby simplifying the manufacturing process of the memory cell 200. In such embodiments, the body line 260 and the semiconductor fin 230 can be integrally formed into one piece to reduce the interface between the body line 260 and the semiconductor fin 230, thus improving charge release efficiency and structural strength.

[0044] In some other embodiments, the body line 260 and the semiconductor fin 230 may comprise different materials, wherein the conductivity of the body line 260 is higher than that of the semiconductor fin 230. This conductivity difference between the body line 260 and the semiconductor fin 230 can increase the charge release efficiency of the body line 260. For example, the semiconductor fin 230 may be formed of silicon, while the body line 260 may be formed of metal.

[0045] In some embodiments, the memory cell 200 may further include an insulating layer 270 covering the body line 260. Since the body line 260 is embedded in the insulating layer 270, the body line 260 may be referred to as an "embedded body line". The insulating layer 270 can separate the body line 260 and the word line 220, such that the body line 260 guides the charge in the semiconductor fin 230 rather than the charge in the word line 220. For example, one side of the semiconductor fin 230 may protrude from the sidewall of the word line 220 along the y-axis, wherein the body line 260 physically contacts one sidewall of the side of the semiconductor fin 230. Accordingly, the remaining sidewalls of the side of the semiconductor fin 230 may physically contact the insulating layer 270. The insulating layer 270 may also be interposed between the bottom surface of the word line 220 and the top surface of the bit line 210 to separate the word line 220 from the bit line 210. It should be noted that, in order to clearly illustrate the configuration of other components in memory cell 200, cross-sectional views (e.g.) are used. Figure 3 and Figure 6 The insulation layer 270 is omitted in the text.

[0046] In some embodiments, the bottom surface of the main body line 260 may be flush with the bottom surface of the channel region 232. For example... Figure 3 As shown in the cross-sectional view, the top surface, bottom surface, and sidewalls of the main body line 260, hidden by the character line 220, are drawn with dashed lines, wherein the bottom surface of the main body line 260 is flush with the bottom surface of the channel region 232. In other words, the bottom surface of the main body line 260 can be flush with the bottom surface of the character line 220. Therefore, the main body line 260 is separated from the bit line 210, allowing the main body line 260 to guide the charge in the semiconductor fin 230 rather than the charge in the bit line 210.

[0047] Additionally, the top surface of the body line 260 may be flush with or lower than the top surface of the channel region 232. In other words, the top surface of the body line 260 may be flush with or lower than the top surface of the word line 220. Therefore, the body line 260 is separated from the memory node contact 240, allowing the body line 260 to conduct the charge in the semiconductor fin 230 rather than the charge in the memory node contact 240. Figure 3 The memory device 100 in the display shows that the top surface of the main body line 260 is flush with the top surface of the channel region 232. According to another embodiment of this disclosure, Figure 4 A cross-sectional view of the memory device 110 is shown. The memory device 110 is similar to... Figure 3 The memory device 100 is in the memory device 110, but the top surface of the main body line 260 of the memory device 110 is lower than the top surface of the channel region 232.

[0048] In some embodiments, the sidewalls of the main line 260 may extend beyond or be flush with the sidewalls of the channel regions 232 closest to the edge of the two-dimensional array of the memory cells 200. In such embodiments, each channel region 232 may have sidewalls completely covered by the main line 260 to increase the charge release efficiency of the main line 260. Figure 4 The memory device 110 in the diagram shows that the sidewall of the main line 260 extends beyond the sidewall of the channel region 232 closest to the edge of the two-dimensional array. According to another embodiment of this disclosure, Figure 5 A cross-sectional view of the memory device 120 is shown. The memory device 120 is similar to... Figure 4 The memory device 110 is in the memory device 120, but the sidewall of the main body line 260 of the memory device 120 is flush with the sidewall of the channel region 232.

[0049] As described above, the vertical-fin field-effect transistor 300 includes a bit line 210, a word line 220 located above the bit line 210, a semiconductor fin 230 located on the bit line 210 and embedded in the word line 220, a body line 260 physically contacting the semiconductor fin 230, and an insulating layer 270 covering the body line 260. A memory cell 200 includes a plurality of vertical-fin field-effect transistors 300, wherein the body line 260 connects the semiconductor fins 230 of these vertical-fin field-effect transistors 300. A memory device 100 includes a plurality of memory cells 200, wherein the body line 260 or the bit line 210 connects these memory cells 200 to form a two-dimensional array.

[0050] For example, such as Figure 1 As shown, the memory device 100 includes a first memory cell 200a, a second memory cell 200b, a third memory cell 200c, and a fourth memory cell 200d. The first memory cell 200a includes a bit line 210a, a word line 220a, a plurality of semiconductor fins 230a located on and embedded in the bit line 210a, and a body line 260a physically contacting a sidewall of each semiconductor fin 230a. The second memory cell 200b includes a bit line 210b adjacent to the bit line 210a, a word line 220a, a plurality of semiconductor fins 230b located on and embedded in the bit line 210b, and a body line 260a physically contacting a sidewall of each semiconductor fin 230b.

[0051] Similarly, the third memory cell 200c includes a bit line 210a, a word line 220b adjacent to the word line 220a, a plurality of semiconductor fins 230c located on the bit line 210a and embedded in the word line 220b, and a body line 260b physically contacting a sidewall of each semiconductor fin 230c, wherein the word line 220a, body line 260a, word line 220b, and body line 260b are arranged alternately. The fourth memory cell 200d includes a bit line 210b, a word line 220b, a plurality of semiconductor fins 230d located on the bit line 210b and embedded in the word line 220b, and a body line 260b physically contacting a sidewall of each semiconductor fin 230d.

[0052] Main line 260a connects semiconductor fins 230a and 230b, bit line 210a connects semiconductor fins 230a and 230c, and main line 260b connects semiconductor fins 230c and 230d. Therefore, the first memory cells 200a to the fourth memory cells 200d are arranged in a 2×2 array in the memory device 100. In some embodiments, the first memory cells 200a to the fourth memory cells 200d can be repeatedly arranged to form a 4F2 structure of dynamic random access memory.

[0053] In some embodiments, the memory device 100 may further include a word line contact 280 connected to the word line 220 to apply a bias voltage to the word line 220. The memory device 100 may also include a body line contact 290 connecting the body line 260 and a ground point to guide charge out of the body line 260. The word line contact 280 and the body line contact 290 may be disposed on opposite sides or the same side of the memory cell 200. Figure 5 The memory device 120 in the present disclosure shows character line contacts 280 and body line contacts 290 located on opposite sides of the memory cell 200. According to another embodiment of the present disclosure, Figure 6 A cross-sectional view of the memory device 130 is shown. The memory device 130 is similar to... Figure 5 The memory device 120 is in the memory cell 200, but the word line contact 280 and the body line contact 290 of the memory device 130 are located on the same side of the memory cell 200.

[0054] According to the above embodiments, the memory device of this disclosure includes a plurality of memory cells, wherein each memory cell includes a bit line, a word line, a semiconductor fin located on the bit line and embedded in the word line, a body line physically contacting the sidewalls of the semiconductor fin, and an insulating layer covering the body line. The bit line, word line, and plurality of semiconductor fins can be used as vertical fin field-effect transistors connected in parallel in the memory cell, thereby improving the cell integration of the memory device. The body line is grounded to guide accumulated charge out of the semiconductor fin, thereby reducing the floating body effect of the vertical fin field-effect transistors in the memory cell.

[0055] The foregoing outlines features of some embodiments to enable those skilled in the art to better understand the ideas presented in this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0056] [Symbol Explanation]

[0057] 100, 110, 120, 130: Memory devices

[0058] 200: Memory unit

[0059] 200a: First memory unit

[0060] 200b: Second memory unit

[0061] 200c: Third Memory Unit

[0062] 200d: Fourth memory unit

[0063] 210, 210a, 210b: Bit lines

[0064] 220, 220a, 220b: Character lines

[0065] 230, 230a, 230b, 230c, 230d: Semiconductor fins

[0066] 232: Passage Area

[0067] 234: Top source / drain region

[0068] 236: Bottom source / drain region

[0069] 240: Storage node contact

[0070] 250: Capacitor

[0071] 260, 260a, 260b: Main body lines

[0072] 270: Insulation layer

[0073] 280: Character line contact

[0074] 290: Main body line contact component

[0075] 300: Vertical Fin Field-Effect Transistor

[0076] AA′: line

[0077] x, y, z: axes.

Claims

1. A vertical fin field-effect transistor, characterized in that, include: Bit line; The character line is located above the bit line; Semiconductor fins, located on the bit lines, wherein the semiconductor fins include: The channel area is surrounded by the character lines; The top source / drain region is located on the top surface of the channel region; and The bottom source / drain region is located below the bottom surface of the channel region; The main wire, physically in contact with one of the multiple sidewalls of the channel region, wherein the main wire is grounded; and An insulating layer covers the main wire.

2. The vertical fin field-effect transistor of claim 1, wherein the semiconductor fins and the body wire are formed of the same material.

3. The vertical fin field-effect transistor according to claim 1, wherein the semiconductor fins and the body wire are integrally formed.

4. The vertical fin field-effect transistor according to claim 1, wherein the conductivity of the body line is higher than the conductivity of the semiconductor fin.

5. The vertical fin field-effect transistor of claim 1, wherein the top surface of the body line is lower than or flush with the top surface of the channel region.

6. The vertical fin field-effect transistor of claim 1, wherein the bottom surface of the body line is flush with the bottom surface of the channel region.

7. The vertical fin field-effect transistor of claim 1, wherein the word line physically contacts the remainder of the plurality of sidewalls of the channel region.

8. The vertical fin field-effect transistor of claim 1, wherein the sidewall of the body line extends beyond another of the plurality of sidewalls of the channel region.

9. The vertical fin field-effect transistor of claim 1, wherein the sidewall of the body line is flush with another of the plurality of sidewalls of the channel region.

10. The vertical fin field-effect transistor of claim 1, wherein the insulating layer separates the body line and the word line.

11. A memory device, characterized in that, include: The first memory unit includes: The first element line; The first character line is located above the first bit line; Multiple first semiconductor fins are located on the first bit line and embedded in the first word line; The first main line physically contacts one of the multiple sidewalls of each of the plurality of first semiconductor fins; and An insulating layer covers the first main wire.

12. The memory device of claim 11, wherein the first memory cell further comprises: Storage node contacts cover multiple top surfaces of the plurality of first semiconductor fins, wherein multiple bottom surfaces of the plurality of first semiconductor fins contact the first bit line; as well as A capacitor is located on the storage node contact.

13. The memory device of claim 12, wherein the first body line is separate from the memory node contact.

14. The memory device of claim 12, wherein the memory node contact comprises: A polycrystalline silicon liner that contacts the plurality of top surfaces of the plurality of first semiconductor fins; as well as A metal layer is located between the polycrystalline silicon liner and the capacitor.

15. The memory device of claim 11, wherein the first word line and the plurality of first semiconductor fins extend along a first direction, and the first word line and the first body line extend along a second direction different from the first direction.

16. The memory device according to claim 11, wherein, Further includes: The second memory unit includes: The second bit line is adjacent to the first bit line; The first character line is located above the second character line; Multiple second semiconductor fins are located on the second bit line and embedded in the first word line; and The first main line physically contacts one of the multiple sidewalls of each of the plurality of second semiconductor fins, wherein the first main line connects the plurality of first semiconductor fins and the plurality of second semiconductor fins.

17. The memory device according to claim 11, wherein, Further includes: The second memory unit includes: The first bit line; The second character line is adjacent to the first character line and located above the first character line; Multiple second semiconductor fins are located on the first bit line and embedded in the second word line; and The second main line physically contacts one of the multiple sidewalls of each of the plurality of second semiconductor fins.

18. The memory device according to claim 11, wherein, Further includes: The second memory cell includes a plurality of second semiconductor fins located on a second bit line and embedded in the first word line, wherein the first body line connects the plurality of first semiconductor fins and the plurality of second semiconductor fins; The third memory cell includes a plurality of third semiconductor fins located on the first bit line and embedded in the second word line; and A fourth memory cell includes a plurality of fourth semiconductor fins located on the second bit line and embedded in the second word line, wherein a second body line connects the plurality of third semiconductor fins and the plurality of fourth semiconductor fins. The first memory unit, the second memory unit, the third memory unit, and the fourth memory unit are arranged in a 2×2 array.

19. The memory device according to claim 11, wherein, Further includes: Character line contact, connected to the first character line; and A main line contact connects the first main line and a ground point, wherein the character line contact and the main line contact are disposed on opposite sides of the first memory cell.

20. The memory device according to claim 11, wherein, Further includes: Character line contact, connected to the first character line; and A main line contact connects the first main line and a ground point, wherein the character line contact and the main line contact are disposed on the same side of the first memory cell.

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