Vertical fin gate transistor and memory device

Abstract

Embodiments of the present disclosure provide a memory device and a vertical fin gate transistor. A memory device includes a memory cell, wherein the memory cell includes a bit line, a word line over the bit line, and a semiconductor substrate on the bit line. The word lines include a plurality of fin-type word lines and a common word line connecting the fin-type word lines, wherein the fin-type word lines partially cover a first sidewall of the semiconductor substrate. The memory cell also includes a body line physically contacting a second sidewall of the semiconductor substrate opposite the first sidewall of the semiconductor substrate, and an insulating layer covering the body line. The body line is grounded to direct accumulated charge out of the semiconductor substrate, thereby reducing floating body effects in the memory cell.

Description

Technical Field

[0001] This disclosure relates to memory devices, and more particularly to memory devices including vertical fin gate transistors. Background Technology

[0002] A gate-around transistor (SGT) is an option for dynamic random access memory (DRAM) designs. Typically, a SGT consists of a columnar channel and a gate surrounding the channel, with the source / drain regions located at the top and bottom of the columnar structure. However, charge can accumulate in the columnar structure, causing a floating body effect in the SGT. Summary of the Invention

[0003] According to some embodiments of this disclosure, a vertical fin gate transistor includes bit lines, word lines located above the bit lines, and a semiconductor substrate located on the bit lines. The word lines include fin word lines and a common word line located on the top surface of the fin word lines. The semiconductor substrate includes a channel region covered by the fin word lines, a top source / drain region located on the top surface of the channel region, and a bottom source / drain region located below the bottom surface of the channel region. The vertical fin gate transistor also includes a body line physically contacting a first sidewall of the channel region and an insulating layer covering the body line, wherein the body line is grounded.

[0004] In some implementations, the semiconductor substrate and the body wire are formed of the same material.

[0005] In some implementations, the semiconductor substrate and the body wire are integrally formed.

[0006] In some implementations, the conductivity of the body wire is higher than that of the semiconductor substrate.

[0007] In some implementations, the top surface of the main body line is lower than or flush with the top surface of the channel region.

[0008] In some implementations, the bottom surface of the main body line is flush with the bottom surface of the channel area.

[0009] In some implementations, the fin-type character line physically contacts the second sidewall of the channel region, wherein the second sidewall is relative to the first sidewall of the channel region.

[0010] In some implementations, the sidewall of the main body line extends beyond the second sidewall of the channel region, wherein the second sidewall is connected to the first sidewall of the channel region.

[0011] In some implementations, the sidewall of the main body line is flush with the second sidewall of the channel region, wherein the second sidewall is connected to the first sidewall of the channel region.

[0012] In some embodiments, a first sidewall of the semiconductor substrate partially covered by fin character lines has a first width, a second sidewall of the semiconductor substrate connected to the first sidewall has a second width, and the ratio of the first width to the second width is in the range of 3:1 to 5:1.

[0013] According to some embodiments of this disclosure, a memory device includes a first memory cell. The first memory cell includes a first bit line, a first word line located above the first bit line, and a first semiconductor substrate located on the first bit line. The first word line includes a plurality of first fin-type word lines and a first common word line connecting the first fin-type word lines, wherein the first fin-type word lines partially cover a first sidewall of the first semiconductor substrate. The first memory cell also includes a first body line physically contacting a second sidewall of the first semiconductor substrate and an insulating layer covering the first body line, wherein the second sidewall of the first semiconductor substrate is opposite to the first sidewall of the first semiconductor substrate.

[0014] In some embodiments, the first memory cell further includes a memory node contact covering the top surface of the first semiconductor substrate and a capacitor located on the memory node contact, wherein the bottom surface of the first semiconductor substrate contacts the first memory line.

[0015] In some implementations, the first main line is separated from the storage node contact.

[0016] In some embodiments, the storage node contact includes a polysilicon liner that contacts the top surface of a first semiconductor substrate, and a metal layer located between the polysilicon liner and the capacitor.

[0017] In some implementations, the first bit line and the first fin bit line extend along a first direction, and the first common bit line and the first body line extend along a second direction different from the first direction.

[0018] In some embodiments, the memory device further includes a second memory cell. The second memory cell includes a second bit line adjacent to the first bit line, a first word line above the second bit line, and a second semiconductor substrate located on the second bit line, wherein a plurality of second fin-type word lines of the first word line partially cover a first sidewall of the second semiconductor substrate. The second memory cell also includes a first body line physically contacting the second sidewall of the second semiconductor substrate, wherein the second sidewall of the second semiconductor substrate is opposite to the first sidewall of the second semiconductor substrate, and the first body line connects the first semiconductor substrate and the second semiconductor substrate.

[0019] In some embodiments, the memory device further includes a second memory cell. The second memory cell includes a first word line, a second word line adjacent to and above the first body line, and a second semiconductor substrate located on the first word line. The second word line includes a plurality of second finned word lines and a second common word line connecting the plurality of second finned word lines, wherein the second finned word lines partially cover a first sidewall of the second semiconductor substrate. The second memory cell also includes a second body line physically contacting a second sidewall of the second semiconductor substrate, wherein the second sidewall of the second semiconductor substrate is relative to the first sidewall of the second semiconductor substrate.

[0020] In some embodiments, the memory device further includes a second memory cell, wherein the second memory cell includes a second semiconductor substrate located on a second word line, and a plurality of second finned word lines of the first word line partially cover a first sidewall of the second semiconductor substrate. The memory device further includes a third memory cell, wherein the third memory cell includes a third semiconductor substrate located on a first word line, and a plurality of third finned word lines of the second word line partially cover a first sidewall of the third semiconductor substrate. The memory device further includes a fourth memory cell, wherein the fourth memory cell includes a fourth semiconductor substrate located on a second word line, and a plurality of fourth finned word lines of the second word line partially cover a first sidewall of the fourth semiconductor substrate. A first body line connects a second sidewall of the first semiconductor substrate and a second sidewall of the second semiconductor substrate. A second body line connects a second sidewall of the third semiconductor substrate and a second sidewall of the fourth semiconductor substrate.

[0021] In some embodiments, the memory device further includes a word line contact connected to a first common word line and a body line contact connecting a first body line and a ground point, wherein the word line contact and the body line contact are disposed on opposite sides of the first memory cell.

[0022] In some embodiments, the memory device further includes a word line contact connected to a first common word line and a body line contact connecting a first body line and a ground point, wherein the word line contact and the body line contact are disposed on the same side of the first memory cell.

[0023] According to the above embodiments, a memory device includes a memory cell, the memory cell including bit lines, word lines including fin word lines and common word lines connecting the fin word lines, a semiconductor substrate having a first sidewall partially covered by the fin word lines, a main line physically contacting the second sidewall of the semiconductor substrate, and an insulating layer covering the main line, wherein the main line is grounded to reduce the floating body effect in the memory cell. Attached Figure Description

[0024] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial methods, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0025] Figure 1 A three-dimensional schematic diagram of a memory device is shown according to one embodiment of the present disclosure.

[0026] Figure 2 For illustration Figure 1 An enlarged top view of the memory device.

[0027] Figure 3 and Figure 4 For illustration Figure 2 A cross-sectional view of the memory device in the diagram.

[0028] Figure 5 A cross-sectional view of a memory device is shown according to another embodiment of the present disclosure.

[0029] Figure 6 A cross-sectional view of a memory device is shown according to another embodiment of the present disclosure.

[0030] Figure 7 A cross-sectional view of a memory device is shown according to another embodiment of the present disclosure.

[0031] Figure 8 A cross-sectional view of a memory device is shown according to another embodiment of the present disclosure. Detailed Implementation

[0032] To achieve the different features of the mentioned subject matter, the following disclosure provides many different implementations or examples. Specific examples of components, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, in the following description, forming a first feature on or above a second feature may include implementations where the first and second features are formed in direct contact, and may also include implementations where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various implementations and / or configurations discussed.

[0033] Furthermore, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to facilitate the description of the relationship between one element or feature and another element or feature as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptive symbols used herein may be interpreted accordingly.

[0034] According to some embodiments of this disclosure, a memory device includes a memory cell, wherein the memory cell includes a bit line, a word line including a fin word line, a semiconductor substrate located on the bit line and having a first sidewall partially covered by the fin word line, a body line physically contacting a second sidewall of the semiconductor substrate, and an insulating layer covering the body line. The bit line, the fin word line, and the semiconductor substrate can be used as vertical fin-gate transistors in the memory cell, wherein the body line is grounded to reduce the floating body effect of the vertical fin-gate transistors.

[0035] According to one embodiment of this disclosure Figure 1 This is a three-dimensional schematic diagram of a memory device 100. The memory device 100 includes a plurality of memory cells 200 arranged in a two-dimensional array. For simplicity, Figure 1 The diagram illustrates nine memory cells 200 arranged in a 3×3 array in the memory device 100. However, this is not intended to limit the number of memory cells 200 that the memory device 100 may include. To clearly illustrate the details of the memory cells 200, Figure 2 For illustration Figure 1 An enlarged top view of the three memory cells 200 of the memory device 100. Figure 3 To illustrate the memory device 100 along Figure 2 The cross-sectional view of line AA′ in the diagram, and Figure 4 To illustrate the memory device 100 along Figure 2 A cross-sectional view of line BB′ in the diagram.

[0036] refer to Figures 1 to 4The memory cell 200 includes bit lines 210, word lines 220 located above the bit lines 210, and a semiconductor substrate 230 located on the bit lines 210. The bit lines 210 extend along the y-axis. The word lines 220 include a plurality of finned word lines 222 separated from each other and a common word line 224 located on the top surface of the finned word lines 222, wherein the common word line 224 connects the plurality of finned word lines 222 together and applies a bias to the finned word lines 222. The finned word lines 222 extend along the y-axis, while the common word line 224 extends along the x-axis. The word lines 220 are separated from the bit lines 210 along the z-axis.

[0037] Semiconductor substrate 230 is electrically connected to bit line 210, and finned word line 222 partially covers semiconductor substrate 230. For example, the bottom surface of semiconductor substrate 230 may contact the top surface of bit line 210, while finned word line 222 may partially cover the sidewall of semiconductor substrate 230. Therefore, bit line 210, multiple finned word lines 222, and semiconductor substrate 230 can be used as multiple vertical fin gate transistors 300 in memory cell 200.

[0038] Specifically, for each finned word line 222, the finned word line 222 covers the middle portion of the sidewall of the semiconductor substrate 230. Since the finned word lines 222 serve as gates for controlling the current in the semiconductor substrate 230, the middle portion of the semiconductor substrate 230 covered by the finned word lines 222 can be referred to as the channel region 232 of the transistor, where the transistor can be called a vertical fin gate transistor 300 due to the finned structure of the finned word lines 222. To clearly illustrate the channel region 232, Figure 4 The finned character line 222 and common character line 224, which are hidden by the semiconductor substrate 230, are shown in dashed lines. In some embodiments, the finned character line 222 may physically contact the sidewall of the channel region 232, and the common character line 224 may be spaced apart from the sidewall of the channel region 232.

[0039] In addition to the channel region 232, the semiconductor substrate 230 includes a top protruding along the z-axis above the fin word line 222, which becomes a top source / drain region 234 located on the top surface of the channel region 232. The semiconductor substrate 230 also includes a bottom protruding along the z-axis below the fin word line 222, which becomes a bottom source / drain region 236 located below the bottom surface of the channel region 232. Therefore, the semiconductor substrate 230 can be used as both the channel and the source / drain region of the vertical fin gate transistor 300.

[0040] In some embodiments, the semiconductor substrate 230 may have a suitable aspect ratio such that the plurality of fin character lines 222 partially cover the same sidewalls of the semiconductor substrate 230. Specifically, the plurality of fin character lines 222 may partially cover a first sidewall of the semiconductor substrate 230, while a second sidewall of the semiconductor substrate 230 is connected to the first sidewall, wherein the first sidewall has a first width and the second sidewall has a second width smaller than the first width. For example, the ratio of the first width to the second width may be in the range of 3:1 to 5:1. In other words, the width of the sidewall of the semiconductor substrate 230 covered by the fin character lines 222 may be greater than the width of the sidewall of the semiconductor substrate 230 not covered by the fin character lines 222.

[0041] In some embodiments, bit lines 210, word lines 220, and semiconductor substrate 230 may be formed of suitable materials to fabricate vertical fin gate transistors 300 in memory cell 200. For example, bit line 210 may include a conductive material, such as tungsten, copper, or other metal, buried in a substrate (not shown). Fin word lines 222 and common word lines 224 may include layers of oxide, polysilicon, high-dielectric-constant materials, metal gate materials, or combinations thereof. Semiconductor substrate 230 may include silicon, polysilicon, compound semiconductors, or other semiconductor materials.

[0042] The memory cell 200 further includes a memory node contact 240 and a capacitor 250 located above the semiconductor substrate 230 along the z-axis direction. The memory node contact 240 covers the top surface of the semiconductor substrate 230 such that the memory node contact 240 is connected to the top source / drain region 234 of the vertical fin gate transistor 300. The capacitor 250 is disposed on the top surface of the memory node contact 240. To clearly illustrate the configuration of other components in the memory cell 200, Figure 2 The capacitor 250 is omitted in the text.

[0043] Since the semiconductor substrate 230 of a memory cell 200 is sandwiched between a bit line 210 and a capacitor 250, the middle portion of the semiconductor substrate 230 covered by the plurality of fin word lines 222 of the memory cell 200 can be referred to as the channel region 232 of the plurality of vertical fin gate transistors 300, wherein these vertical fin gate transistors 300 are connected in parallel in the memory cell 200. In other words, the number of fin word lines 222 covering the sidewalls of a semiconductor substrate 230 corresponds to the number of vertical fin gate transistors 300 in a memory cell 200. The plurality of fin word lines 222 in the memory cell 200 can reduce the critical size of the vertical fin gate transistors 300, thereby improving the cell integration in the memory device 100. Since the fin width and fin height of the fin word line 222 are related to the channel width and channel length of the vertical fin gate transistor 300, the thinned fin word line 222 in the memory cell 200 can also increase the driving current of the vertical fin gate transistor 300.

[0044] The sidewall of the memory node contact 240 can be spaced apart from the sidewall of the semiconductor substrate 230 to avoid physical contact between the memory node contact 240 and the word line 220. For example... Figure 2 As shown, the sidewall 242 of the memory node contact 240 faces the fin character line 222, wherein the sidewall 242 may be spaced apart from the nearest sidewall of the semiconductor substrate 230 by a gap G1 in the y-axis direction. In some embodiments, the sidewall 244 of the memory node contact 240 is connected to the sidewall 242 and does not face the fin character line 222, wherein the sidewall 244 may be spaced apart from the nearest sidewall of the semiconductor substrate 230 by a gap G2 in the x-axis direction. In some other embodiments, the sidewall 244 of the memory node contact 240 may be flush with the sidewall of the semiconductor substrate 230. According to another embodiment of this disclosure, Figure 5 A cross-sectional view of the memory device 110 is shown. The memory device 110 is similar to... Figure 3 The memory device 100 is in the memory device 110, but the sidewall 244 of the memory node contact 240 of the memory device 110 is flush with the sidewall of the semiconductor substrate 230.

[0045] In some embodiments, the memory node contact 240 may include a polysilicon liner adjacent to the semiconductor substrate 230 and a metal layer located between the polysilicon liner and the capacitor 250 to reduce junction leakage between the memory node contact 240 and the semiconductor substrate 230 and to reduce contact resistance between the memory node contact 240 and the capacitor 250. For example, the memory node contact 240 may include a polysilicon liner contacting the top surface of the semiconductor substrate 230, a metal silicide layer on the polysilicon liner, and a metal layer on the metal silicide layer.

[0046] Reference Figures 1 to 4 The memory cell 200 further includes a body line 260 extending along the x-axis and adjacent to the word line 220. The body line 260 serves as a conductive path for the vertical fin gate transistor 300 to release excess charge in the semiconductor substrate 230. Specifically, the body line 260 physically contacts the sidewalls of the semiconductor substrate 230 relative to the word line 220, particularly the sidewalls of the channel regions 232 of the semiconductor substrate 230. In other words, the body line 260 connects multiple channel regions 232 together in the semiconductor substrate 230 of the memory cell 200. When charge accumulates in the channel regions 232 during operation of the vertical fin gate transistor 300, the body line 260 can be grounded to guide the accumulated charge out of the channel regions 232, thereby reducing the floating body effect of the vertical fin gate transistor 300.

[0047] In some embodiments, memory cell 200 may further include an insulating layer 270 covering the body line 260. Since the body line 260 is embedded in the insulating layer 270, the body line 260 may be referred to as an "embedded body line". Additionally, the insulating layer 270 may be interposed between the sidewalls of a plurality of fin word lines 222 to separate the fin word lines 222 from each other. The insulating layer 270 may also be interposed between the bottom surface of the fin word line 222 and the top surface of the bit line 210 to separate the fin word line 222 and the bit line 210. It should be noted that, for clear illustration of the configuration of other components in memory cell 200, cross-sectional views (e.g., Figure 3 and Figure 4 The insulation layer 270 is omitted in the text.

[0048] In some embodiments, the main line 260 and the semiconductor substrate 230 may be formed of the same material, such as silicon or polysilicon, to increase the charge release efficiency of the main line 260. The main line 260 and the semiconductor substrate 230, both made of the same material, can be formed simultaneously, thereby simplifying the manufacturing process of the memory cell 200. In such embodiments, the main line 260 and the semiconductor substrate 230 may be integrally formed into one piece to reduce the interface between the main line 260 and the semiconductor substrate 230, thus improving charge release efficiency and structural strength.

[0049] In some other embodiments, the body line 260 and the semiconductor substrate 230 may comprise different materials, wherein the conductivity of the body line 260 is higher than that of the semiconductor substrate 230. This conductivity difference between the body line 260 and the semiconductor substrate 230 can increase the charge dissipation efficiency of the body line 260. For example, the semiconductor substrate 230 may be formed of silicon, while the body line 260 may be formed of metal.

[0050] In some embodiments, the bottom surface of the main body line 260 may be flush with the bottom surface of the channel region 232. For example... Figure 3 As shown, the top and bottom surfaces of the main body line 260, hidden by the semiconductor substrate 230, are drawn with dashed lines, wherein the bottom surface of the main body line 260 is flush with the channel region 232 (e.g., Figure 4 The bottom surface of the main body line 260 (as shown in the diagram). In other words, the bottom surface of the main body line 260 can be flush with the bottom surface of the fin character line 222. Therefore, the main body line 260 is separated from the bit line 210, so that the main body line 260 guides the charge in the semiconductor substrate 230 instead of the charge in the bit line 210.

[0051] Additionally, the top surface of the main body line 260 may be flush with or lower than the top surface of the channel region 232. In other words, the top surface of the main body line 260 may be flush with or lower than the top surface of the fin character line 222. Therefore, the main body line 260 is separated from the memory node contact 240, allowing the main body line 260 to conduct charges from the semiconductor substrate 230 rather than from the memory node contact 240. Figure 3 The memory device 100 in the middle shows the top surface of the main body line 260 below the channel region 232 (e.g. Figure 4 The top surface (as shown in the diagram). According to another embodiment of this disclosure, Figure 6 A cross-sectional view of the memory device 120 is shown. The memory device 120 is similar to... Figure 3 The memory device 100 is in the middle, but the top surface of the main body line 260 of the memory device 120 is flush with the channel region 232 (e.g., Figure 4 The top surface (as shown in the diagram).

[0052] In some embodiments, the sidewalls of the main line 260 may extend beyond or be flush with the sidewalls of the channel regions 232 closest to the edge of the two-dimensional array of the memory cells 200. In such embodiments, each channel region 232 may have sidewalls completely covered by the main line 260 to increase the charge release efficiency of the main line 260. Figure 3 The memory device 100 in the image shows the sidewall of the main body line 260 extending beyond the channel region 232 closest to the edge of the two-dimensional array (e.g., Figure 4 The sidewall (as shown in the diagram). According to another embodiment of this disclosure, Figure 7 A cross-sectional view of the memory device 130 is shown. The memory device 130 is similar to... Figure 3 The memory device 100 is in the middle, but the sidewall of the main body line 260 of the memory device 130 is flush with the channel region 232 closest to the edge of the two-dimensional array (e.g., Figure 4 The sidewall (as shown in the image).

[0053] As described above, the vertical fin gate transistor 300 includes a bit line 210, a word line 220 located above the bit line 210 and including a fin word line 222 and a common word line 224, a semiconductor substrate 230 located on the bit line 210 and partially covered by the fin word line 222, a body line 260 physically contacting the semiconductor substrate 230, and an insulating layer 270 covering the body line 260. A memory cell 200 includes a plurality of vertical fin gate transistors 300, wherein the body line 260 connects the channel regions of these vertical fin gate transistors 300. A memory device 100 includes a plurality of memory cells 200, wherein the body line 260 or the bit line 210 connects these memory cells 200 to form a two-dimensional array.

[0054] For example, such as Figure 1 As shown, the memory device 100 includes a first memory cell 200a, a second memory cell 200b, a third memory cell 200c, and a fourth memory cell 200d. The first memory cell 200a includes a bit line 210a, a word line 220a including a fin word line 222a and a common word line 224a, a semiconductor substrate 230a located on the bit line 210a and having one sidewall partially covered by the fin word line 222a, and a body line 260a physically in contact with another sidewall of the semiconductor substrate 230a. The second memory cell 200b includes a bit line 210b adjacent to the bit line 210a, a word line 220a including a fin word line 222b and a common word line 224a, a semiconductor substrate 230b located on the bit line 210b and having one sidewall partially covered by the fin word line 222b, and a body line 260a physically in contact with another sidewall of the semiconductor substrate 230b.

[0055] Similarly, the third memory cell 200c includes a bit line 210a, a word line 220b including a finned word line 222c and a common word line 224b, a semiconductor substrate 230c located on the bit line 210a and having one sidewall partially covered by the finned word line 222c, and a body line 260b physically contacting another sidewall of the semiconductor substrate 230c, wherein the word line 220a, body line 260a, word line 220b, and body line 260b are arranged alternately. The fourth memory cell 200d includes a bit line 210b, a word line 220b including a finned word line 222d and a common word line 224b, a semiconductor substrate 230d located on the bit line 210b and having one sidewall partially covered by the finned word line 222d, and a body line 260b physically contacting another sidewall of the semiconductor substrate 230d.

[0056] Main line 260a connects semiconductor substrates 230a and 230b, bit line 210a connects semiconductor substrates 230a and 230c, and main line 260b connects semiconductor substrates 230c and 230d. Therefore, the first memory cells 200a to the fourth memory cells 200d are arranged in a 2×2 array in the memory device 100. In some embodiments, the first memory cells 200a to the fourth memory cells 200d can be repeatedly arranged to form a 4F2 structure of dynamic random access memory.

[0057] In some embodiments, the memory device 100 may further include a word line contact 280 connected to a common word line 224 to apply a bias voltage to the word line 220. The memory device 100 may also include a body line contact 290 connecting a body line 260 and a ground point to guide charge out of the body line 260. The word line contact 280 and the body line contact 290 may be located on opposite sides or the same side of the memory cell 200. Figure 3 The memory device 100 in the present disclosure shows character line contacts 280 and body line contacts 290 located on opposite sides of the memory cell 200. According to another embodiment of the present disclosure, Figure 8 A cross-sectional view of the memory device 140 is shown. The memory device 140 is similar to... Figure 3 The memory device 100 is located in the memory cell 200, but the word line contact 280 and the body line contact 290 of the memory device 140 are located on the same side of the memory cell 200.

[0058] According to the above embodiments, the memory device of this disclosure includes a plurality of memory cells, wherein each memory cell includes a bit line, a finned word line and a common word line, a semiconductor substrate located on the bit line and having one sidewall partially covered by the finned word line, a body line physically contacting the other sidewall of the semiconductor substrate, and an insulating layer covering the body line. The bit line, the plurality of finned word lines and the semiconductor substrate can be used as a plurality of vertical fin gate transistors connected in parallel in the memory cell, thereby improving the cell integration in the memory device. The body line is grounded to guide accumulated charge out of the semiconductor substrate, thereby reducing the floating body effect of the vertical fin gate transistors in the memory cell.

[0059] The foregoing outlines some features of the embodiments to enable those skilled in the art to better understand the ideas presented in this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0060] [Symbol Explanation]

[0061] 100, 110, 120, 130, 140: Memory devices

[0062] 200: Memory unit

[0063] 200a: First memory unit

[0064] 200b: Second memory unit

[0065] 200c: Third Memory Unit

[0066] 200d: Fourth memory unit

[0067] 210, 210a, 210b: Bit lines

[0068] 220, 220a, 220b: Character lines

[0069] 222,222a,222b,222c,222d: Fin-shaped character lines

[0070] 224, 224a, 224b: Common character lines

[0071] 230, 230a, 230b, 230c, 230d: Semiconductor substrates

[0072] 232: Passage Area

[0073] 234: Top source / drain region

[0074] 236: Bottom source / drain region

[0075] 240: Storage node contact

[0076] 242, 244: Sidewall

[0077] 250: Capacitor

[0078] 260, 260a, 260b: Main body lines

[0079] 270: Insulation layer

[0080] 280: Character line contact

[0081] 290: Main body line contact component

[0082] 300: Vertical Fin Gate Transistor

[0083] AA′,BB′: lines

[0084] G1, G2: Gap

[0085] x, y, z: axes.

Claims

1. A vertical fin gate transistor, characterized in that, include: Bit line; Character lines, located above the bit lines, wherein the character lines include: Fin-shaped character lines; and A common character line is located on the top surface of the fin-type character line; A semiconductor substrate is located on the bit line, wherein the semiconductor substrate comprises: The channel area is covered by the fin-shaped character lines; The top source / drain region is located on the top surface of the channel region; and The bottom source / drain region is located below the bottom surface of the channel region; The main wire, physically in contact with a first sidewall of the channel region, wherein the main wire is grounded; and An insulating layer covers the main wire.

2. The vertical fin gate transistor of claim 1, wherein the semiconductor substrate and the body line are formed of the same material.

3. The vertical fin gate transistor according to claim 1, wherein the semiconductor substrate and the body line are integrally formed.

4. The vertical fin gate transistor according to claim 1, wherein the conductivity of the body line is higher than the conductivity of the semiconductor substrate.

5. The vertical fin gate transistor of claim 1, wherein the top surface of the body line is lower than or flush with the top surface of the channel region.

6. The vertical fin gate transistor of claim 1, wherein the bottom surface of the body line is flush with the bottom surface of the channel region.

7. The vertical fin gate transistor of claim 1, wherein the fin word line physically contacts a second sidewall of the channel region, and the second sidewall is relative to the first sidewall of the channel region.

8. The vertical fin gate transistor of claim 1, wherein the sidewall of the body line extends beyond the second sidewall of the channel region, and the second sidewall is connected to the first sidewall of the channel region.

9. The vertical fin gate transistor of claim 1, wherein the sidewall of the body line is flush with the second sidewall of the channel region, and the second sidewall is connected to the first sidewall of the channel region.

10. The vertical fin gate transistor of claim 1, wherein a first sidewall of the semiconductor substrate covered by the fin character line portion has a first width, a second sidewall of the semiconductor substrate connected to the first sidewall has a second width, and the ratio of the first width to the second width is in the range of 3:1 to 5:

1.

11. A memory device, characterized in that, include: The first memory unit includes: The first element line; The first character line is located above the first character line, wherein the first character line includes a plurality of first fin character lines and a first common character line connecting the plurality of first fin character lines; A first semiconductor substrate is located on the first bit line, wherein the plurality of first fin-type bit lines partially cover the first sidewall of the first semiconductor substrate. A first main line physically contacts a second sidewall of the first semiconductor substrate, wherein the second sidewall of the first semiconductor substrate is relative to the first sidewall of the first semiconductor substrate; and An insulating layer covers the first main wire.

12. The memory device of claim 11, wherein the first memory cell further comprises: A storage node contact covers the top surface of the first semiconductor substrate, wherein the bottom surface of the first semiconductor substrate contacts the first bit line; as well as A capacitor is located on the storage node contact.

13. The memory device of claim 12, wherein the first body line is separate from the memory node contact.

14. The memory device of claim 12, wherein the memory node contact comprises: A polycrystalline silicon liner contacts the top surface of the first semiconductor substrate; as well as A metal layer is located between the polycrystalline silicon liner and the capacitor.

15. The memory device of claim 11, wherein the first bit line and the first fin-type word line extend along a first direction, and the first common word line and the first body line extend along a second direction different from the first direction.

16. The memory device according to claim 11, wherein, Further includes: The second memory unit includes: The second bit line is adjacent to the first bit line; The first character line is located above the second character line; A second semiconductor substrate is located on the second word line, wherein a plurality of second fin-type word lines of the first word line partially cover a first sidewall of the second semiconductor substrate; and The first main body line physically contacts the second sidewall of the second semiconductor substrate, wherein the second sidewall of the second semiconductor substrate is relative to the first sidewall of the second semiconductor substrate, and the first main body line connects the first semiconductor substrate and the second semiconductor substrate.

17. The memory device according to claim 11, wherein, Further includes: The second memory unit includes: The first bit line; The second character line is adjacent to the first main line and located above the first character line, wherein the second character line includes a plurality of second fin character lines and a second common character line connecting the plurality of second fin character lines; A second semiconductor substrate is located on the first bit line, wherein the plurality of second fin-type bit lines partially cover the first sidewall of the second semiconductor substrate; and The second main line physically contacts the second sidewall of the second semiconductor substrate, wherein the second sidewall of the second semiconductor substrate is relative to the first sidewall of the second semiconductor substrate.

18. The memory device according to claim 11, wherein, Further includes: The second memory cell includes a second semiconductor substrate located on a second bit line, wherein a plurality of second fin-type word lines of the first word line partially cover a first sidewall of the second semiconductor substrate, and wherein the first main line connects the second sidewall of the first semiconductor substrate and the second sidewall of the second semiconductor substrate. A third memory cell includes a third semiconductor substrate located on the first bit line, wherein a plurality of third fin-type word lines of the second word line partially cover a first sidewall of the third semiconductor substrate; and A fourth memory cell includes a fourth semiconductor substrate located on the second word line, wherein a plurality of fourth fin-type word lines of the second word line partially cover a first sidewall of the fourth semiconductor substrate, and wherein a second body line connects a second sidewall of the third semiconductor substrate and a second sidewall of the fourth semiconductor substrate.

19. The memory device according to claim 11, wherein, Further includes: Character line contact, connected to the first common character line; and A main line contact connects the first main line and a ground point, wherein the character line contact and the main line contact are disposed on opposite sides of the first memory cell.

20. The memory device according to claim 11, wherein, Further includes: Character line contact, connected to the first common character line; and A main line contact connects the first main line and a ground point, wherein the character line contact and the main line contact are disposed on the same side of the first memory cell.

Images