High-temperature-resistant VDMOS power transistor used in extreme environment and preparation method of high-temperature-resistant VDMOS power transistor

Abstract

The invention relates to the technical field of MOS semiconductors, and discloses a high-temperature-resistant VDMOS power transistor used in an extreme environment and a preparation method, the high-temperature-resistant VDMOS power transistor used in the extreme environment comprises a plurality of parallel MOS cells, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a grid electrode and a source electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a lower P + layer, a P well layer and an N well layer, side P + layers are formed on the two sides of the single MOS cell and located between the source electrode and the lower P + layer through ion implantation. The side P + layer and the N well layer are distributed in an axial symmetry mode, and the profile of the section formed after the side P + layer and the N well layer are combined is in a shape like a Chinese character'ao '. According to the invention, through the axisymmetric concave deep junction structure formed by the side P + layer and the N well layer, the lateral expansion capability of a depletion region is obviously enhanced, the parasitic resistance of the P well layer is reduced, the conduction path of a parasitic bipolar transistor is blocked by the structure, and the latch-up effect at high temperature is avoided.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and particularly to a high-temperature-resistant VDMOS power transistor for extreme environments and a preparation method thereof. Background Art

[0002] Traditional VDMOS power transistors have significant defects in extremely high-temperature environments: First, the parasitic resistance of the P-well is prone to trigger the latch-up effect, resulting in device out-of-control failure; second, the electric field concentration in the JFET region squeezes the channel current and causes local breakdown; in addition, the thermal expansion coefficient mismatch at the metal-semiconductor interface is likely to cause contact cracking during high-temperature cycling, and the right-angle structure generates stress concentration points. At the same time, problems such as the long reverse recovery time and high switching loss of the body diode, and the excessive peak value of the drain-end electric field further limit the reliability and power density of the device in high-temperature and high-pressure scenarios.

[0003] The existing patent discloses a high-avalanche-tolerance vertical double-diffused MOS (CN215771155U), which includes an N-type substrate region and an N-epitaxial layer arranged in sequence from bottom to top. P-well regions are provided on the left and right sides above the N-epitaxial layer. N buried layers are arranged directly below the aforementioned P-well regions. N+ source regions are arranged inside the P-well regions. A front metal electrode region is provided on the upper surface at the junction of the two P-well regions and the N-epitaxial layer in the middle position. A metal pre-dielectric BPSG is arranged below the front metal electrode region. This existing technology is difficult to balance high-temperature stability, voltage withstand ability, and heat dissipation performance, and cannot meet the application requirements of extreme environments such as aerospace and geothermal drilling. Summary of the Invention

[0004] The present invention provides a high-temperature-resistant VDMOS power transistor for extreme environments and a preparation method thereof to solve the existing technical problems and address the problems in the above background art.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a high-temperature-resistant VDMOS power transistor for extreme environments includes a plurality of mutually parallel MOS cells. A single MOS cell includes a drain, a semiconductor epitaxial layer, a gate, and a source. The semiconductor epitaxial layer includes an N substrate layer, an N drift layer, a lower P+ layer, a P-well layer, and an N-well layer. Side P+ layers are formed by ion implantation on both sides of a single MOS cell and between the source and the lower P+ layer; the side P+ layers and the N-well layer are axially symmetrically distributed, and the cross-sectional profile after the combination of the side P+ layers and the N-well layer is in a "concave" shape;

[0006] The cross-sectional profile of the source is an inverted "L" shape, where the source includes a horizontal part and a vertical part, and the vertical part of the source is adapted to the sunken part after the combination of the side P+ layers and the N-well layer.

[0007] Further, on both sides of the N drift layer in a single MOS cell, and in the top region close to the P well layer, an N-type fan-shaped layer is formed by ion implantation.

[0008] Further, on both sides of the N drift layer in a single MOS cell, and below the lower P+ layer, a rectangular P- layer is formed by ion implantation, and the rectangular P- layer is in direct contact with the lower P+ layer.

[0009] Further, rectangular polysilicon layers are deposited on both sides of the N substrate layer in a single MOS cell, and the rectangular polysilicon layers are in ohmic contact with the drain.

[0010] Further, the N substrate layer further includes a recessed N substrate, and the junction of the recessed N substrate and the N drift layer is recessed;

[0011] Triangular polysilicon layers are deposited on both sides of the recessed N substrate in a single MOS cell, and the triangular polysilicon layers are in ohmic contact with the drain.

[0012] Further, the N substrate layer further includes a curved N substrate, and the drain further includes an arc-shaped drain.

[0013] Further, the junction of the curved N substrate and the N drift layer, and the junction of the curved N substrate and the arc-shaped drain are both recessed arc-shaped, and the arc-shaped radian of the two junctions is the same.

[0014] A preparation method of a high-temperature resistant VDMOS power transistor for extreme environments, the steps include:

[0015] S1. The N substrate layer forms a recessed N substrate or a curved N substrate structure through an etching process, and an N drift layer is epitaxially grown on the substrate;

[0016] S2. P-type ion implantation is performed between the source and the lower P+ layer to form an axisymmetric "concave" shape profile matching the N well layer;

[0017] S3. N-type ions are implanted in the top regions on both sides of the N drift layer close to the P well layer to form an N-type fan-shaped layer;

[0018] S4. P-type ions are implanted on both sides of the N drift layer and below the lower P+ layer to form a rectangular P- layer;

[0019] S5. Triangular polysilicon layers are deposited on both sides of the recessed N substrate or an arc-shaped drain is synchronously prepared for the curved N substrate;

[0020] S6. First, the recessed regions of the lateral P+ layer and the N well layer are longitudinally filled and deposited, and then the surface of the P well layer is covered transversely;

[0021] S7. Deposit the drain and source on the surface of the semiconductor epitaxial layer by chemical vapor deposition.

[0022] A high-temperature resistant VDMOS power transistor and a preparation method thereof for extreme environments provided by the present invention have the following effects compared with the prior art:

[0023] 1. The present invention forms an axisymmetric "concave" shaped deep junction structure through the side P+ layer and the N well layer, significantly enhancing the lateral expansion ability of the depletion region, reducing the parasitic resistance of the P well layer. This structure blocks the conduction path of the parasitic bipolar transistor and avoids the latch-up effect at high temperatures. At the same time, the longitudinal part of the inverted L-shaped source fills the "concave" shaped depression area, increasing the contact area between the source and the P+ region, reducing the contact resistance. The lateral part covers the surface of the P well, optimizing the lateral conduction path of carriers, and improving the current density and high-temperature stability.

[0024] 2. The present invention injects gradually doped N-type fan-shaped layers on both sides of the top of the P well layer. The fan-shaped profile disperses the electric field peak in the JFET region of the traditional VDMOS, avoiding the channel current being squeezed. This design balances the electric field distribution, prevents premature breakdown caused by local high electric fields, and at the same time broadens the carrier channel, improving the reliability of the device in high-temperature and high-pressure environments.

[0025] 3. The present invention injects a lightly doped rectangular P- layer at the bottom of the N drift layer as a concentration gradient buffer between the lower P+ layer and the N drift layer, reducing the impurity mutation. In this way, it effectively suppresses the minority carrier injection at high temperatures, shortens the reverse recovery time of the body diode, reduces the switching loss, and reduces the high-temperature leakage current, improving the dynamic performance.

[0026] 4. The present invention deposits rectangular polysilicon layers on both sides of the N substrate layer to replace the traditional metal-semiconductor direct contact. The polysilicon layer alleviates the mismatch of the thermal expansion coefficient, avoids cracking at the metal / semiconductor interface during high-temperature cycling, and maintains the stability of the ohmic contact. At the same time, it increases the heat dissipation area of the drain, reduces the thermal resistance, and improves the power density.

[0027] 5. The present invention extends the lateral expansion path of the depletion region through the recessed N substrate structure, dispersing the electric field concentration at the drain end. Cooperating with the deposited triangular polysilicon layer to fill the side wall of the recess, it further increases the heat dissipation area of the drain. And the two work together to reduce the peak electric field at the drain end, improve the breakdown voltage, and at the same time optimize the high-temperature heat dissipation ability, suitable for high-power application scenarios.

[0028] 6. The present invention adopts a matching radian design for the bent N substrate and the arc-shaped drain, eliminating the stress concentration point of the traditional right-angle structure, avoiding interface cracking caused by high-temperature thermal expansion, and synchronously optimizing the current distribution at the arc-shaped junction, reducing the generation of local Joule heat, and improving the structural integrity and long-term reliability of the device under extreme temperature cycling. Description of the Drawings

[0029] Figure 1 Schematic diagram of Embodiment 1 in the present invention;

[0030] Figure 2 Schematic diagram of Embodiment 2 in the present invention;

[0031] Figure 3 Schematic diagram of Embodiment 3 in the present invention;

[0032] Figure 4 Schematic diagram of Embodiment 4 in the present invention;

[0033] Figure 5 Schematic diagram of Embodiment 5 in the present invention;

[0034] Figure 6 Schematic diagram of Embodiment 6 in the present invention.

[0035] In the figure: 1, drain; 2, gate; 3, source; 4, N substrate layer; 5, N drift layer; 6, side P+ layer; 7, lower P+ layer; 8, P well layer; 9, N well layer; 10, N-type fan-shaped layer; 11, rectangular P- layer; 12, rectangular polysilicon layer; 13, triangular polysilicon layer; 41, recessed N substrate; 42, bent N substrate; 101, arc-shaped drain. Detailed implementation manners

[0036] To make the technical solution of the present invention clearer, the following further describes the present invention in detail with reference to the accompanying drawings and specific embodiments.

[0037] As Figure 1-6 shown, a preparation method of a high-temperature resistant VDMOS power transistor for extreme environments includes the following steps:

[0038] Step 1: The N substrate layer 4 forms a recessed N substrate 41 or a bent N substrate 42 structure through an etching process, and an N drift layer 5 is epitaxially grown on the substrate; forming a recessed or bent N substrate structure (recessed N substrate 41 / bent N substrate 42) through etching extends the lateral expansion path of the depletion region and disperses the electric field concentration ( Figure 5-6 ); the matching of the curvature of the bent substrate and the arc-shaped drain eliminates the right-angle stress point and avoids interface cracking caused by high-temperature thermal expansion (Embodiment 6). The epitaxially grown N drift layer 5 provides the main voltage-resistant region.

[0039] Step 2: P-type ion implantation is performed between the source 3 and the lower P+ layer 7 to form an axisymmetric "concave" shape profile that matches the N well layer 9, and the axisymmetric "concave" shape side P+ layer 6 and the N well layer 9 form a deep junction structure ( Figure 1 ), enhancing the depletion region expansion, reducing the parasitic resistance (Rsb) of the P well layer 8, and blocking the conduction path of the parasitic bipolar transistor (Embodiment 1). The groove structure provides an adaptation space for the subsequent inverted L-shaped source;

[0040] Step 3: Inject N-type ions into the top regions near the P-well layer 8 on both sides of the N-drift layer 5 to form an N-type fan-shaped layer 10; inject a gradually doped N-type fan-shaped layer 10 ( Figure 2 ), the fan-shaped profile of which disperses the electric field peak in the JFET region of the conventional VDMOS, avoids the channel current being squeezed, and at the same time optimizes the electric field distribution to prevent local breakdown (Example 2).

[0041] Step 4: Inject P-type ions into both sides of the N-drift layer 5 and below the lower P+ layer 7 to form a rectangular P- layer 11; inject a lightly doped rectangular P- layer 11 ( Figure 3 ), as a concentration gradient buffer zone, to reduce the impurity mutation between the N-drift layer 5 and the lower P+ layer 7. Suppress the injection of minority carriers at high temperatures and shorten the reverse recovery time (trr) of the body diode (Example 3).

[0042] Step 5: Deposit a triangular polysilicon layer 13 on both sides of the recessed N-substrate 41 or synchronously prepare an arc-shaped drain 101 for the curved N-substrate 42; in the recessed N-substrate 41, deposit a triangular polysilicon layer 13 to fill the sidewalls ( Figure 5 ), increase the heat dissipation area of the drain, and cooperate with the recessed structure to reduce the electric field peak at the drain end (Example 5). In the curved N-substrate 42, synchronously prepare an arc-shaped drain 101 with a curvature matching the substrate curvature ( Figure 6 ), eliminate stress concentration, and optimize the current distribution to reduce Joule heat (Example 6).

[0043] Step 6: First deposit a longitudinal part to fill the recessed area of the side P+ layer 6 and the N-well layer 9, and then form a transverse part to cover the surface of the P-well layer 8; first deposit a longitudinal part to fill the "concave"-shaped recessed area, increase the contact area between the source 3 and the P+ region, and reduce the contact resistance; then form a transverse part to cover the surface of the P-well layer 8 to provide a low-resistance transverse conduction path (Example 1). The inverted L-shaped structure is perfectly adapted to the concave-shaped P+ / N-well.

[0044] Step 7: Deposit the drain 1 and the source 3 on the surface of the semiconductor epitaxial layer by vapor deposition. Form the drain 1 and the source 3 on the semiconductor surface by vapor deposition. Combining the aforementioned polysilicon buffer layer (Step 5) and the arc design (Example 6), avoid the cracking of the metal-semiconductor interface during high-temperature cycling and maintain the reliability of the ohmic contact.

[0045] Example 1

[0046] As Figure 1As shown, according to one aspect of the present invention, a high-temperature resistant VDMOS power transistor for extreme environments is provided, which is composed of a plurality of juxtaposed MOS cells. A single MOS cell includes a drain 1, a semiconductor epitaxial layer, a gate 2, and a source 3. The semiconductor epitaxial layer includes an N substrate layer 4, an N drift layer 5, a lower P+ layer 7, a P well layer 8, and an N well layer 9. On both sides of a single MOS cell and between the source 3 and the lower P+ layer 7, a side P+ layer 6 is formed by ion implantation; the side P+ layer 6 and the N well layer 9 are axially symmetrically distributed, and the cross-sectional profile after the combination of the side P+ layer 6 and the N well layer 9 is in the shape of an inverted "U"; the cross-sectional profile of the source 3 is in the shape of an inverted "L", where the source 3 includes a horizontal part and a vertical part, and the vertical part of the source 3 is adapted to the sunken part after the combination of the side P+ layer 6 and the N well layer 9. The side P+ layer 6 and the N well layer 9 form an axially symmetric inverted "U" shape, and the depletion region expansion is enhanced through the deep junction structure of P+ / N well, reducing the parasitic resistance (Rsb) of the P well layer (8), suppressing the conduction of the parasitic bipolar transistor, and avoiding high-temperature latch-up.

[0047] At the same time, the vertical part of the inverted L-shaped source 3 fills the inverted "U" sunken area, expanding the contact area between the source and the P+ region, reducing the source contact resistance; the horizontal part covers the surface of the P well, optimizing the carrier lateral conduction path and enhancing the current capacity.

[0048] Embodiment 2

[0049] As Figure 2 shown, on both sides of the N drift layer 5 in a single MOS cell and in the top region close to the P well layer 8, an N-type fan-shaped layer 10 is formed by ion implantation. The N-type fan-shaped layer 10 is located on both sides of the top of the P well and adopts a gradually doped fan-shaped implantation to weaken the squeezing effect of the JFET effect on the channel current in the traditional VDMOS and broaden the carrier channel. The fan-shaped profile disperses the electric field peak value, avoids local breakdown, and improves the high-temperature reliability.

[0050] Embodiment 3

[0051] As Figure 3 shown, on both sides of the N drift layer 5 in a single MOS cell and below the lower P+ layer 7, a rectangular P- layer 11 is formed by ion implantation, and the rectangular P- layer 11 is in direct contact with the lower P+ layer 7. The rectangular P- layer 11 is closely attached to the lower P+ layer 7 to serve as a lightly doped buffer zone, reducing the impurity concentration gradient between the N drift layer 5 and the lower P+ layer 7. At high temperatures, it suppresses the injection of minority carriers, shortens the reverse recovery time (trr) of the body diode, and reduces the switching loss.

[0052] Embodiment 4

[0053] As Figure 4As shown, rectangular polysilicon layers 12 are deposited on both sides of the N substrate layer 4 in a single MOS cell. The rectangular polysilicon layers 12 are in ohmic contact with the drain 1. The rectangular polysilicon layers 12 are deposited on both sides of the N substrate 4, and the polysilicon forms an ohmic contact with the metal drain 1, replacing the traditional direct metal-semiconductor contact. The polysilicon layer alleviates the problem of the mismatch in the coefficient of thermal expansion, avoids cracking of the contact interface under high-temperature cycling, and improves thermal stability.

[0054] Example 5

[0055] As Figure 5 shown, the N substrate layer 4 further includes a recessed N substrate 41, and the junction of the recessed N substrate 41 and the N drift layer 5 is recessed; triangular polysilicon layers 13 are deposited on both sides of the recessed N substrate 41 in a single MOS cell, and the triangular polysilicon layers 13 are in ohmic contact with the drain 1. In the recessed N substrate 41 and the triangular polysilicon layer 13, the recessed structure extends the lateral expansion path of the depletion region and disperses the electric field concentration; the triangular polysilicon layer 13 fills the side walls of the recess, increasing the heat dissipation area of the drain. The two work together to reduce the peak electric field at the drain end, improve the breakdown voltage (BVdss) and the high-temperature heat dissipation ability.

[0056] Example 6

[0057] As Figure 6 shown, the N substrate layer 4 further includes a curved N substrate 42, and the drain 1 further includes a curved drain 101. The junctions of the curved N substrate 42 and the N drift layer 5 and the junction of the curved N substrate 42 and the curved drain 101 are both recessed arc-shaped, and the arc-shaped curvatures of the two junctions are the same. The curved N substrate 42 and the curved drain 101 have a matching curvature, and the arc-shaped junction eliminates the stress concentration points of the traditional right-angle structure, avoiding interface cracks caused by thermal expansion differences at high temperatures. The curved drain 101 synchronously optimizes the current distribution and reduces local Joule heat.

[0058] The above-described embodiments merely represent several implementation manners of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several deformations and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the appended claims.

Claims

1. A high-temperature resistant VDMOS power transistor for extreme environments, which is composed of a plurality of mutually juxtaposed MOS cells. A single MOS cell includes a drain (1), a semiconductor epitaxial layer, a gate (2), and a source (3). The semiconductor epitaxial layer includes an N substrate layer (4), an N drift layer (5), a lower P+ layer (7), a P well layer (8), and an N well layer (9), and is characterized in that: On both sides of a single MOS cell and between the source electrode (3) and the lower P+ layer (7), side P+ layers (6) are formed by ion implantation; the side P+ layers (6) and the N-well layer (9) are axially symmetrically distributed, and the cross-sectional profile after the combination of the side P+ layers (6) and the N-well layer (9) is in the shape of a "concave" character; The cross-sectional profile of the source electrode (3) is in the shape of an inverted "L" character, where the source electrode (3) includes a horizontal part and a vertical part, and the vertical part of the source electrode (3) is adapted to the sunken part after the combination of the side P+ layer (6) and the N-well layer (9).

2. The high-temperature resistant VDMOS power transistor for extreme environments according to claim 1, characterized in that: On both sides of the N-drift layer (5) in a single MOS cell and in the top region close to the P-well layer (8), N-type fan-shaped layers (10) are formed by ion implantation.

3. The high-temperature resistant VDMOS power transistor for extreme environments according to claim 1, wherein: On both sides of the N-drift layer (5) in a single MOS cell and below the lower P+ layer (7), rectangular P- layers (11) are formed by ion implantation, and the rectangular P- layers (11) are in direct contact with the lower P+ layer (7).

4. The high-temperature resistant VDMOS power transistor for extreme environments according to claim 1, characterized in that: Rectangular polysilicon layers (12) are deposited on both sides of the N-substrate layer (4) in a single MOS cell, and the rectangular polysilicon layers (12) are in ohmic contact with the drain electrode (1).

5. The high-temperature resistant VDMOS power transistor for extreme environments according to claim 1, wherein: The N-substrate layer (4) further includes a sunken N-substrate (41), and the junction of the sunken N-substrate (41) and the N-drift layer (5) is sunken; Triangular polysilicon layers (13) are deposited on both sides of the sunken N-substrate (41) in a single MOS cell, and the triangular polysilicon layers (13) are in ohmic contact with the drain electrode (1).

6. The high-temperature resistant VDMOS power transistor for extreme environments according to claim 1, wherein: The N-substrate layer (4) further includes a curved N-substrate (42), and the drain electrode (1) further includes an arc-shaped drain electrode (101).

7. The high-temperature resistant VDMOS power transistor for extreme environments according to claim 6, characterized in that: The junctions of the curved N-substrate (42) and the N-drift layer (5), and the junctions of the curved N-substrate (42) and the arc-shaped drain electrode (101) are both sunken arc-shaped, and the arc-shaped radian of the two junctions is the same.

8. A preparation method for a high-temperature resistant VDMOS power transistor used in extreme environments, characterized in that, Applied to the VDMOS power transistor according to any one of claims 1-7, the preparation method of the high-temperature-resistant VDMOS power transistor for extreme environments includes the following steps: S1. The N-substrate layer (4) forms a sunken N-substrate (41) or a curved N-substrate (42) structure through an etching process, and an N-drift layer (5) is epitaxially grown on the substrate; S2. P-type ion implantation is carried out between the source electrode (3) and the lower P+ layer (7) to form an axially symmetric "concave" character-shaped profile that matches the N-well layer (9); S3. N-type ions are implanted in the top region close to the P-well layer (8) on both sides of the N-drift layer (5) to form N-type fan-shaped layers (10); S4. P-type ions are implanted on both sides of the N-drift layer (5) and below the lower P+ layer (7) to form rectangular P- layers (11); S5. Triangular polysilicon layers (13) are deposited on both sides of the sunken N-substrate (41) or an arc-shaped drain electrode (101) is synchronously prepared for the curved N-substrate (42); S6. First, the longitudinal part is deposited to fill the sunken area of the side P+ layer (6) and the N-well layer (9), and then the horizontal part is formed to cover the surface of the P-well layer (8); S7. The drain electrode (1) and the source electrode (3) are deposited on the surface of the semiconductor epitaxial layer by chemical vapor deposition.

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