Semiconductor structure and forming method thereof

Abstract

According to the semiconductor structure and the forming method thereof, in the semiconductor structure, a gate structure comprises a gate electrode layer and a gate dielectric layer, and the gate dielectric layer wraps the bottom and the side wall of the gate electrode layer; the source-drain doping layer is located in the fin parts on the two sides of the gate structure; the source-drain interconnection layer is embedded in the substrate from one side of the bottom surface of the substrate and is connected with the source-drain doping layer; the gate dielectric layer wraps the bottom and the side wall of the gate electrode layer, and meanwhile, the source-drain interconnection layer is embedded in the substrate from one side of the bottom surface of the substrate and is connected with the source-drain doping layer, so that the gate dielectric layer can isolate the source-drain interconnection layer from the gate electrode layer; the problem of short circuit between the source-drain interconnection layer and the gate electrode layer caused by position offset or critical dimension floating of the source-drain interconnection layer is reduced, and the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid development of the semiconductor integrated circuit (IC) industry, semiconductor technology has continuously advanced towards smaller process nodes driven by Moore's Law, making integrated circuits develop in the direction of smaller volume, higher circuit precision, and higher circuit complexity.

[0003] In order to better meet the requirements of proportional reduction of device sizes, semiconductor processes have gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as fin field effect transistors (FinFETs). Among them, in a fin field effect transistor, the gate surrounds the fin-shaped channel on three sides. Compared with a planar transistor, the gate of a fin field effect transistor has a stronger control ability over the channel and can better suppress the short-channel effect.

[0004] In a semiconductor integrated circuit, a metal interconnect structure is used to connect different semiconductor devices and plays a role in transmitting signals. However, a short-circuit problem easily occurs between the metal interconnect structure and the gate structure. Therefore, the performance of current semiconductor structures still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same to improve the performance of the semiconductor structure.

[0006] To solve the above problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate including a substrate and a fin portion located on the substrate; a gate structure located on the substrate and spanning the fin portion, the gate structure covering a part of the top and part of the sidewalls of the fin portion, the gate structure including a gate electrode layer and a gate dielectric layer, the gate dielectric layer wrapping the bottom and sidewalls of the gate electrode layer; source / drain doping layers located in the fin portions on both sides of the gate structure; and a source / drain interconnect layer embedded in the substrate from one side of the bottom surface of the substrate and connecting the source / drain doping layers.

[0007] Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate, including a substrate and fins located on the substrate, a gate structure is formed on the substrate and spans the fins, the gate structure covers a part of the top and a part of the sidewalls of the fins, the gate structure includes a gate electrode layer and a gate dielectric layer, and the gate dielectric layer wraps the bottom and sidewalls of the gate electrode layer; source-drain doping layers are formed in the fins on both sides of the gate structure; from one side of the bottom surface of the substrate, a source-drain interconnect layer is formed and embedded in the substrate and connected to the source-drain doping layers.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] In the semiconductor structure provided by the embodiment of the present invention, the gate structure includes a gate electrode layer and a gate dielectric layer, the gate dielectric layer covers the bottom and sidewalls of the gate electrode layer, the source-drain doping layers are located in the fins on both sides of the gate structure, and the source-drain interconnect layer is embedded in the substrate from one side of the bottom surface of the substrate and connected to the source-drain doping layers; since the gate dielectric layer covers the bottom and sidewalls of the gate electrode layer, and at the same time the source-drain interconnect layer is embedded in the substrate from one side of the bottom surface of the substrate and connected to the source-drain doping layers, the gate dielectric layer can isolate the source-drain interconnect layer and the gate electrode layer, reducing the short-circuit problem between the source-drain interconnect layer and the gate electrode layer caused by the position offset or critical dimension floating of the source-drain interconnect layer, and improving the performance of the semiconductor structure.

[0010] Optionally, the bottom of the source-drain doping layer is lower than the bottom of the gate structure, that is, the bottom depth of the source-drain doping layer is larger, which is beneficial to making the width of the part of the source-drain doping layer opposite to the sidewall of the gate structure more consistent, beneficial to improving the sidewall perpendicularity of the part opposite to the sidewall of the gate structure, correspondingly improving the uniformity of the lateral distance between the source-drain doping layer and the gate structure, thereby reducing the equivalent capacitance between the gate structure and the source-drain doping layer, increasing the signal transmission speed, and further improving the performance of the semiconductor structure.

[0011] In the method for forming a semiconductor structure provided by the embodiment of the present invention, the gate structure includes a gate electrode layer and a gate dielectric layer, the gate dielectric layer wraps the bottom and sidewalls of the gate electrode layer, source-drain doping layers are formed in the fins on both sides of the gate structure, and from one side of the bottom surface of the substrate, a source-drain interconnect layer is formed and embedded in the substrate and connected to the source-drain doping layers; since the gate dielectric layer covers the bottom and sidewalls of the gate electrode layer, and at the same time the source-drain interconnect layer is embedded in the substrate from one side of the bottom surface of the substrate and connected to the source-drain doping layers, the gate dielectric layer can isolate the source-drain interconnect layer and the gate electrode layer, reducing the short-circuit problem between the source-drain interconnect layer and the gate electrode layer caused by the position offset or critical dimension floating of the source-drain interconnect layer, and improving the performance of the semiconductor structure.

[0012] Optionally, the bottom of the source-drain doped layer is lower than the bottom of the gate structure, which is beneficial to making the width of the portion of the source-drain doped layer opposite to the side wall of the gate structure more consistent, and is beneficial to improving the verticality of the side wall of the portion opposite to the side wall of the gate structure, and correspondingly improving the uniformity of the lateral distance between the source-drain doped layer and the gate structure, thereby reducing the equivalent capacitance between the gate structure and the source-drain doped layer, improving the signal transmission speed, and further improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figures 1 to 3 It is a schematic diagram of a semiconductor structure;

[0014] Figure 4 and Figure 5 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0015] Figures 6 to 21 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0016] At present, the performance of semiconductor structures still needs to be improved. Now, combined with a method for forming a semiconductor structure, the reasons why the performance of semiconductor structures needs to be improved are analyzed.

[0017] Figures 1 to 3 It is a schematic diagram of a semiconductor structure.

[0018] refer to Figures 1 to 3 , Figure 1 It is a cross-sectional view at the position of the fin along the extending direction of the fin.

[0019] The semiconductor structure includes: a substrate 10; a fin 11, which is located on the substrate 10; a gate structure, which is located on the substrate 10 and spans the fin 11, the gate structure covers part of the top and part of the sidewall of the fin 11, the gate structure includes a gate electrode layer 12 and a gate dielectric layer 15, the gate dielectric layer 15 wraps the bottom and sidewall of the gate electrode layer 12; a source-drain doped layer 13, which is located in the fin 11 on both sides of the gate structure, and a source-drain interconnection layer 14, which connects the source-drain doped layer 13 from the top of the substrate 10.

[0020] like Figure 2 and Figure 3 As shown, Figure 2 and Figure 3 is a cross-sectional view at the fin position along the extending direction of the fin, and Figure 2 It is a schematic diagram showing the position shift of the source-drain interconnection layer. Figure 3 It is a schematic diagram showing when a critical dimension of a source-drain interconnection layer deviates.

[0021] When forming the source / drain interconnect layer 14 on top of the substrate 10, due to the scaling down of semiconductor process nodes, it is easy to cause the position offset or critical dimension floating of the source / drain interconnect layer 14, resulting in the electrical connection between the source / drain interconnect layer 14 and the gate electrode layer 12, and triggering the short - circuit problem between the source / drain interconnect layer 14 and the gate electrode layer 12.

[0022] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, including a substrate and fins located on the substrate; a gate structure, located on the substrate and spanning the fins, the gate structure covering a part of the top and part of the side walls of the fins, the gate structure including a gate electrode layer and a gate dielectric layer, the gate dielectric layer wrapping the bottom and side walls of the gate electrode layer; source / drain doping layers, located in the fins on both sides of the gate structure; source / drain interconnect layers, embedded in the substrate from one side of the bottom surface of the substrate and connecting the source / drain doping layers.

[0023] In the semiconductor structure provided by the embodiment of the present invention, the gate structure includes a gate electrode layer and a gate dielectric layer, the gate dielectric layer covering the bottom and side walls of the gate electrode layer, the source / drain doping layers being located in the fins on both sides of the gate structure, and the source / drain interconnect layers being embedded in the substrate from one side of the bottom surface of the substrate and connecting the source / drain doping layers; because the gate dielectric layer covers the bottom and side walls of the gate electrode layer, and at the same time the source / drain interconnect layers are embedded in the substrate from one side of the bottom surface of the substrate and connect the source / drain doping layers, the gate dielectric layer can isolate the source / drain interconnect layers and the gate electrode layer, reducing the short - circuit problem between the source / drain interconnect layer and the gate electrode layer caused by the position offset or critical dimension floating of the source / drain interconnect layer, and improving the performance of the semiconductor structure.

[0024] In order to make the above - mentioned objects, features and advantages of the embodiments of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0025] Reference Figure 4 and Figure 5 , Figure 4 and Figure 5 are schematic structural diagrams of an embodiment of the semiconductor structure of the present invention.

[0026] Among them, Figure 4 is a cross - sectional view along the extending direction of the fins at the fin position, Figure 5 is a cross - sectional view along the direction perpendicular to the extending direction of the fins at the source / drain doping layer position.

[0027] In this embodiment, the semiconductor structure includes: a substrate 100, the substrate 100 includes a substrate 101 and fin portions 102 located on the substrate 101; a gate structure 110, located on the substrate 101 and spanning the fin portions 102, the gate structure 110 covering a portion of the top and a portion of the sidewalls of the fin portions 102, the gate structure 110 including a gate electrode layer 111 and a gate dielectric layer 112, the gate dielectric layer 112 covering the bottom and sidewalls of the gate electrode layer 111; source / drain doping layers 120, located in the fin portions 102 on both sides of the gate structure 110; and source / drain interconnect layers 130, embedded in the substrate 100 from one side of the bottom surface of the substrate 101 and connecting the source / drain doping layers 120.

[0028] The substrate 100 is used to provide an operating basis for the formation process of the semiconductor structure.

[0029] In this embodiment, the substrate 100 is used to form a field-effect transistor. As an example, the substrate 100 is used to form a fin field-effect transistor.

[0030] In this embodiment, the substrate 101 is a silicon substrate. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0031] The fin portions 102 provide a process basis for the subsequent formation of effective fin portions.

[0032] In this embodiment, the material of the fin portions 102 includes silicon. In other embodiments, the material of the fin portions can also include other materials such as germanium, silicon germanide, or III-V semiconductor materials.

[0033] The gate structure 110 is used to adjust or control the channel current of the field-effect transistor.

[0034] The fin portions 102 covered by the gate structure 110 are used to provide a conductive channel when the semiconductor device is operating.

[0035] The gate structure 110 includes a gate electrode layer 111 and a gate dielectric layer 112. Since the gate dielectric layer 112 covers the bottom and sidewalls of the gate electrode layer 111, and at the same time the source / drain interconnect layers 130 are embedded in the substrate 100 from one side of the bottom surface of the substrate 101 and connect the source / drain doping layers 120, the gate dielectric layer 112 can isolate the source / drain interconnect layers 130 and the gate electrode layer 111, reducing the short-circuit problem between the source / drain interconnect layers 130 and the gate electrode layer 111 caused by the position offset or critical dimension floating of the source / drain interconnect layers 130. As an example, the gate structure 110 is a metal gate structure.

[0036] The gate electrode layer 111 is used to control the opening or closing of the conductive channel.

[0037] The material of the gate electrode layer 111 is a conductive material, and the material of the gate electrode layer 111 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN, and TiAlC.

[0038] The gate electrode layer 111 may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer 111 may only include a work function layer. Among them, the work function layer is used to adjust the threshold voltage of the transistor.

[0039] The gate dielectric layer 112 is used to isolate the gate electrode layer 111 from the conductive channel, so as to realize the control of the gate structure 110 over the channel current.

[0040] The material of the gate dielectric layer 112 is an insulating material, and the material of the gate dielectric layer 112 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0041] Therefore, the gate dielectric layer 112 includes a high-k gate dielectric layer. The material of the high-k gate dielectric layer is a high-k dielectric material, where the high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0042] In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer. As an example, the material of the gate oxide layer can be silicon oxide.

[0043] The source / drain doping layer 120 is used as a source region or a drain region to provide carriers during device operation.

[0044] In this embodiment, the bottom of the source / drain doping layer 120 is lower than the bottom of the gate structure 110.

[0045] The bottom of the source / drain doping layer 120 is lower than the bottom of the gate structure 110, which is conducive to increasing the distance between the source / drain interconnect layer 130 and the gate structure 110, thereby helping to further reduce the short-circuit problem between the source / drain interconnect layer 130 and the gate structure 110 caused by the position offset or critical dimension fluctuation of the source / drain interconnect layer 130.

[0046] Moreover, the morphology of the source / drain doping layer 120 is usually affected by its bottom depth. For example, when the shape of the source / drain doping layer 120 is U-shaped, if the bottom of the source / drain doping layer 120 is lower than the bottom of the gate structure 110, the sidewall perpendicularity of the portion of the source / drain doping layer 120 facing the sidewall of the gate structure 110 is relatively low, which easily leads to a relatively low width consistency of the portion of the source / drain doping layer 120 facing the sidewall of the gate structure 110 (please refer to Figure 1 the situation shown by the dashed circle in

[0047] ), thereby affecting the uniformity of the lateral distance between the source / drain doping layer 120 and the gate structure 110.

[0048] The vertical distance w from the bottom of the source / drain doping layer 120 to the bottom of the gate structure 110 is 10 nm to 20 nm.

[0049] The vertical distance w from the bottom of the source / drain doping layer 120 to the bottom of the gate structure 110 should not be too large or too small. If the vertical distance w from the bottom of the source / drain doping layer 120 to the bottom of the gate structure 110 is too large, it is easy to cause the source / drain doping layer 120 to be too large in volume, thus easily leading to the risk of merging of adjacent source / drain doping layers 120; if the vertical distance w from the bottom of the source / drain doping layer 120 to the bottom of the gate structure 110 is too small, it is easy to result in a poor effect of improving the uniformity of the lateral distance between the source / drain doping layer 120 and the gate structure 110. Therefore, the vertical distance w from the bottom of the source / drain doping layer 120 to the bottom of the gate structure 110 is 10 nm to 20 nm.

[0050] The source / drain doping layer 120 can be doped with P-type ions or N-type ions, and the doping ion type of the source / drain doping layer 120 is determined by the device function.

[0051] In this embodiment, the source / drain interconnect layer 130 is used to achieve signal transmission and current conduction, connect the source / drain doping layer 120 and the back-end interconnect structure, thereby realizing various circuit functions and constituting a complex electronic system, so as to meet diverse application requirements. Specifically, the source / drain interconnect layer 130 is the zero-th interconnect layer (M0).

[0052] Specifically, the source-drain interconnect layer 130 is located between adjacent fin portions 102.

[0053] By locating the source-drain interconnect layer 130 between adjacent fin portions 102, it is beneficial to reduce the damage to the fin portions 102, so that there are still sufficient fin portions 102 at the bottom of the source-drain doping layer 120, thereby avoiding excessive resistance at the connection between the source-drain doping layer 120 and the fin portions 102; moreover, it is also beneficial to reduce the shielding of the source-drain interconnect layer 130, thus facilitating the subsequent electrical connection of the source-drain interconnect layer 130 to the back-end interconnect structure.

[0054] It should be noted that the width of the fin portion 102 at the bottom of the source-drain doping layer 120 is smaller than the width of the fin portion 102 at the bottom of the gate structure 110, which is beneficial to increase the contact area between the source-drain interconnect layer 130 and the source-drain doping layer 120, and further beneficial to reduce the contact resistance.

[0055] The difference between the width of the fin portion 102 at the bottom of the source-drain doping layer 120 and the width of the fin portion 102 at the bottom of the gate structure 110 should not be too small or too large. If the width difference is too large, the structural stability of the fin portion 102 is likely to be poor; if the width difference is too small, the effect of increasing the contact area between the source-drain interconnect layer 130 and the source-drain doping layer 120 is not good. Therefore, the width of the fin portion 102 at the bottom of the source-drain doping layer 120 is greater than or equal to 50% of the width of the fin portion 102 at the bottom of the gate structure 110.

[0056] The material of the source-drain interconnect layer 130 is a conductive material, and the material of the source-drain interconnect layer 130 includes W, Co, Ru, etc.

[0057] It should be noted that since the bottom of the source-drain doping layer 120 is lower than the bottom of the gate structure 110, the overlapping height d of the source-drain interconnect layer 130 and the source-drain doping layer 120 in the longitudinal direction is less than or equal to the vertical distance w from the bottom of the source-drain doping layer 120 to the bottom of the gate structure 110, thereby further improving the isolation effect between the source-drain interconnect layer 130 and the gate electrode layer 111, and correspondingly increasing the process window for forming the source-drain interconnect layer 130.

[0058] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 6 to 21 It is a schematic structural diagram corresponding to each step in an embodiment of the method for forming the semiconductor structure of the present invention.

[0059] Refer to Figure 6 and Figure 7 , Figure 6 is a cross-sectional view along the extending direction of the fin portion at the gate structure position, Figure 7It is a cross-sectional view perpendicular to the extending direction of the fin at the position of the source / drain doping layer.

[0060] A substrate 500 is provided, and the substrate 500 includes a substrate 501, on which discrete fins 502 are formed.

[0061] The substrate 500 is used to provide a process platform for subsequent process steps.

[0062] In this embodiment, the substrate 500 is used to form a field-effect transistor. As an example, the substrate 500 is used to form a fin field-effect transistor.

[0063] In this embodiment, the substrate 501 is a silicon substrate. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0064] The fin 502 provides a process basis for forming an effective fin subsequently.

[0065] In this embodiment, the material of the fin 502 includes silicon. In other embodiments, the material of the fin can also include other materials such as germanium, silicon germanide, or III-V semiconductor materials.

[0066] Continuing to refer to Figure 6 , in this embodiment, a gate structure 510 is formed on the substrate 500 across the fin 502, and the gate structure 510 covers part of the top and part of the sidewalls of the fin 502.

[0067] The gate structure 510 is used to adjust or control the channel current of the field-effect transistor.

[0068] The fin 502 covered by the gate structure 510 is used to provide a conductive channel when the semiconductor device is operating.

[0069] The gate structure 510 includes a gate electrode layer 511 and a gate dielectric layer 512. Since the gate dielectric layer 512 covers the bottom and sidewalls of the gate electrode layer 511, and at the same time the source / drain interconnect layer 530 is embedded in the substrate 500 from one side of the bottom surface of the substrate 501 and connects the source / drain doping layer 520, the gate dielectric layer 512 can isolate the source / drain interconnect layer 530 and the gate electrode layer 511, reducing the short-circuit problem between the source / drain interconnect layer 530 and the gate electrode layer 511 caused by the position offset or critical dimension fluctuation of the source / drain interconnect layer 530.

[0070] As an example, the gate structure 510 is a metal gate structure. The gate electrode layer 511 is used to control the opening or closing of the conductive channel.

[0071] The material of the gate electrode layer 511 is a conductive material, and the material of the gate electrode layer 511 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN, and TiAlC.

[0072] The gate electrode layer 511 may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer 511 may only include a work function layer. Among them, the work function layer is used to adjust the threshold voltage of the transistor.

[0073] The gate dielectric layer 512 is used to isolate the gate electrode layer 511 from the conductive channel, so as to realize the control of the channel current by the gate structure 510.

[0074] The material of the gate dielectric layer 512 is an insulating material, and the material of the gate dielectric layer 512 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0075] Therefore, the gate dielectric layer 512 includes a high-k gate dielectric layer. The material of the high-k gate dielectric layer is a high-k dielectric material, where the high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0076] In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer. As an example, the material of the gate oxide layer can be silicon oxide.

[0077] Continuing to refer to Figure 6 and Figure 7 , source / drain doping layers 520 are formed in the fins 502 on both sides of the gate structure 510.

[0078] The source / drain doping layers 520 are used as source regions or drain regions to provide carriers during device operation.

[0079] In this embodiment, the bottom of the source / drain doping layer 520 is lower than the bottom of the gate structure 510.

[0080] The bottom of the source / drain doping layer 520 being lower than the bottom of the gate structure 510 is conducive to increasing the distance between the source / drain interconnect layer 530 and the gate structure 510, thereby helping to further reduce the short-circuit problem between the source / drain interconnect layer 530 and the gate structure 510 caused by the position offset or critical dimension fluctuation of the source / drain interconnect layer 530.

[0081] Moreover, the morphology of the source-drain doping layer 520 is usually affected by its bottom depth. For example, when the shape of the source-drain doping layer 520 is U-shaped, if the bottom of the source-drain doping layer 520 is lower than the bottom of the gate structure 510, the sidewall perpendicularity of the part of the source-drain doping layer 520 facing the sidewall of the gate structure 510 is relatively low, which easily leads to a relatively low width consistency of the part of the source-drain doping layer 520 facing the sidewall of the gate structure 510 (please refer to the situation shown by the dotted circle in Figure 1 ), thus affecting the uniformity of the lateral distance between the source-drain doping layer 520 and the gate structure 510.

[0082] Therefore, in this embodiment, the bottom of the source-drain doping layer 520 is made lower than the bottom of the gate structure 510, which is beneficial to making the width consistency of the part of the source-drain doping layer 520 facing the sidewall of the gate structure 510 higher, beneficial to improving the sidewall perpendicularity of the part facing the sidewall of the gate structure 510, correspondingly improving the uniformity of the lateral distance between the source-drain doping layer 520 and the gate structure 510, thereby reducing the equivalent capacitance between the gate structure 510 and the source-drain doping layer 520, increasing the signal transmission speed, and further improving the performance of the semiconductor structure.

[0083] The vertical distance W from the bottom of the source-drain doping layer 520 to the bottom of the gate structure 510 is 10 nanometers to 20 nanometers.

[0084] The vertical distance W from the bottom of the source-drain doping layer 520 to the bottom of the gate structure 510 should not be too large or too small. If the vertical distance W from the bottom of the source-drain doping layer 520 to the bottom of the gate structure 510 is too large, it is easy to cause the source-drain doping layer 520 to be too large in volume, thus easily leading to the risk of merging of adjacent source-drain doping layers 520; if the vertical distance W from the bottom of the source-drain doping layer 520 to the bottom of the gate structure 510 is too small, it is easy to result in poor effect of improving the uniformity of the lateral distance between the source-drain doping layer 520 and the gate structure 510. Therefore, the vertical distance W from the bottom of the source-drain doping layer 520 to the bottom of the gate structure 510 is 10 nanometers to 20 nanometers.

[0085] The source-drain doping layer 520 can be doped with P-type ions or N-type ions, and the doping ion type of the source-drain doping layer 520 is determined by the device function.

[0086] With reference to Figures 8 to 19 , among them, Figure 8 , Figure 10 , Figure 12 , Figure 14 , Figure 16 and Figure 18 are cross-sectional views based on Figure 6 , Figure 9 , Figure 11, Figure 13 , Figure 15 , Figure 17 and Figure 19 are cross-sectional views based on Figure 7 .

[0087] In this embodiment, the method for forming the semiconductor structure further includes: forming a source-drain interconnect layer 530 embedded in the substrate 500 and connected to the source-drain doping layer 520 from one side of the bottom surface of the substrate 501.

[0088] The source-drain interconnect layer 530 is used to implement signal transmission and current guiding, connect the source-drain doping layer 520 to the back-end interconnect structure, thereby realizing various circuit functions and constituting a complex electronic system, so as to meet diverse application requirements. Specifically, the source-drain interconnect layer 530 is the zero-th interconnect layer (M0).

[0089] In this embodiment, since the gate dielectric layer 512 covers the bottom and sidewalls of the gate electrode layer 511, and at the same time the source-drain interconnect layer 530 is embedded in the substrate 500 from one side of the bottom surface of the substrate 501 and connected to the source-drain doping layer 520, the gate dielectric layer 512 can isolate the source-drain interconnect layer 530 and the gate electrode layer 511, reducing the short-circuit problem between the source-drain interconnect layer 530 and the gate electrode layer 511 caused by the position offset or critical dimension fluctuation of the source-drain interconnect layer 530.

[0090] The material of the source-drain interconnect layer 530 is a conductive material, and the material of the source-drain interconnect layer 530 includes W, Co, Ru, etc.

[0091] Specifically, in the step of forming the source-drain interconnect layer 530 embedded in the substrate 500 and connected to the source-drain doping layer 520 from one side of the bottom surface of the substrate 501, the source-drain interconnect layer 530 is located between adjacent fin portions 502.

[0092] By making the source-drain interconnect layer 530 located between adjacent fin portions 502, it is beneficial to reduce the damage to the fin portions 502, so that there is still enough fin portion 502 at the bottom of the source-drain doping layer 520, thereby avoiding excessive resistance at the connection between the source-drain doping layer 520 and the fin portion 502; moreover, it is also beneficial to reduce the shielding of the source-drain interconnect layer 530, so as to facilitate the subsequent electrical connection between the source-drain interconnect layer 530 and the back-end interconnect structure.

[0093] It should be noted that since the bottom of the source-drain doping layer 520 is lower than the bottom of the gate structure 510, in the process of forming the source-drain interconnect layer 530 directly connected to the source-drain doping layer 520, the overlapping height D in the longitudinal direction between the source-drain interconnect layer 530 and the source-drain doping layer 520 (as Figure 21As shown), it is less than or equal to the vertical distance W from the bottom of the source-drain doping layer 520 to the bottom of the gate structure 510, thereby further improving the isolation effect between the source-drain interconnection layer 530 and the gate electrode layer 511, and correspondingly increasing the process window for forming the source-drain interconnection layer 530.

[0094] The steps of forming the source-drain interconnection layer 530 include: combining reference Figures 8 to 17 , from the bottom side of the substrate 501, a groove 550 (such as Figure 16 and Figure 17 shown); combined with reference Figures 18 to 19 , the source-drain interconnection layer 530 is formed in the trench 550 .

[0095] The trench 550 is used to provide a process basis for subsequently forming the source-drain interconnection layer 530 .

[0096] By first forming the groove 550 and then forming the source-drain interconnection layer 530 in the groove 550, the complexity of forming the source-drain interconnection layer 530 is reduced. In addition, it is easy to select a suitable material for the source-drain interconnection layer 530 so that the source-drain interconnection layer 530 can meet the requirements for conductive effects.

[0097] Specifically, the trench 550 penetrates the substrate 501 and is located between adjacent fins 502 .

[0098] It should be noted that when the trench 550 is formed in the substrate 501 , a portion of the width of the fin 502 is removed at the same time.

[0099] Removing a portion of the width of the fin 502 is beneficial to increasing the area of the source-drain doped layer 520 exposed by the groove 550, thereby increasing the contact area between the source-drain interconnection layer 530 and the source-drain doped layer 520, thereby facilitating the reduction of contact resistance. Accordingly, after the groove 550 is formed, the width of the fin 502 at the bottom of the source-drain doped layer 520 is smaller than the width of the fin 502 at the bottom of the gate structure 510.

[0100] The width of the fin 502 at the bottom of the source-drain doped layer 520 is greater than or equal to 50% of the width of the fin 502 at the bottom of the gate structure 510 .

[0101] If the width range of the fin portion 502 removed is too large, it is likely to result in poor structural stability. If the width range of the fin portion 502 removed is too small, it is likely to result in poor effectiveness in increasing the area where the trench 550 exposes the source / drain doped layer 520, thereby resulting in poor effectiveness in increasing the contact area between the source / drain interconnect layer 530 and the source / drain doped layer 520. Therefore, the width of the fin portion 502 at the bottom of the source / drain doped layer 520 is greater than or equal to 50% of the width of the fin portion 502 at the bottom of the gate structure 510.

[0102] Specifically, the process of forming the trench 550 in the substrate 500 includes a dry etching process.

[0103] In this embodiment, the step of forming the source / drain interconnect layer 530 in the trench 550 includes: filling a source / drain interconnect material layer in the trench 550; performing a planarization process on the source / drain interconnect material layer to remove the source / drain interconnect material layer above the bottom surface of the substrate 501, so as to form the source / drain interconnect layer 530 located in the trench 550.

[0104] Continue to refer to Figures 8 to 15 , before forming the source / drain interconnect layer 530, the method for forming the semiconductor structure further includes: forming an insulating layer 540 covering the source / drain doped layer 520 on the top of the substrate 511 (as shown in Figure 14 and Figure 15 ).

[0105] In this embodiment, the insulating layer 540 provides a process platform for forming the source / drain interconnect layer 530. Specifically, through the insulating layer 540, the trench 550 can be formed.

[0106] It should be noted that the material of the insulating layer 540 is a dielectric material, so as to improve process compatibility.

[0107] In this embodiment, the step of forming the insulating layer 540 covering the source / drain doped layer 520 on the top of the substrate 501 includes: referring to Figures 8 to 11 , forming a first interlayer dielectric (ILD) 541 on the top of the substrate 501, the top of the first interlayer dielectric 541 is lower than the top of the source / drain doped layer 520 and covers a part of the sidewall of the source / drain doped layer 520; referring to Figure 12 and Figure 13 , forming a contact etch stop layer (CESL) 543 covering the first interlayer dielectric 541.

[0108] The top of the first dielectric layer 541 is lower than the top of the source-drain doping layer 520, thereby providing a spatial position for forming the stop layer 543, enabling the stop layer 543 to cover a part of the source-drain doping layer 520, so as to control the top surface position of the subsequent source-drain interconnect layer. Since the top of the first dielectric layer 541 defines the position of the subsequent formed stop layer, and thus defines the stop position of the subsequent formed source-drain interconnect layer, the top of the first dielectric layer 541 being lower than the top of the source-drain doping layer 520 can prevent the source-drain interconnect layer from being formed too deeply and damaging the source-drain doping layer 520.

[0109] The first dielectric layer 541 is generally an insulating material, and the material of the first dielectric layer 541 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbonitride, and silicon carbon oxynitride.

[0110] In this embodiment, the material of the first dielectric layer 541 is silicon oxide.

[0111] More specifically, the steps of forming the first dielectric layer 541 include: as Figure 8 and Figure 9 shown, forming a first dielectric material layer 544 on the top of the substrate 501 on the side of the fin 502; as Figure 10 and Figure 11 shown, removing a part of the thickness of the first dielectric material layer 544 to form the first dielectric layer 541 covering a part of the sidewalls of the source-drain doping layer 520.

[0112] By first forming the first dielectric material layer 544 with a larger thickness and then removing a part of the thickness of the first dielectric material layer 544, it is beneficial to improve the top surface flatness and thickness uniformity of the first dielectric layer 541.

[0113] It should be noted that in one embodiment, since the first dielectric material layer 544 is usually formed after forming the pseudo-gate structure, then the pseudo-gate structure is removed to form a gate opening in the first dielectric material layer 544, and then the gate structure 510 is formed in the gate opening. Therefore, the formation of the first dielectric layer 541 has a high compatibility with the traditional process and is beneficial to reducing the cost of forming the first dielectric layer 541.

[0114] In some other embodiments, the first dielectric material layer can also be formed separately.

[0115] In this embodiment, the top of the first dielectric material layer 544 is lower than the top of the gate structure 510, thereby reducing material waste.

[0116] The process of removing a part of the thickness of the first dielectric material layer 544 includes a highly selective dry etching process. The process parameters of the highly selective dry etching process include: the reaction gas includes oxygen and a fluorine-containing gas, the reaction power is 300 watts to 500 watts, the reaction pressure is 10 millitorr to 30 millitorr, and the reaction temperature is 50 degrees Celsius to 80 degrees Celsius.

[0117] For the highly selective dry etching process, the thickness of the first dielectric layer 541 along the normal direction of the substrate 501 can be controlled by controlling the process time.

[0118] In the step of forming the trench 550 from the bottom side of the substrate 501, the stop layer 543 serves to define the process stop position, that is, the bottom surface of the stop layer 543 is exposed by the trench 550.

[0119] Correspondingly, during the formation of the source-drain interconnect layer 530, with the bottom surface of the stop layer 543 as the stop position, the source-drain interconnect layer 530 embedded in the substrate 500 and the first dielectric layer 541 is formed, and the top surface of the source-drain interconnect layer 530 is in contact with the bottom of the stop layer 543.

[0120] The process position of forming the stop layer 543 depends on the thickness of the first dielectric layer 541. That is to say, by controlling the thickness of the first dielectric layer 541, the position of the stop layer 543 covering it can be defined, thereby controlling the height position of the top surface of the source-drain interconnect layer 530 on the side close to the source-drain doping layer 520.

[0121] Since the thickness of the first dielectric layer 541 can be relatively accurately controlled during the process, the position of the stop layer 543 can be correspondingly easily defined, which can simplify the process steps.

[0122] The thickness of the first dielectric layer 541 is one-fourth to one-third of the height of the source-drain doping layer 520.

[0123] The thickness of the first dielectric layer 541 should not be too large or too small. If the thickness of the first dielectric layer 541 is too large, it is likely to cause excessive loss of the source-drain doping layer 520 when forming the source-drain interconnect layer subsequently; if the thickness of the first dielectric layer 541 is too small, it is likely to cause insufficient depth of the subsequent formed source-drain interconnect layer, thereby increasing the risk that the contact surface between the source-drain interconnect layer and the source-drain doping layer is too small or even unable to contact, and further resulting in too large contact resistance. Therefore, the thickness of the first dielectric layer 541 is one-fourth to one-third of the height of the source-drain doping layer 520.

[0124] The stop layer 543 is typically made of a specific material and has good etch stop performance. The material of the stop layer 543 includes silicon nitride.

[0125] In this embodiment, the thickness of the stop layer 543 is 5 nanometers to 10 nanometers.

[0126] The thickness of the stop layer 543 should not be too large or too small. If the thickness of the stop layer 543 is too large, it is easy to increase the process time for forming the stop layer 543, thereby affecting the production yield per unit time of the product; if the thickness of the stop layer 543 is too small, it is likely to result in poor effect of the stop layer 543 for defining the stop position. Therefore, the thickness of the stop layer 543 is 5 nanometers to 10 nanometers.

[0127] The stop layer 543 is formed by a deposition process. Therefore, the stop layer 543 also covers the top and sidewalls of the gate structure 510, as well as the exposed source / drain doping layer 520, and can thus protect the gate structure 510 and the source / drain doping layer 520 in subsequent manufacturing processes.

[0128] Reference Figures 14 to 15 , the step of forming the insulating layer 540 covering the source / drain doping layer 520 on the top of the substrate 501 further includes: forming a second interlayer dielectric (ILD) 542 on the stop layer 543, and the second interlayer dielectric 542 covers the top of the source / drain doping layer 520.

[0129] The second interlayer dielectric 542 is located on the top of the stop layer 543. In the step of forming the trench 550 from one side of the bottom surface of the substrate 501, the second interlayer dielectric 542 can support the stop layer 543 and improve the structural stability during the process.

[0130] The second interlayer dielectric 542 is usually an insulating material, and the material of the second interlayer dielectric 542 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, carbon oxide silicon, carbon nitride silicon, and carbon oxynitride silicon. In this embodiment, the material of the second interlayer dielectric 542 is silicon oxide.

[0131] Specifically, the step of forming the second interlayer dielectric 542 includes: forming a second interlayer dielectric material layer (not shown in the figure) on the stop layer 543; removing a part of the thickness of the second interlayer dielectric material layer to form the second interlayer dielectric 542 covering the stop layer 543 above the source / drain doping layer 520.

[0132] In this embodiment, the top of the second interlayer dielectric 542 is lower than the top of the gate structure 510, and the second interlayer dielectric 542 covers the stop layer 543 above the source / drain doping layer 520.

[0133] When the thickness of the second dielectric layer 542 is not too large, when the insulating layer 540 is removed subsequently, it is beneficial to reduce the difficulty of removing the second dielectric layer 542, thereby reducing the damage to the source-drain interconnect layer 530 caused by the process of removing the insulating layer 540.

[0134] Reference Figures 20 to 21 , Figure 20 is a cross-sectional view based on Figure 18 . Figure 21 is a cross-sectional view based on Figure 19 . After forming the source-drain interconnect layer 530, the method for forming the semiconductor structure further includes: removing the insulating layer 540.

[0135] Removing the insulating layer 540 prepares for subsequent process steps, thereby improving the compatibility of the method with existing processes.

[0136] Specifically, the process of removing the insulating layer 540 is a wet process. The solution used in the wet process includes phosphoric acid.

[0137] It should be noted that the semiconductor structure provided in the embodiments of the present invention can be formed by using the formation method described in the foregoing embodiments, or can be formed by using other formation methods. For the specific description of the formation method described in the embodiments of the present invention, reference can be made to the corresponding description in the foregoing embodiments.

[0138] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate, including a substrate body and fins located on the substrate body; A gate structure, located on the substrate body and spanning across the fins, the gate structure covering a partial top and partial sidewalls of the fins, the gate structure including a gate electrode layer and a gate dielectric layer, the gate dielectric layer wrapping the bottom and sidewalls of the gate electrode layer; Source / drain doping layers, located in the fins on both sides of the gate structure; Source / drain interconnect layers, embedded in the substrate from one side of the bottom surface of the substrate body and connecting the source / drain doping layers.

2. The semiconductor structure according to claim 1, wherein The source / drain interconnect layers penetrate through the substrate body and are located between adjacent fins.

3. The semiconductor structure according to claim 1, characterized in that, The bottom of the source / drain doping layers is lower than the bottom of the gate structure.

4. The semiconductor structure according to claim 3, wherein, The vertical distance from the bottom of the source / drain doping layers to the bottom of the gate structure is 10 nanometers to 20 nanometers.

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that, The overlapping height in the longitudinal direction between the source / drain interconnect layers and the source / drain doping layers is less than or equal to the vertical distance from the bottom of the source / drain doping layers to the bottom of the gate structure.

6. A method for forming a semiconductor structure, characterized in that: Providing a substrate, including a substrate body and fins located on the substrate body, a gate structure spanning across the fins being formed on the substrate body, the gate structure covering a partial top and partial sidewalls of the fins, the gate structure including a gate electrode layer and a gate dielectric layer, the gate dielectric layer wrapping the bottom and sidewalls of the gate electrode layer, source / drain doping layers being formed in the fins on both sides of the gate structure; Forming, from one side of the bottom surface of the substrate body, source / drain interconnect layers embedded in the substrate and connecting the source / drain doping layers.

7. The method for forming a semiconductor structure according to claim 6, wherein, The bottom of the source / drain doping layers is lower than the bottom of the gate structure.

8. The method for forming a semiconductor structure according to claim 6, wherein Before forming the source / drain interconnect layers, the method for forming the semiconductor structure further includes: forming an insulating layer covering the source / drain doping layers on the top of the substrate body.

9. The method for forming a semiconductor structure according to claim 8, wherein, The step of forming an insulating layer covering the source / drain doping layers on the top of the substrate body includes: forming a first dielectric layer on the top of the substrate body, the top of the first dielectric layer being lower than the top of the source / drain doping layers and covering partial sidewalls of the source / drain doping layers; Forming a stop layer covering the first dielectric layer; Using the bottom surface of the stop layer as a stop position, forming source / drain interconnect layers embedded in the substrate and the first dielectric layer and connecting the source / drain doping layers, the top surface of the source / drain interconnect layers being in contact with the bottom of the stop layer.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The step of forming the first dielectric layer includes: forming a first dielectric material layer on the top of the substrate body at the side portions of the fins; Removing a partial thickness of the first dielectric material layer to form a first dielectric layer covering partial sidewalls of the source / drain doping layers.

11. The method for forming a semiconductor structure as described in claim 9, wherein, The material of the first dielectric layer includes one or more of silicon nitride and silicon oxynitride.

12. The method for forming a semiconductor structure as claimed in claim 9, wherein, The material of the stop layer includes silicon nitride.

13. The method for forming a semiconductor structure according to claim 9, wherein The thickness of the stop layer is 5 nanometers to 10 nanometers.

14. The method for forming a semiconductor structure according to claim 8, wherein, The step of forming an insulating layer covering the source / drain doping layers on the top of the substrate body further includes: forming a second dielectric layer on the stop layer, the second dielectric layer covering the top of the source / drain doping layers.

15. The method for forming a semiconductor structure according to claim 14, wherein, The material of the second dielectric layer includes one or more of silicon nitride and silicon oxynitride.

16. The method for forming a semiconductor structure according to claim 8, wherein, After forming the source / drain interconnect layers, the method for forming the semiconductor structure further includes: removing the insulating layer.

17. The method for forming a semiconductor structure according to claim 6, wherein, In the step of forming a source-drain interconnect layer embedded in the substrate and connecting the source-drain doping layers from one side of the bottom surface of the substrate, the source-drain interconnect layer penetrates through the substrate and is located between adjacent fin portions.

18. The method for forming a semiconductor structure according to any one of claims 6 to 17, characterized in that, The vertical distance from the bottom of the source-drain doping layer to the bottom of the gate structure is 10 nanometers to 20 nanometers.

19. The method for forming a semiconductor structure according to any one of claims 6 to 17, characterized in that, The step of forming the interconnect layer includes: forming a trench located in the substrate and exposing the source-drain doping layers from one side of the bottom surface of the substrate; Forming the source-drain interconnect layer in the trench.

Images