Semiconductor structure and manufacturing method thereof

Abstract

The method includes forming a lower semiconductor region; forming an upper semiconductor region overlapping the lower semiconductor region; forming a lower gate dielectric and an upper gate dielectric on the lower semiconductor region and the upper semiconductor region, respectively; forming a lower gate electrode on the lower gate dielectric and the upper gate dielectric; etching back the lower gate electrode; forming a gate isolation layer on the etched-back lower gate electrode; and forming an upper gate electrode over the gate isolation layer. An upper gate electrode is on the upper gate dielectric. The embodiment of the invention also relates to a semiconductor structure and a manufacturing method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of manufacturing the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor layer over a semiconductor substrate; and patterning the individual material layers using lithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuing to reduce the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size is reduced, additional problems arise that should be addressed. Summary of the Invention

[0004] Some embodiments of the present application provide a method of manufacturing a semiconductor structure, including: forming a lower semiconductor region; forming an upper semiconductor region overlapping the lower semiconductor region; forming a lower gate dielectric and an upper gate dielectric on the lower semiconductor region and the upper semiconductor region, respectively; forming a lower gate electrode on the lower gate dielectric and the upper gate dielectric; etching back the lower gate electrode; forming a gate isolation layer on the etched-back lower gate electrode; and forming an upper gate electrode over the gate isolation layer, wherein the upper gate electrode is located on the upper gate dielectric.

[0005] Some other embodiments of the present application provide a semiconductor structure, including: a lower transistor, including: a first semiconductor region; a first gate dielectric located on the first semiconductor region; and a lower gate electrode located on the first gate dielectric; and an upper transistor, including: a second semiconductor region overlapping the first semiconductor region; a second gate dielectric located on the second semiconductor region; and an upper gate electrode located on the second gate dielectric; and a gate isolation layer located on and contacting the lower gate electrode, wherein the gate isolation layer is also located under and contacts the upper gate electrode.

[0006] Some embodiments of the present application provide a semiconductor structure, including: a first complementary field-effect transistor (CFET) structure, including: a first lower field-effect transistor (FET), including a first lower gate electrode; a first upper field-effect transistor, including a first upper gate electrode overlapping with the first lower gate electrode; and a first gate isolation layer, located between the first lower gate electrode and the first upper gate electrode and bonded to the first lower gate electrode and the first upper gate electrode; a second complementary field-effect transistor structure, including: a second lower field-effect transistor, including a second lower gate electrode; and a second upper field-effect transistor, including a second upper gate electrode overlapping with the second lower gate electrode; and an isolation region, including: a first sidewall, contacting a first edge of the first lower gate electrode and the first upper gate electrode; and a second sidewall, contacting a second edge of the second lower gate electrode and the second upper gate electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of embodiments of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for the sake of clear discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 A perspective view of an exemplary complementary field-effect transistor (CFET) in accordance with some embodiments is shown.

[0009] Figures 2 to 7A 、 Figure 7B 、 Figure 8A 、 Figure 8B 、 Figures 9 to 13 、 Figure 14A 、 Figure 14B and Figure 14C are views of intermediate stages in the fabrication of a CFET in accordance with some embodiments.

[0010] Figures 15 to 22 is a view of an intermediate stage in the fabrication of a CFET in accordance with some embodiments.

[0011] Figure 23 A perspective view of a CFET structure in accordance with some embodiments is shown.

[0012] Figure 24 A flow chart for forming a CFET in accordance with some embodiments is shown. DETAILED DESCRIPTION

[0013] The following disclosure provides various embodiments or examples for implementing different features of the embodiments of the present disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming the first component above or on the second component may include embodiments where the first component and the second component are in direct contact, and may also include embodiments where additional components may be formed between the first component and the second component such that the first component and the second component are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for simplicity and clarity purposes and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] In addition, for ease of description, spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another (or other) element or component as shown in the figures. In addition to the orientation depicted in the figures, the spatially relative terms are intended to include different orientations of the device during use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0015] A complementary field effect transistor (CFET) structure and a method of forming the same are provided. Throughout the description, the terms "FET" and "transistor" may be used interchangeably. According to some embodiments, the CFET structure includes a lower FET and an upper FET overlapping the lower FET. A gate dielectric isolation layer is formed above the gate electrode of the lower FET and below the gate electrode of the upper FET. Thus, the gate electrode of the lower FET is electrically isolated from the gate electrode of the upper FET.

[0016] It should be understood that although all-around gate (GAA) transistors (such as nanostructure FETs) are discussed as examples, the concepts of the embodiments of the present disclosure may also be applicable to the formation of other types of transistors, such as planar transistors, fin field effect transistors (FinFETs), etc.

[0017] Figure 1 An example of a CFET 10 (including FETs (transistors) 10U and 10L) according to some embodiments is shown. Figure 1 is a three-dimensional view, where some components of the CFET are omitted for clarity of illustration.

[0018] The CFET 10 may include a lower nanostructure FET 10L of a first device type (e.g., n-type / p-type) and an upper nanostructure FET 10U of a second device type (e.g., p-type / n-type) opposite to the first device type. The nanostructure FETs 10U and 10L include a semiconductor nanostructure 26' (including a lower semiconductor nanostructure 26'L and an upper semiconductor nanostructure 26'U), wherein the semiconductor nanostructure 26' is used as a channel region for the nanostructure FET. The lower semiconductor nanostructure 26'L is used for the lower nanostructure FET 10L, and the upper semiconductor nanostructure 26'U is used for the upper nanostructure FET 10U.

[0019] The gate dielectric 78 surrounds the corresponding semiconductor nanostructure 26'. The gate electrode 80 (including the lower gate electrode 80L and the upper gate electrode 80U) is located on the gate dielectric 78. The source / drain region 62 (including the lower source / drain region 62L and the upper source / drain region 62U) is disposed on opposite sides of the gate dielectric 78 and the corresponding gate electrode 80. The source / drain region may refer to a source or a drain, individually or collectively depending on the context. An isolation feature (not shown) may be formed to separate the desired source / drain region 62 and / or the desired gate electrode 80.

[0020] Figure 1 Reference cross sections used in subsequent figures are also shown. Cross section AA' is a vertical cross section perpendicular to cross section BB' and along the longitudinal axis of the gate electrode 80 of the CFET. Cross section BB' is a vertical cross section parallel to the longitudinal axis of the semiconductor nanostructure 26' of the CFET and in the direction of current flow, for example, between the source / drain regions 62 of the CFET. For clarity, subsequent figures may refer to these reference cross sections.

[0021] Figures 2 to 14A , Figure 14B and Figure 14C A CFET according to some embodiments (eg Figure 1 The corresponding process is also schematically shown in FIG. Figure 24 In the process flow 200 shown in .

[0022] exist Figure 2In it, a wafer 2 is provided, and the wafer 2 includes a substrate 20. The substrate 20 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., with p-type or n-type dopants) or undoped. The SOI substrate can include a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is provided on a substrate such as a silicon or glass substrate. Other substrates can also be used, such as multi-layer or gradient substrates. In some embodiments, the semiconductor material of the substrate 20 can include: silicon, germanium, carbon-doped silicon, III-V group compound semiconductors; etc. or combinations thereof.

[0023] A multi-layer stack 22 is formed above the substrate 20. The multi-layer stack 22 includes alternating pseudo-semiconductor layers 24 (including pseudo-semiconductor layer 24A and pseudo-semiconductor layer 24B) and semiconductor layers 26 (including a lower semiconductor layer 26L and an upper semiconductor layer 26U). The lower semiconductor layer 26L and the upper semiconductor layer 26U are respectively used to form a lower FET and an upper FET.

[0024] Appropriate wells (not shown separately) can be formed in the lower semiconductor layer 26L and the upper semiconductor layer 26U. For example, the semiconductor layers 26L and 26U can be doped in-situ (when epitaxially grown) and / or implanted to the desired conduction type.

[0025] In the illustrated example, the multi-layer stack 22 includes six pseudo-semiconductor layers 24 and six semiconductor layers 26. It should be understood that the multi-layer stack 22 can include any number of pseudo-semiconductor layers 24 and semiconductor layers 26. Each layer of the multi-layer stack 22 can be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), and deposited by a process such as chemical vapor deposition (CVD) process or atomic layer deposition (ALD) process, etc.

[0026] The pseudo-semiconductor layer 24A is formed of a first semiconductor material, and the pseudo-semiconductor layer 24B is formed of a second semiconductor material different from the first semiconductor material. The first semiconductor material and the second semiconductor material can be selected from the candidate semiconductor materials of the substrate 20. The first semiconductor material and the second semiconductor material have a high etching selectivity to each other. Therefore, in subsequent processes, the pseudo-semiconductor layer 24B can be removed at a rate faster than that of the pseudo-semiconductor layer 24A.

[0027] The semiconductor layer 26 (including the lower semiconductor layer 26L and the upper semiconductor layer 26U) is formed of one or more semiconductor materials. The semiconductor materials can be selected from the candidate semiconductor materials of the substrate 20. The lower semiconductor layer 26L and the upper semiconductor layer 26U can be formed of the same semiconductor material, or can be formed of different semiconductor materials.

[0028] In some embodiments, the pseudo-semiconductor layer 24A is formed of or includes silicon germanium, the semiconductor layer 26 is formed of silicon, and the pseudo-semiconductor layer 24B may be formed of germanium or silicon germanium having a higher percentage of germanium atoms than in the semiconductor layer 24A.

[0029] In Figure 3 this, the patterned multi-layer stack 22 and the substrate 20 are patterned to form semiconductor bars 28. The corresponding process is shown as process 202 in process flow 200 as shown in Figure 24 this. Each of the semiconductor bars 28 includes a semiconductor bar 20’ (a portion of the original substrate 20) and a multi-layer stack 22’, where the multi-layer stack 22’ is the remaining portion of the multi-layer stack 22. The remaining portion 22’ of the multi-layer stack 22 is hereinafter referred to as a nanostructure, which refers to the corresponding reference number using the “’” symbol immediately following. Thus, the multi-layer stack 22’ includes a pseudo-nanostructure 24’A, a pseudo-nanostructure 24’B, a lower semiconductor nanostructure 26’L, an intermediate semiconductor nanostructure 26’M, and an upper semiconductor nanostructure 26’U. The etching can be implemented by any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching can be anisotropic. The pseudo-nanostructure 24’A and the pseudo-nanostructure 24’B can be further collectively referred to as the pseudo-nanostructure 24’. The lower semiconductor nanostructure 26’L and the upper semiconductor nanostructure 26’U can be further collectively referred to as the semiconductor nanostructure 26’.

[0030] The lower semiconductor nanostructure 26’L will serve as the channel region of the lower nanostructure FET for the CFET. The upper semiconductor nanostructure 26’U will serve as the channel region of the upper nanostructure FET for the CFET. The intermediate semiconductor nanostructure 26’M is the semiconductor nanostructure 26’ directly above / below (e.g., in contact with) the pseudo-nanostructure 24’B. The intermediate semiconductor nanostructure 26’M can be used for isolation and may or may not serve as the channel region for the CFET. The pseudo-nanostructure 24’B will subsequently be replaced with an isolation structure. The isolation structure and the intermediate semiconductor nanostructure 26’M can define the boundaries of the lower nanostructure FET and the upper nanostructure FET.

[0031] In Figure 4 this, an isolation region 32 is formed above the substrate 20 and between adjacent semiconductor bars 28. The isolation region 32 may include a dielectric pad and a dielectric material above the dielectric pad.

[0032] Then the isolation region 32 is recessed. Some upper portions of the semiconductor bars 28 (including the multi-layer stack 22’) protrude above the remaining isolation region 32 to form protruding fins 34.

[0033] Then, a pseudo-dielectric layer 36 is formed on the protruding fin 34. The pseudo-dielectric layer 36 can be formed of or include, for example, silicon oxide, silicon nitride, their combinations, etc., and can be deposited or thermally grown according to acceptable techniques. A pseudo-gate layer 38 is formed above the pseudo-dielectric layer 36. The pseudo-gate layer 38 can be deposited, for example, by physical vapor deposition (PVD), CVD, or other techniques, and then planarized, such as by a chemical mechanical polishing (CMP) process. The material of the pseudo-gate layer 38 can be conductive or non-conductive, and can be selected from the group including amorphous silicon, polysilicon (poly-Si), poly-silicon germanium (poly-SiGe), etc. A mask layer 40 that can include, for example, silicon nitride, silicon oxynitride, etc. is formed above the planarized pseudo-gate layer 38.

[0034] Next, the mask layer 40 can be patterned by a photolithography and etching process to form a mask, and then the mask is used to etch and pattern the pseudo-gate layer 38, and possibly etch and pattern the pseudo-dielectric layer 36. The resulting structure is shown in Figure 5 The remaining portions of the mask layer 40, the pseudo-gate layer 38, and the pseudo-dielectric layer 36 form a pseudo-gate stack 42.

[0035] In Figure 5 , a gate spacer 44 is formed above the multi-layer stack 22' and on the exposed sidewalls of the pseudo-gate stack 42. The gate spacer 44 can be formed by conformally forming one or more dielectric layers and then anisotropically etching the dielectric layers. Applicable dielectric materials can include silicon oxide, silicon nitride, silicon oxynitride, carbon oxynitride, etc., which can be formed by deposition processes such as CVD, ALD, etc. A fin spacer 45 is also formed.

[0036] Then, source / drain trenches 46 are formed in the semiconductor strip 28. The source / drain trenches 46 are formed by etching and can extend through the multi-layer stack 22' and into the semiconductor strip 20'. The bottom surface of the source / drain trenches 46 can be located above, below, or at a level flush with the top surface of the isolation region 32. In the etching process, the gate spacer 44 and the pseudo-gate stack 42 mask some portions of the semiconductor strip 28. The etching can include a single etching process or multiple etching processes. When the source / drain trenches 46 reach the desired depth, a timed etching process can be used to stop the etching of the source / drain trenches 46.

[0037] In a subsequent process, the pseudo-nanostructure 24'A is laterally recessed, and a dielectric material is filled into the corresponding trenches to form an internal spacer 54, which is a dielectric spacer. The resulting structure is shown in Figure 6 In addition, the pseudo-nanostructure 24'B is also removed and filled with a dielectric material to form a dielectric isolation layer 56.

[0038] Next, a lower epitaxial source / drain region 62L is formed in a lower portion of the source / drain recess 46 ( Figure 5 ). The lower epitaxial source / drain region 62L contacts the lower semiconductor nanostructure 26’L and does not contact the upper semiconductor nanostructure 26’U. The inner spacer 54 electrically insulates the lower epitaxial source / drain region 62L from the dummy nanostructure 24’A, which will be replaced with a replacement gate in a subsequent process.

[0039] The lower epitaxial source / drain region 62L is epitaxially grown and has a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure FET. When the lower epitaxial source / drain region 62L is an n-type source / drain region, the corresponding material may include silicon or carbon-doped silicon, doped with an n-type dopant such as phosphorus, arsenic, etc. When the lower epitaxial source / drain region 62L is a p-type source / drain region, the corresponding material may include silicon or silicon germanium, doped with a p-type dopant such as boron, indium, etc. The lower epitaxial source / drain region 62L may be in-situ doped and may or may not be implanted with a corresponding p-type or n-type dopant.

[0040] A first contact etch stop layer (CESL) 66 and a first ILD 68 are formed. The first CESL 66 may be formed of a dielectric material having a high etch selectivity with respect to the etch of the first ILD 68, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which may be formed by any suitable deposition process, such as CVD, ALD, etc. The first ILD 68 may be formed of a dielectric material, which may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. Suitable dielectric materials for the first ILD 68 may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), silicon oxide, etc.

[0041] The forming process may include: depositing a conformal CESL layer; depositing a material for the ILD 68; and subsequent planarization processes and then an etch-back process. In some embodiments, the first ILD 68 is first etched, leaving the first CESL 66 unetched. Then an anisotropic etch process is implemented to remove portions of the first CESL 66 that are above the recessed first ILD 68. After the recessing, the sidewalls of the upper semiconductor nanostructure 26’U are exposed.

[0042] Next, an upper epitaxial source / drain region 62U is formed in the upper portion of the source / drain recess 46. The material of the upper epitaxial source / drain region 62U can be selected from the same group of candidate materials used to form the lower epitaxial source / drain region 62L, depending on the desired conductivity type of the upper epitaxial source / drain region 62U.

[0043] The conductivity type of the upper epitaxial source / drain region 62U can be opposite to that of the lower epitaxial source / drain region 62L. In other words, the upper epitaxial source / drain region 62U can be doped oppositely to the lower epitaxial source / drain region 62L. The upper epitaxial source / drain region 62U can be in-situ doped and / or can be implanted with an n-type or p-type dopant.

[0044] Next, a second CESL 70 and a second ILD 72 are formed. The materials and formation methods can be respectively similar to those of the first CESL 66 and the first ILD 68, and will not be discussed in detail here. The formation process can include: depositing layers for the CESL 70 and the ILD 72; and performing a planarization process to remove the excess portions of the corresponding layers. After the planarization process, the top surfaces of the second ILD 72, the gate spacers 44, and the dummy gate stack 42 are coplanar (within process variations). The planarization process can remove the mask 40 or leave the hard mask 40 unremoved.

[0045] Then, the dummy gate stack 42 is removed in one or more etching processes, thereby forming a recess 74, as Figure 7A and Figure 7B shown in. The corresponding process is shown as process 204 in process flow 200 as shown in Figure 24 Each exposed portion of the multi-layer stack 22' and / or is located above a portion of the multi-layer stack 22' in the recess 74.

[0046] As Figure 7B shown in, the cross-section can be the vertical cross-section A-A' as shown in Figure 1 . In Figure 7B , three device regions 400, 500, and 600 are shown. Each of the device regions 400, 500, and 600 is for forming a CFET including an upper FET and a lower FET. Each of the device regions 400, 500, and 600 can also be obtained from the vertical cross-section 14A-14A as shown in Figure 23 , which cuts through the metal gate to be formed.

[0047] Then, the pseudo-nanostructure 24'A is removed by etching ( Figure 6The remainder of (), such that the recess 74 extends between the semiconductor nanostructures 26'. In the etching process, the dummy nanostructures 24'A are etched at a rate faster than the semiconductor nanostructures 26', the dielectric isolation layer 56, and the internal spacers 54. The etching can be isotropic. For example, when the dummy nanostructures 24'A are formed of silicon germanium and the semiconductor nanostructures 26' are formed of silicon, the etching process can include a wet etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc.

[0048] Figure 8A , Figure 8B , Figures 9 to 13 , Figure 14A , Figure 14B and Figure 14C show details for forming the gate dielectric 78 and the gate electrodes 80 (including 80U and 80L) according to some embodiments. In Figure 8A and Figure 8B , the gate dielectric 78 is formed in the recess 74 and on the exposed semiconductor nanostructures 26'. The corresponding process is shown as process 206 in process flow 200 as shown in Figure 24 . The gate dielectric 78 is formed on the exposed surfaces of the exposed components including the semiconductor nanostructures 26' and the gate spacers 44. The gate dielectric 78 wraps all (e.g., four) sides of the semiconductor nanostructures 26'.

[0049] Each of the gate dielectrics 78 can include an interfacial layer 78IL, which is shown but not separately labeled. The interfacial layer 78IL can include oxides such as silicon oxide or metal oxides, silicates such as metal silicates, combinations thereof, multilayers thereof, etc. The interfacial layer 78IL can be formed by a thermal oxidation process and / or a deposition process.

[0050] Each gate dielectric 78 can also include a high-k dielectric layer 78HK above the interfacial layer, which has a high dielectric constant (high-k) value greater than, for example, about 7.0, about 21 or higher. The high-k dielectric layer 78HK can be formed of or include metal oxides or silicates of metals selected from hafnium, zirconium, barium, titanium, lead, and combinations thereof. The method for forming the high-k dielectric layer 78HK can be selected from molecular beam deposition (MBD), ALD, PECVD, etc. The high-k dielectric layer 78HK can have a thickness in the range between about 1 nm and about 5 nm. The gate dielectrics 78 in the device regions 400, 500, and 600 can be formed in a common process.

[0051] Referring to Figure 9 , the lower gate electrode 80L is formed. The corresponding process is shown as in Figure 24Process 208 in the process flow 200 shown in the figure. According to some embodiments, the lower gate electrode 80L includes a work function layer and may also include other layers, such as a capping layer below the work function layer, a barrier layer above the work function layer, and may or may not include a metal fill layer above the barrier layer. The formation of the lower gate electrode 80L may include deposition processes such as ALD, metal organic chemical vapor deposition (MOCVD), PECVD, etc. After depositing the layers of the lower gate electrode 80L, a planarization process is implemented to make the top surface of the lower gate electrode 80L flush.

[0052] According to some embodiments, the capping layer and the barrier layer may include TiN or TiSiN, and the material of the work function layer depends on whether the lower FET is an NFET or a PFET. For example, when the lower FET is an NFET, the work function layer may include TiAlN, TiAl, TiN, tungsten, etc. When the lower FET is a PFET, the work function layer may include TiN, TaN, tungsten, etc.

[0053] According to some embodiments, the lower gate electrode 80L may (or may not) include a seam 81. The bottom of the seam 81 is close to the bottom of the lower gate electrode 80L. According to some embodiments, the width W1 of the seam 81 may be in the range between about 1 nm and about 5 nm.

[0054] Reference Figure 10 , an etch-back process is implemented to recess the lower gate electrode 80L. The corresponding process is shown as process 210 in the process flow 200 shown in Figure 24 the figure. The top surface of the remaining lower gate electrode 80L is lower than the top surface of the upper one of the intermediate semiconductor nanostructures 26’M and higher than the bottom surface of the lower one of the intermediate semiconductor nanostructures 26’M.

[0055] The etch-back process can be implemented using a dry etching process or a wet etching process. For example, when dry etching is employed, chlorine (Cl2) can be used as the etching gas, and carrier gases such as Ar, N2, etc. can be used. Due to the etching process, the seam 81 may be exposed. According to some embodiments, the etch-back process can be implemented by adding some by-product generating gases, such as SiCl4, O2, CH4, N2, BCl3, etc. Thus, by-products 84 are generated that fill the seam 81 during the etch-back process. Depending on the gases added, the by-products 84 may include inorganic materials such as SiCO, SiCN, BN, etc., polymeric materials such as polymeric carbon nitride (CN), or combinations thereof. The by-products 84 can also be dielectric materials. The generated by-products that fill the seam 81 are also referred to as the by-product region 84.

[0056] According to some embodiments, the by-product region 84 completely occupies the seam 81. According to alternative embodiments, the by-product region 84 partially occupies the seam 81. For example, the by-product region 84 may occupy the lower portion of the seam 81, leaving the upper portion unfilled. The by-product region 84 may also form a conformal liner of the sidewalls of the seam 81, leaving the central portion of the seam 81 unfilled. Throughout the description, the seam 81 and the by-product region 84 are referred to as region 81 / 84, which means that the corresponding region is the seam 81 and / or the by-product region 84 in the form of an air gap.

[0057] Figure 11 The formation of the gate isolation layer 86 is shown. The corresponding process is shown as process 212 in process flow 200 as shown in Figure 24 According to some embodiments, the gate isolation layer 86 includes a dielectric material such as SiO, SiN, SiCN, SiOC, SiOCN, SiON, etc. The formation process may include: depositing the gate isolation layer 86 by a deposition process such as an ALD process, a CVD process, a PVD process, etc.; planarizing the top surface of the gate isolation layer 86 (e.g., by CMP or mechanical polishing); and etching back the dielectric layer. The resulting gate isolation layer 86 has a top surface lower than the top surface of the upper one of the intermediate semiconductor nanostructures 26’M.

[0058] Figure 12 An alternative patterning of the gate isolation layer 86 is shown, which may be implemented by forming an etch mask (such as a patterned photoresist, not shown) and etching the gate isolation layer 86. The corresponding process is shown as process 214 in process flow 200 as shown in Figure 24 After patterning the gate isolation layer 86, the region 81 / 84 may be exposed, covered by the gate isolation layer 86, or have some portions of the gate isolation layer 86 exposed and other portions of the gate isolation layer 86 covered by the gate isolation layer 86.

[0059] Figure 13 The formation of the upper gate electrode 80U according to some embodiments is shown. The corresponding process is shown as process 216 in process flow 200 as shown in Figure 24 The formation of the upper gate electrode 80U may include: depositing a plurality of conductive layers; and performing a planarization process. The structure and material of the upper gate electrode 80U can be found with reference to the discussion of the lower gate electrode 80L, except that the corresponding upper FET may have a conductivity type opposite to that of the lower FET, and the material of the work function layer in the upper gate electrode 80U is selected to be suitable for the conductivity type of the upper FET.

[0060] According to some embodiments, a seam 81’ is formed in the upper gate electrode 80U. The seam 81’ (when formed) may have a width W2, and W2 may be less than the width W1 (Figure 9 )。According to an alternative embodiment, the seam 81' is not formed.

[0061] Figure 14A The formation of the isolation region 88 is shown, which electrically and physically isolates the gate electrodes 80L and 80U in the device regions 400, 500, and 600 from each other. The corresponding process is shown as the process 218 in the process flow 200 as shown in Figure 24 . The formation process may include etching the upper gate electrode 80U and the lower gate electrode 80L to form an opening until the underlying gate dielectric 78 is exposed. The gate dielectric 78 may be etched to expose the underlying STI region 32, or the gate dielectric 78 may not be etched. In a subsequent process, a dielectric material is filled into the opening to form the gate isolation region 88.

[0062] According to some embodiments, after the formation of the gate isolation region 88, the corresponding regions 81 / 84 are completely removed. According to an alternative embodiment, after the formation of the gate isolation region 88, the corresponding regions 81 / 84 are partially removed and partially retained, as Figure 14A shown. According to still some other alternative embodiments, the entire regions 81 / 84 are retained because the corresponding gate isolation regions 88 are not formed (while other gate isolation regions 88 may still be formed).

[0063] According to some embodiments, the isolation region 88 may be formed simultaneously with the formation of the contact etch stop layer (CESL 90) and the interlayer dielectric (ILD) 92, and the material filling the openings of the CESL 90 and the ILD 92 forms the isolation region. In other embodiments, the isolation region 88 is formed by a process different from the formation of the CESL 90 and the ILD 92. According to some embodiments, the CESL 90 may be formed of a nitride such as SiN, SiC, SiOCN, etc., while the ILD 92 may be formed of an oxide such as SiO, SiOC, SiOCN, etc. The gate contact plug 94 is formed to extend into the ILD 92 to be electrically connected to the upper gate electrode 80U. An electrical connection to the lower gate electrode 80L is also formed and not shown.

[0064] Throughout the description, the gate electrode 80L and the underlying gate dielectric 78 are collectively referred to as the gate stack 94L, and the gate electrode 80U and the underlying gate dielectric 78 are collectively referred to as the gate stack 94U. Thus, the CFET 10 is formed, and the CFET 10 includes a lower FET 10L (including the gate stack 94L and the source / drain region 62L ( Figure 14B )) and an upper FET 10U (including the gate stack 94U and the source / drain region 62U ( Figure 14B ))).

[0065] The gate isolation layer 86 may be located at the same level as the dielectric isolation layer 56. According to an alternative embodiment, as Figure 14A shown, the gate isolation layer 86 may have a top surface that is flush with the top surface of the upper one of the intermediate semiconductor nanostructures 26’M, and the corresponding gate isolation layer 86 is marked by the dashed line 86’. According to an alternative embodiment, the gate isolation layer 86 may have a bottom surface that is flush with the bottom surface of the lower one of the intermediate semiconductor nanostructures 26’M, and the corresponding gate isolation layer 86 is marked by the dashed line 86”. The gate isolation layer 86 may also be located at any position between the positions marked by the dashed lines 86’ and 86”.

[0066] Figure 23 A perspective view of a CFET 10 according to some embodiments is shown. The source / drain regions 62L and 62U, the gate electrodes 80L and 80U, the gate isolation layer 86, the STI region 32, etc. are marked.

[0067] Figure 14A The cross-sectional view shown in Figure 23 is obtained from the vertical cross-section 14A-14A (and Figure 1 the vertical cross-section A-A’ shown in Figure 14B ), which cuts through the metal gate electrode. Figure 23 The vertical cross-section 14B-14B (and Figure 1 the vertical cross-section B-B’ shown in Figure 14C is shown, which cuts through the nanostructures 26U and 26L (channel regions) and the source / drain regions 62U and 62L. Figure 23 The vertical cross-section 14C-14C shown in

[0068] is shown, which cuts through the STI region 32 and the gate isolation region 88 to separate the adjacent gate electrodes 80U and 80L from each other. Figure 14A In some embodiments, as shown in Figure 14A , in the formation of the gate isolation region 88, the regions 81 / 84 may be completely removed. Some or all of the regions 81 / 84 may have some portions retained, also as shown in Figure 13 , depending on the widths of the regions 81 / 84 and the gate isolation region 88. According to some embodiments, some of the gate isolation regions 88 are not formed, and thus the regions 81 / 84 shown in

[0069] Figures 15 to 22 A structure formed according to an alternative embodiment is shown. It should be understood that the structure formed according to these embodiments and Figure 14A , Figure 14B and Figure 14CThe structures shown in can coexist in the same device die and the same device wafer and are formed using the same formation process.

[0070] Figure 15 and Figure 16 Illustrated is the formation of a lower gate electrode 80L, a gate isolation layer 86, and an upper gate electrode 80U according to some embodiments. A by-product region 84 is shown. By forming the by-product region 84, it is easier to seal the underlying seam 81 for the gate isolation layer 86.

[0071] Figure 17 and Figure 18 Illustrated is the formation of a lower gate electrode 80L, a gate isolation layer 86, and an upper gate electrode 80U according to alternative embodiments. The shown seam 81 is not filled with the by-product region 84, or may be partially filled with the by-product region 84, e.g., having a filled lower portion. Optionally, the by-product region 84 can be formed as a conformal liner. Such a structure can be generated when no by-product generating gas is added during the etch-back process of the lower gate electrode 80L. Optionally, such a structure can be generated when by-products are generated, but not filled into the shown seam 81, or filled with an insufficient amount. Thus, the gate isolation layer 86 will have some portions that extend into and fill some portions of the upper portion of the underlying seam 81.

[0072] Figure 19 and Figure 20 Illustrated is the formation of a lower gate electrode 80L, a gate isolation layer 86, and an upper gate electrode 80U according to yet further alternative embodiments. The shown seam 81 is not filled with the by-product region 84, or may be partially filled, e.g., having a filled lower portion. According to some embodiments, the gate isolation layer 86 is deposited by a bottom-up deposition process. Thus, the gate isolation layer 86 will fill the remaining underlying seam 81. The seam 81 may or may not include by-products, and if by-products are generated, the remaining seam 81 not filled by the by-products will be completely filled by the gate isolation layer 86.

[0073] Figure 21 Illustrated is the formation of a lower gate electrode 80L, a gate isolation layer 86, and an upper gate electrode 80U according to some embodiments. The gate isolation layer 86 is patterned, and the underlying seam 81 may be exposed again. Thus, the upper gate electrode 80U will seal the underlying seam 81. Additionally, the upper gate electrode 80U may extend into the underlying seam 81.

[0074] According to some embodiments, Figure 22 the structures shown in exist in Figure 23 the final structure shown in . According to alternative embodiments, after forming Figure 22 the structures shown in , Figure 14AThe process shown in , and a gate isolation region 88 is formed, which is shown by the dashed line.

[0075] Embodiments of the present disclosure have some advantageous features. By forming a horizontal gate isolation layer between the upper gate electrode and the lower gate electrode in the CFET structure, the upper gate electrode and the lower gate electrode are electrically isolated from each other. The process can be adjusted to fill the gaps that may be formed in the lower gate electrode.

[0076] According to some embodiments of the present disclosure, the method includes: forming a lower semiconductor region; forming an upper semiconductor region overlapping the lower semiconductor region; respectively forming a lower gate dielectric and an upper gate dielectric on the lower semiconductor region and the upper semiconductor region; forming a lower gate electrode on the lower gate dielectric and the upper gate dielectric; etching back the lower gate electrode; forming a gate isolation layer on the etched-back lower gate electrode; and forming an upper gate electrode above the gate isolation layer, wherein the upper gate electrode is located on the upper gate dielectric.

[0077] In an embodiment, the method further includes patterning the gate isolation layer. In an embodiment, forming the gate isolation layer includes: depositing a dielectric layer; planarizing the dielectric layer; and etching back the dielectric layer, wherein the remaining portion of the dielectric layer forms the gate isolation layer. In an embodiment, a seam is formed in the lower gate electrode, and wherein, after etching back the lower gate electrode, the seam is exposed.

[0078] In an embodiment, during the etching back of the lower gate electrode, by-products are generated to at least partially fill the seam. In an embodiment, during the etching back of the lower gate electrode, a silicon-containing process gas is added, and the by-products include a silicon-containing dielectric. In an embodiment, the by-products completely fill the seam. In an embodiment, the method further includes: etching the lower gate electrode and the upper gate electrode; and filling a dielectric region in the space left by the etched lower gate electrode and the etched upper gate electrode.

[0079] In an embodiment, a seam is formed in the lower gate electrode, and wherein the gate isolation layer at least partially fills the seam. In an embodiment, the gate isolation layer completely fills the seam. In an embodiment, the lower semiconductor region includes a first semiconductor nanostructure, and the upper semiconductor region includes a second semiconductor nanostructure, and the method further includes: forming a first source / drain region bonded to the first semiconductor nanostructure; and forming a second source / drain region bonded to the second semiconductor nanostructure.

[0080] According to some embodiments of the present disclosure, a structure includes: a lower transistor, including: a first semiconductor region; a first gate dielectric located on the first semiconductor region; and a lower gate electrode located on the first gate dielectric; and an upper transistor, including: a second semiconductor region overlapping with the first semiconductor region; a second gate dielectric located on the second semiconductor region; and an upper gate electrode located on the second gate dielectric; and a gate isolation layer located on and in contact with the lower gate electrode, wherein the gate isolation layer is also located under and in contact with the upper gate electrode. In an embodiment, the lower transistor and the upper transistor have opposite conduction types.

[0081] In an embodiment, the structure further includes: an isolation region including sidewalls contacting edges of the lower gate electrode, the gate isolation layer, and the upper gate electrode. In an embodiment, the lower gate electrode further includes a silicon-containing dielectric region. In an embodiment, the lower gate electrode further includes a seam filled with the same material as the gate isolation layer. In an embodiment, the lower gate electrode further includes the seam as an air gap.

[0082] According to some embodiments of the present disclosure, a structure includes: a first CFET structure, including: a first lower FET including a first lower gate electrode; a first upper FET including a first upper gate electrode overlapping with the first lower gate electrode; and a first gate isolation layer located between and bonded to the first lower gate electrode and the first upper gate electrode; a second CFET structure, including: a second lower FET including a second lower gate electrode; and a second upper transistor including a second upper gate electrode overlapping with the second lower gate electrode; and an isolation region including: a first sidewall contacting a first edge of the first lower gate electrode and the first upper gate electrode; and a second sidewall contacting a second edge of the second lower gate electrode and the second upper gate electrode. In an embodiment, the structure further includes: a second gate isolation layer located between and bonded to the second lower gate electrode and the second upper gate electrode. In an embodiment, the second lower gate electrode physically contacts the second upper gate electrode.

[0083] Some embodiments of the present application provide a method for manufacturing a semiconductor structure, including: forming a lower semiconductor region; forming an upper semiconductor region overlapping with the lower semiconductor region; respectively forming a lower gate dielectric and an upper gate dielectric on the lower semiconductor region and the upper semiconductor region; forming a lower gate electrode on the lower gate dielectric and the upper gate dielectric; etching back the lower gate electrode; forming a gate isolation layer on the etched-back lower gate electrode; and forming an upper gate electrode above the gate isolation layer, wherein the upper gate electrode is located on the upper gate dielectric.

[0084] In some embodiments, the method further includes patterning the gate isolation layer. In some embodiments, forming the gate isolation layer includes: depositing a dielectric layer; planarizing the dielectric layer; and etching back the dielectric layer, wherein a remaining portion of the dielectric layer forms the gate isolation layer. In some embodiments, a seam is formed in the lower gate electrode, and wherein after etching back the lower gate electrode, the seam is exposed. In some embodiments, during etching back the lower gate electrode, by-products are generated to at least partially fill the seam. In some embodiments, during etching back the lower gate electrode, a silicon-containing process gas is added, and the by-products include a silicon-containing dielectric. In some embodiments, the by-products completely fill the seam. In some embodiments, the method further includes: etching the lower gate electrode and the upper gate electrode; and filling a dielectric region in a space left by the etched lower gate electrode and the etched upper gate electrode. In some embodiments, a seam is formed in the lower gate electrode, and wherein the gate isolation layer at least partially fills the seam. In some embodiments, the gate isolation layer completely fills the seam. In some embodiments, the lower semiconductor region includes a first semiconductor nanostructure, and the upper semiconductor region includes a second semiconductor nanostructure, and the method further includes: forming a first source / drain region joined to the first semiconductor nanostructure; and forming a second source / drain region joined to the second semiconductor nanostructure.

[0085] Some other embodiments of the present application provide a semiconductor structure, including: a lower transistor, including: a first semiconductor region; a first gate dielectric located on the first semiconductor region; and a lower gate electrode located on the first gate dielectric; and an upper transistor, including: a second semiconductor region overlapping with the first semiconductor region; a second gate dielectric located on the second semiconductor region; and an upper gate electrode located on the second gate dielectric; and a gate isolation layer located above and in contact with the lower gate electrode, wherein the gate isolation layer is further located below and in contact with the upper gate electrode.

[0086] In some embodiments, the lower transistor and the upper transistor have opposite conduction types. In some embodiments, the semiconductor structure further includes: an isolation region including sidewalls contacting edges of the lower gate electrode, the gate isolation layer, and the upper gate electrode. In some embodiments, the lower gate electrode further includes a silicon-containing dielectric region. In some embodiments, the lower gate electrode further includes a seam filled with the same material as the gate isolation layer. In some embodiments, the lower gate electrode further includes a seam as an air gap.

[0087] Some other embodiments of the present application provide a semiconductor structure, including: a first complementary field-effect transistor (CFET) structure, including: a first lower field-effect transistor (FET), including a first lower gate electrode; a first upper field-effect transistor, including a first upper gate electrode overlapping with the first lower gate electrode; and a first gate isolation layer, located between the first lower gate electrode and the first upper gate electrode and joined to the first lower gate electrode and the first upper gate electrode; a second complementary field-effect transistor structure, including: a second lower field-effect transistor, including a second lower gate electrode; and a second upper field-effect transistor, including a second upper gate electrode overlapping with the second lower gate electrode; and an isolation region, including: a first sidewall, contacting a first edge of the first lower gate electrode and the first upper gate electrode; and a second sidewall, contacting a second edge of the second lower gate electrode and the second upper gate electrode.

[0088] In some embodiments, the semiconductor structure further includes: a second gate isolation layer, located between the second lower gate electrode and the second upper gate electrode and joined to the second lower gate electrode and the second upper gate electrode. In some embodiments, the second lower gate electrode physically contacts the second upper gate electrode.

[0089] The features of several embodiments are outlined above so that those skilled in the art can better understand various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also realize that such equivalent structures do not depart from the spirit and scope of the embodiments of the present disclosure, and various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method of fabricating a semiconductor structure, comprising: forming a lower semiconductor region; forming an upper semiconductor region overlapping the lower semiconductor region; forming a lower gate dielectric and an upper gate dielectric on the lower semiconductor region and the upper semiconductor region, respectively; forming a lower gate electrode on the lower gate dielectric and the upper gate dielectric; etching back the lower gate electrode; forming a gate isolation layer on the etched-back lower gate electrode; and forming an upper gate electrode above the gate isolation layer, wherein the upper gate electrode is located on the upper gate dielectric.

2. The method according to claim 1, further comprising patterning the gate isolation layer.

3. The method according to claim 1, wherein Forming the gate isolation layer comprises: depositing a dielectric layer; planarizing the dielectric layer; and etching back the dielectric layer, wherein a remaining portion of the dielectric layer forms the gate isolation layer.

4. The method according to claim 1, wherein A seam is formed in the lower gate electrode, and wherein after etching back the lower gate electrode, the seam is exposed.

5. The method according to claim 4, wherein, During etching back the lower gate electrode, by-products are generated to at least partially fill the seam.

6. The method according to claim 5, wherein During etching back the lower gate electrode, a silicon-containing process gas is added, and the by-products comprise a silicon-containing dielectric.

7. The method according to claim 5, wherein The by-products completely fill the seam.

8. The method according to claim 1, further comprising: etching the lower gate electrode and the upper gate electrode; and filling a dielectric region in a space left by the etched lower gate electrode and the etched upper gate electrode.

9. A semiconductor structure, comprising: a lower transistor, comprising: a first semiconductor region; a first gate dielectric located on the first semiconductor region; and a lower gate electrode located on the first gate dielectric; and an upper transistor, comprising: a second semiconductor region overlapping the first semiconductor region; a second gate dielectric located on the second semiconductor region; and an upper gate electrode located on the second gate dielectric; and a gate isolation layer located above and in contact with the lower gate electrode, wherein the gate isolation layer is also located below and in contact with the upper gate electrode.

10. A semiconductor structure, comprising: a first complementary field effect transistor (CFET) structure, comprising: a first lower field effect transistor (FET) comprising a first lower gate electrode; a first upper field effect transistor comprising a first upper gate electrode overlapping the first lower gate electrode; and a first gate isolation layer located between the first lower gate electrode and the first upper gate electrode and joined to the first lower gate electrode and the first upper gate electrode; a second complementary field effect transistor structure, comprising: a second lower field effect transistor comprising a second lower gate electrode; and a second upper field effect transistor comprising a second upper gate electrode overlapping the second lower gate electrode; and an isolation region, comprising: a first sidewall contacting a first edge of the first lower gate electrode and the first upper gate electrode; and a second sidewall contacting a second edge of the second lower gate electrode and the second upper gate electrode.

Images