Heterojunction battery structure and preparation method thereof

Abstract

The invention provides a heterojunction cell structure and a preparation method thereof, and relates to the technical field of solar cells, and the heterojunction cell structure comprises a substrate, and a metal contact region and a non-metal contact region which are formed on the front surface of the substrate; the metal contact region and the non-metal contact region form an interdigital arrangement structure; the metal contact region is provided with a metal electrode and comprises a polished surface, a passivation contact structure, a conductive layer and a passivation antireflection layer which are sequentially formed on the surface of the substrate; the non-metal contact area comprises a suede and a passivation antireflection layer which are sequentially formed on the surface of the substrate. The problems that due to the fact that an existing heterojunction cell massively uses hydrogenated amorphous silicon passivation, parasitic absorption is high, contact resistance is large, ultraviolet attenuation is caused, and cell efficiency is not high enough are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and particularly to a heterojunction cell structure and a preparation method thereof. Background Art

[0002] Most of the existing HJT cell structures use hydrogenated amorphous silicon to passivate the cell surface to obtain a relatively high open-circuit voltage (>750 mV). However, there are some problems with setting hydrogenated amorphous silicon on the substrate surface: hydrogenated amorphous silicon has serious parasitic absorption, resulting in cell current loss and restricting the improvement of cell efficiency; hydrogenated amorphous silicon contains a large number of Si-H bonds, and the Si-H bonds are easily broken by ultraviolet rays, causing the efficiency attenuation of the cell module. At present, some applications use a light conversion film (a film that converts ultraviolet rays into visible light) to solve this problem, but this greatly increases the cost of the cell. The inventors of the present application found that using a doped polysilicon / tunneling oxide layer passivation contact structure (TOPCON technology) to replace hydrogenated amorphous silicon passivation is one of the solutions to the problem. However, when introducing the TOPCON passivation contact structure on the textured surface, although the problems of amorphous silicon parasitic absorption and ultraviolet attenuation can be solved, the tips, edges, and bottoms of the textured pyramids cannot obtain uniform chemical passivation of the tunneling oxide layer and N+ internal diffusion field passivation, resulting in an inability to balance the parasitic absorption, ultraviolet attenuation, and passivation performance after replacement. Summary of the Invention

[0003] In order to overcome the above technical defects, the purpose of the present invention is to provide a heterojunction cell structure and a preparation method thereof, so as to solve the problems of high parasitic absorption, large contact resistance, ultraviolet attenuation, and insufficient cell efficiency caused by the extensive use of hydrogenated amorphous silicon passivation in existing heterojunction cells.

[0004] The present invention discloses a heterojunction cell structure. It includes a substrate and a metal contact area and a non-metal contact area formed on the surface of the substrate. The metal contact area and the non-metal contact area form an interdigitated arrangement structure. The metal contact area is provided with metal electrodes, including a polished surface, a passivation contact structure, a conductive layer, and a passivation antireflection layer formed in sequence on the surface of the substrate. The non-metal contact area includes a textured surface and a passivation antireflection layer formed in sequence on the surface of the substrate.

[0005] Preferably, the width of the metal contact area is 30 μm - 200 μm, and the width of the non-metal contact area is 100 μm - 600 μm. The area ratio of the metal contact area to the non-metal contact area is 1:1 - 1:6.

[0006] Preferably, the passivated contact structure includes a tunneling oxide layer and a phosphorus-doped polysilicon layer that are sequentially distributed on the polished surface; and / or, the passivation and antireflection layer includes one or more combinations of aluminum oxide, silicon oxide, silicon oxynitride, silicon nitride, magnesium fluoride, hydrogenated amorphous silicon, and amorphous silicon.

[0007] Preferably, the conductive layer includes one or more combinations of metals, metal compounds, and carbon-based compounds; When the conductive layer is formed only by depositing a metal to form a metal film, a protective mask is deposited on the metal film.

[0008] Preferably, the non-metal contact area includes the conductive layer and is located between the textured surface and the passivation and antireflection layer.

[0009] Preferably, the metal contact area and the non-metal contact area are located on the front side of the substrate; A hydrogenated intrinsic amorphous silicon layer, a boron-doped amorphous silicon layer, a boron-doped microcrystalline carbon silicon oxide layer, a transparent conductive film, and a metal electrode are sequentially formed on the back side of the substrate.

[0010] The present invention also provides a method for manufacturing a heterojunction cell structure for manufacturing the heterojunction cell structure according to any one of the above, including: Depositing a passivated contact structure, a conductive layer, and a passivation and antireflection layer on the surface of the substrate in sequence, wherein the metal contact area and the non-metal contact area formed on the surface of the substrate are prepared by multiple film opening and etching processes.

[0011] Preferably, after preparing the passivated contact structure on the front side of the double-sided polished substrate, local film opening is performed to form a non-metal contact area on the front side of the substrate; after removing the passivated contact structure in the non-metal contact area, texturing is performed to form an interdigitated arrangement structure of the polished surface and the textured surface on the front side of the substrate; After preparing the conductive layer and the passivation and antireflection layer on the front side of the substrate, local film opening is performed again on the metal contact area outside the non-metal contact area, and a metal electrode is prepared after removing the passivation and antireflection layer in the metal contact area; A hydrogenated intrinsic amorphous silicon layer, a boron-doped amorphous silicon layer, a boron-doped microcrystalline carbon silicon oxide layer, a transparent conductive film, and a metal electrode are sequentially prepared on the back side of the substrate to form a heterojunction cell.

[0012] Preferably, after preparing the passivated contact structure and the conductive layer on the front side of the double-sided polished substrate, local film opening is performed to form a non-metal contact area on the front side of the substrate; after removing the passivated contact structure and the conductive layer in the non-metal contact area, texturing is performed to form an interdigitated arrangement structure of the polished surface and the textured surface on the substrate; After preparing the passivation and antireflection layer on the front side of the substrate, local film opening is performed again on the metal contact area outside the non-metal contact area, and a metal electrode is prepared after removing the passivation and antireflection layer in the metal contact area; Deposit an intrinsic amorphous hydrogenated silicon layer, a boron-doped amorphous silicon layer, a boron-doped microcrystalline carbon oxide silicon layer, a transparent conductive film, and a metal electrode on the back surface of the substrate to form a heterojunction battery.

[0013] Preferably, the conductive layer is formed only by depositing a metal to form a metal film, and a protective mask is deposited on the metal film before forming the non-metal contact area; after the film is opened again, the protective mask in the metal contact area is removed.

[0014] After adopting the above technical solutions, compared with the prior art, the following beneficial effects are obtained: 1. The heterojunction battery structure provided in this application has a metal contact area and a non-metal contact area. In the non-metal contact area (light-receiving area), passivation and antireflection materials such as alumina and silicon nitride are deposited on the textured surface for antireflection and passivation. In the metal contact area (where the metal electrode is arranged), a passivated contact structure (tunneling oxide layer, phosphorus-doped polysilicon layer) is deposited on the polished surface to achieve passivated contact, solving the problems of high parasitic absorption, large contact resistance, and ultraviolet attenuation caused by the use of amorphous hydrogenated silicon passivation in most existing heterojunction batteries.

[0015] 2. Preparing a passivated contact structure on the polished surface of the metal contact area avoids the problem of low passivation of the structure on the textured surface. Separately setting a passivated contact structure in the metal contact area can increase the polysilicon thickness, reduce the contact resistance, and improve the efficiency of the prepared battery without affecting the optical loss.

[0016] 3. Applying plate-type PVD for non-bypass plating and single-sided deposition can improve the preparation efficiency and reduce the complexity of the preparation process; 4. Optionally, a metal film with a low sheet resistance can be used to form the conductive layer, which can obtain a low contact resistance while greatly reducing the preparation cost. Description of the Drawings

[0017] Figure 1 Schematic diagram of a heterojunction battery structure in Embodiments 1 and 2 of a heterojunction battery structure and its preparation method according to the present invention; Figure 2 In Embodiment 2 of a heterojunction battery structure and its preparation method according to the present invention, the preparation Figure 1 Schematic diagram of the structure of the textured surface formed after the first film opening when preparing the heterojunction battery structure shown; Figure 3 In Embodiment 2 of a heterojunction battery structure and its preparation method according to the present invention, the preparation Figure 1 Schematic diagram of the structure after preparing the conductive layer and the passivated antireflection film when preparing the heterojunction battery structure shown; Figure 4 In Embodiment 2 of a heterojunction battery structure and its preparation method according to the present invention, the preparation Figure 1 Schematic diagram of the structure after the second film opening when preparing the heterojunction battery structure shown; Figure 5 Schematic diagram of another heterojunction battery structure in Embodiment 1 and Embodiment 2 of the heterojunction battery structure and its preparation method according to the present invention; Figure 6 During the preparation of the heterojunction battery structure shown in Embodiment 2 of the heterojunction battery structure and its preparation method according to the present invention Figure 5 Schematic diagram of the structure with a textured surface formed after the first film opening when preparing the heterojunction battery structure shown; Figure 7 During the preparation of the heterojunction battery structure shown in Embodiment 2 of the heterojunction battery structure and its preparation method according to the present invention Figure 5 Schematic diagram of the structure after preparing the passivation antireflection film when preparing the heterojunction battery structure shown; Figure 8 During the preparation of the heterojunction battery structure shown in Embodiment 2 of the heterojunction battery structure and its preparation method according to the present invention Figure 5 Schematic diagram of the structure after the second film opening when preparing the heterojunction battery structure shown.

[0018] Reference numerals: 1 - Substrate; 21 - N+ inner diffusion region; 22 - Tunnel oxide layer; 23 - Phosphorus-doped polysilicon layer; 3 - Conductive layer; 4 - Protection mask; 51 - Aluminum oxide; 52 - Silicon nitride; 61 - Intrinsic amorphous silicon layer; 62 - Boron-doped amorphous silicon layer and boron-doped microcrystalline carbon oxide silicon layer; 63 - Conductive film; 7 - Metal electrode. Detailed implementation manners

[0019] The advantages of the present invention will be further elaborated below in conjunction with the accompanying drawings and specific embodiments.

[0020] Here, the exemplary embodiments will be described in detail, and the examples are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present disclosure. On the contrary, they are merely examples of the devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0021] The terms used in the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. The singular forms "a", "the" and "said" used in the present disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0022] In the description of the present invention, it should be understood that the orientation or positional relationships indicated by the terms "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationships shown in the drawings. These are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present invention.

[0023] Embodiment 1: This embodiment discloses a heterojunction battery structure. A metal contact area and a non-metal contact area are defined on the surface of the substrate. The metal contact area is used to arrange metal electrodes, and the non-metal contact area is the light-receiving area. By integrating the TOPCON passivation contact structure and the textured surface in different areas, the contact resistance can be reduced without affecting the optical loss, so as to obtain a battery with better performance.

[0024] Specifically, referring to Figure 1 or Figure 5 (It should be noted that the colors in the drawings are only used to distinguish / represent each layer), the battery structure includes a substrate and a metal contact area (where the metal electrode is located, and the substrate surface is a straight line) and a non-metal contact area (the substrate surface is a textured surface indicated by a broken line) formed on the surface (front surface) of the substrate; the metal area contact area and the non-metal contact area form an interdigitated arrangement structure; it can be understood that this "interdigitated arrangement structure" means that the metal contact area and the non-metal contact area are arranged alternately and share a diffusion area (when the battery is annealed, phosphorus atoms enter the substrate to form an N+ inner diffusion area), and the alternate arrangement effectively utilizes the space. Specifically, preferably, the width of the metal contact area is set to be 30 μm - 200 μm, and the width of the non-metal contact area is 100 μm - 600 μm; the area ratio of the metal contact area to the non-metal contact area is 1:1 - 1:6 to achieve a better spatial layout, better optical effect, passivation effect, and contact resistance.

[0025] The above metal contact region is provided with metal electrodes, including a polished surface, a passivated contact structure, a conductive layer, and a passivated antireflection layer formed in sequence on the surface of the substrate; the non-metal contact region includes a textured surface and a passivated antireflection layer formed in sequence on the surface of the substrate. Specifically, a passivated contact structure is separately provided in the metal region, which can increase the polysilicon thickness and reduce the contact resistance without affecting the optical loss; a passivated contact structure (including an N+ in-diffusion region (formed after annealing), a tunneling oxide layer, and phosphorus-doped polysilicon) is deposited on the polished surface to achieve passivated contact, reducing the problem of low passivation of the TOPCON structure on the textured surface. A passivated contact structure is separately provided in the metal contact region; in the non-metal contact region, a passivated antireflection material is deposited on the textured surface for antireflection and passivation, reducing the use of materials with high parasitic absorption such as amorphous silicon and polysilicon, reducing the battery current loss, and avoiding ultraviolet attenuation at the same time. Thus, through the integration of the non-metal contact region and the metal contact region, a battery structure is provided in which a passivated antireflection film on the textured surface of the non-metal contact region and a polysilicon patterned interdigitated arrangement on the polished surface of the metal contact region are formed, effectively solving the problems of high parasitic absorption, large contact resistance, and ultraviolet attenuation caused by the extensive use of hydrogenated amorphous silicon passivation in existing heterojunction batteries.

[0026] Specifically, the above passivated contact structure includes a tunneling oxide layer and a phosphorus-doped polysilicon layer distributed in sequence on the polished surface; that is, the TOPCON structure, that is, the doped polysilicon / tunneling oxide layer passivated contact structure (TOPCON technology) replaces the commonly used hydrogenated amorphous silicon passivation at present, reducing the problems of high parasitic absorption, large contact resistance, and ultraviolet attenuation.

[0027] It can be understood that the above phosphorus-doped polysilicon layer is formed by annealing a phosphorus-doped amorphous silicon layer. The passivated contact structure may also include other polysilicon layers formed by annealing, such as an intrinsic amorphous silicon layer and an oxygen-doped amorphous silicon layer, further optimizing the parasitic absorption and current loss of the battery; other existing methods for forming a phosphorus-doped polysilicon layer and / or adding other layers that do not affect the battery structure can also be used here.

[0028] Based on the above, the (combined passivation) battery structure provided in this embodiment includes a patterned interdigitated arrangement structure integrating the textured surface and the polished surface on the substrate surface. A passivated antireflection layer is provided on the textured surface, which can not only achieve surface passivation and antireflection, but also not directly deposit a passivated contact structure (TOPCON structure) with a tunneling oxide layer on the textured surface. Utilizing the tunneling effect, allowing majority electrons to tunnel into the polysilicon layer, the passivated contact structure is deposited on the polished surface of the metal contact region, and a passivated antireflection layer with passivation and antireflection functions is placed on the textured surface. Thus, the problem that the tips, edges, and bottoms of the pyramids on the textured surface cannot obtain uniform high-quality tunneling oxide layer chemical passivation and N+ in-diffusion field passivation can be solved.

[0029] Specifically, the passivation antireflection layer can not only reduce the reflection of light, but also effectively passivate the surface and reduce the recombination rate of carriers. The passivation antireflection layer includes one or more combinations of aluminum oxide, silicon oxide, silicon oxynitride, silicon nitride, magnesium fluoride, hydrogenated amorphous silicon, amorphous silicon, etc. Preferably, the film thickness is set to be 40 nm - 150 nm, and the refractive index is 1.8 - 2.2.

[0030] Specifically, a metal electrode is arranged in the metal contact area, which has a conductive layer for collecting and transporting photo-generated carriers (electrons and holes) from the inside of the battery to the external circuit during battery application. The above-mentioned conductive layer can include, but is not limited to, one or more combinations of metals, metal compounds, carbon-based compounds, etc. The conductive layer can include one or more combinations of, for example, Ti, Cu, Sn, Al, Ag, Au, ITO, IWO, TiO, TiN, AZO, graphene, etc. Preferably, the film thickness is set to be 30 nm - 150 nm, and the sheet resistance is 50 - 120.

[0031] However, it should be noted that when the conductive layer is only formed by depositing a metal to form a metal film, and a protective mask is deposited on the metal film, the metal film requires high-temperature annealing for activation, and the protective mask is arranged for the metal high-temperature annealing protection layer. When using a metal compound, there is no need to add an additional mask; specifically, the protective mask can be a silicon nitride mask, or other masks such as a silicon oxide mask. Based on the above, choosing a metal to form the conductive film can replace expensive and scarce metal oxides such as ITO, effectively reducing the preparation cost, and can be selected according to actual applications.

[0032] In this embodiment, as a better choice, the metal contact area and the non-metal contact area are arranged on the front side of the substrate; on the back side of the substrate, a hydrogenated intrinsic amorphous silicon layer, a boron-doped amorphous silicon layer, a boron-doped microcrystalline carbon silicon oxide layer, a transparent conductive film, and a metal electrode are sequentially formed. That is, an interdigitated arrangement structure integrating the metal contact area and the non-metal contact area is formed on the front side of the substrate to solve the problems of low passivation of the TOPCON passivation structure prepared on the textured surface on the front side of the battery and large parasitic absorption of polysilicon with low contact resistance. And on the back side of the substrate, a passivation structure formed by boron-doped amorphous silicon can be used, and other common structures on the back side of existing batteries can also be used for this.

[0033] In a better embodiment, further, the non-metal contact area also includes the above-mentioned conductive layer, which is deposited between the textured surface and the passivation antireflection layer. As described above, the conductive layer is beneficial to the current transfer of the metal electrode. The non-metal contact area can be provided with or without the conductive layer. Optionally, the non-metal contact area can be provided with the same conductive layer as the metal contact area or a different one.

[0034] Optionally as a supplement, the above metal electrodes include one or a combination of silver, copper, aluminum, and tin. The width of the metal electrode is set to 10 μm - 50 μm, and the height of the metal electrode is set to 5 μm - 20 μm. The transparent conductive film on the back includes, but is not limited to, one or a combination of ITO (indium tin oxide), IWO (indium tungsten oxide), TiO (titanium dioxide), TiN (titanium nitride), and AZO (aluminum-doped zinc oxide, etc.). The film thickness is set to 70 nm - 150 nm, and the sheet resistance is set to 50 - 120. The same design can also be applied to the front conductive layer.

[0035] In the passivated contact structure of the metal contact area on the front of the substrate, the phosphorus-doped polysilicon layer / tunneling oxide layer / N+ inner diffusion layer formed after annealing, phosphorus-doped polysilicon thickness: 15 nm - 300 nm, effective doping concentration: 5E19 cm -3 -1E22 cm -3 , tunneling oxide layer thickness: 0.5 nm - 3 nm, ratio of tunneling silicon oxide to polysilicon thickness 1:20 - 1:300, N+ inner diffusion depth: 20 nm - 100 nm. In the structure on the back of the substrate, the boron-doped amorphous silicon includes a layer of boron-doped amorphous silicon and a layer of boron-doped carbon oxide silicon microcrystals. Intrinsic hydrogenated amorphous silicon thickness: 3 nm - 10 nm, boron-doped amorphous silicon thickness: 3 nm - 10 nm, boron-doped carbon oxide silicon microcrystal thickness: 10 nm - 30 nm, boron-doped amorphous silicon doping concentration: 1E19 cm -3 -5E19 cm -3 , boron-doped carbon oxide silicon microcrystal doping concentration: 5E19 cm -3 -2E20 cm -3 。

[0036] Optionally as a further supplement, the substrate includes an N-type silicon base. Specifically, it includes one of Czochralski single crystal and ingot single crystal. The parameters of the polished surfaces on the front and back: alkali-polished tower base morphology, reflectivity: 35% - 45%, tower base size: 5 μm - 15 μm. The parameters of the textured surface on the front include reflectivity: 9% - 12%, pyramid height: 0.8 μm - 5 μm, pyramid width: 1 μm - 5 μm.

[0037] An optional heterojunction battery structure can be formed based on the above.

[0038] Based on the above, two specific examples of heterojunction battery structures are provided in this embodiment: Example 1: Refer to Figure 1 , heterojunction battery structure: Silicon-based front side: The metal contact area is arranged from outside to inside: front metal electrode, passivation and antireflection film (silicon nitride and alumina in sequence), conductive layer (AZO), phosphorus-doped polysilicon, tunneling oxide layer, alkali-polished tower base morphology (polished surface), N+ inner diffusion region; The non-metal contact area is arranged from outside to inside: passivation and antireflection film (silicon nitride and alumina in sequence), conductive layer (AZO), textured surface. The textured surface and the polished surface are on the surface of the substrate (silicon-based), and the N+ inner diffusion region is formed by diffusing phosphorus into the silicon-based substrate.

[0039] Silicon-based back side: It is arranged from outside to inside: back metal electrode, transparent conductive film, boron-doped hydrogenated amorphous silicon, intrinsic hydrogenated amorphous, back alkali-polished tower base morphology (polished surface).

[0040] In the heterojunction cell structure in the above Example 1, conductive layers are provided in both the metal contact area and the non-metal contact area. The conductive layer is formed by applying a metal oxide and does not require a mask.

[0041] Example 2: Refer to Figure 5 , the heterojunction cell structure: Silicon-based front side: The metal contact area is arranged from outside to inside: front metal electrode, passivation and antireflection film (silicon nitride and alumina in sequence), conductive layer (Ti film, silicon nitride mask), phosphorus-doped polysilicon, tunneling oxide layer, alkali-polished tower base morphology (polished surface), N+ inner diffusion region; The non-metal contact area is arranged from outside to inside: passivation and antireflection film (silicon nitride and alumina in sequence), textured surface. The textured surface and the polished surface are on the surface of the substrate (silicon-based), and the N+ inner diffusion region is formed by diffusing phosphorus into the silicon-based substrate.

[0042] Silicon-based back side: It is arranged from outside to inside: back metal electrode, transparent conductive film, boron-doped hydrogenated amorphous silicon, intrinsic hydrogenated amorphous, back alkali-polished tower base morphology (polished surface).

[0043] In the heterojunction cell structure in the above Example 2, a conductive layer is provided in the metal contact area, and no conductive layer is provided in the non-metal contact area. The conductive layer is formed by applying a metal to form a metal film, a silicon nitride mask is provided, and the front metal electrode is connected to the Ti film.

[0044] Embodiment 2: This embodiment also provides a preparation method for a heterojunction cell structure, which is used to prepare the heterojunction cell structure described in any one of the above Embodiment 1, including: sequentially depositing a passivation contact structure, a conductive layer, and a passivation and antireflection layer on the surface of the substrate, and forming the metal contact area and the non-metal contact area (refer to the description in the above Embodiment 1) formed on the surface of the substrate by multiple (local) film opening and etching during the preparation process.

[0045] In this embodiment, based on the above-mentioned first embodiment, it is known that the heterojunction cell structure includes a metal contact region and a non-metal contact region formed on the surface of the substrate. The metal contact region and the non-metal contact region include different layers, which can improve the polysilicon thickness and add an ultra-low sheet resistance conductive film to reduce the contact resistance and improve the cell efficiency without affecting the optical loss.

[0046] It can be understood that during the preparation, each region (metal contact region and non-metal contact region) can be deposited / prepared separately. In this embodiment, to improve the preparation efficiency and optimize the preparation method, operations such as film opening, etching, and texturing are carried out during the deposition of the passivated contact structure, conductive layer, and passivated antireflection layer on the substrate to realize the preparation of the heterojunction cell with the above structure.

[0047] As an illustration, for the passivated contact structure, that is, phosphorus-doped polysilicon and tunneling oxide layer, since the non-metal contact region needs to be removed, it can be achieved by film opening and etching after preparation (so that phosphorus atoms enter the substrate to form an N+ inner diffusion region after annealing), and then texturing is carried out to realize the interdigitated arrangement structure of the polished surface and the textured surface corresponding to the metal contact region and the non-metal contact region; further, after depositing the conductive layer and the passivated antireflection layer, the passivated antireflection layer of the metal contact region is removed by film opening again to connect the metal electrode.

[0048] That is, the preparation of the above-mentioned heterojunction cell structure is realized by at least two times of film opening and etching. Further, it is also possible to optionally further open the film to prepare / connect existing other structures to meet the application requirements of different scenarios. Specifically, a laser film opening method or a pattern mask etching method can be selected for preparation. The laser film opening method has the advantages of fast speed and low cost. The laser can use nanosecond laser, picosecond laser, femtosecond laser, etc. Further, picosecond laser with low cost, low loss, and high film opening rate is preferably used, combined with subsequent wet etching to remove damage to achieve damage-free patterning preparation.

[0049] Specifically, in this embodiment, taking the heterojunction cell structures of the two examples in the above-mentioned first embodiment as an example: Specific preparation method 1: The preparation method of the heterojunction cell structure of Example 1 in Example 1 ( Figure 1 ) includes: locally opening the film after preparing the passivated contact structure on the front surface of the double-sided polished substrate to form a non-metal contact region on the front surface of the substrate; removing the passivated contact structure of the non-metal contact region and then texturing to form an interdigitated arrangement structure of the polished surface and the textured surface on the front surface of the substrate; preparing a conductive layer and a passivated antireflection layer on the front surface of the substrate, and then locally opening the film again for the metal contact region outside the non-metal contact region, removing the passivated antireflection layer in the metal contact region and then preparing a metal electrode; sequentially preparing a hydrogenated intrinsic amorphous silicon layer, a boron-doped amorphous silicon layer, a boron-doped microcrystalline carbon oxide silicon layer, a transparent conductive film, and a metal electrode on the back surface of the substrate to form a heterojunction cell.

[0050] It is understandable that in order to provide a conductive layer (metal oxide) for both the metal contact area and the non-metal contact area, the conductive layer and the passivation antireflection layer are prepared after the first film opening.

[0051] The specific preparation steps are as follows: S1: Provide a clean double-sided polished silicon wafer In this step, a wet cleaning method is used to obtain a clean silicon wafer surface. The specific implementation steps and results are as follows: The surface of the silicon wafer is cleaned with a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-15%) to remove the dirt on the silicon wafer surface. Process temperature: 55°C - 70°C, process time: 2 min - 5 min; The surface drug residues and dirt are removed by water washing. Cleaning time: 2 min - 3 min; The surface of the silicon wafer is polished with a mixed solution of potassium hydroxide (1%-10%) and an additive (0.5%-5%) to form an alkaline polishing tower base morphology and remove the cutting damage. Process temperature: 60°C - 85°C, process time (3 min - 5 min); The surface drug residues and dirt are removed by water washing. Cleaning time: 2 min - 3 min; The surface of the silicon wafer is cleaned with a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-20%) to remove the additive residues. Process temperature: 55°C - 70°C, process time: 2 min - 5 min; The surface drug residues and dirt are removed by water washing. Cleaning time: 2 min - 3 min; The surface of the silicon wafer is cleaned with a mixed solution of hydrofluoric acid (0.1%-2%), hydrochloric acid (0.1%-2%) and O3 (10 ppm - 50 ppm). At the same time, the weak etching system of O3 and HF lubricates the silicon wafer surface and reduces the burr defects on the silicon wafer surface (more conducive to amorphous silicon passivation). Process temperature: 15°C - 25°C, process time: 2 min - 3 min; The surface drug residues and dirt are removed by water washing. Cleaning time: 2 min - 3 min; The surface of the silicon wafer is cleaned with a mixed solution of hydrofluoric acid (1%-10%) and hydrochloric acid (1%-10%). Process temperature: room temperature, process time: 3 min - 5 min; The surface drug residues and dirt are removed by water washing. Cleaning time: 2 min - 3 min; The surface dirt of the silicon wafer is removed by slow lifting to dehydrate the silicon wafer. Cleaning time 0.5 min - 1 min, cleaning temperature: 20°C - 70°C; The silicon wafer is placed in a drying tank and purged at high temperature to dry the silicon wafer surface. Purging gas: nitrogen or compressed air, temperature: 80°C - 100°C, drying time: 5 min - 15 min; Taking a silicon wafer with a size of 182.2 as an example, in this step, the weight loss of the silicon wafer is: 0.3 g - 0.6 g; Surface reflectivity: 35% - 45%; Tower base size: 5μm - 15μm.

[0052] S2: Preparation of the front N+ inner diffusion region / tunneling oxide layer / phosphorus-doped polysilicon passivation contact structure: Based on the above, deposit a tunneling oxide layer and phosphorus-doped amorphous silicon on the front of the silicon wafer, and then through high-temperature annealing, crystallize the phosphorus-doped amorphous silicon into phosphorus-doped polysilicon. At the same time, phosphorus atoms are pushed into the tunneling oxide layer and enter the silicon substrate to form tunneling pinholes, thus forming an N+ inner diffusion region; In this step, the tunneling oxide layer can be prepared by tube LP, PE, ALD, plate PE, PVD, ALD, or wet oxidation in a tank; phosphorus-doped amorphous silicon can be prepared by plate PVD, PE, tube LP, or PE; it is preferably to use plate PECVD to prepare the tunneling oxide layer and plate PVD to prepare phosphorus-doped amorphous silicon. Plate PVD has the characteristics of single-sided deposition without overplating, fast deposition rate, easy in-situ doping, and easy crystallization. At the same time, plate equipment has the advantage of integrating different types of film layers for coating, reducing equipment investment and the frequency of battery vacuum-breaking coating.

[0053] In this step, when using plate PECVD to prepare the tunneling oxide layer, it can be prepared by using O2, O3, N2O, or a combination of SiH4 and one or more of the above gases. It is preferably to use O2 with low cost and high safety for preparation; the phosphorus doping source can be phosphine, phosphorus, phosphorus-doped target, etc.; it is preferably to use phosphine as the doping gas. Phosphine has the characteristics of high doping efficiency, easy decomposition, etc., and has a high matching degree with PVD coating; Adopt the plate PECVD method to oxidize the front of the polished silicon wafer (obtained in S1) to prepare the tunneling oxide layer, and use the plate PVD method to deposit a layer of phosphorus-doped amorphous silicon on the front of the oxidized silicon wafer. Adopt the high-temperature oxidation annealing method to prepare the phosphorus-doped polysilicon layer and N+ inner diffusion; The polished silicon wafer is placed on a perforated carrier plate, and the carrier plate is transferred to the loading chamber 1. The chamber is evacuated, and the carrier plate is transferred to the PECVD1 reaction chamber 1. Use the PECVD method to ionize O2 into plasma, and oxidize the surface of the silicon wafer from bottom to top through the perforated carrier plate to prepare the tunneling silicon oxide. The carrier plate is transferred to the transition chamber, the chamber is evacuated, the carrier plate is transferred to the buffer chamber 1, and then transferred to the PVD1 reaction chamber 2. Use the PVD method to deposit phosphorus-doped amorphous silicon from bottom to top through the perforated carrier plate, and then transferred to the buffer chamber 2. The carrier plate is transferred to the cooling chamber 1, the carrier plate is transferred to the unloading chamber 1, the unloading chamber is backfilled with nitrogen to the atmospheric state, the carrier plate is transferred out of the chamber, and the silicon wafer is collected to complete the film layer preparation; The silicon wafer with the front coating completed is inserted into a quartz carrier and transferred to a high-temperature annealing furnace tube. After opening the furnace door - loading the boat - evacuating - heating up - maintaining a constant temperature - leak detection - heating up - maintaining a constant temperature - oxidation - cooling down - breaking the vacuum - unloading the boat, oxidation annealing is carried out to complete the preparation of phosphorus-doped polysilicon, tunneling oxide layer, and N+ inner diffusion; Among them, gradient heating is adopted to reduce the annealing process effect differences caused by the starting temperature differences due to opening the furnace door at the furnace mouth - furnace middle - furnace tail. The specific heating method is as follows: 800°C - 820°C - 840°C - 860°C - 880°C replaces the traditional 800°C - 840°C - 880°C; different oxidation annealing temperatures are adopted in different temperature zones to reduce the annealing process effect differences at different positions caused by the rapid cooling at the furnace mouth and tail due to the water cooling of the furnace tube and the slow heating at the furnace mouth and fast heating at the furnace tail caused by opening the furnace door. The specific temperature setting method is as follows: furnace mouth - furnace middle - furnace tail: 890°C - 880°C - 885°C replaces the traditional furnace mouth - furnace middle - furnace tail: 880°C - 880°C - 880°C; oxidation annealing time: 30 min - 120 min; oxidation annealing temperature: 840°C - 950°C; oxidation annealing pressure: 600 mBar - 900 mBar; tunneling oxide layer thickness: 0.5 nm - 3 nm, which can be freely adjusted by power, belt speed, flow rate, and temperature to meet the process requirements; effective doping concentration of phosphorus-doped polysilicon doping: 5E19cm -3 -1E22cm -3 , which can be freely adjusted by phosphine flow rate, process pressure, and process time to meet the process requirements; thickness of phosphorus-doped polysilicon: 15 nm - 300 nm, which can be freely adjusted by power, belt speed, flow rate, temperature, and the number of silicon targets to meet the process requirements; thickness of annealed silicon oxide: 20 nm - 50 nm, which can be freely adjusted by oxygen flow rate, annealing time, and annealing temperature to meet the process requirements; phosphorus internal diffusion depth: 20 nm - 100 nm.

[0054] S3: The first film opening to prepare a patterned interdigital structure (forming a non-metal contact area): In this exemplary embodiment, the battery is placed on a horizontal tabletop, and a pulsed ultraviolet picosecond laser is used to etch the front annealing oxide layer to the phosphorus-doped polysilicon layer, leaving part of the phosphorus-doped polysilicon layer and the tunneling oxide layer; laser power: 50W - 500W; film opening width: 100μm - 600μm; width of the remaining annealing oxide layer: 30μm - 200μm.

[0055] S4: Texturing the front film opening area, annealing the front and back oxide layers (formed by preparing the passivation contact structure in S2), and deep cleaning In this embodiment, the selective etching of silicon and silicon oxide by potassium hydroxide is used to prepare a polished and textured interdigital arrangement structure on the front.

[0056] Clean the surface of the silicon wafer with a mixed solution of potassium hydroxide (1% - 10%) and hydrogen peroxide (5% - 15%) to remove dirt and laser dust on the silicon wafer surface. Process temperature: 55°C - 70°C, process time: 0.5 min - 1 min; Use water washing to remove the residual chemicals and dirt on the surface, washing time: 2 min - 3 min; Use a mixed solution of potassium hydroxide (1% - 10%) and additive (0.5% - 5%) to remove polysilicon and tunneling oxide layer in the front opening film area and texture at the same time. Process temperature: 60°C - 85°C, process time: 0.5 min - 1 min; Use water washing to remove the residual chemicals and dirt on the surface, washing time: 2 min - 3 min; Clean the surface of the silicon wafer with a mixed solution of potassium hydroxide (1% - 10%) and hydrogen peroxide (5% - 20%) to remove the residual additive. Process temperature: 55°C - 70°C, process time: 0.5 min - 1 min; Use water washing to remove the residual chemicals and dirt on the surface, washing time: 2 min - 3 min; Clean the surface of the silicon wafer with a mixed solution of hydrofluoric acid (1% - 10%) and hydrochloric acid (1% - 10%). Process temperature: room temperature, process time: 3 min - 5 min; Use water washing to remove the residual chemicals and dirt on the surface, washing time: 2 min - 3 min; Use slow lifting to remove dirt on the silicon wafer surface and dehydrate the silicon wafer. Washing time: 0.5 min - 1 min, washing temperature: 20°C - 70°C; Place the silicon wafer in a drying tank and blow it with high temperature to dry the surface of the silicon wafer. Blowing gas: nitrogen or compressed air, temperature: 80°C - 100°C, drying time: 5 min - 15 min; Washing method: The silicon wafer enters the solution vertically, the laser line direction of the silicon wafer is perpendicular to the solution surface, and the detachment of the residual chemicals on the silicon wafer surface is not affected by the back groove morphology; Taking the 182.2 - sized silicon wafer as an example, the silicon wafer loses weight by 0.1 g - 0.2 g after this step; The reflectivity of the textured surface: 9% - 12%.

[0057] Refer to Figure 2 , after this step, the battery structure includes a substrate, a non - metal contact area including a textured surface, and a metal contact area including a tunneling oxide layer and a phosphorus - doped polysilicon layer.

[0058] S5: Deposition of the front conductive layer and the passivation antireflection film: In this step, the conductive film layer can be prepared by plate - type PVD, plate - type RPD, or plate - type ALD; Taking AZO as an example, it is preferably deposited by plate - type PVD coating method; Plate - type PVD has the characteristics of fast deposition rate and excellent uniformity between and within wafers; AZO has the characteristics of high light transmittance, high conductivity, and high thermal stability; AZO is prepared by plate-type PVD. The silicon wafer is placed on a carbon fiber carrier plate and transferred to the process chamber. An AZO target is used, and argon and oxygen are used as working gases. Process temperature: 100 - 250 °C, process pressure: 0.2 Pa - 2 Pa, A r / O2 flow ratio: 200:1 - 100:1, power: 5000 W - 40000 W; AZO thickness: 30 nm - 150 nm; AZO sheet resistance: 50 - 120; As described above, the passivation and antireflection layer includes one or a combination of aluminum oxide, silicon oxide, silicon oxynitride, silicon nitride, magnesium fluoride, hydrogenated amorphous silicon, and amorphous silicon. It is preferably to use aluminum oxide and silicon nitride as the passivation and antireflection film. Aluminum oxide can be prepared by plate-type PECVD, plate-type ALD, plate-type PVD, tube-type PECVD, or tube-type ALD; silicon nitride can be prepared by plate-type PECVD, plate-type PVD, or tube-type PECVD; it is preferably to use plate-type ALD to prepare the front-side aluminum oxide and plate-type PECVD to prepare the front-side silicon nitride. The plate-type coating equipment has no overcoating and no pinching marks, and the front side of the battery is beautiful.

[0059] The front-side aluminum oxide is prepared by plate-type ALD. The silicon wafer is placed on a carbon fiber carrier plate and transferred to the process chamber. Trimethylaluminum and water are used as process gases. Process temperature: 200 °C - 400 °C, process time: 3 min - 30 min, trimethylaluminum / water flow ratio: 1:2 - 2:1; the front-side silicon nitride is prepared by plate-type PECVD. The silicon wafer is placed on a carbon fiber carrier plate and transferred to the process chamber. Silane and ammonia are used as process gases. Process temperature: 400 °C - 450 °C, process time: 2 min - 10 min, silane / ammonia flow ratio: 1:3 - 3:1; aluminum oxide thickness: 2 nm - 40 nm; silicon nitride thickness: 40 nm - 150 nm, refractive index: 1.8 - 2.2.

[0060] Applying plate-type PECVD and depositing at 400 - 450 degrees Celsius can better protect the passivation of the excited aluminum oxide H, activate the AZO crystal at the same time, reduce the AZO sheet resistance, and improve the conductivity.

[0061] Refer to Figure 3 , after this step, the battery structure includes a substrate, a non-metal contact area including a textured surface, AZO, aluminum oxide, and silicon nitride, and a metal contact area including a tunneling oxide layer, a phosphorus-doped polysilicon layer, AZO, aluminum oxide, and silicon nitride.

[0062] S6: Preparation of depositing a hydrogenated intrinsic amorphous silicon layer, a boron-doped amorphous silicon layer, and a boron-doped microcrystalline carbon oxide silicon layer on the back: The deposition method can be plate-type PECVD or plate-type HWCVD, and it is preferably to use plate-type PECVD for deposition.

[0063] In this step: The carbon and oxygen sources for the boron-doped microcrystalline carbon oxide silicon layer can be one or more of CH4, CO2, TMB, and O2; preferably, CO2 and TMB are used as the carbon and oxygen sources.

[0064] Using the planar PECVD method, first deposit a layer of i-a:Si (hydrogenated intrinsic amorphous silicon layer) on the back side of the silicon wafer after front-side coating from top to bottom, then perform HPT cleaning (H ion cleaning) on the deposited surface, and finally use the planar PECVD method to deposit P-a:Si on the back side of the silicon wafer from top to bottom. The deposition includes (a layer of P-a:Si (boron-doped amorphous silicon layer) and a layer of P-uc-SiO x C y (boron-doped microcrystalline carbon oxide silicon layer)); The silicon wafers that have been cleaned on both sides are placed on a perforated carrier plate. The carrier plate is transferred to the loading chamber 2, the chamber is evacuated, the carrier plate is transferred to the preheating buffer chamber 3, and then transferred to the PECVD2 reaction chamber 3 to deposit a layer of i-a:Si from top to bottom. Then it is transferred to the HPT cleaning buffer chamber 4 for H ion cleaning of the deposited surface to complete the preparation of i-a:Si. The carrier plate is first transferred to the transition chamber 2, then to the buffer chamber 5, and then to the PECVD3 reaction chamber 4 to deposit a layer of P-a:Si and a layer of P-uc-SiOxCy from top to bottom, and then transferred to the buffer chamber 6 to complete the preparation of P-a:Si. The carrier plate is transferred to the unloading chamber 2, backfilled with nitrogen to atmospheric pressure, the carrier plate is taken out, and the silicon wafers are collected to complete the preparation of the back passivation film layer; PECVD2 reaction chamber 3: Prepare i-a:Si by the PECVD method, using SiH4 and H2 as process gases, process temperature: 100°C - 250°C, process pressure: 10 Pa - 50 Pa, SiH4:H2 flow ratio: 1:10 - 1:30, power: 50W - 300W; PECVD3 reaction chamber 4: Prepare P-a:Si by the PECVD method. P-a:Si is divided into two layers: conventionally B-doped (boron) amorphous silicon (P-a:Si) and B-doped microcrystalline carbon oxide silicon (P-uc-SiO x C y ). The preparation of conventionally B-doped amorphous silicon (P-a:Si) uses SiH4, H2, and B2H6 as process gases, process temperature: 100°C - 250°C, process pressure: 10 Pa - 50 Pa, SiH4:H2:B2H6 (2%) flow ratio: 1:20:5 - 1:30:15, power: 50W - 300W; The B-doped microcrystalline carbon oxide silicon (P-uc-SiO x C y) Preparation: Using SiH4, H2, B2H6, CO2, and TMB as process gases, process temperature: 100°C - 250°C, process pressure: 50 Pa - 100 Pa, SiH4:H2:B2H6 (2%); flow rate ratio: 1:30:10 - 1:60:30, CO2 and TMB are micro-doping gas flow rates: 5 sccm - 20 sccm, power: 300 w - 500 W; HPT cleaning buffer chamber: Using the PECVD method to ionize H to clean the deposited surface of the silicon wafer, with H2 as the process gas, Process temperature: 100°C - 250°C, process pressure: 50 Pa - 100 Pa, power: 50 W - 400 W; i: a-Si thickness: 2 nm - 10 nm, which can be freely adjusted by power, belt speed, flow rate, temperature, and the number of ion sources to meet the process requirements; P: a-Si thickness: 10 nm - 20 nm, P-uc-SiO x C y Thickness: 20 nm - 50 nm, which can be freely adjusted by power, belt speed, flow rate, temperature, and the number of ion sources to meet the process requirements; P: a-Si doping concentration: 1E+18cm -3 -5E+18cm -3 : P-uc-SiO x C y Doping concentration: 5E+18cm -3 -2E+19cm -3 , and the doping amount can be freely adjusted by belt speed, pressure, flow rate, and temperature to meet the process requirements.

[0065] S7: Backside deposition (transparent) conductive film ITO: In this step, the transparent conductive film layer can be prepared using plate PVD, plate RPD, or plate ALD. The transparent conductive film can be one or a combination of ITO, IWO, TiO, TiN, AZO, etc.; preferably, the plate PVD coating method is used to deposit ITO to prepare the backside transparent conductive film; plate PVD has the characteristics of fast deposition rate and excellent uniformity between and within wafers; ITO has the characteristics of high light transmittance and high conductivity; a layer of ITO is deposited from bottom to top on the backside of the amorphous-deposited silicon wafer using a flat plate PVD. The amorphous-deposited silicon wafer is placed face up on the perforated carrier plate, first transferred to the loading chamber 3 for vacuum pumping, then transferred to the transition chamber 3, then to the buffer chamber 7, and finally to the PVD2 reaction chamber 5 to deposit a layer of ITO from bottom to top, completing the backside ITO deposition; the silicon wafer with backside ITO deposition is first transferred to the buffer chamber 8, then to the cooling chamber 2, and finally to the unloading chamber 3, filled with nitrogen to backfill the atmosphere, the carrier plate is taken out of the chamber, and the silicon wafers are collected. PVD2 Reaction Chamber 5: When preparing the back ITO using the PVD method, an ITO target (In2O3 / SnO2 mass ratio: 90:10) is used, and argon and oxygen are used as working gases. Process temperature: 100 - 250 °C, process pressure: 0.2 Pa - 2 Pa, Ar / O2 flow ratio: 200:1 - 100:1, power: 5000 W - 40000 W; ITO thickness: 70 nm - 150 nm; ITO sheet resistance: 50 - 120.

[0066] S8: Second Local Film Opening on the Front (Metal Contact Area) Local film opening removes the surface alumina and silicon nitride, exposing AZO; in this step, film opening can be prepared using the laser film opening method or the pattern mask etching method; preferably, the laser film opening method is used for preparation, and the laser film opening method has the advantages of fast speed and low cost; The battery is placed on a horizontal tabletop, and a pulsed ultraviolet femtosecond laser is used to locally remove the surface alumina and silicon nitride by laser film opening, exposing AZO; film opening width: 10 μm - 50 μm.

[0067] Refer to Figure 4 , after this step, the battery structure includes a substrate; on the front of the substrate: the non-metal contact area includes a textured surface, AZO, alumina, and silicon nitride, and the metal contact area includes a tunneling oxide layer, a phosphorus-doped polysilicon layer, AZO, alumina, and silicon nitride (film opening / grooving in the metal contact area); on the back of the substrate: i: a-Si, p: a-Si / P-uc-SiO x C y , TCO.

[0068] S9: Metallization: Prepare metal electrodes on the surfaces of the front and back transparent conductive films The metallization method can be electroplating or the method of curing screen-printed metal paste; in this article, the simple and environmentally friendly method of curing screen-printed metal paste is preferably used; the metal paste can be one or a combination of silver paste, silver-coated copper paste, and copper paste, and silver-coated copper paste is preferably used in this article; The silicon wafer after laser film opening is placed on a horizontal tabletop. Through screen printing technology, silver-coated copper paste is printed on the front and back of the battery. After printing, the silicon wafer is transferred to a curing furnace, dried and cured to form an ohmic contact with the conductive layer; the battery is transferred to an annealing furnace for annealing and light injection to excite H and improve passivation; the battery preparation is completed; among them, the width of the metal electrode: 10 μm - 50 μm; the height of the metal electrode: 5 μm - 20 μm.

[0069] Thus, the battery structure as described in Example 1, Example 1 is prepared ( Figure 1 ).

[0070] Specific Preparation Method 2, for the heterojunction battery structure of Example 2 in Example 1 ( Figure 5The preparation method of () includes: preparing a passivation contact structure and a conductive layer on the front side of a double-sided polished substrate, and then locally opening the film to form a non-metal contact area located on the front side of the substrate; removing the passivation contact structure and the conductive layer in the non-metal contact area and then texturing to form an interdigitated arrangement structure of a polished surface and a textured surface on the substrate; preparing a passivation antireflection layer on the front side of the substrate, and then locally opening the film again for the metal contact area outside the non-metal contact area, removing the passivation antireflection layer in the metal contact area and then preparing a metal electrode; depositing a hydrogenated intrinsic amorphous silicon layer, a boron-doped amorphous silicon layer, a boron-doped microcrystalline carbon oxide silicon layer, a transparent conductive film, and a metal electrode on the back side of the substrate to form a heterojunction battery. It can be understood that in order to set the conductive layer (metal film and protective mask) only in the metal contact area, a conductive layer is prepared again before the first film opening (i.e., before forming the non-metal contact area below). The conductive layer is formed only by metal deposition to form a metal film, and a protective mask is deposited on the metal film before forming the non-metal contact area; the protective mask in the metal contact area is removed after the film is opened again.

[0071] Referring to the above specific preparation steps, the difference from it is that: In step S2, when preparing phosphorus-doped polysilicon and N+ internal diffusion, a silicon oxide mask is deposited on the back side of the oxidized silicon wafer by using a flat PVD method at the same time: the thickness of the silicon oxide mask: 50 nm - 100 nm, which can be freely adjusted by power, belt speed, flow rate, temperature, and the number of silicon targets to meet the process requirements; Before step S3, pickling is used to remove the front annealing oxide layer, the front conductive layer (Ti layer), and deposit a silicon nitride mask, and then the above-mentioned first film opening (forming a non-metal contact area) is carried out.

[0072] Specifically, pickling is used to remove the front annealing oxide layer: In this step, hydrofluoric acid and hydrochloric acid are used to remove the front annealing oxide layer on the surface of the silicon wafer and partially remove the silicon oxide mask on the back side; (utilizing the thickness difference between the front annealing silicon oxide and the back side silicon oxide, the front side removes part of the back side and retains it) Water washing is used to remove the surface drug residues and dirt, and the washing time: 2 min - 3 min; the silicon wafer surface is washed with a mixed solution of hydrofluoric acid (1% - 10%) and hydrochloric acid (1% - 10%), the process temperature: room temperature, the process time: 3 min - 5 min; water washing is used to remove the surface drug residues and dirt, and the washing time: 2 min - 3 min; slow lifting is used to remove the dirt on the surface of the silicon wafer to dehydrate the silicon wafer, and the washing time is 0.5 min - 1 min, the washing temperature: 20℃ - 70℃; the silicon wafer is placed in a drying tank, and high-temperature blowing is carried out to dry the surface of the silicon wafer, the blowing gas: nitrogen or compressed air, the temperature: 80℃ - 100℃, the drying time: 5 min - 15 min; the remaining thickness of the silicon oxide mask: 10 nm - 30 nm Deposition of the front conductive layer (Ti layer) and the silicon nitride mask: The deposition method can be PVD, RPD, CVD, ALD, spin coating, etc.; preferably, the plate-type PVD coating method is used to deposit Ti to prepare the front conductive film; the plate-type PVD has the characteristics of fast deposition rate and excellent uniformity between and within wafers; Ti has the characteristics of high conductivity and high stability; a layer of metal Ti is deposited on the front of the pickled silicon wafer by plate-type PVD, and then a layer of silicon nitride mask is deposited on the front of the silicon wafer by plate-type PECVD; The pickled silicon wafer is placed face down on the hollow carrier plate, first transferred to the loading chamber 2 for evacuation, then transferred to the transition chamber 2 for secondary evacuation using a molecular pump, then transferred to the buffer chamber 3, and then transferred to the PVD3 reaction chamber 4. A layer of metal Ti conductive film is deposited from bottom to top by plate-type PVD, and then transferred to the buffer chamber 4 to complete the preparation of metal Ti; the silicon wafer after metal Ti deposition is first transferred to the transition chamber 3 for evacuation, then transferred to the PECVD2 reaction chamber 5 to deposit a layer of silicon nitride from bottom to top, then transferred to the cooling chamber 2, and finally transferred to the unloading chamber 2. Nitrogen is used to backfill the atmosphere, the carrier plate is taken out of the chamber, and the silicon wafer is collected; the silicon wafer after film deposition is transferred to a high-temperature annealing furnace for sintering by a track conveyor to complete the ohmic contact between polysilicon and Ti, Ti annealing, and H implantation of the silicon nitride mask; (Preparation method and function of the metal film as a conductive layer) PVD3 reaction chamber 4: When preparing the front Ti conductive film by the PVD method, a Ti target is used as the Ti source, and argon is used as the working gas. Process temperature: 100 - 250 °C, process pressure: 0.2 Pa - 2 Pa, power: 5000 W - 40000 W; PECVD2 reaction chamber 5: The silicon nitride mask is prepared by the PECVD method, using SiH4, NH3, and N2 as process gases. Process temperature: 100 °C - 450 °C, process pressure: 10 Pa - 50 Pa, SiH4:NH3:N2 flow ratio: 1:1:1 - 5:1:1, power: 50 W - 300 W; Ti film thickness: 5 nm - 150 nm; silicon nitride mask thickness: 50 nm - 100 nm; sheet resistance after annealing: 0 - 120; annealing temperature: 500 °C - 900 °C; annealing time: 1 min - 10 min.

[0073] After the above steps, open the film on the front to prepare a patterned interdigital structure (the above S3), refer to Figure 6 ; Then perform step S4: texturing in the front opening area and cleaning the silicon oxide mask on the back (refer to Figure 6 ); In S5, since the conductive layer is deposited in the above S3, depositing a passivation antireflection film (refer to Figure 7 ) is sufficient, and the deposition of the passivation antireflection film is the same as that in the previous description.

[0074] S6 - S7 is the same as described above. In S8, the second local film opening of the metal contact area (refer to Figure 8 ), the above - mentioned alumina and silicon nitride are removed. The difference between this preparation method and the above is that in local film opening, the surface alumina, silicon nitride, and silicon nitride mask are removed to expose the conductive layer, and then a metal electrode is prepared through operations similar to step S9 above.

[0075] Thus, a battery structure as described in Example 1, Example 2 ( Figure 5 ) is prepared.

[0076] It can be understood that by referring to Figures 1 - 8 it can be known that: the main differences in the preparation methods of the battery structures of Example 1, Example 2 and those of Example 1, Example 1 are mainly reflected in the preparation of the conductive layer and before and after the first film opening of the conductive layer preparation: in the battery structure of Example 1, Example 1, the conductive layer is AZO, and it is prepared together with the passivation and antireflection film after the first film opening, so that the non - metal contact area has a conductive layer; in the battery structure of Example 1, Example 1, the conductive layer is a Ti film + silicon nitride mask, which is prepared before the first film opening, so that the non - metal contact area does not have a conductive layer. In its second film opening, the silicon nitride mask is removed so that the metal electrode is connected to the Ti film.

[0077] Based on the above, a structure with a matte passivation and antireflection film in the front non - metal contact area - a polished surface polycrystalline silicon patterned interdigitated arrangement in the metal contact area is prepared by plate - type PVD non - wrap - around single - side deposition, optimizing the problem of polycrystalline silicon parasitic absorption, reducing resistance, improving battery performance and efficiency, and optimizing the preparation yield and efficiency.

[0078] It should be noted that the embodiments of the present invention have good implementability and are not any form of limitation to the present invention. Any person skilled in the art may use the disclosed technical content to change or modify it into an equivalent effective embodiment. However, as long as it does not depart from the technical content of the present invention, any modification, equivalent change, or modification made to the above embodiments according to the technical essence of the present invention still falls within the scope of the technical solution of the present invention.

Claims

1. A heterojunction battery structure, characterized in that: It includes a substrate and a metal contact area and a non-metal contact area formed on the surface of the substrate; The metal contact area and the non-metal contact area form an interdigitated arrangement structure; The metal contact area is provided with metal electrodes, including a polished surface, a passivated contact structure, a conductive layer, and a passivated antireflection layer formed on the surface of the substrate in sequence; The non-metal contact area includes a textured surface and a passivated antireflection layer formed on the surface of the substrate in sequence.

2. The heterojunction battery structure according to claim 1, characterized in that: The width of the metal contact area is 30 μm - 200 μm, and the width of the non-metal contact area is 100 μm - 600 μm; The area ratio of the metal contact area to the non-metal contact area is 1:1 - 1:

6.

3. The heterojunction battery structure according to claim 1, characterized in that: The passivated contact structure includes a tunneling oxide layer and a phosphorus-doped polysilicon layer distributed on the polished surface in sequence; And / or, the passivated antireflection layer includes one or a combination of alumina, silica, silicon oxynitride, silicon nitride, magnesium fluoride, hydrogenated amorphous silicon, amorphous silicon, etc.

4. The heterojunction battery structure according to claim 1, characterized in that: The conductive layer includes one or a combination of metals, metal compounds, carbon-based compounds, etc.; When the conductive layer is formed only by metal deposition to form a metal film, a protective mask is deposited on the metal film.

5. The heterojunction battery structure according to claim 1 or 4, characterized in that: The non-metal contact area includes the conductive layer and is located between the textured surface and the passivated antireflection layer.

6. The heterojunction battery structure according to claim 1, characterized in that: The metal contact area and the non-metal contact area are located on the front side of the substrate; A hydrogenated intrinsic amorphous silicon layer, a boron-doped amorphous silicon layer, a boron-doped microcrystalline carbon oxide silicon layer, a transparent conductive film, and a metal electrode are formed on the back side of the substrate in sequence.

7. A method for preparing a heterojunction battery structure, characterized in that, A method for preparing the heterojunction battery structure according to any one of claims 1 - 6, including: Depositing a passivated contact structure, a conductive layer, and a passivated antireflection layer on the surface of the substrate in sequence, and preparing the metal contact area and the non-metal contact area formed on the surface of the substrate by multiple film opening and etching.

8. The preparation method according to claim 7, characterized in that: After preparing the passivated contact structure on the front side of the double-sided polished substrate, locally open the film to form a non-metal contact area on the front side of the substrate; after removing the passivated contact structure in the non-metal contact area, texture to form an interdigitated arrangement structure of the polished surface and the textured surface on the front side of the substrate; After preparing the conductive layer and the passivated antireflection layer on the front side of the substrate, locally open the film again for the metal contact area outside the non-metal contact area, and prepare the metal electrode after removing the passivated antireflection layer in the metal contact area; Deposit a hydrogenated intrinsic amorphous silicon layer, a boron-doped amorphous silicon layer, a boron-doped microcrystalline carbon oxide silicon layer, a transparent conductive film, and a metal electrode on the back side of the substrate in sequence to form a heterojunction battery.

9. The preparation method according to claim 7, characterized in that: After preparing a passivation contact structure and a conductive layer on the front side of a double-sided polished substrate and locally opening the film, a non-metal contact area located on the front side of the substrate is formed; after removing the passivation contact structure and the conductive layer in the non-metal contact area, texturing is performed to form an interdigitated arrangement structure of a polished surface and a textured surface on the substrate. After preparing a passivation antireflection layer on the front side of the substrate, the film is locally opened again in the metal contact area outside the non-metal contact area, and a metal electrode is prepared after removing the passivation antireflection layer in the metal contact area. A hydrogenated intrinsic amorphous silicon layer, a boron-doped amorphous silicon layer, a boron-doped microcrystalline carbon oxide silicon layer, a transparent conductive film, and a metal electrode are deposited on the back side of the substrate to form a heterojunction battery.

10. The preparation method according to claim 9, wherein: The conductive layer is formed only by depositing a metal to form a metal film, and a protective mask is deposited on the metal film before forming the non-metal contact area; the protective mask in the metal contact area is removed after the film is opened again.

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