Carbon nanotube transistor with fully-coated ohmic electrode structure and preparation method thereof

Abstract

The invention discloses a carbon nanotube transistor with a fully-coated ohmic electrode structure and a preparation method, the transistor adopts a double-layer fully-coated ohmic electrode structure, and a carbon nanotube is in double-sided contact with a source electrode and a drain electrode. By optimizing the electrode material and structural design of the carbon nanotube field effect transistor, a carbon nanotube transistor structure in which the metal electrode with the metal adhesion layer is combined with the 360-degree full-coating ohmic electrodes at the two ends of the carbon nanotube is provided, and the contact performance and reliability of a device are remarkably improved. According to the invention, a two-step metal deposition process is adopted, so that the carbon nanotube is clamped between the upper metal electrode layer and the lower metal electrode layer, the effective contact area between the carbon nanotube and the metal electrode is enlarged, the contact resistance between the carbon nanotube and the metal electrode is reduced, and the conductivity and environmental stability of a carbon nanotube transistor device are enhanced; and the method has good process compatibility and engineering application potential.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronics technology, and further relates to a carbon nanotube transistor with an all-clad ohmic electrode structure and a preparation method thereof in the field of semiconductor device technology. The present invention can be used to manufacture flexible electronic devices, wearable devices, and carbon nanotube thin film transistors in the field of new integrated circuit technology with high performance and high reliability requirements. Background Art

[0002] Carbon nanotube field effect transistors are widely regarded as ideal materials for next-generation electronic devices due to their extremely high electron mobility, excellent thermal conductivity, and flexibility. Among them, the source-drain (ohmic) electrode is a key part affecting device performance and long-term reliability. However, the traditional electrode design has the problem of electrode peeling off, which seriously affects the electrical characteristics and stability of the device. Electrode peeling off will cause the contact between the ohmic electrode and the carbon nanotube film to be interrupted, increase the contact resistance, thereby reducing conductivity and increasing power loss. In integrated circuit applications, this loss may cause device failure and even disconnect the entire circuit. Electrode peeling off also reduces the production yield of integrated circuits, increases the manufacturing cost, and limits large-scale commercial applications in the field of engineering technology. The problem of electrode peeling off not only affects the immediate performance but also threatens the long-term stability of the device. In environments such as high temperature, humidity, or mechanical vibration, the bonding force between the electrode and the carbon nanotube film weakens, increasing the risk of electrode peeling off and affecting the long-term reliability and stability of the device. At the same time, insufficient electrode adhesion may lead to misoperation or device failure during the production process. In existing electrode material solutions, low work function metals (such as Ti, Cr) are often used to enhance electrode adhesion, but the work functions of such metals are usually lower than that of carbon nanotubes (4.5–5.0 eV), resulting in poor energy level alignment, thus forming a relatively high Schottky barrier and increasing the contact resistance. This not only limits the current transmission efficiency of the device but also may cause the switching speed of the device to decrease, affecting high-frequency applications. Low work function metals may also introduce additional interface states on the surface of carbon nanotubes, further deteriorating the contact performance. Although the Ti / Au structure can effectively improve the adhesion of the electrode, since Ti directly contacts the carbon nanotube, it seriously affects the conductivity and switching characteristics of the device. On the other hand, Pd, as a high work function metal (work function about 5.1 eV), can effectively reduce the contact resistance of carbon nanotubes and improve the conductivity of the device. However, the adhesion of Pd to common substrate materials (such as SiO) is poor and it is easy to peel off during device manufacturing or use, resulting in unstable contact.

[0003] Lijun Liu fabricated a top-gate field-effect transistor by using the dip-coating method to prepare an arrayed carbon nanotube film in his published paper "Aligned, high-density semiconducting carbon nanotube arrays for high-performance electronics" (Science 368, 850-856 (2020)). The steps of this preparation method are as follows: First, grow an arrayed carbon nanotube film on a substrate. Subsequently, deposit a palladium (Pd) layer and a gold (Au) layer sequentially on the carbon nanotube film to form an ohmic electrode, where the thickness of the Pd layer is 30 nm and the thickness of the Au layer is 50 nm. This method uses a high-work-function metal Pd to directly contact the carbon nanotubes to optimize the ohmic contact performance, thereby reducing the contact resistance. However, this method still has certain limitations. Experiments show that the adhesion force between Pd metal and SiO is weak, mainly affected by its surface free energy and interfacial interaction. Therefore, in the manufacturing of microelectronics and nanodevices, it is usually necessary to introduce an adhesion layer (such as Ti or Cr) to enhance the adhesion of Pd on the substrate. The Pd film without an adhesion layer is prone to peeling off after multiple process treatments (such as annealing, wet cleaning, or solvent treatment), thus affecting the long-term use stability of the device.

[0004] Zhenfei Hou disclosed a method for fabricating ohmic electrodes in the paper "Carbon nanotube network film-based field-effect transistor interface state optimization by ambient air annealing" (J. Appl. Phys. 28 March 2023; 133(12): 125303). The fabrication process of this method is as follows: First, an array of carbon nanotube films is grown on a substrate. Subsequently, the ohmic electrodes are fabricated using the standard lift-off process, and the electrode material is Ti / Au (5 nm / 45 nm), where the Ti layer is deposited first and directly contacts the carbon nanotube film, and then the Au layer is deposited. This structure uses Ti as an adhesion layer to enhance the adhesion of the electrode to the substrate, while Au serves as the dominant conductive layer to improve the overall conductivity of the electrode. Although this method has obvious advantages in terms of adhesion. That is, Pd is prone to electrode detachment after multiple process treatments (such as lithography, etching, cleaning, etc.) due to its weak adhesion to the substrate (such as SiO), which affects the long-term stability of the device. As a typical adhesion layer metal, Ti has a strong binding force with both the substrate and the Au layer, making the Ti / Au structure more stable during the manufacturing process, reducing the risk of electrode peeling, and improving the process compatibility and mechanical reliability of the device. However, this method still has the following deficiencies. Since Ti is a low work function metal (about 4.3 eV), while the work function of carbon nanotubes is usually between 4.5 and 5.0 eV, the work function matching between Ti and carbon nanotubes is poor, resulting in a relatively high contact resistance. This poor ohmic contact characteristic may affect the current transmission efficiency, thereby reducing the switching speed and on-state performance of the device. In contrast, Pd, as a high work function metal (about 5.1 eV), can form a lower contact resistance when directly contacting carbon nanotubes, which is beneficial to improving the conductivity of the device. Therefore, although the Ti / Au scheme improves the electrode adhesion and long-term stability, it is inferior to the Pd / Au scheme in terms of contact resistance, which may affect the performance of some high-performance devices (such as high-speed transistors, high-frequency RF devices, low-noise sensors, and high-performance field-effect transistors).

[0005] Boyuan Tian disclosed a method for fabricating carbon nanotube field effect transistors (CNTFETs) using conventional lithography and metallization processes in his paper "Wafer scale fabrication of carbon nanotube thin film transistors with high yield" (J. Appl. Phys., 21 July 2016; 120(3): 034501). The implementation steps of this technical solution are as follows. First, a metal layer of Ti / Pd (5 / 45 nm) is sequentially deposited on the substrate as the metal layer of the bottom gate, where Ti is deposited first as an adhesion layer, and Pd is deposited subsequently as a high work function metal. Then, a thin hafnium oxide (HfO) layer is grown at 90 °C by atomic layer deposition (ALD) as the gate dielectric. Subsequently, the source and drain are fabricated using the same metallization process, where the Ti / Pd thickness is 0.5 / 60 nm, and the deposition sequence is still to deposit Ti first and then Pd. Finally, the carbon nanotube thin film is deposited on the substrate that has completed the pretreatment, thus completing the entire transistor structure. In this structure, since the carbon nanotube thin film is deposited last, it only directly contacts the top of the source and drain electrodes, rather than being embedded inside the metal electrodes, which limits the effective contact area. This method takes into account the adhesion of the electrodes and the low contact resistance to a certain extent. Ti as an adhesion layer enhances the adhesion of the Pd electrode on the substrate, reduces the risk of electrode detachment, and improves the long-term stability of the device; while Pd as a high work function metal directly contacts the carbon nanotubes, reducing the contact resistance and improving the conductivity and switching performance of the device. However, this method still has the following deficiencies. Since the carbon nanotube thin film is deposited on the top of the source and drain electrodes, only a small part of the surface area of the electrodes forms direct contact with the carbon nanotubes, and most of the Pd layer does not participate in the effective contact. This limitation may lead to an increase in the local contact resistance, thus affecting the overall performance stability of the device. In addition, the carbon nanotubes are exposed to the air, making the device vulnerable to environmental factors (such as humidity and gas adsorption), resulting in a large hysteresis phenomenon and further reducing the stability of the device. Therefore, although this method can take into account the adhesion and low contact resistance to a certain extent, due to the limited effective contact area between the carbon nanotubes and the electrodes, it may still affect the performance and long-term reliability of the device.

[0006] The University of Electronic Science and Technology of China disclosed a carbon nanotube field effect transistor and its preparation method in the patent document "A suspended carbon nanotube field effect transistor and its preparation method" (application number 202110548713.1, authorization announcement number CN 113193115 B) applied for by it. The device includes a back gate electrode, a high-κ gate dielectric layer, a drain electrode, a source electrode and an active channel layer from bottom to top. The specific steps of the preparation method of the device are: first, a drain electrode and a source electrode are prepared on the front side of a clean substrate, and a back gate electrode is prepared on the back side of the substrate; then, a nanosilver (Ag) conductive film is deposited by electron beam evaporation, and a layer of semiconducting carbon nanotubes is deposited by a printing process to form an active channel layer of the transistor; finally, the nanosilver film is sintered by high-temperature annealing treatment, so that the nanosilver film of the channel layer collapses to form a suspended carbon nanotube field effect transistor. However, the structure and preparation method of the carbon nanotube field effect transistor still have certain shortcomings. First, this method uses low-work-function metal silver (Ag) as the source and drain electrode material, while the work function of silver is about 4.1-4.7eV, which is not higher than the work function of carbon nanotubes (usually 4.5-5.0eV), resulting in poor energy level alignment for electron injection or hole injection, and easily forming a high Schottky barrier, thereby increasing the contact resistance and affecting the conductivity and switching performance of the device. In contrast, high-work-function metals (such as Pd and Au) have a better match with the work function of carbon nanotubes, which can reduce the contact resistance and improve the current transmission efficiency of the device. Secondly, the carbon nanotubes prepared by this method are only printed on the surface of the metal electrode, rather than embedded in the metal electrode, which results in a limited effective contact area. Since the contact mode between the carbon nanotube and the silver electrode mainly depends on the surface contact, the interface coupling between the electrode and the carbon nanotube is weak, which further limits the efficient injection of carriers and increases the contact resistance. In addition, during the subsequent high-temperature annealing process, the collapse of the nanosilver film may cause the morphology of the electrode surface to change, reducing the contact uniformity of the carbon nanotube, thereby affecting the performance stability of the device. Summary of the invention

[0007] The purpose of the present invention is to provide a carbon nanotube transistor with a fully enclosed ohmic electrode structure and a preparation method in view of the deficiencies in the above-mentioned prior art, aiming to solve the problems in the prior art of excessively high contact resistance caused by low work function metals, electrode detachment caused by poor adhesion of high work function metals, and device performance stability caused by reduced contact uniformity of carbon nanotubes.

[0008] The technical concept for achieving the object of the present invention is to optimize the overall structural design of the carbon nanotube field-effect transistor, especially to make systematic improvements in the material selection, deposition process, and structural configuration of the ohmic electrodes, so as to enhance the contact quality and interface stability between the carbon nanotubes and the metal electrodes, reduce the contact resistance, strengthen the electrode adhesion, and comprehensively improve the conductivity, switching speed, and long-term reliability of the device. This optimization not only solves the problems existing in the prior art such as easy electrode detachment, unstable contact, and insufficient contact area, but also significantly improves the performance of the device in integrated circuit applications, laying a solid technical foundation for the large-scale manufacturability and commercial application of high-performance carbon nanotube transistors.

[0009] Specifically, in terms of material selection, the present invention uses a high work function metal as the main contact layer of the ohmic electrode, making it directly contact with the carbon nanotubes to achieve excellent energy level matching and significantly reduce the contact resistance. At the same time, an adhesion layer is introduced and deposited between the high work function metal and the substrate to effectively improve the adhesion of the metal electrode on substrate materials such as silicon oxide, thus solving the problem of poor adhesion of some traditional high work function metals, and improving the mechanical stability and environmental adaptability of the device.

[0010] In terms of process, the present invention proposes an improved method for preparing a double-layer metal structure, that is, first depositing the first metal electrode layer, then completing the transfer of the carbon nanotube film, and subsequently depositing another layer of metal on the carbon nanotubes, so that both ends of the carbon nanotubes are covered by the upper and lower layers of metal electrodes, realizing a "sandwich-style" 360° omnidirectional contact structure. Compared with the traditional top contact structure, this structure greatly increases the effective contact area between the carbon nanotubes and the electrodes, enhances the interface coupling, effectively reduces the local contact resistance, and reduces the device performance fluctuations caused by uneven contact or stress concentration. In addition, this covered structure also improves the physical stability and environmental shielding ability between the carbon nanotubes and the metal, enabling the device to still have good electrical performance and long-term reliability under complex working conditions such as high temperature, humidity change, and mechanical perturbation.

[0011] The technical solution for achieving the object of the present invention is a carbon nanotube transistor with a fully covered ohmic electrode structure, including a substrate, source and drain metal electrodes, a semiconducting carbon nanotube film, a gate dielectric layer, and a gate electrode; the transistor adopts a double-layer fully covered ohmic electrode structure for double-sided contact between the carbon nanotubes and the source-drain electrodes.

[0012] Further, the double-layer fully-clad ohmic electrode structure is composed of a substrate, a metal electrode adhesion layer, a first-layer metal electrode, a semiconducting carbon nanotube film, and a second-layer metal electrode, which are arranged successively from bottom to top; wherein, the first-layer metal electrode is composed of a source electrode and a drain electrode arranged at intervals, with a gap therebetween to form a conductive channel region; the carbon nanotube film spans over the first-layer metal electrode and is arranged as a conductive channel layer; the second-layer metal electrode covers the carbon nanotube film and corresponds vertically to the source electrode and the drain electrode below respectively, so as to construct a "360° fully-clad" metal electrode structure at both ends of the carbon nanotubes.

[0013] Further, the composition material of the gate dielectric layer is any one of SiO2, HfO2, or ZrO2.

[0014] The metal material of the metal electrode adhesion layer is one of Ti, Cr, W or an alloy formed by one or more of these metals.

[0015] The metal materials of the first-layer metal electrode and the second-layer metal electrode are both one of Pd, Au, Pt, Sc, Al or an alloy formed by one or more of these metals.

[0016] A method for preparing a carbon nanotube transistor with a fully-clad ohmic electrode structure according to the present invention includes the following steps:

[0017] Step 1, cleaning the Si substrate and lithographically aligning marks;

[0018] Step 2, preparing the first-layer metal electrode: on the pre-treated substrate, successively using lithography and Lift-off processes, depositing a metal electrode adhesion layer and a first-layer metal material to form the source and drain metal electrodes of the first layer;

[0019] Step 3, depositing a high-purity semiconducting carbon nanotube film by a solution method, completing the transfer of the carbon nanotube film, and forming a conductive channel region covering between the source and drain metal electrodes;

[0020] Step 4, using lithography and plasma etching techniques to remove the semiconducting carbon nanotube film in non-conductive channel regions, only retaining the conductive channel region between the required source and drain metal electrodes;

[0021] Step 5, preparing the second-layer metal electrode: using lithography and Lift-off processes, performing pattern definition again, and depositing an upper-layer metal material through a second metallization process, so that the semiconducting carbon nanotube film is sandwiched between the upper and lower metal layers of the source and drain metal electrodes, realizing a fully-clad ohmic contact structure on both sides of the semiconducting carbon nanotube film;

[0022] Step 6: Using atomic layer deposition technology, form a high-k gate dielectric layer above the semiconducting carbon nanotube film;

[0023] Step 7: Form a gate structure through photolithography and metal deposition, and open holes in the metal electrode regions of the source and drain to complete the construction of the overall structure of the carbon nanotube transistor.

[0024] Furthermore, the steps of depositing a metal electrode adhesion layer and a first layer of metal using photolithography and Lift-off technology are as follows:

[0025] The first step: Through photolithography, define the source and drain electrode patterns on the surface of the pre-treated substrate, and use alignment marks for precise alignment;

[0026] The second step: Use oxygen plasma etching to remove the residual photoresist after photolithography to ensure a clean surface for metal deposition;

[0027] The third step: In the photolithography pattern area, deposit an adhesion layer metal and a first layer of metal electrode by vacuum evaporation to form the source and drain metal electrodes of the first layer;

[0028] The fourth step: Remove the excess metal through Lift-off technology, and only retain the source and drain metal electrodes of the first layer in the pattern area;

[0029] Furthermore, the steps of transferring the carbon nanotube film are as follows:

[0030] The first step: Immerse the silicon wafer with the prepared first layer of metal electrode into the semiconducting carbon nanotube solution, and keep it in a static state to deposit the semiconducting carbon nanotube film;

[0031] The third step: Keep the deposition time for 12 hours to enable the semiconducting carbon nanotubes to deposit uniformly and stably on the silicon wafer surface, forming a large-area continuous semiconducting carbon nanotube film.

[0032] The third step: Take out the silicon wafer, and perform appropriate drying or post-treatment to ensure that the semiconducting carbon nanotube film adheres well as a conductive channel layer and has good conductivity.

[0033] Furthermore, the steps of redefining the pattern are as follows:

[0034] The first step: Use photolithography to redefine the source and drain metal electrode patterns again, and precisely align with the position of the first layer of metal electrode to achieve a fully encapsulated structure of the semiconducting carbon nanotube film;

[0035] The second step: Deposit a second layer of metal by vacuum evaporation to form a second layer of metal electrode covering layer;

[0036] In the third step, perform the second Lift-off process on the second-layer metal electrode coating to remove the excess metal and complete the preparation of the electrode structure.

[0037] Compared with the prior art, the present invention has the following advantages:

[0038] First, through the optimization of the selection of ohmic electrode materials, the present invention improves the combined structure of the metal electrodes in the carbon nanotube field-effect transistor. By directly contacting the high work function metal palladium with the carbon nanotubes, excellent ohmic contact characteristics are achieved, effectively reducing the contact resistance and improving the conductivity of the device. At the same time, a material with good adhesion performance is introduced as the transition layer between the substrate and palladium, enhancing the adhesion of the metal electrode on common substrates such as silicon oxide, and avoiding problems such as contact interruption, power loss, and even device failure caused by electrode detachment in the traditional structure, overcoming defects such as easy detachment and unstable contact of the traditional Pd electrode. The carbon nanotube field-effect transistor of the present invention not only takes into account the contact performance and adhesion stability, but also significantly improves the reliability of the device under harsh environments such as high temperature, humidity, and mechanical vibration.

[0039] Second, the carbon nanotube field-effect transistor of the present invention optimizes the electrode structure design and adopts a "360° full-coverage" ohmic electrode structure. By optimizing the layout of the upper and lower metal layers, both ends of the carbon nanotube film are simultaneously in complete covered contact with the upper and lower palladium layers. This structure solves the problem of limited contact area in the traditional "top contact" or "side contact" methods, significantly expanding the effective contact area between the carbon nanotubes and the metal electrode, improving the charge injection efficiency, and reducing the local contact resistance. This structure not only improves the overall electrical performance and current driving ability of the device, but also enhances the thermal stability and mechanical coupling ability of the contact interface.

[0040] Third, the present invention develops a "two-step" metal electrode deposition process, which improves the device preparation quality and contact performance through the optimization of the process flow. First, deposit the adhesion layer metal and the first-layer metal electrode on the pretreated substrate and complete the initial electrode patterning. Then, after the transfer of the carbon nanotube film is completed, deposit the upper-layer metal electrode through the second metallization process, sandwiching the carbon nanotubes between the upper and lower metal electrode layers to form a complete covered structure. The preparation process of the present invention not only ensures the direct contact between the metal electrode and the carbon nanotubes, maximizing the advantage of its low contact resistance, but also maintains the enhanced effect of the adhesion layer metal on the overall adhesion of the electrode. At the same time, this process has good repeatability and process compatibility, is applicable to the existing integrated circuit manufacturing platform, and provides a process basis and engineering feasibility for the popularization and application of carbon nanotube field-effect transistors in large-scale integration. Description of the Drawings

[0041] Figure 1 is a schematic structural diagram of the carbon nanotube transistor of the present invention;

[0042] Figure 2 is a process flow chart for manufacturing the carbon nanotube transistor of the present invention;

[0043] Figure 3 is a topographic diagram of the channel carbon nanotube film of the carbon nanotube transistor of the present invention, a structural design flow chart of the device, and diagrams of electrode detachment and electrode topography change after testing;

[0044] Figure 4 is a transmission line (TLM) model diagram of the carbon nanotube transistor of the present invention;

[0045] Figure 5 is an electrical characteristic curve diagram of the carbon nanotube transistor of the present invention. Detailed implementation manners

[0046] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0047] Refer to Figure 1 , and a further detailed description will be given to the structure of the carbon nanotube transistor according to the embodiments of the present invention. Among them, Figure 1 (a) is a schematic structural diagram of a carbon nanotube transistor without an adhesion layer metal, and the carbon nanotube film is located between the substrate and the metal electrode; Figure 1 (b) is a schematic structural diagram of a carbon nanotube transistor with an adhesion layer metal, and the carbon nanotube film is located between the substrate and the adhesion layer metal; Figure 1 (c) is a schematic structural diagram of a carbon nanotube transistor with an adhesion layer metal, and the carbon nanotube film is located above the metal electrode; Figure 1 (d) is a schematic structural diagram of a carbon nanotube transistor with a fully encapsulated ohmic electrode structure, and the carbon nanotube film is located between the first metal electrode and the second metal electrode.

[0048] Figure 1 The SWCNT in [[ ]] represents the carbon nanotube film.

[0049] The fully encapsulated ohmic electrode structure means that the metal electrode is composed of upper and lower layers of metal electrodes. The first metal electrode is located below the carbon nanotube film, and an adhesion layer is provided between it and the substrate to provide good adhesion; the second metal electrode is located above the carbon nanotube film and is vertically aligned with the lower metal electrode. The carbon nanotube film is sandwiched between the upper and lower electrodes, so as to achieve a double-sided ohmic contact structure between the carbon nanotube and the metal in the source-drain region. This structure is also called a "360° fully encapsulated" electrode structure, which significantly increases the contact area and the interface coupling strength, reduces the contact resistance, and enhances the stability and reliability of the device.

[0050] The upper and lower metal electrodes can be made of the same or different metal materials, which can be selected and optimized according to specific application requirements. In the embodiments of the present invention, the lower metal electrode adopts a Ti / Pd structure to improve the adhesion to the substrate and achieve a low contact resistance, while the upper metal electrode can be made of a high work function metal Pd or Au alone to further enhance the conductivity or thermal stability. The combined design of different metals provides greater structural flexibility and material compatibility for the device, which helps to meet various process and electrical performance requirements.

[0051] Referring to Figure 2 The process flow of the carbon nanotube transistor with the all - covered ohmic electrode structure of the embodiments of the present invention will be further described.

[0052] Step 1: Cleaning of the substrate and lithography of alignment marks.

[0053] Step 1.1: Cleaning the Si substrate.

[0054] The cleaning process includes acetone ultrasonic cleaning (3 minutes, 80 - 100W), 60 °C stripping solution treatment (15 minutes), isopropyl alcohol ultrasonic cleaning (3 minutes, 80 - 100W), and ultrapure water rinsing (2 - 3 minutes), and finally drying with N gas.

[0055] Step 1.2: Performing lithography.

[0056] First, bake on a hot plate at 200 °C for 5 minutes to remove moisture and enhance the adhesion of the photoresist. The photoresist used is AZ5214, spin - coated at a speed of 5000 rpm / s for 30 seconds to form a photoresist layer with a thickness of 1.25 μm. Perform pre - baking (1 minute, 100 °C), then expose. The exposure conditions are ultraviolet light, light intensity 400W / cm 2 , exposure time 22 seconds, and finally develop for 60 seconds, rinse with ultrapure water for 2 minutes, and then dry with N gas.

[0057] Step 1.3: Fabricating "FIDU" alignment marks.

[0058] After lithography, use SF6 / O2 gas for etching. The gas flow rates are 50 sccm and 30 sccm respectively. The etching power is 150W for the upper electrode and 50W for the lower electrode, the etching time is 10 minutes, and the etching depth is 200 - 400 nm.

[0059] Step 2: Preparing the first - layer metal electrode.

[0060] Step 2.1: Pattern the electrode material by the Lift - off process.

[0061] Select the bimetallic structure Ti / Pd as the lower ohmic electrode material, and deposit a titanium (Ti) layer and a palladium (Pd) layer in sequence. Among them, Ti acts as an adhesion layer to enhance the adhesion between the metal Pd and the substrate, while Pd acts as a high work function metal and is in direct contact with the carbon nanotubes. The core steps of this process include photolithographic pattern definition, resist residue removal, metal evaporation, and metal lift-off. Define the patterns of the source and drain electrodes on the substrate surface through photolithography, and achieve precise alignment by using the "FIDU" pattern as a registration mark. The process parameters are the same as those of the "FIDU" photolithography process. After photolithography, there may be a small amount of photoresist residue, which affects the quality of subsequent metal deposition and lift-off. Therefore, it is necessary to use oxygen plasma etching to remove the resist residue. Use O gas to etch the resist residue, with a flow rate of 200 sccm, a power of 100 W, and a processing time of 5 min to ensure the cleanliness of the sample surface and provide a high-quality substrate for metal evaporation. In the photolithographic pattern area, form the bottom source and drain electrodes by evaporating the Ti / Pd bilayer metal. The Ti layer is used for adhesion, with a thickness of 10 nm; the Pd layer acts as a high work function electrode, also with a thickness of 10 nm. The evaporation process needs to be carried out under the condition of a vacuum degree ≤ 2.0×10 -6 Torr to prevent metal oxidation or contamination. At the same time, monitor the thickness of the metal evaporation in real time through a quartz crystal oscillator monitor to ensure that the thicknesses of the Ti and Pd layers meet the requirements.

[0062] Step 2.2, after the metal evaporation is completed, it is necessary to remove the excess metal outside the photolithographic pattern and only retain the source and drain electrodes in the pattern area.

[0063] First, perform ultrasonic treatment with acetone twice, each time for 3 min, to remove the excess metal. Then, use isopropyl alcohol for ultrasonic cleaning for 3 minutes to remove the residual organic matter and photoresist on the surface. Finally, rinse with ultrapure water for 2 - 3 minutes, and then dry the sample with nitrogen to ensure the cleanliness of the sample surface and prepare for subsequent processing.

[0064] Step 3, carbon nanotube film deposition.

[0065] Use a solution of semiconducting single-walled carbon nanotubes (s-SWCNT) with a purity as high as 99.9%, place the silicon wafer in the solution, and carry out deposition for 12 hours. This process can enable the s-SWCNT to be deposited evenly and stably on the surface of the silicon wafer, forming a large-area carbon nanotube film as the conductive channel of the device.

[0066] Step 4, device isolation process (MESA).

[0067] After the deposition of the carbon nanotube film is completed, the device is isolated. The carbon nanotubes outside the channel are etched away, leaving only the carbon nanotubes within the channel region. First, photolithography of the channel pattern is performed, using photoresist as a mask to protect the carbon nanotubes in the channel region. The process parameters are the same as those of the photolithography process of "FIDU". Then, an inductively coupled plasma (ICP) device is used for etching. During the etching process, oxygen plasma is used, with a gas flow rate set at 200 sccm, a power of 100 W, and a processing time of 1 minute. During the etching process, the carbon nanotubes outside the channel are selectively removed by oxygen plasma, while the channel region is protected by the photoresist and is not affected by the etching. Care should be taken to avoid damage or denaturation of the photoresist due to excessive temperature during the etching process.

[0068] Step 5, fabricate the second-layer metal electrode.

[0069] Step 5.1, perform secondary photolithography of OHMC using the same photolithography parameters as those for the one-time fabrication of the source and drain electrodes. The main purpose of this step is to define the position and shape of the source and drain electrodes on the substrate, ensuring an accurate photolithography process, so as to achieve full encapsulation of the carbon nanotubes in subsequent steps.

[0070] Step 5.2, deposit 40 nm of Pd metal by vacuum evaporation technology. After the metal deposition, an appropriate lift-off process is used to remove the excess metal to ensure that the source and drain electrodes form only a covering layer at both ends of the carbon nanotubes. The specific lift-off steps are the same as those in the fabrication scheme of "one-time source and drain electrodes".

[0071] Step 6, grow the gate dielectric HfO₂.

[0072] Using atomic layer deposition (ALD) technology, with a deposition temperature of 90 - 300 °C, a 10 nm thick HfO₂ layer is obtained through 100 deposition cycles to complete the growth of the HfO₂ gate dielectric substrate.

[0073] Step 7, fabrication and opening of the gate of the device.

[0074] The gate metal is fabricated by the Lift-off process, which is the same as the fabrication scheme of the source and drain electrodes. First, photolithography is used to define the gate pattern on the substrate; subsequently, a 10 nm titanium (Ti) layer and a 50 nm palladium (Pd) layer are sequentially evaporated and deposited to form the gate electrode, and ultrasonic lift-off is used to remove the excess metal. Finally, after the device fabrication is completed, photolithography and etching processes are used to open holes in the source and drain electrodes. The etching gas is Cl₂ / BCl₃, and the etching rate is 1.35 nm / min.

[0075] Refer to Figure 3 , for a further detailed description of the arrangement of the channel carbon nanotubes, the device structure design, and the electrode detachment and electrode morphology changes after testing of the carbon nanotube transistor with a fully encapsulated ohmic electrode structure.

[0076] Figure 3 (a) is the SEM image of the carbon nanotube in the channel of the carbon nanotube transistor. The carbon nanotube film at the channel of the carbon nanotube transistor has a random network structure.

[0077] Figure 3 (b) is the SEM image of the device structure of the carbon nanotube transistor. Figure 3 In (b), S, G, and D represent the source, gate, and drain respectively. Figure 3 In (b), the channel length of the carbon nanotube transistor is 6 μm, the channel width is 8 μm, and the gate width is 4 μm.

[0078] Figure 3 (c) is the schematic diagram of the electrode detachment morphology after multiple tests of the carbon nanotube transistor without an adhesion layer metal.

[0079] Figure 3 (d) is the schematic diagram of the complete morphology of the carbon nanotube transistor with the all - covered ohmic electrode structure of the present invention, and the metal electrode does not fall off after multiple tests.

[0080] It can be seen from Figure 3 that the present invention effectively solves the problem of easy electrode detachment existing in the prior art.

[0081] Refer to Figure 4 for a further description of the transmission line (TLM) model of the carbon nanotube transistor with the all - covered ohmic electrode structure of the embodiments of the present invention.

[0082] Figure 4 (a) is the current - voltage curve obtained by testing. Each curve represents the test results of different source - drain spacings (L ch ). Figure 4 The curves marked as TLM3, TLM5, TLM8, TLM13, and TLM20 in (a) represent the test result curves of the devices with spacings of 3 μm, 5 μm, 8 μm, 13 μm, and 20 μm respectively.

[0083] Figure 4 (b) is the curve of source - drain spacing - resistance converted from the Figure 4 (a) current - voltage curve. The contact resistance (R c ) of the carbon nanotube transistor with the all - covered ohmic electrode structure is 14.66 Ω, and the sheet resistance (R ch ) of the carbon nanotube film at the channel is 3700 Ω / sq.

[0084] It can be seen from Figure 4 that the present invention solves the problem of large contact resistance caused by insufficient contact area existing in the prior art.

[0085] Referring to Figure 5 , the output characteristic curve and transfer characteristic curve of the carbon nanotube transistor with an all - encapsulated ohmic electrode structure according to the embodiments of the present invention are further described.

[0086] Figure 5 (a) is the output characteristic curve diagram of the carbon nanotube transistor with an all - encapsulated ohmic electrode structure, Figure 5 The different curves in (a) correspond to different gate - source voltage (V gs ) test conditions, Figure 5 The curves marked as 0, - 1, - 2, - 3, - 4, - 5 in (a) correspond to gate voltages of 0V, - 1V, - 2V, - 3V, - 4V, - 5V respectively.

[0087] Figure 5 (b) is the transfer characteristic curve diagram of the carbon nanotube transistor with an all - encapsulated ohmic electrode structure, where the bias voltage (V ds ) is - 1V. Under this condition, the maximum current (I dmax ) of the device is 2.28 mA / mm, and the on - off ratio (I on / I off ) reaches 10 5 .

[0088] It can be seen from Figure 5 that the device of the present invention has good overall electrical properties and current driving ability.

Claims

1. A carbon nanotube transistor with an all - encapsulated ohmic electrode structure, comprising a substrate, source and drain metal electrodes, a semiconducting carbon nanotube film, a gate dielectric layer, and a gate electrode; characterized in that: The transistor adopts a double-layer fully-clad ohmic electrode structure with double-sided contact between carbon nanotubes and source / drain electrodes.

2. The carbon nanotube transistor according to claim 1, wherein The double-layer fully-clad ohmic electrode structure includes a substrate, a metal electrode adhesion layer, a first-layer metal electrode, a semiconducting carbon nanotube film, and a second-layer metal electrode, which are arranged in sequence from bottom to top. Among them, the first-layer metal electrode includes source and drain electrodes arranged at intervals, with a gap therebetween to form a conductive channel region. The carbon nanotube film spans above the first-layer metal electrode and is set as a conductive channel layer. The second-layer metal electrode covers above the carbon nanotube film and corresponds vertically to the source and drain electrodes below, respectively, so as to construct a "360° fully-clad" metal electrode structure at both ends of the carbon nanotubes.

3. The carbon nanotube transistor according to claim 1, wherein, The composition material of the gate dielectric layer is any one of SiO2, HfO2, or ZrO2.

4. The carbon nanotube transistor according to claim 2, wherein The metal material of the metal electrode adhesion layer is one of Ti, Cr, W or an alloy formed by one or more of these metals.

5. The carbon nanotube transistor according to claim 2, wherein The metal materials of the first-layer metal electrode and the second-layer metal electrode are both an alloy formed by one or more of Pd, Au, Pt, Sc, and Al.

6. The method for fabricating a carbon nanotube transistor with a fully encapsulated ohmic electrode structure of the carbon nanotube transistor according to claims 1-5, characterized in that, This preparation method includes the following steps: Step 1: Clean the Si substrate and lithographically align the marks. Step 2: Prepare the first-layer metal electrode: On the pretreated substrate, use photolithography and Lift-off processes to deposit the metal electrode adhesion layer and the first-layer metal material successively to form the source and drain metal electrodes of the first layer. Step 3: Deposit a high-purity semiconducting carbon nanotube film by a solution method, complete the transfer of the carbon nanotube film, and form a conductive channel region covering between the source and drain metal electrodes. Step 4: Use photolithography and plasma etching techniques to remove the semiconducting carbon nanotube film in non-conductive channel regions, leaving only the conductive channel region between the required source and drain metal electrodes. Step 5: Prepare the second-layer metal electrode: Use photolithography and Lift-off processes to perform pattern definition again, deposit the upper-layer metal material through a second metallization process, and sandwich the semiconducting carbon nanotube film between the upper and lower metal layers of the source and drain metal electrodes to achieve a clad ohmic contact structure on both the upper and lower sides of the semiconducting carbon nanotube film. Step 6: Use atomic layer deposition technology to form a high-k gate dielectric layer above the semiconducting carbon nanotube film. Step 7: Form a gate structure through photolithography and metal deposition, and open holes in the metal electrode regions of the source and drain to complete the construction of the overall structure of the carbon nanotube transistor.

7. The preparation method of the carbon nanotube transistor according to claim 6, characterized in that, The steps of depositing the metal electrode adhesion layer and the first-layer metal by using photolithography and Lift-off processes in Step 2 are as follows: The first step: Define the source and drain electrode patterns on the surface of the pretreated substrate by photolithography and use alignment marks for precise alignment. The second step: Use oxygen plasma etching to remove the residual photoresist after lithography to ensure a clean surface for metal deposition. The third step: In the lithography pattern region, deposit the adhesion layer metal and the first-layer metal electrode by vacuum evaporation to form the source and drain metal electrodes of the first layer. In the fourth step, the excess metal is removed by the Lift-off process, and only the source and drain metal electrodes of the first layer in the patterned area are retained.

8. The method for preparing a carbon nanotube transistor according to claim 6, wherein The steps of the carbon nanotube film transfer described in step 3 are as follows: In the first step, the silicon wafer with the first layer of metal electrodes prepared is immersed in the semiconducting carbon nanotube solution, and the semiconducting carbon nanotube film is deposited while keeping it in a static state. In the third step, the deposition time is maintained for 12 hours to uniformly and stably deposit the semiconducting carbon nanotubes on the silicon wafer surface, forming a large-area continuous semiconducting carbon nanotube film. In the third step, the silicon wafer is taken out and subjected to appropriate drying or post-treatment to ensure that the semiconducting carbon nanotube film adheres well as the conductive channel layer and has good conductivity.

9. The manufacturing method of the carbon nanotube transistor according to claim 6, characterized in that, The steps of the re-patterning described in step 5 are as follows: In the first step, photolithography is used to re-define the source and drain metal electrode patterns and precisely align them with the positions of the first layer of metal electrodes to achieve a fully encapsulated structure of the semiconducting carbon nanotube film. In the second step, the second layer of metal is deposited by vacuum evaporation to form a second layer of metal electrode covering layer. In the third step, the second Lift-off stripping process is performed on the second layer of metal electrode covering layer to remove the excess metal and complete the preparation of the electrode structure.

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