Display panel, preparation method of display panel and electronic equipment

Abstract

The embodiment of the invention provides a display panel, a preparation method of the display panel and electronic equipment, and relates to the technical field of display. In the display panel, an organic planarization layer above an array driving layer is replaced by an inorganic planarization layer, water vapor in an organic film layer in the array driving layer can be blocked through the inorganic planarization layer, and the water vapor in the organic film layer in the array driving layer is completely isolated from a light-emitting device; display dark spots of the light-emitting device due to water vapor invasion are avoided, and normal display of the light-emitting device is ensured; besides, the inorganic planarization layer does not adsorb moisture in the use process, so that the moisture can be prevented from corroding the target conductive layer, the stability of signal transmission of the target conductive layer is ensured, the display panel has a good display effect, and the market competitiveness of the electronic equipment carrying the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and in particular, to a display panel, a method for manufacturing a display panel, and an electronic device. Background Art

[0002] Organic Light Emitting Diode (OLED) is considered the next-generation display technology after liquid crystal display technology. It has been widely used in various consumer electronic products such as smartphones, TVs, laptops, desktop computers, in-vehicle displays, and wearable devices due to its excellent color and image quality, and has become the mainstream technology in display panels. In the process of manufacturing traditional display panels, the light-emitting pixel patterning is usually achieved through a Fine Metal Mask (FMM). The FMM technology is mature and has rich mass production experience. However, the FMM technology also has problems such as limited precision, high development cost, and long development cycle. The maskless fine metal technology eliminates the limitations of traditional OLED processes on display screen size, resolution, and other screen performance, and has the advantages of high performance, full-domain size, and agile delivery. Patents CN118251982A, CN116648095A, CN117062489A, CN 118742138A, CN118678783A, CN118660598A, CN118675450A, CN118824188A, CN118781966A record the relevant content of the maskless fine metal technology for reference.

[0003] However, the process performance of current OLED display products still needs to be further improved. Summary of the Invention

[0004] In order to overcome the technical problems mentioned in the above technical background, the present application provides a display panel, a method for manufacturing a display panel, and an electronic device.

[0005] In a first aspect of the present application, a display panel is provided, and the display panel includes:

[0006] A substrate, the substrate includes a stacked substrate, an array driving layer, and an inorganic planarization layer. The array driving layer includes a plurality of conductive layers stacked on the substrate and insulating layers located between adjacent conductive layers. Among them, a target conductive layer is included on the side away from the substrate among the plurality of conductive layers, and at least a part of the inorganic planarization layer covers the surface of the target conductive layer;

[0007] An isolation structure, located on the side of the inorganic planarization layer away from the substrate and enclosing to form an isolation opening;

[0008] The light-emitting device is at least partially located in the isolation opening.

[0009] In a possible implementation manner of the present application, the inorganic planarization layer is a single-layer film structure or a multi-layer film structure;

[0010] The inorganic planarization layer is a single-layer film structure of silicon nitride or silicon oxide, or the inorganic planarization layer is a stacked structure of silicon nitride and silicon oxide.

[0011] In a possible implementation manner of the present application, the display panel further includes a pixel definition layer, and the pixel definition layer is located on the side of the isolation structure facing the substrate;

[0012] The pixel definition layer includes a pixel opening, the orthographic projection of the pixel opening on the substrate is located within the orthographic projection of the isolation opening on the substrate, and at least part of the light-emitting device is located within the pixel opening;

[0013] Preferably, the pixel definition layer is an inorganic pixel definition layer;

[0014] Preferably, the pixel definition layer is a single-layer structure of silicon oxide or silicon nitride, or a stacked structure formed by alternating silicon oxide and silicon nitride.

[0015] In a possible implementation manner of the present application, in a direction away from the substrate, the light-emitting device includes a first electrode, a light-emitting material layer, and a second electrode stacked in sequence;

[0016] The first electrode is located on the side of the inorganic planarization layer away from the substrate, the pixel opening exposes at least part of the first electrode, and the second electrode is electrically connected to the isolation structure.

[0017] In a possible implementation manner of the present application, the array driving layer is formed with a pixel circuit, and the inorganic planarization layer includes a film layer through hole penetrating the inorganic planarization layer in a direction perpendicular to the plane where the substrate is located;

[0018] The first electrode is connected to the pixel circuit through the film layer through hole;

[0019] Preferably, the orthographic projection of the film layer through hole on the substrate is located within the orthographic projection of the first electrode on the substrate.

[0020] In a possible implementation manner of the present application, the array driving layer includes a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer stacked in sequence on the substrate;

[0021] The fourth conductive layer is the target conductive layer;

[0022] The insulating layer includes an organic planarization layer, and the organic planarization layer is located between the third conductive layer and the fourth conductive layer.

[0023] In a possible implementation manner of the present application, the display panel further includes a thin film encapsulation film layer, and the thin film encapsulation film layer is located on the light-emitting side of the light-emitting device;

[0024] The thin film encapsulation film layer includes a first encapsulation layer, and the first encapsulation layer includes a plurality of encapsulation units for encapsulating the light-emitting devices in the isolation openings;

[0025] Preferably, the thin film encapsulation film layer further includes a second encapsulation layer, and the second encapsulation layer is located on the side of the encapsulation unit away from the substrate, and the second encapsulation layer at least covers the encapsulation unit;

[0026] Preferably, the thin film encapsulation film layer further includes a third encapsulation layer, and the third encapsulation layer is located on the side of the second encapsulation layer away from the substrate;

[0027] Preferably, the first encapsulation layer and the third encapsulation layer are inorganic encapsulation layers, and the second encapsulation layer is an organic encapsulation layer.

[0028] In a possible implementation manner of the present application, the isolation structure includes a first isolation portion and a second isolation portion stacked, the second isolation portion is disposed on the side of the first isolation portion away from the substrate, and the orthographic projection of the first isolation portion on the substrate is located within the orthographic projection of the second isolation portion on the substrate;

[0029] Preferably, the second isolation portion is a conductive isolation portion, and the first electrode of the light-emitting device is electrically connected to the second isolation portion.

[0030] In a possible implementation manner of the present application, the isolation structure further includes a third isolation portion. In the direction away from the substrate, the third isolation portion, the first isolation portion, and the second isolation portion are stacked in sequence, and the orthographic projection of the first isolation portion on the substrate is located within the orthographic projection of the third isolation portion on the substrate;

[0031] Preferably, the orthographic projection of the third isolation portion on the substrate is located within the orthographic projection of the second isolation portion on the substrate;

[0032] Preferably, the third isolation portion is a conductive isolation portion, and the first electrode is further electrically connected to the third isolation portion;

[0033] Preferably, the material of the first isolation portion includes aluminum, silver or copper, the material of the second isolation portion includes titanium or molybdenum, and the material of the third isolation portion includes molybdenum or titanium.

[0034] The second aspect of the present application further provides a method for manufacturing a display panel, the method comprising:

[0035] Providing a substrate;

[0036] Fabricating an array driving layer on the substrate, wherein the array driving layer includes a plurality of conductive layers stacked on the substrate and insulating layers located between adjacent conductive layers, and among the plurality of conductive layers, a target conductive layer is included on the side away from the substrate;

[0037] Fabricating an inorganic planarization layer on the side of the target conductive layer away from the substrate, wherein at least a part of the inorganic planarization layer covers the surface of the target conductive layer;

[0038] Fabricating an isolation structure and an isolation opening on the side of the inorganic planarization layer away from the substrate;

[0039] Fabricating a light-emitting device in the isolation opening.

[0040] In a possible implementation manner of the present application, the step of fabricating an inorganic planarization layer on the side of the target conductive layer away from the substrate includes:

[0041] Fabricating an inorganic material layer on the side of the target conductive layer away from the substrate;

[0042] Polishing the side of the inorganic material layer away from the substrate until a flat surface is formed on the side of the inorganic material layer away from the substrate, thereby obtaining the inorganic planarization layer.

[0043] In a possible implementation manner of the present application, the step of fabricating an inorganic planarization layer on the side of the target conductive layer away from the substrate includes:

[0044] Fabricating an inorganic material layer on the side of the target conductive layer away from the substrate;

[0045] Fabricating a photoresist layer on the side of the inorganic material layer away from the substrate;

[0046] Forming an etching pattern on the photoresist layer by using a halftone mask, wherein the thickness of the photoresist layer in the etching pattern is inversely proportional to the protrusion height of the inorganic material layer relative to the substrate;

[0047] Etching the inorganic material layer through the etching pattern until a flat surface is etched on the side of the inorganic material layer away from the substrate, thereby obtaining the inorganic planarization layer.

[0048] In a possible implementation manner of the present application, the step of fabricating an inorganic material layer on the side of the target conductive layer away from the substrate includes:

[0049] Place the substrate with the array driving layer fabricated thereon into a chemical vapor deposition chamber;

[0050] Deposit the inorganic material layer on the side of the target conductive layer away from the substrate by chemical vapor deposition.

[0051] In a possible implementation manner of the present application, the step of fabricating an inorganic planarization layer on the side of the target conductive layer away from the substrate includes:

[0052] Place the substrate with the array driving layer fabricated thereon into a chemical vapor deposition chamber, wherein a distance sensor is disposed at the top of the chemical vapor deposition chamber;

[0053] Deposit an inorganic material on the side of the target conductive layer away from the substrate by chemical vapor deposition;

[0054] Detect the distances between various position regions on the side of the substrate where the inorganic material is deposited and the top through the distance sensor;

[0055] When the distance between a certain target position region and the top reaches a preset distance, control an occlusion member to occlude the target position region until the distances between all position regions on the side of the substrate where the inorganic material is deposited and the top are all the preset distance, thereby obtaining the inorganic planarization layer.

[0056] In a third aspect of the present application, there is also provided an electronic device, which includes a display panel in any one of the possible implementation manners of the first aspect, or a display panel prepared by the display panel preparation method in any one of the possible implementation manners of the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and thus should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can also be obtained based on these drawings without creative efforts.

[0058] Figure 1 Schematically shows the positional relationship between the isolation structure and the isolation opening provided in this embodiment;

[0059] Figure 2 Schematically shows Figure 1 One of the cross-sectional views at the AA position in

[0060] Figure 3 Schematically shows Figure 1 Another cross-sectional view at the AA position in

[0061] Figure 4 Illustrates Figure 1 The third cross-sectional schematic diagram at the AA position in

[0062] Figure 5 Illustrates Figure 1 The fourth cross-sectional schematic diagram at the AA position in

[0063] Figure 6 Illustrates Figure 1 The fifth cross-sectional schematic diagram at the AA position in

[0064] Figure 7 Illustrates a cross-sectional schematic diagram of the isolation structure provided in this embodiment;

[0065] Figure 8 Illustrates another cross-sectional schematic diagram of the isolation structure provided in this embodiment;

[0066] Figure 9 Illustrates a flowchart of the method for manufacturing a display panel provided in this embodiment;

[0067] Figure 10 Is Figure 9 The corresponding process flow chart;

[0068] Figure 11 To implement Figure 9 A process flow chart for step S13 in

[0069] Figure 12 To implement Figure 9 Another process flow chart for step S13 in

[0070] Icon: 1 - Display panel; 11 - Substrate; 1001 - Target conductive layer; 110 - Array driving layer; 1101 - Substrate; 1102 - Buffer layer; 1103 - Active layer; 1104 - Gate insulating layer; 1105 - Gate; 1106 - Source; 1107 - Drain; 1108 - Capacitor dielectric layer; 1109 - Interlayer insulating layer; 110 - Film layer via hole; 111 - Transistor; 1110 - First capacitor electrode; 1111 - Second capacitor electrode; 1112 - Organic planarization layer; 12 - Isolation structure; 120 - Inorganic planarization layer; 1201 - Isolation opening; 121 - First isolation part; 122 - Second isolation part; 123 - Third isolation part; 13 - Light-emitting device; 131 - First electrode; 132 - Light-emitting material layer; 133 - Second electrode; 14 - Pixel defining layer; 1401 - Pixel opening; 161 - First encapsulation layer; 1611 - Encapsulation unit; 162 - Second encapsulation layer; 163 - Third encapsulation layer; 30 - Inorganic material layer; 40 - Photoresist layer; 50 - Halftone mask. Detailed implementation manners

[0071] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the following will clearly and completely describe the technical solutions in the embodiments of this application with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are some, but not all, of the embodiments of this application. The components of the embodiments of this application usually described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0072] In the description of this application, it should be noted that the orientation or positional relationship indicated by terms such as "upper" and "lower" is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the products of this application are usually placed during use. It is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to this application.

[0073] Improving the density of light-emitting devices in a display panel (i.e., pixel density) is an important way to improve the display effect. However, currently, the display panels manufactured using the fine metal evaporation mask (FMM) technology are limited by technology and cannot further increase the density of light-emitting devices. After long-term research, the inventor found that to solve the technical problem that the density of light-emitting devices cannot be further improved, an isolation structure is provided in some display panels. When the light-emitting material layer and the electrode are evaporated in one layer, the light-emitting material layer and the electrode can be disconnected at the position of the isolation structure. Different-color light-emitting devices can be formed in different isolation openings through multiple evaporation and multiple etching processes. The above process is also called light-emitting device patterning.

[0074] In the above display panel, there is a problem that some light-emitting devices show dark spots, which will affect the overall display effect of the display panel, seriously affect the user experience of consumers, and reduce the market competitiveness of electronic products equipped with this display panel. To solve the above problems, the inventor innovatively designed the following technical solutions. The following will detail the specific implementation solutions of this application with reference to the accompanying drawings. It should be noted that the defects existing in the above solutions in the prior art are all the results obtained by the inventor through practice and careful research. Therefore, the discovery process of the above technical problems and the solutions proposed by the embodiments of this application below for the above problems should be the contributions made by the inventor to this application during the invention and creation process, rather than being understood as the technical content known to those skilled in the art.

[0075] Please refer to Figure 1 and Figure 2 , Figure 1 illustrates a schematic diagram of the distribution of the isolation structure and the isolation openings, Figure 2 illustrates Figure 1Cross-sectional schematic view in the AA direction. In this embodiment, the display panel 1 includes a substrate 11, an isolation structure 12, and a light-emitting device 13. The substrate 11 includes a substrate 1101, an array driving layer 110, and an inorganic planarization layer 120. The array driving layer 110 is located on the substrate 1101. The array driving layer 110 at least includes a plurality of stacked conductive layers and an insulating layer located between adjacent conductive layers. Among them, the plurality of conductive layers include a target conductive layer 1001 on the side away from the substrate 1101, that is, the target conductive layer 1001 is the conductive layer farthest from the substrate 1101 among the plurality of conductive layers. At least part of the inorganic planarization layer 120 covers the surface of the target conductive layer 1001. The inorganic planarization layer 120 contacts and covers the surface of the target conductive layer 1001. The side of the inorganic planarization layer 120 away from the substrate 1101 has a flat surface.

[0076] The isolation structure 12 is located on the side of the inorganic planarization layer 120 facing away from the substrate 1101. The isolation structure 12 encloses an isolation opening 1201 on the side of the inorganic planarization layer 120 facing away from the substrate 1101. The isolation structure 12 will form an undercut structure. Through this undercut structure, the light-emitting device layer (such as the light-emitting material layer, electrode layer) deposited on the whole surface can be disconnected at this position, so as to independently form the film layer of the light-emitting device in different isolation openings 1201.

[0077] The light-emitting device 13 is at least partially located in the corresponding isolation opening 1201. The light-emitting device 13 corresponds to the isolation opening 1201 one by one. One light-emitting device 13 corresponds to one isolation opening 1201. The display panel 1 includes light-emitting devices 13 of multiple different light-emitting colors. Exemplarily, the display panel 1 includes a red light-emitting device, a blue light-emitting device, and a green light-emitting device. Among them, adjacent red light-emitting devices, blue light-emitting devices, and green light-emitting devices can form a pixel unit. By controlling the light-emitting brightness of the red light-emitting device, blue light-emitting device, and green light-emitting device in each pixel unit, the display brightness and color of each pixel unit can be controlled, thereby realizing the display of the picture on the display panel 1.

[0078] The inventor found that the main reason for the dark spot defect in the light-emitting device 13 is that water vapor in the organic film layer (such as the organic planarization layer) in the array driving layer 110 enters the light-emitting material layer of the light-emitting device 13. In the above structure provided in this embodiment, in the substrate 11, the organic planarization layer above the array driving layer 110 is replaced by an inorganic planarization layer. The inorganic planarization layer 120 can block the water vapor in the organic film layer in the array driving layer 110, completely isolate the water vapor in the organic film layer in the array driving layer 110 from the light-emitting device 13, and avoid the defect of display dark spots in the light-emitting device 13 due to water vapor intrusion. In addition, the inorganic planarization layer 120 will not adsorb moisture during use, so that the moisture corrosion of the target conductive layer 1001 can be avoided, the stability of the signal transmission of the target conductive layer 1001 can be ensured, the light-emitting device 13 can display normally, the display panel 1 has a good display effect, and the market competitiveness of the electronic device equipped with the display panel 1 can be improved.

[0079] In this embodiment, the inorganic planarization layer 120 can be a single-film layer structure or a multi-film layer structure. Exemplarily, the inorganic planarization layer 120 can be a single-film layer structure of silicon nitride (SiNx), the inorganic planarization layer 120 can also be a single-film layer structure of silicon oxide (SiOx), and the inorganic planarization layer 120 can also be a stacked structure of silicon oxide and silicon nitride. When the inorganic planarization layer 120 is a stacked structure of silicon oxide and silicon nitride, the inorganic planarization layer 120 can be a multi-stacked structure formed by alternating silicon oxide and silicon nitride.

[0080] The film layer formed by silicon nitride and / or silicon nitride has high density and will not form micro-cracks through which water vapor can pass. Compared with the organic planarization layer that can transmit moisture in the prior art, the inorganic planarization layer 120 formed by silicon nitride and / or silicon nitride will not only not adsorb moisture, but also block the intrusion of moisture through its own dense film layer structure. In this way, the target conductive layer 1001 covered by it can be protected, and the stability of its signal transmission affected by the moisture corrosion of the target conductive layer 1001 can be avoided, and the performance stability of the display panel 1 can be improved.

[0081] Further, please refer to Figure 3In this embodiment, the display panel 1 further includes a pixel defining layer 14, the pixel defining layer 14 is located on one side of the substrate 11, and the isolation structure 12 is located on the side of the pixel defining layer 14 away from the substrate 11, that is, at least part of the pixel defining layer 14 is located between the isolation structure 12 and the substrate 11. The pixel defining layer 14 includes a plurality of pixel openings 1401. In this embodiment, the pixel defining layer 14 may be an organic pixel defining layer or an inorganic pixel defining layer. Preferably, the pixel defining layer 14 is an inorganic pixel defining layer. When the pixel defining layer 14 is an inorganic pixel defining layer, the pixel defining layer 14 may be a single-layer structure of silicon oxide (SiOx) or silicon nitride (SiNx), or a stacked structure formed alternately of silicon oxide and silicon nitride.

[0082] In this embodiment, the pixel opening 1401 is connected to the corresponding isolation opening 1201 . Exemplarily, the orthographic projection of the pixel opening 1401 on the substrate 11 is located within the orthographic projection of the isolation opening 1201 on the substrate 11 . At least part of the light emitting device 13 is located within the corresponding pixel opening 1401 .

[0083] Further, please refer again to Figure 3 , in a direction away from the substrate 1101 (Z direction in the figure), the light emitting device 13 includes a first electrode 131, a light emitting material layer 132 and a second electrode 133 which are stacked in sequence. The first electrode 131 is located on a side of the inorganic planarization layer 120 away from the substrate 1101, the pixel opening 1401 exposes at least a portion of the first electrode 131, and the second electrode 133 is electrically connected to the isolation structure 12. In this embodiment, the first electrode 131 may be an anode of the light emitting device 13, and the second electrode 133 may be a cathode of the light emitting device 13.

[0084] In this embodiment, the isolation structure 12 can enclose a plurality of isolation openings 1201. The setting of the isolation structure 12 can form film layers of light-emitting devices 13 of different colors in different isolation openings 1201 without the need for a fine metal mask, thereby reducing the manufacturing cost of the display panel 1. The isolation structure 12 can separate the light-emitting material layer 132 and the second electrode 133 in the light-emitting device 13, so that different light-emitting devices 13 are independent of each other, so as to improve the crosstalk between adjacent light-emitting devices 13 and enhance the display effect. Adjacent light-emitting devices 13 can be independently packaged to improve the packaging yield. At the same time, due to the existence of the isolation structure 12, the light-emitting material layer 132 and the second electrode 133 in the light-emitting device 13 of each color in the display panel 1 can be first prepared on the entire surface and then patterned, thereby eliminating the fine metal mask to save the manufacturing cost of the display panel 1.

[0085] In this embodiment, a pixel circuit is formed in the array driving layer 110. The pixel circuit is composed of a plurality of transistors and a capacitor. For example, the pixel circuit can be a 3T1C circuit or an 8T1C circuit, etc. The specific structure of the pixel circuit is not limited herein.

[0086] Please refer to again Figure 3 , the inorganic planarization layer 120 includes a film layer through hole penetrating the inorganic planarization layer 120 in a direction perpendicular to the plane where the substrate 1101 is located. The first electrode 131 can be electrically connected to the pixel circuit through the film layer through hole. Specifically, the first electrode 131 is electrically connected to the transistor in the pixel circuit through the film layer through hole.

[0087] Optionally, the orthographic projection of the film layer through hole on the substrate 1101 is located within the orthographic projection of the first electrode 131 on the substrate 1101.

[0088] Please refer to Figure 4 , the array driving layer 110 further includes an active layer 1103. The active layer 1103 includes a source region (S region), a channel region (P-si region), and a drain region (D region). The transistor 111 includes a gate 1105, a source electrode 1106, and a drain electrode 1107 formed by a conductive layer. The orthographic projection of the gate 1105 on the substrate 1101 overlaps with the orthographic projection of the channel region on the substrate 1101. The source electrode 1106 is connected to the source region, and the drain electrode 1107 is connected to the drain region. In this embodiment, the first electrode 131 is connected to the source electrode 1106 or the drain electrode 1107 of the transistor 111 through the target conductive layer 1001.

[0089] Please refer to again Figure 4 , the specific film layer structure of the array driving layer 110 will be described in detail below.

[0090] The array driving layer 110 may include a buffer layer 1102, an active layer 1103, a plurality of conductive layers, and an insulating layer located between adjacent conductive layers on the substrate 1101.

[0091] The substrate 1101 can be a rigid substrate (such as a glass substrate) or a flexible substrate (such as including a polyimide layer). The buffer layer 1102 is located on one side of the substrate 1101. The active layer 1103 is located on the side of the buffer layer 1102 away from the substrate 1101. In this embodiment, the buffer layer 1102 can be prepared from inorganic materials such as silicon oxide, silicon nitride, silicon oxynitride, etc. In this embodiment, the buffer layer 1102 can be a double-layer structure of a silicon nitride (SiNx) layer and a silicon oxide (SiOx) layer formed on the substrate 1101 in sequence.

[0092] The active layer 1103 is formed on the buffer layer 1102 and partially covers the buffer layer 1102. The active layer 1103 can be formed of an inorganic semiconductor (such as amorphous silicon or polysilicon), an organic semiconductor, or an oxide semiconductor. The active layer 1103 can include a source region (S), a drain region (D), and a channel region (such as, P-Si).

[0093] A plurality of conductive layers and insulating layers located between adjacent conductive layers form a gate insulating layer 1104, a gate 1105, a source electrode 1106, a drain electrode 1107, a capacitor dielectric layer 1108, an interlayer insulating layer 1109, and a first capacitor electrode 1110 and a second capacitor electrode 1111 for forming a capacitor. The storage capacitor can include the first capacitor electrode 1110 and the second capacitor electrode 1111.

[0094] The gate insulating layer 1104 is formed on the active layer 1103 and the buffer layer 1102 not covered by the active layer 1103 to insulate and isolate the active layer 1103 and the gate 1105. The gate insulating layer 1104 can be made of materials such as silicon oxide or silicon nitride, but is not limited thereto.

[0095] The gate 1105 is formed on one side of the gate insulating layer 1104 corresponding to the position of the active layer 1103. The gate 1105 can be formed of one or more of metals such as Al, Mo, Cu, Ti, or other metal materials with low resistivity. At the same time, a first capacitor electrode 1110 of the capacitor is also formed on the gate insulating layer 1104. The first capacitor electrode 1110 is formed on the gate insulating layer 1104 and partially covers the gate insulating layer 1104. The material of the first capacitor electrode 1110 and the gate 1105 can be the same. A first conductive layer (such as, a first metal layer M1) can be fabricated on the gate insulating layer 1104 to achieve the purpose of fabricating the gate 1105 and the first capacitor electrode 1110 simultaneously.

[0096] The capacitive dielectric layer 1108 is formed on the gate insulating layer 1104 and covers the gate 1105 and the first capacitive electrode 1110. The second capacitive electrode 1111 is located on the side of the capacitive dielectric layer 1108 corresponding to the first capacitive electrode 1110 away from the substrate 1101. The orthographic projection of the second capacitive electrode 1111 on the substrate 1101 overlaps with the orthographic projection of the first capacitive electrode 1110 on the substrate 1101. The capacitive dielectric layer 1108 is used to insulate and isolate the gate 1105 from the source 1106 and the drain 1107, and to insulate and isolate the first capacitive electrode 1110 from the second capacitive electrode 1111. The capacitive dielectric layer 1108 electrically insulates the gate 1105 from the source 1106 and the drain 1107 respectively, and forms a storage capacitor between the first capacitive electrode 1110 and the second capacitive electrode 1111. The capacitive dielectric layer 1108 can also be formed of inorganic materials such as silicon nitride and silicon oxide. The second capacitive electrode 1111 is located in the second conductive layer (for example, the second metal layer M2) fabricated above the capacitive dielectric layer 1108.

[0097] The interlayer insulating layer 1109 is formed on the capacitive dielectric layer 1108 and covers the second capacitive electrode 1111, and is used to isolate the source 1106, the drain 1107 from the second capacitive electrode 1111, so that the source 1106, the drain 1107 and the second capacitive electrode 1111 are insulated from each other. The interlayer insulating layer 1109 can also be formed of inorganic materials (such as silicon nitride and silicon oxide). The structure of the interlayer insulating layer 1109 can be a bilayer or a structure with three or more layers formed of silicon nitride and silicon oxide.

[0098] The source 1106 and the drain 1107 are formed on the interlayer insulating layer 1109. The source 1106 is electrically connected to the source region (S) in the active layer 1103 through a via hole, and the drain 1107 is electrically connected to the drain region (D) in the active layer 1103 through a via hole. The electrode materials of the gate 1105, the source 1106, the drain 1107, the first capacitive electrode 1110, and the second capacitive electrode 1111 can be the same metal such as Al, Mo, Cu, Ti or one or more of other metal materials with low resistivity. The source 1106 and the drain 1107 are located in the third conductive layer (the third metal layer M3 in the figure) fabricated on the interlayer insulating layer 1109. In this embodiment, the driving layer includes a TFT (Thin Film Transistor) structure formed by the gate 1105, the source 1106, the drain 1107, and the active layer 1103, etc.

[0099] The organic planarization layer 1112 is located on the side of the third conductive layer away from the substrate 1101 and covers the source electrode 1106 and the drain electrode 1107. The fourth conductive layer (the fourth metal layer M4 in the figure) is located on the side of the organic planarization layer 1112 away from the substrate 1101. The fourth conductive layer is formed with a conductive portion that is electrically connected to the source electrode 1106 or the drain electrode 1107 of the transistor through the via hole in the film layer of the organic planarization layer 1112. The first electrode 131 of the light-emitting device 13 is electrically connected to the source electrode 1106 or the drain electrode 1107 of the transistor 111 through the conductive portion.

[0100] The film layer structure of the above array driving layer 110 is only an example provided in this embodiment. In other embodiments, the array driving layer 110 may include more film layers or only include some of the above film layers.

[0101] In the film layer structure of the array driving layer 110 in the above example, the fourth conductive layer is the target conductive layer 1001.

[0102] Further, please refer to Figure 5 , in this embodiment, the display panel 1 further includes a first encapsulation layer 161. The first encapsulation layer 161 includes a plurality of encapsulation units 1611. Different encapsulation units 1611 are used to encapsulate the light-emitting devices 13 in different isolation openings 1201. Each encapsulation unit 1611 is used to independently encapsulate the light-emitting device 13 in one isolation opening 1201. When the light-emitting devices 13 in adjacent isolation openings 1201 are light-emitting devices of the same color, two adjacent encapsulation units 1611 are connected on the side of the isolation structure 12 away from the substrate 11. When the light-emitting devices 13 in adjacent isolation openings 1201 are light-emitting devices of different colors, two adjacent encapsulation units 1611 are disconnected on the side of the isolation structure 12 away from the substrate 11, and there is a gap between the encapsulation unit 1611 located on the side of the isolation structure 12 away from the substrate 11 and the isolation structure 12.

[0103] Please refer to Figure 6, the display panel 1 also includes a second encapsulation layer 162 and a third encapsulation layer 163, the second encapsulation layer 162 covers the isolation structure 12 and the light-emitting device 13, the second encapsulation layer 162 also fills the isolation opening 1201, and the side of the second encapsulation layer 162 away from the substrate 11 includes a flat surface. The third encapsulation layer 163 is located on the side of the second encapsulation layer 162 away from the substrate 11. Among them, the first encapsulation layer 161 and the third encapsulation layer 163 are inorganic encapsulation layers, and the second encapsulation layer 162 is an organic encapsulation layer. For example, the first encapsulation layer 161 and the third encapsulation layer 163 can be formed by chemical vapor deposition (Chemical Vapor Deposition, CVD), and the second encapsulation layer 162 can be formed by inkjet printing (Ink-jet Printing, IJP). The first encapsulation layer 161, the second encapsulation layer 162 and the third encapsulation layer 163 form a thin film encapsulation structure of the display panel 1.

[0104] It is understandable that the display panel 1 may also include a touch function layer, an optical adhesive layer, a polarizer, a cover plate and other film layers stacked in sequence on the side of the third packaging layer 163 away from the substrate 11. The above film layers are conventional film layers of the display panel and will not be described in detail here.

[0105] For further information, please refer to Figure 7 The isolation structure 12 includes a first isolation portion 121 and a second isolation portion 122 which are stacked in sequence. The orthographic projection of the first isolation portion 121 on the substrate 11 is located within the orthographic projection of the second isolation portion 122 on the substrate 11. The second isolation portion 122 extends toward the corresponding isolation opening 1201 relative to the first isolation portion 121. In a cross section perpendicular to the plane of the substrate 11 and passing through the center of the isolation opening 1201, the cross section of the isolation structure 12 may be T-shaped. The first isolation portion 121 is a conductive isolation portion, and the second electrode 133 may be electrically connected to the first isolation portion 121. Exemplarily, the second electrode 133 is electrically connected by overlapping with the first isolation portion 121.

[0106] For further information, please refer to Figure 8 In the present embodiment, the isolation structure 12 further includes a third isolation portion 123. In the direction away from the substrate 11, the third isolation portion 123, the first isolation portion 121 and the second isolation portion 122 are stacked in sequence. Among them, the orthographic projection of the first isolation portion 121 on the substrate 11 may be located within the orthographic projection of the third isolation portion 123 on the substrate 11. In a cross section perpendicular to the plane of the substrate 11 and passing through the center of the isolation opening 1201, the cross section of the isolation structure 12 may be I-shaped. The third isolation portion 123 is a conductive isolation portion, and the second electrode 133 may also be electrically connected to the third isolation portion 123. Exemplarily, the second electrode 133 is electrically connected by overlapping with the third isolation portion 123.

[0107] Optionally, the material of the first isolation part 121 includes aluminum, silver or copper, the material of the second isolation part 122 includes titanium or molybdenum, and the material of the third isolation part 123 includes molybdenum or titanium.

[0108] Based on the same inventive concept, this embodiment also provides a method for manufacturing a display panel. Please refer to Figure 9 and Figure 10 , where Figure 9 illustrates a schematic flowchart of the method for manufacturing the display panel provided in this embodiment, Figure 10 is Figure 9 the corresponding process flow chart. The method for manufacturing the display panel provided in this embodiment will be described in detail below with reference to Figure 9 and Figure 10 .

[0109] Step S11: Provide a substrate 1101.

[0110] In this embodiment, the substrate 1101 can be a rigid substrate (such as a glass substrate) or a flexible substrate (such as including a polyimide layer).

[0111] Step S12: Fabricate an array driving layer 110 on the substrate 1101.

[0112] In this embodiment, the array driving layer 110 includes a plurality of conductive layers stacked on the substrate 1101 and insulating layers located between adjacent conductive layers. Among them, the plurality of conductive layers include a target conductive layer on the side far from the substrate 1101.

[0113] Step S13: Fabricate an inorganic planarization layer 120 on the side of the target conductive layer far from the substrate 1101.

[0114] The inorganic planarization layer 120 is in contact with the target conductive layer, and at least a part of the inorganic planarization layer 120 covers the surface of the target conductive layer.

[0115] Step S14: Fabricate an isolation structure 12 and an isolation opening 1201 on the side of the inorganic planarization layer 120 far from the substrate 1101.

[0116] Step S15: Fabricate a light-emitting device 13 in the isolation opening 1201.

[0117] In the above method, the isolation structure 12 can enclose to form a plurality of isolation openings 1201. The setting of the isolation structure 12 can form the film layers of light-emitting devices 13 with different colors in different isolation openings 1201 without the need for a fine metal mask, thereby reducing the manufacturing cost of the display panel 1. In addition, an inorganic planarization layer 120 is fabricated on the array driving layer 110. The inorganic planarization layer 120 can isolate the water vapor in the organic film layer in the array driving layer 110, preventing the water vapor from invading the light-emitting device 13 and causing dark spot defects of the light-emitting device 13, ensuring that the light-emitting device 13 can display normally, and the display panel 1 has a good display effect.

[0118] In an implementation manner of this embodiment, please refer to Figure 11 , step S13 can be implemented in the following manner.

[0119] First, an inorganic material layer 30 is fabricated on the side of the target conductive layer away from the substrate 1101.

[0120] Specifically, the substrate 1101 with the array driving layer 110 fabricated thereon can be placed in a chemical vapor deposition chamber, and the inorganic material layer 30 is deposited on the side of the target conductive layer away from the substrate 1101 by chemical vapor deposition. Since the side of the array driving layer 110 away from the substrate 1101 is uneven, the side of the fabricated inorganic material layer 30 away from the substrate 1101 is also uneven.

[0121] Next, the side of the inorganic material layer 30 away from the substrate 1101 is polished until a flat surface is formed on the side of the inorganic material layer 30 away from the substrate 1101, obtaining the inorganic planarization layer 120.

[0122] In another implementation manner of this embodiment, please refer to Figure 12 , step S13 can be implemented in the following manner.

[0123] First, an inorganic material layer 30 is fabricated on the side of the target conductive layer away from the substrate 1101.

[0124] Specifically, the substrate 1101 with the array driving layer 110 fabricated thereon can be placed in a chemical vapor deposition chamber, and the inorganic material layer 30 is deposited on the side of the target conductive layer away from the substrate 1101 by chemical vapor deposition. Since the side of the array driving layer 110 away from the substrate 1101 is uneven, the side of the fabricated inorganic material layer 30 away from the substrate 1101 is also uneven.

[0125] Next, a photoresist layer 40 is fabricated on the side of the inorganic material layer 30 away from the substrate 1101.

[0126] Then, a halftone mask 50 is used to form an etching pattern on the photoresist layer 40.

[0127] Exemplarily, the photoresist layer 40 may be a positive photoresist layer, and the halftone mask 50 includes a plurality of light-transmitting openings with different light transmittances. Among them, in the etched pattern, the thinner the photoresist in the area corresponding to the light-transmitting opening with a larger light transmittance. The light-transmitting opening with a large light transmittance may correspond to the area where the convex height of the inorganic material layer 30 relative to the substrate 1101 is higher. That is, in the etched pattern, the thickness of the photoresist layer 40 is inversely proportional to the convex height of the inorganic material layer 30 relative to the substrate 1101.

[0128] Finally, the inorganic material layer 30 is etched through the etched pattern until a flat surface is etched on the side of the inorganic material layer 30 away from the substrate 1101, and the inorganic planarization layer 120 is obtained.

[0129] In another implementation manner of this embodiment, step S13 can be implemented in the following way.

[0130] First, the substrate with the array driving layer is placed in the chemical vapor deposition chamber, and a distance sensor is provided at the top of the chemical vapor deposition chamber.

[0131] Next, an inorganic material is deposited on the side of the target conductive layer away from the substrate by chemical vapor deposition.

[0132] Then, the distance between each position area on the side of the substrate where the inorganic material is deposited and the top is detected by the distance sensor;

[0133] Finally, when the distance between a certain target position area and the top reaches a preset distance, a shielding member is controlled to shield the target position area until the distance between all position areas on the side of the substrate where the inorganic material is deposited and the top is the preset distance, and the inorganic planarization layer is obtained.

[0134] Based on the same inventive concept, the embodiment of the present application also provides an electronic device. The electronic device includes the display panel provided by the embodiment of the present application. The electronic device may include a smart phone, a tablet computer, a vehicle-mounted display device, a smart wearable device, a television, a notebook computer, and other devices with a display function.

[0135] An embodiment of the present application provides a display panel, a preparation method of the display panel, and an electronic device. In the display panel, the organic planarization layer above the array driving layer is replaced with an inorganic planarization layer, which can block the water vapor in the organic film layer in the array driving layer, completely isolate the water vapor in the organic film layer in the array driving layer from the light-emitting device, and avoid the defect of display dark spots caused by the invasion of water vapor into the light-emitting device. In addition, the inorganic planarization layer does not adsorb moisture during use, so as to avoid the corrosion of the target conductive layer by moisture, ensure the stability of the signal transmission of the target conductive layer, ensure that the light-emitting device can display normally, the display panel has a good display effect, and improve the market competitiveness of the electronic device equipped with the display panel.

[0136] The foregoing is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A display panel, characterized in that, The display panel includes: a substrate, which includes a stacked substrate, an array driving layer, and an inorganic planarization layer. The array driving layer includes a plurality of conductive layers stacked on the substrate and insulating layers located between adjacent conductive layers. Among them, among the plurality of conductive layers, there is a target conductive layer on the side away from the substrate, and at least part of the inorganic planarization layer covers the surface of the target conductive layer; an isolation structure, located on the side of the inorganic planarization layer away from the substrate and enclosing to form an isolation opening; a light-emitting device, at least part of which is located in the isolation opening.

2. The display panel according to claim 1, wherein The inorganic planarization layer is a single-layer structure or a multi-layer structure; The inorganic planarization layer is a single-layer structure of silicon nitride or silicon oxide, or the inorganic planarization layer is a stacked structure of silicon nitride and silicon oxide.

3. The display panel according to claim 1, wherein The display panel further includes a pixel defining layer, which is located on the side of the isolation structure facing the substrate; The pixel defining layer includes a pixel opening, the orthographic projection of the pixel opening on the substrate is located within the orthographic projection of the isolation opening on the substrate, and at least part of the light-emitting device is located within the pixel opening; Preferably, the pixel defining layer is an inorganic pixel defining layer; Preferably, the pixel defining layer is a single-layer structure of silicon oxide or silicon nitride, or a stacked structure formed by alternating silicon oxide and silicon nitride.

4. The display panel according to claim 3, wherein In the direction away from the substrate, the light-emitting device includes a first electrode, a light-emitting material layer, and a second electrode stacked in sequence; The first electrode is located on the side of the inorganic planarization layer away from the substrate, the pixel opening exposes at least part of the first electrode, and the second electrode is electrically connected to the isolation structure.

5. The display panel according to claim 4, wherein The array driving layer forms a pixel circuit, and the inorganic planarization layer includes a film layer through hole penetrating the inorganic planarization layer in a direction perpendicular to the plane where the substrate is located; The first electrode is connected to the pixel circuit through the film layer through hole; Preferably, the orthographic projection of the film layer through hole on the substrate is located within the orthographic projection of the first electrode on the substrate.

6. The display panel according to claim 1, wherein The array driving layer includes a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer stacked in sequence on the substrate; The fourth conductive layer is the target conductive layer; The insulating layer includes an organic planarization layer, and the organic planarization layer is located between the third conductive layer and the fourth conductive layer.

7. The display panel according to any one of claims 1-6, characterized in that The display panel further includes a thin film encapsulation film layer, which is located on the light-emitting side of the light-emitting device; The thin film encapsulation film layer includes a first encapsulation layer, and the first encapsulation layer includes a plurality of encapsulation units for encapsulating the light-emitting device in the isolation opening; Preferably, the thin film encapsulation film layer further includes a second encapsulation layer, which is located on the side of the encapsulation unit away from the substrate, and the second encapsulation layer at least covers the encapsulation unit; Preferably, the thin film encapsulation film layer further includes a third encapsulation layer, which is located on the side of the second encapsulation layer away from the substrate; Preferably, the first encapsulation layer and the third encapsulation layer are inorganic encapsulation layers, and the second encapsulation layer is an organic encapsulation layer.

8. The display panel according to any one of claims 1-6, characterized in that The isolation structure includes a first isolation portion and a second isolation portion which are stacked, the second isolation portion is disposed on a side of the first isolation portion away from the substrate, and a positive projection of the first isolation portion on the substrate is located within a positive projection of the second isolation portion on the substrate; Preferably, the second isolation portion is a conductive isolation portion, and a first electrode of the light-emitting device is electrically connected to the second isolation portion.

9. The display panel according to claim 8, wherein The isolation structure further includes a third isolation portion. In a direction away from the substrate, the third isolation portion, the first isolation portion, and the second isolation portion are sequentially stacked, and a positive projection of the first isolation portion on the substrate is located within a positive projection of the third isolation portion on the substrate; Preferably, a positive projection of the third isolation portion on the substrate is located within a positive projection of the second isolation portion on the substrate; Preferably, the third isolation portion is a conductive isolation portion, and the first electrode is further electrically connected to the third isolation portion; Preferably, the material of the first isolation portion includes aluminum, silver or copper, the material of the second isolation portion includes titanium or molybdenum, and the material of the third isolation portion includes molybdenum or titanium.

10. A method for preparing a display panel, characterized in that, The method includes: Providing a substrate; Fabricating an array driving layer on the substrate, wherein the array driving layer includes a plurality of conductive layers stacked on the substrate and insulating layers located between adjacent conductive layers, and among the plurality of conductive layers, there is a target conductive layer on a side away from the substrate; Fabricating an inorganic planarization layer on a side of the target conductive layer away from the substrate, wherein at least a part of the inorganic planarization layer covers the surface of the target conductive layer; Fabricating an isolation structure and an isolation opening on a side of the inorganic planarization layer away from the substrate; Fabricating a light-emitting device in the isolation opening.

11. The manufacturing method of the display panel according to claim 10, wherein, The step of fabricating the inorganic planarization layer on the side of the target conductive layer away from the substrate includes: Fabricating an inorganic material layer on the side of the target conductive layer away from the substrate; Polishing a side of the inorganic material layer away from the substrate until a flat surface is formed on the side of the inorganic material layer away from the substrate to obtain the inorganic planarization layer.

12. The manufacturing method of the display panel according to claim 10, characterized in that, The step of fabricating the inorganic planarization layer on the side of the target conductive layer away from the substrate includes: Fabricating an inorganic material layer on the side of the target conductive layer away from the substrate; Fabricating a photoresist layer on a side of the inorganic material layer away from the substrate; Forming an etching pattern on the photoresist layer by using a halftone mask, wherein a thickness of the photoresist layer in the etching pattern is inversely proportional to a height of a protrusion of the inorganic material layer relative to the substrate; Etching the inorganic material layer through the etching pattern until a flat surface is etched on the side of the inorganic material layer away from the substrate to obtain the inorganic planarization layer.

13. The method for manufacturing a display panel according to claim 11 or 12, characterized in that, The step of fabricating an inorganic material layer on the side of the target conductive layer away from the substrate includes: Placing the substrate with the array driving layer fabricated thereon into a chemical vapor deposition chamber; Depositing the inorganic material layer on the side of the target conductive layer away from the substrate by chemical vapor deposition.

14. The manufacturing method of the display panel according to claim 10, characterized in that, The step of fabricating an inorganic planarization layer on a side of the target conductive layer away from the substrate includes: Placing the substrate with the array driving layer fabricated thereon into a chemical vapor deposition chamber, wherein a distance sensor is disposed at the top of the chemical vapor deposition chamber; Depositing an inorganic material on a side of the target conductive layer away from the substrate by chemical vapor deposition; Detecting distances between respective position regions on a side of the substrate where the inorganic material is deposited and the top by means of the distance sensor; When the distance between a certain target position region and the top reaches a preset distance, controlling an occlusion member to occlude the target position region until the distances between all position regions on a side of the substrate where the inorganic material is deposited and the top are all the preset distance, thereby obtaining the inorganic planarization layer.

15. An electronic device, characterized in that, The electronic device includes the display panel according to any one of claims 1-9, or the display panel prepared by the preparation method of the display panel according to any one of claims 10-14.

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