Tracker circuit, communication device, and tracking method

Abstract

The present invention relates to a tracker circuit, a communication device, and a tracking method, the tracker circuit (1) being provided with: a switched capacitor circuit (20) configured so as to generate a plurality of discrete voltages; and an output switching circuit (30) configured to selectively output at least one of the plurality of discrete voltages to the power amplifier (2), the switched capacitor circuit (20) being configured to generate the plurality of discrete voltages on the basis of a difference between the first input voltage and a variable second input voltage lower than the first input voltage.

Description

Technical Field

[0001] The present invention relates to a tracker circuit, a communication device, and a tracking method. Background Art

[0002] In Patent Document 1, improvement in power efficiency is achieved by applying a digital envelope tracking (ET) mode in which a plurality of discrete voltages are supplied to a power amplifier.

[0003] Patent Document 1: U.S. Patent No. 8,829,993 specification.

[0004] However, in the digital ET mode, further improvement in power efficiency is desired. Summary of the Invention

[0005] Accordingly, the present invention provides a tracker circuit, a communication device, and a tracking method capable of improving power efficiency.

[0006] A tracker circuit according to one embodiment of the present invention includes: a switched capacitor circuit configured to generate a plurality of discrete voltages; and an output switch circuit configured to selectively output at least one of the plurality of discrete voltages to a power amplifier, the switched capacitor circuit being configured to generate the plurality of discrete voltages based on a difference between a first input voltage and a variable second input voltage lower than the first input voltage.

[0007] A tracker circuit according to one embodiment of the present invention includes: a switched capacitor circuit configured to include a first input terminal for receiving a first input voltage and a second input terminal for receiving a variable second input voltage lower than the first input voltage, and to generate a plurality of discrete voltages; an output switch circuit configured to selectively output at least one of the plurality of discrete voltages to a power amplifier; a first capacitor connected between the first input terminal and ground; and a second capacitor connected between the second input terminal and ground.

[0008] In a tracking method according to one embodiment of the present invention, a first input voltage and a second input voltage lower than the first input voltage are received, a plurality of first discrete voltages are generated based on a first difference between the first input voltage and the second input voltage, at least one of the plurality of first discrete voltages is selectively output to a power amplifier, a third input voltage and a fourth input voltage lower than the third input voltage are received, the fourth input voltage is different from the second input voltage, a plurality of second discrete voltages are generated based on a second difference between the third input voltage and the fourth input voltage, and at least one of the plurality of second discrete voltages is selectively output to the power amplifier.

[0009] According to the tracker circuit and the like according to one embodiment of the present invention, power efficiency can be improved. Brief Description of the Drawings

[0010] Figure 1A It is a graph showing an example of the change in the power supply voltage in the APT mode.

[0011] Figure 1B It is a graph showing an example of the change in the power supply voltage in the analog ET mode.

[0012] Figure 1C It is a graph showing an example of the change in the power supply voltage in the digital ET mode.

[0013] Figure 2 It is a circuit structure diagram of the communication device according to Embodiment 1.

[0014] Figure 3 It is a circuit structure diagram of the tracker circuit and the pre - conditioner circuit according to Embodiment 1.

[0015] Figure 4 It is a flowchart showing the tracking method according to Embodiment 1.

[0016] Figure 5A It is a graph showing the high - frequency signal modulated by QPSK and multiple discrete voltages.

[0017] Figure 5B It is a graph showing the relationship between the output power and the occurrence frequency of the power amplifier that amplifies the high - frequency signal modulated by QPSK.

[0018] Figure 5C It is a graph showing the relationship between the output power and the power efficiency of the power amplifier that amplifies the high - frequency signal modulated by QPSK.

[0019] Figure 6A It is a graph showing the high - frequency signal modulated by 256QAM and multiple discrete voltages.

[0020] Figure 6B It is a graph showing the relationship between the output power and the occurrence frequency of the power amplifier that amplifies the high - frequency signal modulated by 256QAM.

[0021] Figure 6C It is a graph showing the relationship between the output power and the power efficiency of the power amplifier that amplifies the high - frequency signal modulated by 256QAM.

[0022] Figure 7 It is a circuit structure diagram of the tracker circuit according to the modified example of Embodiment 1.

[0023] Figure 8 It is a circuit structure diagram of the communication device according to Embodiment 2.

[0024] Figure 9 This is a circuit structure diagram of the tracker circuit and the pre-tuner circuit according to Embodiment 2.

[0025] Figure 10 This is a circuit structure diagram of the communication device according to Embodiment 3.

[0026] Figure 11 This is a circuit structure diagram of the tracker circuit and the pre-tuner circuit according to Embodiment 3. Detailed Embodiment

[0027] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the embodiments described below are all general or specific examples. The values, shapes, materials, constituent elements, configurations of the constituent elements, connection methods, etc. shown in the following embodiments are examples and do not limit the gist of the present invention.

[0028] Among them, each figure is a schematic diagram appropriately emphasized, omitted, or adjusted in ratio to represent the present invention, and is not necessarily a strictly illustrated structure, and sometimes differs from the actual shape, positional relationship, and ratio. In each figure, the same reference numerals are given to substantially the same structures, and repeated descriptions may be omitted or simplified.

[0029] In the circuit structure of the present invention, the so-called "connection" includes not only the case of direct connection through connection terminals and / or wiring conductors, but also the case of electrical connection via other circuit elements. The so-called "direct connection" means direct connection through connection terminals and / or wiring conductors without passing through other circuit elements. The so-called "C is connected between A and B" means that one end of C is connected to A and the other end of C is connected to B. The so-called "path between A and B" means a path formed by conductors that electrically connect A and B.

[0030] In the circuit structure of the present invention, the so-called "terminal" means the point where the conductor in the element ends. In addition, when the impedance of the conductor between elements is sufficiently low, the terminal is interpreted not only as a single point but also as any point on the conductor between elements or the entire conductor.

[0031] In addition, terms indicating the relationship between elements such as "parallel" and "perpendicular" and terms indicating the shape of elements such as "rectangle", as well as numerical ranges do not only represent strict meanings, but also include substantially equivalent ranges, for example, an error of about a few percent.

[0032] As a technique for efficiently amplifying high-frequency signals, a tracking mode in which a power supply voltage dynamically adjusted over time is supplied to a power amplifier based on a high-frequency signal will be described. The so-called tracking mode is a mode in which the power supply voltage applied to the power amplifier is dynamically adjusted. There are several types of tracking modes. Here, refer toFigures 1A to 1C The average power tracking (APT) mode, the analog ET mode, and the digital ET mode will be described. In Figures 1A to 1C , the horizontal axis represents time and the vertical axis represents voltage. In addition, the thick solid line represents the power supply voltage supplied to the power amplifier, and the thin solid line (waveform) represents the modulation wave.

[0033] Figure 1A is a graph showing an example of the change in the power supply voltage in the APT mode. In the APT mode, based on the average power, the power supply voltage is changed to a plurality of discrete voltage levels in units of one frame. As a result, the power supply voltage signal forms a rectangular wave.

[0034] A frame refers to a unit that constitutes a high-frequency signal (modulation wave). For example, in 5G NR (5th Generation New Radio) and LTE (Long Term Evolution), a frame includes 10 subframes, each subframe includes a plurality of time slots, and each time slot is composed of a plurality of symbols. The subframe length is 1 ms, and the frame length is 10 ms.

[0035] In addition, a mode in which the voltage level is changed in units of one frame or a unit larger than one frame based on the average power is called the APT mode, which is distinguished from a mode in which the voltage level is changed in a unit smaller than one frame (for example, a subframe, a time slot, or a symbol). For example, a mode in which the voltage level is changed in units of symbols is called the symbol power tracking (SPT) mode, which is distinguished from the APT mode.

[0036] Figure 1B is a graph showing an example of the change in the power supply voltage in the analog ET mode. In the analog ET mode, the envelope of the modulation wave is tracked by continuously changing the power supply voltage based on the envelope signal.

[0037] The envelope signal is a signal representing the envelope of the modulation wave. The envelope value is represented by, for example, the square root of (I 2 +Q 2 ). Here, (I, Q) represents a constellation point. A constellation point is a point representing a signal modulated by digital modulation on a constellation diagram. (I, Q) is determined, for example, by a BBIC (baseband Integrated Circuit) based on the transmission information.

[0038] Figure 1CIt is a graph showing an example of the change in the power supply voltage in the digital ET mode. In the digital ET mode, the power supply voltage is changed to a plurality of discrete voltage levels within one frame based on the envelope signal to track the envelope of the modulation wave. As a result, the power supply voltage signal forms a rectangular wave.

[0039] (Embodiment 1)

[0040] Hereinafter, Embodiment 1 will be described.

[0041] [1.1 Circuit Structure of Communication Device 7]

[0042] First, refer to Figure 2 and describe the communication device 7 according to this embodiment. Figure 2 It is a circuit structure diagram of the communication device 7 according to this embodiment.

[0043] In addition, Figure 2 It is an exemplary circuit structure, and the communication device 7 can be installed using any of a variety of circuit installations and circuit technologies. Therefore, the description of the communication device 7 provided below should not be construed in a limited manner.

[0044] The communication device 7 corresponds to a user terminal (UE: User Equipment) in a cellular network. Typically, it is a mobile phone, a smart phone, a tablet computer, a wearable device, etc. In addition, the communication device 7 can also be an IoT (Internet of Things) sensor device, a medical / health device, a vehicle, an unmanned aerial vehicle (UAV: Unmanned Aerial Vehicle) (so-called drone), or an automated guided vehicle (AGV). Additionally, the communication device 7 can also function as a BS (Base Station) in a cellular network.

[0045] As Figure 2 shown, the communication device 7 includes a tracker circuit 1, a high-frequency circuit 4, an RFIC (Radio Frequency Integrated Circuit) 5, an antenna 6, a preconditioner circuit 10, and a DC power supply 50.

[0046] The tracker circuit 1 can supply a plurality of discrete voltages to the power amplifier 2 in the digital ET mode. As Figure 2 shown, the tracker circuit 1 includes a switched capacitor circuit 20, an output switch circuit 30, and a digital control circuit 60.

[0047] The switched-capacitor circuit 20 is a differential switched-capacitor circuit, and is sometimes also referred to as a Differential Switched-Capacitor Voltage Balancer. The switched-capacitor circuit 20 is capable of generating a plurality of discrete voltages including a first output voltage, a second output voltage, and a third output voltage based on the difference between a first input voltage and a second input voltage received from the preconditioner circuit 10. Specifically, the switched-capacitor circuit 20 is capable of generating a third output voltage such that if the difference between the first input voltage and the second input voltage increases, each of the difference between the first output voltage and the third output voltage and the difference between the second output voltage and the third output voltage increases. That is, the step width of the plurality of discrete voltages can be controlled by the difference between the first input voltage and the second input voltage. At this time, the first output voltage is based on the first input voltage and is equal to the first input voltage in the present embodiment. The second output voltage is based on the second input voltage and is equal to the second input voltage in the present embodiment. The third output voltage is based on the difference between the first input voltage and the second input voltage and is lower than the first output voltage (first input voltage) and higher than the second output voltage (second input voltage) in the present embodiment. Use Figure 3 the circuit structure of the switched-capacitor circuit 20 described later.

[0048] The output switch circuit 30 can selectively output at least one of the plurality of discrete voltages generated by the switched-capacitor circuit 20 to the power amplifier 2. That is, the output switch circuit 30 can select at least one voltage from the plurality of discrete voltages and output the selected voltage to the power amplifier 2. Use Figure 3 the circuit structure of the output switch circuit 30 described later.

[0049] The digital control circuit 60 can control the switched-capacitor circuit 20 and the output switch circuit 30 based on a digital control signal from the RFIC 5. Specifically, the digital control circuit 60 can generate and output a control signal for controlling the switches included in the switched-capacitor circuit 20 and a control signal for controlling the switches included in the output switch circuit 30. Use Figure 3 the circuit structure of the digital control circuit 60 described later. In addition, the digital control circuit 60 may not be included in the tracker circuit 1.

[0050] The pre - regulator circuit 10 is an example of a converter circuit, and is sometimes also referred to as a magnetic regulator or a DC (Direct Current) / DC converter. In the present embodiment, the pre - regulator circuit 10 is a buck - boost converter with one input and two outputs, capable of converting the power supply voltage supplied from the DC power supply 50 into two independent and variable voltages (the first input voltage and the second input voltage of the switched - capacitor circuit 20). The pre - regulator circuit 10 can vary the first input voltage and the second input voltage of the switched - capacitor circuit 20, for example, based on a control signal from the RFIC 5. Specifically, the pre - regulator circuit 10 can switch the difference between the first input voltage and the second input voltage according to the modulation method of the high - frequency signal amplified by the power amplifier 2. More specifically, it can be that the higher the bit rate of the modulation method, the greater the difference between the first input voltage and the second input voltage that the pre - regulator circuit 10 makes. Such a switching of the difference between the first input voltage and the second input voltage can also be performed at the switching of the frame of the high - frequency signal. Using Figure 3 the circuit structure of the pre - regulator circuit 10 described later.

[0051] The modulation method of the high - frequency signal can be determined by measuring the constellation points of the high - frequency signal. The higher the bit rate of the modulation method, the greater the number of constellation points that can be separated.

[0052] In addition, the conditions for switching the difference between the first input voltage and the second input voltage are not limited to the modulation method. For example, the difference between the first input voltage and the second input voltage can also be switched according to the power level and the like.

[0053] The DC power supply 50 can supply a power supply voltage to the pre - regulator circuit 10. As the DC power supply 50, for example, a rechargeable battery can be used, but it is not limited thereto.

[0054] The high - frequency circuit 4 can transmit high - frequency signals between the RFIC 5 and the antenna 6. As Figure 2 shown, the high - frequency circuit 4 includes a power amplifier 2 and a filter 3.

[0055] The power amplifier 2 is connected between the RFIC 5 and the filter 3. And the power amplifier 2 is connected to the tracker circuit 1. The power amplifier 2 can use a plurality of discrete voltages received from the tracker circuit 1 to amplify the high - frequency signal received from the RFIC 5.

[0056] The filter 3 is connected between the power amplifier 2 and the antenna 6. The filter 3 is a band - pass filter having a pass - band including a specified frequency band. In addition, the filter 3 may not be included in the high - frequency circuit 4.

[0057] A specified frequency band is a frequency band for a communication system constructed using a radio access technology (RAT), and is predefined by a standardization body or the like (such as 3GPP (registered trademark) (3rd Generation Partnership Project) and IEEE (Institute of Electrical and Electronics Engineers), etc.). As an example of a communication system, a 5G NR system, an LTE system, a WLAN (Wireless Local Area Network) system, etc. can be cited.

[0058] The antenna 6 transmits the high-frequency signal input from the high-frequency circuit 4. In addition, the antenna 6 may not be included in the communication device 7.

[0059] In addition, Figure 2 The circuit structure of the illustrated communication device 7 is an example and is not limited thereto. For example, the communication device 7 may also include a baseband signal processing circuit that performs signal processing using an intermediate frequency band lower than the high-frequency signal.

[0060] [1.2 Circuit Structure of Tracker Circuit 1]

[0061] Next, refer to Figure 3 and describe the circuit structure of the tracker circuit 1. Figure 3 is a circuit structure diagram of the tracker circuit 1 and the pre-tuner circuit 10 according to the present embodiment.

[0062] In addition, Figure 3 is an illustrated circuit structure, and the tracker circuit 1 and the pre-tuner circuit 10 can be installed using any of a variety of circuit installations and circuit technologies. Therefore, the description of each circuit provided below should not be construed in a limiting sense.

[0063] As described above, the tracker circuit 1 includes a switched capacitor circuit 20, an output switch circuit 30, and a digital control circuit 60. In addition, the tracker circuit 1 may also include a filter circuit (not shown) between the output switch circuit 30 and the power amplifier 2.

[0064] Hereinafter, the circuit structures of the switched capacitor circuit 20, the output switch circuit 30, and the digital control circuit 60 will be described in sequence.

[0065] [1.2.1 Circuit Structure of Switched Capacitor Circuit 20]

[0066] First, refer to Figure 3The circuit configuration of the switched capacitor circuit 20 will be described. The switched capacitor circuit 20 includes capacitors C11, C12, C20, and C30, switches S11 to S14 and S21 to S24, input terminals 121 and 122, and output terminals 123 to 125. Energy and charge are input from the preconditioner circuit 10 to nodes N1 and N3 via the input terminals 121 and 122, and are led out from nodes N1 to N3 to the output switch circuit 30 via the output terminals 123 to 125.

[0067] The input terminal 121 is an example of the first input terminal and is a terminal for receiving the first input voltage (V3) from the preconditioner circuit 10. The input terminal 121 is connected to the preconditioner circuit 10 outside the switched capacitor circuit 20 and is connected to the node N3 inside the switched capacitor circuit 20.

[0068] The input terminal 122 is an example of the second input terminal and is a terminal for receiving the second input voltage (V1) from the preconditioner circuit 10. The input terminal 122 is connected to the preconditioner circuit 10 outside the switched capacitor circuit 20 and is connected to the node N1 inside the switched capacitor circuit 20.

[0069] The output terminal 123 is a terminal for supplying the first output voltage (V3) to the output switch circuit 30. The output terminal 123 is connected to the output switch circuit 30 outside the switched capacitor circuit 20 and is connected to the node N3 inside the switched capacitor circuit 20. In addition, the output terminal 123 may be integrated with the input terminal 121.

[0070] The output terminal 124 is a terminal for supplying the third output voltage (V2) to the output switch circuit 30. The output terminal 124 is connected to the output switch circuit 30 outside the switched capacitor circuit 20 and is connected to the node N2 inside the switched capacitor circuit 20.

[0071] The output terminal 125 is a terminal for supplying the second output voltage (V1) to the output switch circuit 30. The output terminal 125 is connected to the output switch circuit 30 outside the switched capacitor circuit 20 and is connected to the node N1 inside the switched capacitor circuit 20. In addition, the output terminal 125 may be integrated with the input terminal 122.

[0072] Capacitors C11 and C12 function as flying capacitors (also sometimes referred to as transfer capacitors), respectively. That is, capacitors C11 and C12 are respectively used to boost and / or step down the first input voltage and the second input voltage supplied from the prescaler circuit 10. More specifically, capacitors C11 and C12 cause charges to move between capacitors C11 and C12 and nodes N1 to N3 so that V1 to V3 that satisfy (V3 - V2)∶(V2 - V1) = 1∶1 and V3 > V2 > V1 are maintained at the three nodes N1 to N3.

[0073] The first output voltage (V3) is based on the first input voltage and is equal to the first input voltage (V3) in this embodiment. In addition, the first output voltage is higher than the second output voltage and the third output voltage.

[0074] The second output voltage (V1) is based on the second input voltage and is equal to the second input voltage (V1) in this embodiment. In addition, the second output voltage is lower than the first output voltage and the third output voltage.

[0075] The third output voltage (V2) is based on the difference between the first input voltage (V3) and the second input voltage (V1) and is lower than the first output voltage and higher than the second output voltage in this embodiment.

[0076] Capacitor C11 has two electrodes. One of the two electrodes of capacitor C11 is connected to one end of switch S11 and one end of switch S12. The other of the two electrodes of capacitor C11 is connected to one end of switch S21 and one end of switch S22.

[0077] Capacitor C12 has two electrodes. One of the two electrodes of capacitor C12 is connected to one end of switch S13 and one end of switch S14. The other of the two electrodes of capacitor C12 is connected to one end of switch S23 and one end of switch S24.

[0078] Capacitors C11 and C12 can be charged and discharged complementarily by repeating the first stage and the second stage.

[0079] Specifically, in the first stage, switches S12, S13, S22, and S23 are turned on. As a result, one of the two electrodes of capacitor C11 is connected to node N3, the other of the two electrodes of capacitor C11 and one of the two electrodes of capacitor C12 are connected to node N2, and the other of the two electrodes of capacitor C12 is connected to node N1.

[0080] On the other hand, in the second stage, switches S11, S14, S21, and S24 are set to ON. As a result, one of the two electrodes of capacitor C12 is connected to node N3, the other of the two electrodes of capacitor C12 and one of the two electrodes of capacitor C11 are connected to node N2, and the other of the two electrodes of capacitor C11 is connected to node N1.

[0081] By repeating such a first stage and second stage, for example, when one of capacitors C11 and C12 is charged from node N1, the other of capacitors C11 and C12 can discharge to capacitor C20. That is, capacitors C11 and C12 can be charged and discharged complementarily.

[0082] Capacitors C20 and C30 function as smoothing capacitors, respectively. That is, capacitors C20 and C30 are used for holding and smoothing the first to third output voltages (V3, V1, V2) at nodes N1 to N3, respectively.

[0083] Capacitor C20 is connected between node N2 and N1. Specifically, one of the two electrodes of capacitor C20 is connected to node N2. On the other hand, the other of the two electrodes of capacitor C20 is connected to node N1.

[0084] Capacitor C30 is connected between node N3 and N2. Specifically, one of the two electrodes of capacitor C30 is connected to node N3. On the other hand, the other of the two electrodes of capacitor C30 is connected to node N2.

[0085] Switch S11 is connected between one of the two electrodes of capacitor C11 and node N2. Specifically, one end of switch S11 is connected to one of the two electrodes of capacitor C11. On the other hand, the other end of switch S11 is connected to node N2.

[0086] Switch S12 is connected between one of the two electrodes of capacitor C11 and node N3. Specifically, one end of switch S12 is connected to one of the two electrodes of capacitor C11. On the other hand, the other end of switch S12 is connected to node N3.

[0087] Switch S21 is connected between the other of the two electrodes of capacitor C11 and node N1. Specifically, one end of switch S21 is connected to the other of the two electrodes of capacitor C11. On the other hand, the other end of switch S21 is connected to node N1.

[0088] Switch S22 is connected between the other of the two electrodes of capacitor C11 and node N2. Specifically, one end of switch S22 is connected to the other of the two electrodes of capacitor C11. On the other hand, the other end of switch S22 is connected to node N2.

[0089] The switch S13 is connected between one of the two electrodes of the capacitor C12 and the node N2. Specifically, one end of the switch S13 is connected to one of the two electrodes of the capacitor C12. On the other hand, the other end of the switch S13 is connected to the node N2. That is to say, the other end of the switch S13 is connected to the other end of the switch S11 and the other end of the switch S22.

[0090] The switch S14 is connected between one of the two electrodes of the capacitor C12 and the node N3. Specifically, one end of the switch S14 is connected to one of the two electrodes of the capacitor C12. On the other hand, the other end of the switch S14 is connected to the node N3. That is to say, the other end of the switch S14 is connected to the other end of the switch S12.

[0091] The switch S23 is connected between the other of the two electrodes of the capacitor C12 and the node N1. Specifically, one end of the switch S23 is connected to the other of the two electrodes of the capacitor C12. On the other hand, the other end of the switch S23 is connected to the node N1. That is to say, the other end of the switch S23 is connected to the other end of the switch S21.

[0092] The switch S24 is connected between the other of the two electrodes of the capacitor C12 and the node N2. Specifically, one end of the switch S24 is connected to the other of the two electrodes of the capacitor C12. On the other hand, the other end of the switch S24 is connected to the node N2. That is to say, the other end of the switch S24 is connected to the other end of the switch S11, the other end of the switch S22, and the other end of the switch S13.

[0093] The switches of the first group including the switches S12, S13, S22, and S23 and the switches of the second group including the switches S11, S14, S21, and S24 are switched on and off complementarily based on the control signal from the digital control circuit 60. Specifically, in the first stage, the switches of the first group are set to be on, and the switches of the second group are set to be off. On the contrary, in the second stage, the switches of the first group are set to be off, and the switches of the second group are set to be on.

[0094] For example, in one of the first stage and the second stage, charging from the capacitor C11 to the capacitors C20 and C30 is performed, and in the other of the first stage and the second stage, charging from the capacitor C12 to the capacitors C20 and C30 is performed. That is to say, charging is always performed from the capacitor C11 or C12 to the capacitors C20 and C30. Therefore, even if a current flows at high speed from the nodes N1 to N3 to the output switch circuit 30, charges can be replenished to the nodes N1 to N3 at high speed, and potential fluctuations of the nodes N1 to N3 can be suppressed.

[0095] By operating in this way, the switched capacitor circuit 20 can maintain substantially equal voltages across the respective capacitors C20 and C30. Specifically, among the four nodes labeled V1 to V3, V1 to V3 (voltages relative to the ground potential) that satisfy (V3−V2):(V2−V1)=1:1 are maintained. V1 to V3 correspond to a plurality of discrete voltages that can be supplied from the switched capacitor circuit 20 to the output switch circuit 30.

[0096] In addition, (V3−V2):(V2−V1) is not limited to 1:1 and can be designed as an arbitrary ratio (e.g., 2:1, 3:1, 3:2, 1:2, 2:3, etc.).

[0097] In addition, Figure 3 The structure of the shown switched capacitor circuit 20 is an example and is not limited thereto. For example, the switched capacitor circuit 20 is configured to supply voltages of three discrete voltage levels, but it may also be configured to supply voltages of any number of discrete voltage levels of four or more.

[0098] [1.2.2 Circuit Structure of Output Switch Circuit 30]

[0099] Next, with reference to Figure 3 the circuit structure of the output switch circuit 30 will be described. The output switch circuit 30 includes input terminals 131 to 133, switches S51 to S53, and an output terminal 134.

[0100] The input terminals 131 to 133 are terminals for receiving the first to third output voltages of the switched capacitor circuit 20. The input terminals 131 to 133 are respectively connected to the output terminals 123 to 125 of the switched capacitor circuit 20 outside the output switch circuit 30 and are respectively connected to the switches S51 to S53 inside the output switch circuit 30.

[0101] The output terminal 134 is a terminal for selectively supplying at least one of a plurality of discrete voltages to the power amplifier 2. The output terminal 134 is connected to the power amplifier 2 outside the output switch circuit 30 and is connected to the switches S51 to S53 inside the output switch circuit 30.

[0102] The switch S51 is connected between the input terminal 131 and the output terminal 134. Specifically, the switch S51 includes a terminal connected to the input terminal 131 and a terminal connected to the output terminal 134. In this connection structure, the switch S51 is switched between on and off by a control signal from the digital control circuit 60, thereby enabling the connection and non-connection between the input terminal 131 and the output terminal 134 to be switched.

[0103] The switch S52 is connected between the input terminal 132 and the output terminal 134. Specifically, the switch S52 includes a terminal connected to the input terminal 132 and a terminal connected to the output terminal 134. In this connection structure, the switch S52 is switched on / off by a control signal from the digital control circuit 60, thereby enabling the switching between the connection and non-connection between the input terminal 132 and the output terminal 134.

[0104] The switch S53 is connected between the input terminal 133 and the output terminal 134. Specifically, the switch S53 includes a terminal connected to the input terminal 133 and a terminal connected to the output terminal 134. In this connection structure, the switch S53 is switched on / off by a control signal from the digital control circuit 60, thereby enabling the switching between the connection and non-connection between the input terminal 133 and the output terminal 134.

[0105] In the present embodiment, these switches S51 to S53 are controlled to be exclusively turned on. That is, only one of the switches S51 to S53 is set to be on, and the remaining switches S51 to S53 are set to be off. Thereby, the output switch circuit 30 can output one voltage selected from the first to third output voltages of the switched capacitor circuit 20 to the power amplifier 2.

[0106] In addition, Figure 3 The structure of the output switch circuit 30 shown is an example and is not limited thereto. In particular, as long as the switches S51 to S53 can selectively connect at least one of the three input terminals 131 to 133 to the output terminal 134, they can have any structure and can be controlled arbitrarily. For example, two of the switches S51 to S53 can be set to be on, and the remaining one of the switches S51 to S53 can be set to be off.

[0107] In addition, when four or more discrete voltages are supplied from the switched capacitor circuit 20, the output switch circuit 30 can further include one or more switches in addition to the switches S51 to S53.

[0108] [1.2.3 Circuit Structure of the Digital Control Circuit 60]

[0109] Next, with reference to Figure 3 the circuit structure of the digital control circuit 60 will be described. The digital control circuit 60 includes a first controller 61, a second controller 62, and control terminals 161 to 164.

[0110] The first controller 61 processes the source-synchronous digital control signals received from the RFIC 5 via the control terminals 161 and 162, and can generate control signals for controlling the switched capacitor circuit 20. The on / off states of the switches S11 to S14 and S21 to S24 included in the switched capacitor circuit 20 are controlled by the control signals from the first controller 61.

[0111] In addition, the digital control signals processed by the first controller 61 are not limited to the source-synchronous digital control signals. For example, the first controller 61 can also process clock-embedded digital control signals. Additionally, the first controller 61 can also generate control signals for controlling the output switch circuit 30.

[0112] Furthermore, in this embodiment, a set of clock signals and data signals are used, but it is not limited thereto. For example, as the digital control signals, multiple sets of clock signals and data signals can also be used.

[0113] The second controller 62 processes the digital control logic (DCL: Digital Control Logic / Line) signals (DCL1, DCL2) received from the RFIC 5 via the control terminals 163 and 164, and generates control signals for controlling the output switch circuit 30. The DCL signals (DCL1, DCL2) are generated by the RFIC 5 based on the envelope signal of the high-frequency signal. The on / off states of the switches S51 to S53 included in the output switch circuit 30 are controlled by the control signals from the second controller 62.

[0114] The DCL signals (DCL1, DCL2) are each 1-bit signals. The voltages V1 to V3 are each represented by a combination of two 1-bit signals. For example, V1, V2, and V3 are represented by "00", "01", and "10", respectively. The representation of the voltage levels can also use the Gray code.

[0115] In addition, in this embodiment, two digital control logic signals are used for the control of the output switch circuit 30, but the number of digital control logic signals is not limited thereto. For example, depending on the number of selectable voltage levels of each of the output switch circuits 30, any number of digital control logic signals, such as one or three or more, can be used. Additionally, the digital control signals for the control of the output switch circuit 30 are not limited to digital control logic signals.

[0116] [1.3 Circuit Structure of the Predistorter Circuit 10]

[0117] Next, refer to Figure 3The circuit structure of the pre-tuner circuit 10 will be described. The pre-tuner circuit 10 includes an input terminal 110, output terminals 111 and 112, switches S71 to S75, a power inductor L71, and capacitors C71 and C72.

[0118] The input terminal 110 is a terminal for receiving a power supply voltage from the DC power supply 50. The input terminal 110 is connected to the DC power supply 50 outside the pre-tuner circuit 10 and is connected to the switch S71 inside the pre-tuner circuit 10.

[0119] The output terminal 111 is an example of a first output terminal and is a terminal for supplying a first input voltage (V3) to the switched capacitor circuit 20. The output terminal 111 is connected to the input terminal 121 of the switched capacitor circuit 20 outside the pre-tuner circuit 10 and is connected to the switch S73 inside the pre-tuner circuit 10.

[0120] The output terminal 112 is an example of a second output terminal and is a terminal for supplying a second input voltage (V1) to the switched capacitor circuit 20. The output terminal 112 is connected to the input terminal 122 of the switched capacitor circuit 20 outside the pre-tuner circuit 10 and is connected to the switch S74 inside the pre-tuner circuit 10.

[0121] The power inductor L71 is an inductor for boosting and bucking a DC voltage. One end of the power inductor L71 is connected to the switches S71 and S72, and the other end of the power inductor L71 is connected to the switches S73 to S75.

[0122] The switch S71 is connected between the input terminal 110 and one end of the power inductor L71. Specifically, the switch S71 includes a terminal connected to the input terminal 110 and a terminal connected to one end of the power inductor L71. In this connection structure, the switch S71 can switch the connection and non-connection between the input terminal 110 and one end of the power inductor L71 by switching on and off.

[0123] The switch S72 is connected between one end of the power inductor L71 and the ground. Specifically, the switch S72 includes a terminal connected to one end of the power inductor L71 and a terminal connected to the ground. In this connection structure, the switch S72 can switch the connection and non-connection between one end of the power inductor L71 and the ground by switching on and off.

[0124] Switch S73 is an example of the first switch and is connected between the other end of the power inductor L71 and the output terminal 111. Specifically, switch S73 includes a terminal connected to the other end of the power inductor L71 and a terminal connected to the output terminal 111. In this connection structure, switch S73 can switch the connection and non-connection between the other end of the power inductor L71 and the output terminal 111 by switching on and off.

[0125] Switch S74 is an example of the second switch and is connected between the other end of the power inductor L71 and the output terminal 112. Specifically, switch S74 includes a terminal connected to the other end of the power inductor L71 and a terminal connected to the output terminal 112. In this connection structure, switch S74 can switch the connection and non-connection between the other end of the power inductor L71 and the output terminal 112 by switching on and off.

[0126] The withstand voltage of switches S73 and S74 is lower than that of switches S11 - S14 and S21 - S24 included in the switched capacitor circuit 20. Conversely, the withstand voltage of switches S11 - S14 and S21 - S24 included in the switched capacitor circuit 20 is higher than that of switches S73 and S74 included in the pre-regulator circuit 10.

[0127] In addition, the withstand voltages of the two switches can be compared by the number of transistors connected in series. Specifically, the withstand voltage of a switch with a larger number of transistors connected in series is higher than that of a switch with a smaller number of transistors connected in series.

[0128] Switch S75 is an example of the third switch and is connected between the other end of the power inductor L71 and the ground. Specifically, switch S75 includes a terminal connected to the other end of the power inductor L71 and a terminal connected to the ground. In this connection structure, switch S75 can switch the connection and non-connection between the other end of the power inductor L71 and the ground by switching on and off.

[0129] Capacitor C71 is an example of the first capacitor and is connected between the path between switch S73 and output terminal 111 and the ground. Specifically, one of the two electrodes of capacitor C71 is connected to switch S73 and output terminal 111, and the other of the two electrodes of capacitor C71 is connected to the ground.

[0130] Capacitor C72 is an example of the second capacitor and is connected between the path between switch S74 and output terminal 112 and the ground. Specifically, one of the two electrodes of capacitor C72 is connected to switch S74 and output terminal 112, and the other of the two electrodes of capacitor C72 is connected to the ground.

[0131] The thus configured pre - conditioner circuit 10 can convert the power supply voltage into two independent variable voltages (the first input voltage and the second input voltage of the switched - capacitor circuit 20).

[0132] In addition, Figure 3 The structure of the pre - conditioner circuit 10 shown is an example and is not limited thereto. For example, a part of the switches S71 - S75 can also be replaced by diodes. In addition, a part or all of the pre - conditioner circuit 10 can also be included in the tracker circuit 1.

[0133] [1.4 Tracking Method]

[0134] Next, with reference to Figure 4 、 Figures 5A to 5C and Figures 6A to 6C the method of supplying a plurality of discrete voltages to the tracker circuit 1 configured as above, that is, the tracking method, will be described. Figure 4 is a flowchart showing the tracking method according to the present embodiment. Figure 5A is a graph showing the high - frequency signal RF1 after QPSK modulation and a plurality of discrete voltages. Figure 5B is a graph showing the relationship between the output power and the generation frequency of the power amplifier that amplifies the high - frequency signal RF1 after QPSK modulation. Figure 5C is a graph showing the relationship between the output power and the power efficiency of the power amplifier 2 that amplifies the high - frequency signal RF1 after QPSK modulation. Figure 6A is a graph showing the high - frequency signal RF2 after 256QAM modulation and a plurality of discrete voltages. Figure 6B is a graph showing the relationship between the output power and the generation frequency of the power amplifier 2 that amplifies the high - frequency signal RF2 after 256QAM modulation. Figure 6C is a graph showing the relationship between the output power and the power efficiency of the power amplifier 2 that amplifies the high - frequency signal RF2 after 256QAM modulation.

[0135] <Step S10>

[0136] The switched capacitor circuit 20 receives a first input voltage and a second input voltage from the pre - conditioner circuit 10. For example, in the case where a high - frequency signal RF1 modulated by DFTs - OFDM QPSK (Discrete Fourier Transform spreading - Orthogonal Frequency Division Multiplexing Quadrature Phase Shift Keying, hereinafter simply referred to as QPSK) is amplified by the power amplifier 2, the switched capacitor circuit 20 receives the first input voltage (Vmax1) and the second input voltage (Vmin1) from the pre - conditioner circuit 10. In addition, QPSK is an example of a modulation method with a lower bit rate.

[0137] <Step S20>

[0138] The switched capacitor circuit 20 generates a plurality of first discrete voltages based on a first difference between the first input voltage and the second input voltage. Specifically, the switched capacitor circuit 20 generates a first output voltage based on the first input voltage, a second output voltage based on the second input voltage, and a third output voltage based on the difference between the first input voltage and the second input voltage. For example, in the case where a high - frequency signal RF1 modulated by QPSK is amplified by the power amplifier 2, the switched capacitor circuit 20 generates, as a plurality of first discrete voltages, a first output voltage (Vmax1) equal to the first input voltage, a second output voltage (Vmin1) equal to the second input voltage, and a third output voltage (Vmid1 = Vmax1 - Vd1 = Vmin1 + Vd1) that is lower than the first input voltage by half of the first difference (Vd1) and higher than the second input voltage by half of the first difference (Vd1) based on the first difference (2Vd1) between the first input voltage (Vmax1) and the second input voltage (Vmin1).

[0139] <Step S30>

[0140] The output switch circuit 30 selectively outputs at least one of the plurality of first discrete voltages to the power amplifier 2. For example, in the case where a high - frequency signal RF1 modulated by QPSK is amplified by the power amplifier 2, the output switch circuit 30 selectively outputs the first output voltage (Vmax1), the second output voltage (Vmin1), and the third output voltage (Vmid1) to the power amplifier 2 based on the envelope signal. Thus, as Figure 5A shown, a voltage based on the envelope of the high - frequency signal RF1 is supplied to the power amplifier 2.

[0141] Through such steps S10 - S30, as Figure 5B and Figure 5CAs shown, it is capable of outputting a first output voltage (Vmax1) corresponding to the maximum output power of the high-frequency signal RF1, and outputting a second output voltage (Vmin1) corresponding to the output power Pout1 with the highest occurrence frequency of the high-frequency signal RF1. Thereby, it can support the maximum output power of the high-frequency signal RF1 and improve the power efficiency with respect to the output power with the highest occurrence frequency of the high-frequency signal RF1. Furthermore, it can also output a third output voltage (Vmid1) intermediate between the first output voltage (Vmax1) and the second output voltage (Vmin1), so it can also improve the power efficiency with respect to the output power between the maximum output power and the average output voltage.

[0142] <Step S40>

[0143] The switched capacitor circuit 20 receives a third input voltage and a fourth input voltage from the preconditioner circuit 10. Here, the second difference between the third input voltage and the fourth input voltage is different from the first difference between the first input voltage and the second input voltage. For example, in the case where the high-frequency signal RF2 modulated by CP-OFDM 256QAM (Cyclic Prefix-Orthogonal Frequency Division Multiplexing 256 Quadrature Amplitude Modulation) (hereinafter, simply referred to as 256QAM) is amplified by the power amplifier 2, the switched capacitor circuit 20 receives a third input voltage (Vmax2) and a fourth input voltage (Vmin2) from the preconditioner circuit 10. At this time, since the bit rate of 256QAM is higher than that of QPSK, the second difference (2Vd2) is larger than the first difference (2Vd1).

[0144] In addition, 256QAM is an example of a modulation method with a higher bit rate. Generally speaking, QAM (e.g., 256QAM, 64QAM, 16QAM, etc.) has a higher bit rate and a larger PAPR (Peak to Average Power Ratio) compared with PSK (e.g., QPSK, BPSK (Binary Phase-Shift Keying)).

[0145] <Step S50>

[0146] The switched capacitor circuit 20 generates a plurality of second discrete voltages based on a second difference between a third input voltage and a fourth input voltage. The second difference between the third input voltage and the fourth input voltage is different from the first difference between the first input voltage and the second input voltage, so the plurality of second discrete voltages are different from the plurality of first discrete voltages. For example, in the case where the high-frequency signal RF2 after 256QAM modulation is amplified by the power amplifier 2, the switched capacitor circuit 20 generates a fourth output voltage (Vmax2) equal to the third input voltage, a fifth output voltage (Vmin2) equal to the fourth input voltage, and a sixth output voltage (Vmid2 = Vmax2 - Vd2 = Vmin2 + Vd2) that is lower than the third input voltage by half of the second difference (Vd2) and higher than the fourth input voltage by half of the second difference (Vd2) based on the second difference (2Vd2) between the third input voltage (Vmax2) and the fourth input voltage (Vmin2) as the plurality of second discrete voltages.

[0147] <Step S60>

[0148] The output switching circuit 30 selectively outputs at least one of the plurality of second discrete voltages to the power amplifier 2. For example, in the case where the high-frequency signal RF2 after 256QAM modulation is amplified by the power amplifier 2, the output switching circuit 30 selectively outputs the fourth output voltage (Vmax2), the fifth output voltage (Vmin2), and the sixth output voltage (Vmid2) to the power amplifier 2 based on the envelope signal. Thus, as Figure 6A shown, the voltage based on the envelope of the high-frequency signal RF2 is supplied to the power amplifier 2.

[0149] Through such steps S40 to S60, as Figure 6B and Figure 6C shown, it is possible to output the fourth output voltage (Vmax2) corresponding to the maximum output power of the high-frequency signal RF2, and output the fifth output voltage (Vmin2) corresponding to the output power Pout2 with the highest occurrence frequency of the high-frequency signal RF2. Thus, it is possible to support the maximum output power of the high-frequency signal RF2 and improve the power efficiency with respect to the output power with the highest occurrence frequency of the high-frequency signal RF2. Furthermore, since it is possible to output the sixth output voltage (Vmid2) intermediate between the fourth output voltage (Vmax2) and the fifth output voltage (Vmin2), it is also possible to improve the power efficiency with respect to the output power between the maximum output power and the average output voltage.

[0150] As described above, for high-frequency signals with different characteristics (in particular, PAPR) due to different modulation methods, the input voltage is changed, so that output voltages corresponding to the output power with the highest occurrence frequency (the second output voltage and the fifth output voltage) and the output voltage corresponding to the maximum output power (the first output voltage and the fourth output voltage) can be generated. As a result, even if the number of multiple discrete voltages generated by the switched-capacitor circuit 20 is reduced, a decrease in the power efficiency of the power amplifier 2 can be suppressed, and the structure of the switched-capacitor circuit 20 can be simplified.

[0151] [1.5 Effects, etc.]

[0152] As described above, the tracker circuit 1 according to the present embodiment includes: a switched-capacitor circuit 20 configured to generate multiple discrete voltages; and an output switch circuit 30 configured to selectively output at least one of the multiple discrete voltages to the power amplifier 2. The switched-capacitor circuit 20 is configured to generate multiple discrete voltages based on the difference between the first input voltage and a variable second input voltage lower than the first input voltage.

[0153] Accordingly, multiple discrete voltages are generated in the switched-capacitor circuit based on the difference between the first input voltage and the second input voltage. Therefore, compared with the case of generating multiple discrete voltages based on one input voltage, the multiple discrete voltages can be set more flexibly, and the power efficiency of the power amplifier 2 can be improved. Also, even if the number of multiple discrete voltages (i.e., the number of levels) generated by the switched-capacitor circuit 20 is reduced, a decrease in the power efficiency of the power amplifier 2 can be suppressed by changing the second input voltage. Therefore, the structure of the switched-capacitor circuit 20 can be simplified, and the power efficiency of the tracker circuit 1 can also be improved.

[0154] In addition, for example, in the tracker circuit 1 according to the present embodiment, the first input voltage may also be variable.

[0155] Accordingly, both the first input voltage and the second input voltage are variable, so that the multiple discrete voltages can be set more flexibly. Therefore, the power efficiency of the power amplifier 2 can be further improved, and the structure of the switched-capacitor circuit 20 can be simplified more.

[0156] In addition, for example, in the tracker circuit 1 according to the present embodiment, the multiple discrete voltages may also include a first output voltage based on the first input voltage, a second output voltage based on the second input voltage, and a third output voltage based on the difference between the first input voltage and the second input voltage.

[0157] Accordingly, as long as only the third output voltage among the first output voltage, the second output voltage, and the third output voltage is generated based on the difference between the first input voltage and the second input voltage, the power consumption for generating the first output voltage and the second output voltage can be suppressed, and multiple discrete voltages can be generated more stably.

[0158] In addition, for example, in the tracker circuit 1 according to the present embodiment, the third output voltage may also be lower than the first output voltage.

[0159] Accordingly, the power efficiency of the switched capacitor circuit 20 can be improved, and multiple discrete voltages can be generated more stably.

[0160] In addition, for example, in the tracker circuit 1 according to the present embodiment, the switched capacitor circuit 20 may also generate the third output voltage such that if the difference between the first input voltage and the second input voltage increases, the difference between the first output voltage and the third output voltage and the difference between the second output voltage and the third output voltage increase respectively.

[0161] Accordingly, the step width among multiple discrete voltages can be controlled by the difference between the first input voltage and the second input voltage. Therefore, multiple discrete voltages suitable for the characteristics of high-frequency signals (such as PAPR, etc.) can be generated, and the power efficiency can be improved.

[0162] In addition, for example, in the tracker circuit 1 according to the present embodiment, the difference between the first input voltage and the second input voltage may also be switched according to the modulation method of the high-frequency signal amplified by the power amplifier 2.

[0163] Accordingly, when the characteristics of the high-frequency signal (such as PAPR, etc.) change due to the modulation method, the step width of multiple discrete voltages can be changed, and the power efficiency can be improved.

[0164] In addition, for example, in the tracker circuit 1 according to the present embodiment, it may also be that the higher the bit rate of the modulation method of the high-frequency signal, the greater the difference between the first input voltage and the second input voltage.

[0165] Accordingly, the higher the bit rate of the modulation method, the more the step width of multiple discrete voltages can be expanded, the PAPR increasing with the increase in the bit rate can be dealt with, and the power efficiency can be improved.

[0166] In addition, for example, in the tracker circuit 1 according to the present embodiment, the difference between the first input voltage and the second input voltage may also be switched when switching the frames of the high-frequency signal amplified by the power amplifier 2.

[0167] Accordingly, the deterioration of the high-frequency signal caused by the instability of multiple discrete voltages during the switching of the difference between the first input voltage and the second input voltage can be suppressed.

[0168] In addition, for example, the tracker circuit 1 according to this embodiment may also be connected to a preconditioner circuit 10 configured to convert a power supply voltage into a first input voltage and a second input voltage.

[0169] Accordingly, the tracker circuit 1 is connected to the one-input two-output preconditioner circuit 10, so that the number of preconditioner circuits 10 can be reduced.

[0170] In addition, the communication device 7 according to this embodiment includes: a tracker circuit 1; a preconditioner circuit 10 configured to convert a power supply voltage into a first input voltage and a second input voltage; an RFIC 5 configured to process high-frequency signals; and a high-frequency circuit 4 configured to include a power amplifier 2 and transmit high-frequency signals between the RFIC 5 and an antenna 6.

[0171] Accordingly, the same effect as that of the tracker circuit 1 can be achieved. As a result, the power consumption of the communication device 7 can be suppressed, and the battery durability of the communication device 7 can be improved.

[0172] In addition, in the tracking method according to this embodiment, a first input voltage and a second input voltage lower than the first input voltage are received (S10), a plurality of first discrete voltages are generated based on a first difference between the first input voltage and the second input voltage (S20), at least one of the plurality of first discrete voltages is selectively output to the power amplifier 2 (S30), a third input voltage and a fourth input voltage lower than the third input voltage are received (S40), the fourth input voltage is different from the second input voltage, a plurality of second discrete voltages are generated based on a second difference between the third input voltage and the fourth input voltage (S50), and at least one of the plurality of second discrete voltages is selectively output to the power amplifier 2 (S60).

[0173] Accordingly, a plurality of first discrete voltages are generated based on the first difference between the first input voltage and the second input voltage, and a plurality of second discrete voltages are generated based on the second difference between the third input voltage and the fourth input voltage. Therefore, compared with the case of generating a plurality of discrete voltages based on one input voltage, a plurality of discrete voltages can be set more flexibly by changing two input voltages, and the power efficiency of the power amplifier 2 can be improved. And even if the number of the plurality of discrete voltages is reduced, a decrease in the power efficiency of the power amplifier 2 can be suppressed by changing the second input voltage. Therefore, the structure of the tracker circuit 1 can be simplified, and the power efficiency of the tracker circuit 1 can also be improved.

[0174] (Modification Example of Embodiment 1)

[0175] Next, a modification of Embodiment 1 will be described. As described in Embodiment 1 above, the tracker circuit 1 may also include a part or all of the pre-tuner circuit 10. Therefore, as Figure 7 shown, the tracker circuit 1 according to this modification includes all of the pre-tuner circuit 10. In addition, the tracker circuit 1 may also include only a part of the pre-tuner circuit 10. For example, it may include only the capacitors C71 and C72.

[0176] As described above, the tracker circuit 1 according to this modification includes: a switched-capacitor circuit 20 including an input terminal 121 for receiving a first input voltage and an input terminal 122 for receiving a variable second input voltage lower than the first input voltage, configured to generate a plurality of discrete voltages; an output switching circuit 30 configured to selectively output at least one of the plurality of discrete voltages to the power amplifier 2; a capacitor C71 connected between the input terminal 121 and the ground; and a capacitor C72 connected between the input terminal 122 and the ground.

[0177] Accordingly, the first input voltage and the second input voltage are received via the input terminals 121 and 122 shunt-connected to the two different capacitors C71 and C72, respectively. Therefore, the switched-capacitor circuit 20 can receive the first input voltage and the second input voltage independently of each other. Therefore, compared with the case of generating a plurality of discrete voltages based on one input voltage, the plurality of discrete voltages can be set more flexibly, and the power efficiency of the power amplifier 2 can be improved. And even if the number of the plurality of discrete voltages (i.e., the number of levels) generated by the switched-capacitor circuit 20 is reduced, a decrease in the power efficiency of the power amplifier 2 can be suppressed. Therefore, the structure of the switched-capacitor circuit 20 can be simplified, and the power efficiency of the tracker circuit 1 can also be improved.

[0178] In addition, for example, the tracker circuit 1 according to this modification may further include a pre-tuner circuit 10. The pre-tuner circuit 10 may include: a power inductor L71, an output terminal 111 connected to the input terminal 121 of the switched-capacitor circuit 20, an output terminal 112 connected to the input terminal 122 of the switched-capacitor circuit 20, a switch S73 connected between the output terminal of the power inductor L71 and the output terminal 111, a switch S74 connected between the output terminal of the power inductor L71 and the output terminal 112, a switch S75 connected between the output terminal of the power inductor L71 and the ground, the capacitors C71 and C72. The capacitor C71 may be connected between the path between the switch S73 and the output terminal 111 and the ground, and the capacitor C72 may be connected between the path between the switch S74 and the output terminal 112 and the ground.

[0179] Accordingly, a preconditioner circuit 10 with one input and two outputs is included in the tracker circuit 1. Therefore, there is no need to separately prepare the preconditioner circuit 10, and the tracker circuit 1 can be easily incorporated into the communication device 7.

[0180] In addition, for example, in the tracker circuit 1 according to this modification, the breakdown voltage of the switches included in the switched capacitor circuit 20 can also be higher than the breakdown voltages of the switches S73 and S74 included in the preconditioner circuit 10.

[0181] Accordingly, the breakdown voltage of the switches included in the switched capacitor circuit 20 can be made relatively high, the breakdown of the switched capacitor circuit 20 can be suppressed when the difference between the first input voltage and the second input voltage is large, and multiple discrete voltages can be set more flexibly.

[0182] (Embodiment 2)

[0183] Next, Embodiment 2 will be described. In this embodiment, the main difference from the above Embodiment 1 is that the switched capacitor circuit receives two input voltages from two preconditioner circuits respectively. Hereinafter, this embodiment will be described mainly focusing on the differences from the above Embodiment 1 with reference to the drawings.

[0184] [2.1 Circuit Structure of Communication Device 7A]

[0185] Refer to Figure 8 and the communication device 7A according to this embodiment will be described. Figure 8 is the circuit structure diagram of the communication device 7A according to this embodiment.

[0186] In addition, Figure 8 is an exemplary circuit structure, and the communication device 7A can be installed using any one of a variety of circuit arrangements and circuit technologies. Therefore, the description of the communication device 7A provided below should not be construed in a limiting sense.

[0187] The communication device 7A according to this embodiment includes a tracker circuit 1, a high-frequency circuit 4, an RFIC 5, an antenna 6, preconditioner circuits 10A and 10B, and a DC power supply 50.

[0188] The preconditioner circuit 10A is an example of a first converter circuit and is a step-down / step-up converter with one input and one output. The preconditioner circuit 10A can convert the power supply voltage supplied from the DC power supply 50 into a variable voltage (the first input voltage of the switched capacitor circuit 20). The preconditioner circuit 10A can change the first input voltage based on, for example, a control signal from the RFIC 5. Use Figure 9 the circuit structure of the preconditioner circuit 10A described later.

[0189] The pre - regulator circuit 10B is an example of the second converter circuit and is a step - down / step - up converter with one input and one output. The pre - regulator circuit 10B can convert the power supply voltage supplied from the DC power supply 50 into a variable voltage (the second input voltage of the switched - capacitor circuit 20). The pre - regulator circuit 10B can, for example, vary the second input voltage based on a control signal from the RFIC 5. Using Figure 9 the circuit structure of the pre - regulator circuit 10B described later.

[0190] The pre - regulator circuits 10A and 10B can, for example, switch the difference between the first input voltage and the second input voltage according to the modulation method of the high - frequency signal amplified by the power amplifier 2. More specifically, the pre - regulator circuits 10A and 10B may increase the difference between the first input voltage and the second input voltage as the bit rate of the modulation method increases. Such a switching of the difference between the first input voltage and the second input voltage can also be performed at the time of switching of the frame of the high - frequency signal.

[0191] [2.2 Circuit Structure of the Pre - regulator Circuit 10A]

[0192] Refer to Figure 9 and explain the circuit structure of the pre - regulator circuit 10A. Figure 9 is the circuit structure diagram of the tracker circuit 1 and the pre - regulator circuits 10A and 10B according to this embodiment.

[0193] In addition, Figure 9 is an exemplary circuit structure, and the tracker circuit 1 and the pre - regulator circuits 10A and 10B can be implemented using any of a variety of circuit arrangements and circuit technologies. Therefore, the descriptions of the circuits provided below should not be construed in a limiting sense.

[0194] The pre - regulator circuit 10A includes an input terminal 110A, an output terminal 111A, switches S71A - S73A and S75A, a power inductor L71A, and a capacitor C71A.

[0195] The input terminal 110A is a terminal for receiving the power supply voltage from the DC power supply 50. The input terminal 110A is connected to the DC power supply 50 outside the pre - regulator circuit 10A and is connected to the switch S71A inside the pre - regulator circuit 10A.

[0196] The output terminal 111A is a terminal for supplying the first input voltage (V3) to the switched - capacitor circuit 20. The output terminal 111A is connected to the input terminal 121 of the switched - capacitor circuit 20 outside the pre - regulator circuit 10A and is connected to the switch S73A inside the pre - regulator circuit 10A.

[0197] The power inductor L71A is an inductor used for boosting and bucking DC voltages. One end of the power inductor L71A is connected to switches S71A and S72A, and the other end of the power inductor L71A is connected to switches S73A and S75A.

[0198] The switch S71A is connected between the input terminal 110A and one end of the power inductor L71A. Specifically, the switch S71A includes a terminal connected to the input terminal 110A and a terminal connected to one end of the power inductor L71A. In this connection structure, by switching on / off, the switch S71A can switch the connection and non-connection between the input terminal 110A and one end of the power inductor L71A.

[0199] The switch S72A is connected between one end of the power inductor L71A and the ground. Specifically, the switch S72A includes a terminal connected to one end of the power inductor L71A and a terminal connected to the ground. In this connection structure, by switching on / off, the switch S72A can switch the connection and non-connection between one end of the power inductor L71A and the ground.

[0200] The switch S73A is connected between the other end of the power inductor L71A and the output terminal 111A. Specifically, the switch S73A includes a terminal connected to the other end of the power inductor L71A and a terminal connected to the output terminal 111A. In this connection structure, by switching on / off, the switch S73A can switch the connection and non-connection between the other end of the power inductor L71A and the output terminal 111A.

[0201] The switch S75A is connected between the other end of the power inductor L71A and the ground. Specifically, the switch S75A includes a terminal connected to the other end of the power inductor L71A and a terminal connected to the ground. In this connection structure, by switching on / off, the switch S75A can switch the connection and non-connection between the other end of the power inductor L71A and the ground.

[0202] The capacitor C71A is connected between the path between the switch S73A and the output terminal 111A and the ground. Specifically, one of the two electrodes of the capacitor C71A is connected to the switch S73A and the output terminal 111A, and the other of the two electrodes of the capacitor C71A is connected to the ground.

[0203] The thus-constituted pre-regulator circuit 10A can convert the power supply voltage into a variable voltage V3 (the first input voltage of the switched capacitor circuit 20).

[0204] In addition, Figure 9The structure of the tuner circuit 10A shown is an example and is not limited thereto. For example, a part of switches S71A to S73A and S75A may also be replaced with diodes. In addition, a part or all of the tuner circuit 10A may also be included in the tracker circuit 1 in the same manner as the tuner circuit 10 according to the modification example of Embodiment 1.

[0205] [2.3 Circuit Structure of Tuner Circuit 10B]

[0206] Refer to Figure 9 and the circuit structure of the tuner circuit 10B will be described. The tuner circuit 10B includes an input terminal 110B, an output terminal 112B, switches S71B, S72B, S74B, and S75B, a power inductor L71B, and a capacitor C72B.

[0207] The input terminal 110B is a terminal for receiving a power supply voltage from the DC power supply 50. The input terminal 110B is connected to the DC power supply 50 outside the tuner circuit 10B and is connected to the switch S71B inside the tuner circuit 10B.

[0208] The output terminal 112B is a terminal for supplying a second input voltage (V1) to the switched capacitor circuit 20. The output terminal 112B is connected to the input terminal 122 of the switched capacitor circuit 20 outside the tuner circuit 10B and is connected to the switch S74B inside the tuner circuit 10B.

[0209] The power inductor L71B is an inductor for boosting and bucking a DC voltage. One end of the power inductor L71B is connected to the switches S71B and S72B, and the other end of the power inductor L71B is connected to the switches S74B and S75B.

[0210] The switch S71B is connected between the input terminal 110B and one end of the power inductor L71B. Specifically, the switch S71B includes a terminal connected to the input terminal 110B and a terminal connected to one end of the power inductor L71B. In this connection structure, the switch S71B can switch the connection and non-connection between the input terminal 110B and one end of the power inductor L71B by switching on and off.

[0211] The switch S72B is connected between one end of the power inductor L71B and the ground. Specifically, the switch S72B includes a terminal connected to one end of the power inductor L71B and a terminal connected to the ground. In this connection structure, the switch S72B can switch the connection and non-connection between one end of the power inductor L71B and the ground by switching on and off.

[0212] The switch S74B is connected between the other end of the power inductor L71B and the output terminal 112B. Specifically, the switch S74B includes a terminal connected to the other end of the power inductor L71B and a terminal connected to the output terminal 112B. In this connection structure, by switching on / off, the switch S74B can switch the connection and non-connection between the other end of the power inductor L71B and the output terminal 112B.

[0213] The switch S75B is connected between the other end of the power inductor L71B and the ground. Specifically, the switch S75B includes a terminal connected to the other end of the power inductor L71B and a terminal connected to the ground. In this connection structure, by switching on / off, the switch S75B can switch the connection and non-connection between the other end of the power inductor L71B and the ground.

[0214] The capacitor C72B is connected between the path between the switch S74B and the output terminal 112B and the ground. Specifically, one of the two electrodes of the capacitor C72B is connected to the switch S74B and the output terminal 112B, and the other of the two electrodes of the capacitor C72B is connected to the ground.

[0215] The pre-regulator circuit 10B configured in this way can convert the power supply voltage into a variable voltage V1 (the second input voltage of the switched capacitor circuit 20).

[0216] In addition, Figure 9 The structure of the pre-regulator circuit 10B shown is an example and is not limited thereto. For example, a part of the switches S71B, S72B, S74B, and S75B can also be replaced with diodes. In addition, a part or all of the pre-regulator circuit 10B can also be included in the tracker circuit 1 in the same way as the pre-regulator circuit 10 related to the modification example of Embodiment 1.

[0217] [2.4 Effects, etc.]

[0218] As described above, the tracker circuit 1 according to the present embodiment is connected to the pre-regulator circuit 10A configured to convert the power supply voltage into the first input voltage and the pre-regulator circuit 10B configured to convert the power supply voltage into the second input voltage.

[0219] Accordingly, a one-input one-output buck-boost converter that is mostly used in existing communication devices can be applied, and the tracker circuit 1 can be easily introduced into the communication device 7A.

[0220] (Embodiment 3)

[0221] Next, Embodiment 3 will be described. In this embodiment, the voltage supplied from the pre-tuner circuit is stepped down within the tracker circuit, and thus the points for generating the two input voltages of the switched capacitor circuit are mainly different from those in Embodiment 1 and Embodiment 2 described above. Hereinafter, this embodiment will be described with a focus on the differences from Embodiment 1 and Embodiment 2 described above, with reference to the accompanying drawings.

[0222] [3.1 Circuit Structure of Communication Device 7B]

[0223] Refer to Figure 10 and the communication device 7B related to this embodiment will be described. Figure 10 is the circuit structure diagram of the communication device 7B related to this embodiment.

[0224] In addition, Figure 10 is an exemplary circuit structure, and the communication device 7B can be installed using any one of a variety of circuit arrangements and circuit technologies. Therefore, the description of the communication device 7B provided below should not be construed in a limited manner.

[0225] The communication device 7B related to this embodiment includes a tracker circuit 1B, a high-frequency circuit 4, an RFIC 5, an antenna 6, a pre-tuner circuit 10A, and a DC power supply 50.

[0226] The tracker circuit 1B can supply a plurality of discrete voltages to the power amplifier 2 in digital ET mode. As Figure 10 shown, the tracker circuit 1B includes a pre-tuner circuit 10C, a switched capacitor circuit 20, an output switch circuit 30, and a digital control circuit 60B.

[0227] The pre-tuner circuit 10C is an example of a converter circuit and is a buck converter. The pre-tuner circuit 10C can step down the first input voltage supplied from the pre-tuner circuit 10A into a variable second input voltage. The pre-tuner circuit 10C can vary the second input voltage based on a control signal from the digital control circuit 60. Use Figure 11 the circuit structure of the pre-tuner circuit 10C described later.

[0228] The pre-tuner circuits 10A and 10C can, for example, switch the difference between the first input voltage and the second input voltage according to the modulation method of the high-frequency signal amplified by the power amplifier 2. More specifically, it may be that the higher the bit rate of the modulation method, the more the pre-tuner circuits 10A and 10C increase the difference between the first input voltage and the second input voltage. Such a switching of the difference between the first input voltage and the second input voltage can also be performed at the switching of the frame of the high-frequency signal. In addition, the pre-tuner circuit 10A may be included in the tracker circuit 1B in the same manner as the pre-tuner circuit 10 related to the modification of Embodiment 1.

[0229] The digital control circuit 60B can control the pre - conditioner circuit 10C based on the digital control signal from the RFIC5, in addition to the switched - capacitor circuit 20 and the output switch circuit 30. Specifically, the digital control circuit 60B can also generate and output a control signal for controlling the switches included in the pre - conditioner circuit 10C. Using Figure 11 the circuit structure of the digital control circuit 60B described later. In addition, the digital control circuit 60B may not be included in the tracker circuit 1B.

[0230] [3.2 Circuit structure of the tracker circuit 1B]

[0231] Refer to Figure 11 and explain the circuit structure of the tracker circuit 1B. Figure 11 is the circuit structure diagram of the tracker circuit 1B and the pre - conditioner circuit 10A according to this embodiment.

[0232] In addition, Figure 11 is an exemplary circuit structure. The tracker circuit 1B and the pre - conditioner circuit 10A can be implemented using any of a variety of circuit arrangements and circuit technologies. Therefore, the descriptions of the circuits provided below should not be construed in a limiting sense.

[0233] As described above, the tracker circuit 1B includes the pre - conditioner circuit 10C, the switched - capacitor circuit 20, the output switch circuit 30, and the digital control circuit 60B. In addition, the tracker circuit 1B may also include a filter circuit (not shown) between the output switch circuit 30 and the power amplifier 2.

[0234] Hereinafter, the circuit structures of the pre - conditioner circuit 10C and the digital control circuit 60B will be described in sequence.

[0235] [3.2.1 Circuit structure of the pre - conditioner circuit 10C]

[0236] First, refer to Figure 11 and explain the circuit structure of the pre - conditioner circuit 10C. The pre - conditioner circuit 10C includes an input terminal 110C, an output terminal 112C, switches S71C and S72C, a power inductor L71C, and a capacitor C72C.

[0237] The input terminal 110C is a terminal for receiving the first input voltage from the pre - conditioner circuit 10A. The input terminal 110C is connected to the pre - conditioner circuit 10A outside the pre - conditioner circuit 10C and is connected to the switch S71C inside the pre - conditioner circuit 10C.

[0238] The output terminal 112C is a terminal for supplying the second input voltage (V1) to the switched capacitor circuit 20. The output terminal 112C is connected to the input terminal 122 of the switched capacitor circuit 20 outside the pre - regulator circuit 10C, and is connected to the power inductor L71C inside the pre - regulator circuit 10C.

[0239] The power inductor L71C is an inductor for boosting and bucking a DC voltage. One end of the power inductor L71C is connected to the switches S71C and S72C, and the other end of the power inductor L71C is connected to the output terminal 112C.

[0240] The switch S71C is connected between the input terminal 110C and one end of the power inductor L71C. Specifically, the switch S71C includes a terminal connected to the input terminal 110C and a terminal connected to one end of the power inductor L71C. In this connection structure, the switch S71C can switch the connection and non - connection between the input terminal 110C and one end of the power inductor L71C by switching on and off.

[0241] The switch S72C is connected between one end of the power inductor L71C and the ground. Specifically, the switch S72C includes a terminal connected to one end of the power inductor L71C and a terminal connected to the ground. In this connection structure, the switch S72C can switch the connection and non - connection between one end of the power inductor L71C and the ground by switching on and off.

[0242] The capacitor C72C is connected between the path between the other end of the power inductor L71C and the output terminal 112C and the ground. Specifically, one of the two electrodes of the capacitor C72C is connected to the other end of the power inductor L71C and the output terminal 112C, and the other of the two electrodes of the capacitor C72C is connected to the ground.

[0243] The pre - regulator circuit 10C configured in this way can step down the variable voltage V3 (the first input voltage of the switched capacitor circuit 20) to the variable voltage V1 (the second input voltage of the switched capacitor circuit 20).

[0244] In addition, Figure 11 The structure of the pre - regulator circuit 10C shown is an example and is not limited thereto. For example, the switch S72C can also be replaced with a diode. In addition, the pre - regulator circuit 10C can also be a boost converter. In this case, the pre - regulator circuit 10C can be configured to receive the second input voltage from the pre - regulator circuit 10A and boost the second input voltage to the first input voltage.

[0245] [3.2.2 Circuit Structure of the Digital Control Circuit 60B]

[0246] Next, refer toFigure 11 The circuit structure of the digital control circuit 60B will be described. The digital control circuit 60B includes a first controller 61B, a second controller 62 , and control terminals 161 to 164 .

[0247] The first controller 61B processes the source synchronous digital control signal received from the RFIC5 via the control terminals 161 and 162, and can generate a control signal for controlling the switched capacitor circuit 20 and the pre-regulator circuit 10C. The on / off of the switches S71C and S72C included in the pre-regulator circuit 10C is controlled by the control signal from the first controller 61B.

[0248] In addition, the digital control signal processed by the first controller 61B is not limited to the source synchronous digital control signal. For example, the first controller 61B may also process the clock embedded digital control signal. In addition, the first controller 61B may also generate a control signal for controlling the output switch circuit 30.

[0249] In addition, in the present embodiment, a set of clock signals and data signals is used, but the present invention is not limited thereto. For example, a plurality of sets of clock signals and data signals may be used as digital control signals. For example, sets of clock signals and data signals may be used independently for the pre-regulator circuit 10C and the switched capacitor circuit 20, respectively.

[0250] [3.3 Effects, etc.]

[0251] As described above, the tracker circuit 1B according to the present embodiment further includes the pre-regulator circuit 10C configured to step down the first input voltage to the second input voltage.

[0252] This makes it possible to apply a one-input one-output buck-boost converter that is often used in existing communication devices, and to operate the tracker circuit 1B using a single buck-boost converter. Therefore, the tracker circuit 1B can be more easily introduced into the communication device 7B.

[0253] (Other Embodiments)

[0254] The tracker circuit, communication device, and tracking method of the present invention are described above based on the embodiments, but the tracker circuit, communication device, and tracking method of the present invention are not limited to the above embodiments. Other embodiments implemented by combining any of the constituent elements in the above embodiments, modified examples obtained by implementing various modifications that can be conceived by those skilled in the art to the above embodiments without departing from the gist of the present invention, and various devices having the above tracker circuit built therein are also included in the present invention.

[0255] For example, in the circuit structures of various circuits involved in the above-described embodiments, other circuit elements and wirings, etc. may also be inserted between the paths connecting the circuit elements and signal paths disclosed in the attached drawings. For example, an inductor and / or a capacitor may be inserted between the tracker circuit 1 and the power amplifier 2.

[0256] In addition, in the above-described embodiments, the first input voltage is supplied to the node N3 of the switched capacitor circuit 20, and the second input voltage is supplied to the node N1, but it is not limited thereto. For example, the first input voltage may be supplied to the node N2, and the second input voltage may be supplied to the node N1. In this case, the third output voltage based on the difference between the first input voltage and the second input voltage is output from the output terminal 123. Additionally, the first input voltage may be supplied to the node N3, and the second input voltage may be supplied to the node N2. In this case, the third output voltage based on the difference between the first input voltage and the second input voltage is output from the output terminal 125.

[0257] In addition, in the above-described embodiments, the switched capacitor circuit 20 generates three discrete voltages, but the number of discrete voltages is not limited to three. For example, the switched capacitor circuit 20 may also generate four or more discrete voltages.

[0258] In addition, the tracker circuit 1 and / or 1B involved in the above-described embodiments may also include a plurality of output switch circuits. In this case, the tracker circuit 1 and / or 1B can supply different voltages to a plurality of power amplifiers.

[0259] Industrial Applicability

[0260] The present invention can be widely used as a tracker circuit for supplying voltage to a power amplifier in communication devices such as mobile phones.

[0261] Explanation of Reference Numerals

[0262] 1, 1B... tracker circuit; 2... power amplifier; 3... filter; 4... high-frequency circuit; 5... RFIC; 6... antenna; 7, 7A, 7B... communication device; 10, 10A, 10B, 10C... pre-tuner circuit; 20... switched capacitor circuit; 30... output switch circuit; 50... DC power supply; 60, 60B... digital control circuit; 61, 61B... first controller; 62... second controller; 110, 110A, 110B, 110C, 121, 122, 131, 132, 133... input terminal; 111, 111A, 112, 112B, 112C, 123, 124, 125, 134... output terminal; 161, 162, 163, 164... control terminal.

Claims

1. A tracker circuit comprising: A switched capacitor circuit configured to generate a plurality of discrete voltages; and An output switch circuit configured to selectively output at least one of the plurality of discrete voltages to a power amplifier, The switched capacitor circuit is configured to generate the plurality of discrete voltages based on a difference between a first input voltage and a variable second input voltage lower than the first input voltage.

2. The tracker circuit according to claim 1, wherein The first input voltage is variable.

3. The tracker circuit according to claim 2, wherein The plurality of discrete voltages includes a first output voltage based on the first input voltage, a second output voltage based on the second input voltage, and a third output voltage based on a difference between the first input voltage and the second input voltage.

4. The tracker circuit according to claim 3, wherein The third output voltage is lower than the first output voltage.

5. The tracker circuit according to claim 3 or 4, wherein The switched capacitor circuit generates the third output voltage such that if the difference between the first input voltage and the second input voltage increases, the difference between the first output voltage and the third output voltage and the difference between the second output voltage and the third output voltage increase respectively.

6. The tracker circuit according to any one of claims 1 to 5, wherein The difference between the first input voltage and the second input voltage is switched according to a modulation method of a high-frequency signal amplified by the power amplifier.

7. The tracker circuit according to claim 6, wherein The higher the bit rate of the modulation method of the high-frequency signal, the greater the difference between the first input voltage and the second input voltage.

8. The tracker circuit according to claim 6 or 7, wherein When switching frames of the high-frequency signal amplified by the power amplifier, the difference between the first input voltage and the second input voltage is switched.

9. The tracker circuit according to any one of claims 1 to 8, wherein The tracker circuit is connected to a converter circuit configured to convert a power supply voltage into the first input voltage and the second input voltage.

10. The tracker circuit according to any one of claims 1 to 8, wherein The tracker circuit is connected to a first converter circuit configured to convert a power supply voltage into the first input voltage and a second converter circuit configured to convert the power supply voltage into the second input voltage.

11. The tracker circuit according to any one of claims 1 to 8, wherein The tracker circuit further includes a converter circuit configured to step down the first input voltage to the second input voltage.

12. A communication device comprising: The tracker circuit according to any one of claims 1 to 11; A converter circuit configured to convert a power supply voltage into the first input voltage and the second input voltage; A signal processing circuit configured to process a high-frequency signal; and A high-frequency circuit configured to include the power amplifier and transmit the high-frequency signal between the signal processing circuit and an antenna.

13. A tracker circuit comprising: A switched capacitor circuit configured to include a first input terminal for receiving a first input voltage and a second input terminal for receiving a variable second input voltage lower than the first input voltage, and generating a plurality of discrete voltages; An output switch circuit configured to selectively output at least one of the plurality of discrete voltages to a power amplifier; A first capacitor connected between the first input terminal and ground; And A second capacitor connected between the second input terminal and ground.

14. The tracker circuit according to claim 13, wherein The tracker circuit further comprises a converter circuit, The converter circuit includes: A power inductor; A first output terminal connected to the first input terminal of the switched capacitor circuit; A second output terminal connected to the second input terminal of the switched capacitor circuit; A first switch connected between the output terminal of the power inductor and the first output terminal; A second switch connected between the output terminal of the power inductor and the second output terminal; A third switch connected between the output terminal of the power inductor and ground; And The first capacitor and the second capacitor, The first capacitor is connected between the path between the first switch and the first output terminal and ground, The second capacitor is connected between the path between the second switch and the second output terminal and ground.

15. The tracker circuit according to claim 14, wherein The breakdown voltage of the switches included in the switched capacitor circuit is higher than the breakdown voltage of the first switch and the second switch included in the converter circuit.

16. The tracker circuit according to any one of claims 13 to 15, wherein The plurality of discrete voltages include a first output voltage based on the first input voltage, a second output voltage based on the second input voltage, and a third output voltage based on the difference between the first input voltage and the second input voltage.

17. The tracker circuit according to claim 16, wherein The third output voltage is lower than the first output voltage.

18. The tracker circuit according to claim 16 or 17, wherein The switched capacitor circuit generates the third output voltage such that if the difference between the first input voltage and the second input voltage increases, the difference between the first output voltage and the third output voltage and the difference between the second output voltage and the third output voltage increase respectively.

19. A communication device comprising: The tracker circuit according to any one of claims 13 to 18; A converter circuit configured to convert a power supply voltage into the first input voltage and the second input voltage; A signal processing circuit configured to process a high-frequency signal; and A high-frequency circuit configured to include the power amplifier and transmit the high-frequency signal between the signal processing circuit and an antenna.

20. A tracking method, wherein Receiving a first input voltage and a second input voltage lower than the first input voltage, Generating a plurality of first discrete voltages based on a first difference between the first input voltage and the second input voltage, Selectively outputting at least one of the plurality of first discrete voltages to a power amplifier, Receiving a third input voltage and a fourth input voltage lower than the third input voltage, the fourth input voltage being different from the second input voltage, Generating a plurality of second discrete voltages based on a second difference between the third input voltage and the fourth input voltage, Selectively outputting at least one of the plurality of second discrete voltages to the power amplifier.

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