Oscilloscope intelligent trigger setting method

Abstract

The invention discloses an oscilloscope intelligent trigger setting method. Firstly, an ADC in an oscilloscope is used for collecting an input signal to obtain a sampling signal; carrying out statistics on the maximum amplitude Vmax and the minimum amplitude Vmin in all sampling points through a histogram; the amplitudes of all the sampling points are added and then averaged to obtain an initial trigger level Vinitial; and finally, based on the maximum amplitude Vmax, the minimum amplitude Vmin and the initial trigger level Vinitial of the sampling signal, rising edge trigger, pulse width trigger, slope trigger and quartile method intelligent trigger setting of the intelligent oscilloscope are realized, the debugging time is shortened, and the debugging efficiency is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of oscilloscopes, and more specifically, relates to a method for setting intelligent oscilloscope triggers. Background Art

[0002] With the continuous improvement of the technological level and the increasing complexity of the acquisition system, the capture of certain special signals becomes extremely important. The trigger module is an indispensable part. It can capture some sudden and tiny abnormal signals, facilitating scientists or circuit enthusiasts to find signals that are difficult to observe with the naked eye, and stably display the signal, improving the debugging efficiency of the hardware circuit or facilitating the observation of some complex signals.

[0003] For signals with different characteristics, the applicable trigger types are also different. Edge trigger can be used for some periodic signals with steep edges; pulse width trigger can be used for some signals with specific pulse widths; slope trigger can be used for capturing signals with rapid changes and steepness. Automatically selecting the appropriate trigger type can not only capture the waveform of interest faster, but also quickly locate problems, which is exactly where the intelligent advantage lies.

[0004] For example, in a communication network, intelligent triggering can be used to monitor and analyze various communication signals. For example, automatically identify and capture the pulse width of signal pulses, the jump edges of signal levels, or the slope of signal changes that conform to specific protocols to detect the transmission quality of signals and identify abnormal signals; in motor control and monitoring: during the operation of the motor, intelligent triggering can automatically select the appropriate trigger mode to monitor signals such as the current, voltage, or speed of the motor. In medical devices, such as electrocardiogram and electroencephalogram monitoring devices, intelligent triggering can automatically select the trigger mode according to the characteristics of human physiological signals, accurately capture and analyze the electrical activity signals of organs such as the heart and brain, and help doctors diagnose and treat diseases.

[0005] When using traditional triggers, users need to set trigger conditions according to the measured signal and the signal characteristics of interest. First, they need to select the appropriate trigger type according to the waveform characteristics, and then further set the trigger conditions. Many oscilloscope users have limited understanding of the trigger function and it is difficult to accurately set the conditions to capture the waveform. Previously, they relied on the automatic setting function of the oscilloscope to configure the trigger, but it could only set the relevant conditions for edge trigger. When facing complex signals and needing to use different types of triggers for observation, users still face challenges in reasonably setting trigger conditions. Summary of the Invention

[0006] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a method for setting intelligent oscilloscope triggers, which selects the optimal trigger mode based on statistical laws and solves the automatic recognition of trigger conditions for arbitrarily complex signals.

[0007] To achieve the above-mentioned invention object, an intelligent trigger setting method for an oscilloscope according to the present invention is characterized by including the following steps:

[0008] (1) Initial setting of the oscilloscope;

[0009] (2) Using the ADC in the oscilloscope to collect the input signal to obtain a sampling signal;

[0010] (3) Through histogram statistics, obtaining the maximum amplitude V max of all sampling points, the minimum amplitude V min ; and adding up the amplitudes of all sampling points and then taking the average to obtain the initial trigger level V initial ;

[0011] (4) Based on the maximum amplitude V max of the sampling signal, the minimum amplitude V min and the initial trigger level V initial to implement the rising edge trigger, pulse width trigger, slope trigger and quartile method intelligent trigger setting of the intelligent oscilloscope.

[0012] The invention object of the present invention is achieved as follows:

[0013] An intelligent trigger setting method for an oscilloscope according to the present invention first uses the ADC in the oscilloscope to collect the input signal to obtain a sampling signal; then through histogram statistics, obtaining the maximum amplitude V max of all sampling points, the minimum amplitude V min ; and adding up the amplitudes of all sampling points and then taking the average to obtain the initial trigger level V initial ; finally, based on the maximum amplitude V max of the sampling signal, the minimum amplitude V min and the initial trigger level V initial to implement the rising edge trigger, pulse width trigger, slope trigger and quartile method intelligent trigger setting of the intelligent oscilloscope, shortening the debugging time and improving the debugging efficiency.

[0014] Meanwhile, an oscilloscope trigger setting method according to the present invention also has the following beneficial effects:

[0015] (1) The present invention can quickly and accurately locate the abnormal features in the waveform, facilitating the user to quickly locate the trigger and select the optimal trigger method, solving the automatic recognition of trigger conditions for complex and variable arbitrary signals, thereby being able to shorten the debugging time and improve the debugging efficiency, having advantages that are incomparable to artificially setting trigger conditions.

[0016] (2) For beginners who are new to oscilloscopes and technicians who do not often use oscilloscopes, this intelligent trigger algorithm enables users to quickly get started and eliminates the need to consult cumbersome trigger condition settings, thereby improving the user experience. Description of the Drawings

[0017] Figure 1 is a flowchart of a method for setting the trigger of an oscilloscope according to the present invention;

[0018] Figure 2 is a schematic diagram of a pulse width comparison circuit;

[0019] Figure 3 is a schematic diagram of a positive pulse;

[0020] Figure 4 is a schematic diagram of a slope comparison circuit;

[0021] Figure 5 is a schematic diagram of pulses with two polarities of positive and negative slopes. Detailed Embodiments

[0022] The following describes the detailed embodiments of the present invention with reference to the accompanying drawings, so that those skilled in the art can better understand the present invention. It should be particularly noted that in the following description, when the detailed description of known functions and designs may obscure the main content of the present invention, these descriptions will be omitted here.

[0023] Embodiment

[0024] In this embodiment, as Figure 1 shown, a method for intelligent trigger setting of an oscilloscope according to the present invention samples the measured waveform through an ADC and sends it to an intelligent trigger algorithm module. After obtaining a suitable trigger type and trigger conditions, it is sent to the trigger module in the FPGA for triggering. Finally, the waveform in the storage module is displayed through a display module. The following is a detailed description of the specific process, including the following steps:

[0025] (1) Initial settings of the oscilloscope;

[0026] (1.1) Set the oscilloscope to work in the highest sampling rate mode, and use the ADC in the oscilloscope to collect the input signal to obtain a sampling signal;

[0027] (1.2) Statistically calculate the maximum amplitude and minimum amplitude in the sampling signal through a histogram, and then calculate the difference ΔV between the two;

[0028] (1.3) Calculate the amplitude V of the entire screen of the oscilloscope range= b * h, where b is the total number of vertical or horizontal sensitivity grids on the oscilloscope screen, and h is the vertical sensitivity; in this embodiment, there are 10 grids for both vertical and horizontal sensitivity on the oscilloscope screen;

[0029] Calculate the ratio α of the waveform of the sampled signal occupying the entire oscilloscope screen as α = ΔV / V range ;

[0030] The intelligent trigger module will automatically adjust the vertical sensitivity according to the ratio α to make α ≥ 0.8, that is, the waveform of the sampled signal occupies more than 80% of the entire screen. Thus, the amplitude range setting is completed;

[0031] (1.4) Determine whether the sampled signal is a periodic signal. If the sampled signal is a periodic signal, the intelligent trigger module automatically identifies the period T of the waveform and adjusts the horizontal sensitivity g so that 10 * g ≥ 4T, that is, the waveform of the sampled signal is completely displayed for more than 4 cycles on the screen; if the waveform is a non-periodic signal, the intelligent trigger module automatically adjusts to the real-time mode;

[0032] (2) Use the ADC in the oscilloscope to collect the input signal to obtain a sampled signal, denoted as {x1, x2, …, x i , … x N},x i represents the i-th sampling point, and N is the number of sampling points;

[0033] (3) Statistically calculate the maximum amplitude V max and minimum amplitude V min among all sampling points through a histogram; after adding the amplitudes of N sampling points and taking the average, the initial trigger level is obtained:

[0034]

[0035] where V i is the amplitude of x i ;

[0036] (4) Rising edge trigger setting;

[0037] Determine whether the sampled signal is a periodic signal. If the sampled signal is a periodic signal, then use V initial as the trigger level and the rising edge as the trigger condition, and send it to the FPGA to end the trigger setting; otherwise, enter step (5);

[0038] (5) Pulse width trigger setting;

[0039] (5.1) Extract the positive and negative pulses in the sampled signal;

[0040] Through a pulse width comparison circuit, such as Figure 2As shown, the sampled signal is compared with the initial trigger level by a comparator. If the amplitude of a certain sampling point in the sampled signal is greater than the initial trigger level V initial , the counter starts counting. When it is less than the initial trigger level V initial , the counter stops counting, and a positive pulse is obtained. If the amplitude of a certain sampling point in the sampled signal is less than the initial trigger level V initial , the counter starts counting. When it is greater than the initial trigger level V initial , the counter stops counting, and a negative pulse is obtained;

[0041] (5.2) After all sampling points in the sampled signal are compared, assume that m positive pulses and k negative pulses are obtained;

[0042] (5.3) The number of sampling points in each positive pulse is counted as the positive pulse width value. If there is a unique positive pulse width value, then using V initial as the trigger level and the unique positive pulse width value as the trigger condition, it is sent to the FPGA, and the trigger setting ends. Otherwise, the number of sampling points in each negative pulse is counted as the negative pulse width value. If there is a unique negative pulse width value, then using V initial as the trigger level and the unique negative pulse width value as the trigger condition, it is sent to the FPGA, and the trigger setting ends. If there is no unique width value in both positive and negative pulses, go to step (5);

[0043] In this embodiment, the initial trigger level V initial is used as the reference voltage. The positive or negative pulse is intercepted by the counter, and then the pulse width count value of the positive or negative pulse is counted. In this embodiment, the pulse width trigger setting is taken as an example with positive pulses. All intercepted positive pulses are as shown in Figure 3 ;

[0044] In this embodiment, assume that 5 positive pulses are obtained. If the positive pulse width values of the 5 positive pulses are (5, 3, 4, 5, 4) respectively, and there is a unique positive pulse width value of 3, then using V initial as the trigger level and the unique positive pulse width value of 3 as the trigger condition, it is sent to the FPGA. If the positive pulse width values of the 5 positive pulses are (5, 5, 4, 5, 4) respectively and there is no unique pulse width value, step (6) needs to be performed;

[0045] (6) Slope trigger setting;

[0046] (6.1) Set the voltage difference Δy = (V max + V min ) / 8;

[0047] Set the high - level threshold V h = (V max + V min ) / 16;

[0048] Set the low - level threshold V l = -(V max + V min ) / 16;

[0049] (6.2), The sampling signal passes through a slope comparison circuit, as Figure 4 shown, traversing the amplitudes of each sampling point in the sampling signal. If the sampling signal first passes through the low - level threshold and then through the high - level threshold, a positive pulse with a positive slope polarity is obtained through the counter, that is: the counter starts counting from the first sampling point greater than V l and stops counting at the first sampling point less than V h , intercepting the continuous sampling points where V l ≤ V i ≤ V h to obtain a positive pulse representing a positive slope; if the sampling signal first passes through the high - level threshold and then through the low - level threshold, a pulse with a negative slope polarity is obtained through the counter, that is: the counter starts counting from the first sampling point less than V h and stops counting at the first sampling point greater than V l , intercepting the continuous sampling points where V l ≤ V i ≤ V h to obtain a negative pulse representing a negative slope;

[0050] In this embodiment, after each sampling point in the sampling signal is compared with the high and low level thresholds, we can intercept pulses of two slope polarities, as Figure 5 shown;

[0051] (6.3), When all sampling points in the sampling signal are traversed, assume that n positive pulses and q negative pulses are obtained;

[0052] (6.4), Calculate the positive slope of each positive pulse;

[0053]

[0054] Calculate the negative slope of each negative pulse;

[0055]

[0056] where λ is the number of sampling points included in the positive pulse, α is the number of sampling points included in the negative pulse, and Δt is the sampling interval time between two adjacent sampling points;

[0057] (6.5), Among the n positive slope values, if there is a unique positive slope value, then use V h 、V lThe trigger level and the only positive slope value are sent to the FPGA as trigger conditions, and the trigger setting is completed; otherwise, continue to count among the q negative slope values. If a unique negative slope value appears, then use V h , V l as the trigger level and the only negative slope value are sent to the FPGA as trigger conditions, and the trigger setting is completed; if no unique slope value appears among all the positive and negative slope values, then go to step (7);

[0058] In this embodiment, assume that 5 pulses with positive slope polarity are obtained. If the slopes of the 5 pulses with positive slope polarity are (3, 3, 0.5, 0.5, 15) respectively, and a unique slope value 15 appears, then use V h , V l as the trigger level and the slope 15 are sent to the FPGA as trigger conditions; if the slope values of the 5 pulses with positive slope polarity are (0.5, 0.5, 0.4, 0.5, 0.4) respectively and no unique positive slope value appears, then continue to count whether a unique negative slope value appears among the negative slope values. If a unique negative slope value appears, then use V h , V l as the trigger level and the negative slope value are sent to the FPGA as trigger conditions; otherwise, step (7) needs to be performed;

[0059] (7). Adjust the pulse width trigger condition;

[0060] (7.1). Set the adjustment step ΔV of the initial trigger level V initial =(V max +V min ) / 64, and set the adjustment range as [V min , V max ;

[0061] (7.2). Calculate the variance of the obtained positive and negative pulse widths respectively. If the variance of the positive pulse width is large, then within the adjustment range [V min , V max , increase V initial by ΔV, otherwise decrease V initial by ΔV, and then re - execute step (5). If a unique width value appears, then use V initial +ΔV or V initial -ΔV as the trigger level and the only pulse width value as the trigger condition are sent to the FPGA, and the trigger setting is completed; otherwise, go to step (8);

[0062] (8). Adjust the slope trigger condition;

[0063] (8.1). Set the high - low level adjustment step ΔV'=(V max +V min) / 32, set the adjustment range to [V min , V max ;

[0064] (8.2) Calculate the variances of the obtained positive and negative slopes respectively. If the variance of the positive slope is large, then within the adjustment range [V min , V max , expand the high and low level thresholds V h , V l simultaneously by ΔV'. Otherwise, reduce the high and low level thresholds V h , V l simultaneously by ΔV'. Then re - execute steps (6.2) - (6.4). If a unique slope value appears, use V h + ΔV', V l + ΔV' or V h - ΔV', V l - ΔV' as the trigger level and the unique slope value as the trigger condition to send to the FPGA, and the trigger setting ends; otherwise, return to step (7);

[0065] (9) Intelligent setting of trigger conditions by the quartile method;

[0066] If neither a unique pulse width value nor a unique slope value is found within the adjustment range [V min , V max , then based on the last adjusted level V last , re - execute steps (5.1) - (5.3) to count the positive pulse width values of each positive pulse;

[0067] Use the quartile method to detect whether the positive pulse width value of each positive pulse is an outlier: set the outlier threshold ρ. When the positive pulse width value of a certain positive pulse is greater than the outlier threshold ρ, then determine that this positive pulse width value is an outlier;

[0068] Count the number of outliers. If only the positive pulse width value of one positive pulse is greater than the outlier threshold ρ, then use V last as the trigger level and this positive pulse width value as the trigger condition; if there are multiple positive pulse width values greater than the outlier threshold ρ, then select the largest positive pulse width value from the multiple positive pulse width values greater than the outlier threshold ρ, and then use V last as the trigger level and the largest positive pulse width value as the trigger condition to send to the FPGA, and the trigger setting ends.

[0069] In this embodiment, assume that 5 positive pulses are obtained through the trigger level V last . If the pulse width values of the 5 positive pulses are (3, 6, 5, 4, 11) respectively, and the outlier threshold ρ calculated by the quartile method is 9, and the pulse width value 11 of the positive pulse is greater than 9, then this positive pulse is the outlier, and then use Vlast The pulse width value 11 of the positive pulse is sent to the FPGA as the trigger level and the trigger condition. If the pulse width values of 5 positive pulses are respectively (2, 6, 1, 8, 11), the outlier threshold ρ is calculated to be 5 by the quartile method. The pulse width values 6, 8, and 11 of the positive pulses are all greater than 5. The largest value among the positive pulse width values that meet the outlier characteristics is selected as the trigger condition, then taking V last as the trigger level and the positive pulse width value 11 as the trigger condition are sent to the FPGA; otherwise, step (7) needs to be performed;

[0070] Finally, after the trigger type and the trigger condition are sent to the trigger module in the FPGA for triggering, the waveforms in the storage module can be displayed through the display module.

[0071] Although the above illustrative specific embodiments of the present invention have been described to facilitate those skilled in the art to understand the present invention, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention defined and determined by the appended claims, these changes are obvious, and all inventions created using the concept of the present invention are within the scope of protection.

Claims

1. An intelligent trigger setting method for an oscilloscope, characterized in that, The following steps are involved: (1) Initial setting of the oscilloscope; (1.1) Set the oscilloscope to work in the highest sampling rate mode, and use the ADC in the oscilloscope to collect the input signal to obtain the sampling signal; (1.2) The maximum and minimum amplitudes of the sampled signal are counted by histogram, and then the difference ΔV between the two is calculated; (1.3), Calculate the amplitude V of the entire oscilloscope screen range = b * h, where b is the total number of grids of the vertical sensitivity or horizontal sensitivity on the oscilloscope screen, and h is the vertical sensitivity; Calculate the ratio α of the waveform of the sampled signal occupying the entire oscilloscope screen: α = ΔV / V range ; The intelligent trigger module will automatically adjust the vertical sensitivity according to the ratio α, so that α ≥ 0.8, that is, the waveform of the sampling signal occupies more than 80% of the entire screen. At this point, the amplitude gear setting is completed; (1.4) Determine whether the sampling signal is a periodic signal. If the sampling signal is a periodic signal, the intelligent trigger module automatically identifies the period T of the waveform and adjusts the horizontal sensitivity g so that 10*g≥4T, that is, the waveform of the sampling signal is fully displayed on the screen for more than 4 periods; if the waveform is a non-periodic signal, the intelligent trigger module automatically adjusts to the real-time mode; (2) Use the ADC in the oscilloscope to collect the input signal to obtain a sampled signal, denoted as {x1, x2, …, x i , … x N}, where xi i represents the i-th sampling point and N is the number of sampling points; (3) Statistically calculate the maximum amplitude V among all sampling points through a histogram max , the minimum amplitude V min ; Add up the amplitudes of N sampling points and then calculate the average to obtain the initial trigger level: Among them, V i is the amplitude of x i ; (4) Rising edge trigger setting; Determine whether the sampling signal is a periodic signal. If the sampling signal is a periodic signal, use V initial as the trigger level and the rising edge as the trigger condition, and send it to the FPGA to end the trigger setting; otherwise, go to step (5); (5) Pulse width trigger setting; (5.1) Extract the positive and negative pulses from the sampled signal; The sampled signal is compared with the initial trigger level by a comparator. If the amplitude of a certain sampling point in the sampled signal is greater than the initial trigger level V initial , the counter starts counting. When it is less than the initial trigger level V initial , the counter stops counting and a positive pulse is obtained. If the amplitude of a certain sampling point in the sampled signal is less than the initial trigger level V initial , the counter starts counting. When it is greater than the initial trigger level V initial , the counter stops counting and a negative pulse is obtained. (5.2) After all sampling points in the sampling signal are compared, it is assumed that m positive pulses and k negative pulses are obtained; (5.3) Count the number of sampling points in each positive pulse as the positive pulse width value. If there is a unique positive pulse width value, use V initial as the trigger level and the unique positive pulse width value as the trigger condition to send to the FPGA, and the trigger setting ends; otherwise, count the number of sampling points in each negative pulse as the negative pulse width value. If there is a unique negative pulse width value, use V initial as the trigger level and the unique negative pulse width value as the trigger condition to send to the FPGA, and the trigger setting ends; if there is no unique width value in both positive and negative pulses, go to step (6); (6) Slope trigger setting; (6.1) Set the voltage difference Δy = (V max + V min ) / 8; Set the high-level threshold V h =(V max +V min ) / 16; Set the low-level threshold V l = -(V max + V min ) / 16; (6.2) Traverse the amplitudes of each sampling point in the sampling signal. The counter starts counting from the first sampling point greater than V l and stops counting at the first sampling point less than V h . Intercept the continuous sampling points where V l ≤V i ≤V h to obtain a positive pulse with a positive slope; The counter starts counting from the first sampling point less than V h and stops counting at the first sampling point greater than V l . Intercept the continuous sampling points where V l ≤V i ≤V h to obtain a negative pulse with a negative slope; (6.3) After all sampling points in the sampled signal are traversed, it is assumed that n positive pulses and q negative pulses are obtained; (6.4), calculate the positive slope of each positive pulse; Calculate the negative slope of each negative pulse; Among them, λ is the number of sampling points contained in the positive pulse, α is the number of sampling points contained in the negative pulse, and Δt is the sampling interval between two adjacent sampling points; (6.5) Among the n positive slope values, if there is a unique positive slope value, then use V h and V l as the trigger levels, and use the unique positive slope value as the trigger condition to send it to the FPGA, and the trigger setting ends; otherwise, continue to count among the q negative slope values. If there is a unique negative slope value, then use V h and V l as the trigger levels, and use the unique negative slope value as the trigger condition to send it to the FPGA, and the trigger setting ends; if there is no unique slope value among all positive and negative slope values, then go to step (7); (6) Adjust the pulse width trigger conditions; (7.1) Set the initial trigger level V initial with an adjustment step ΔV = (V max + V min ) / 64, and set the adjustment range to [V min , V max ; (7.2) Calculate the variances of the positive and negative pulse width values obtained in step (5) respectively. If the variance of the positive pulse width value is large, within the adjustment range [V min , V max , increase V initial by ΔV; otherwise, decrease V initial by ΔV, and then re - execute step (5). If a unique pulse width value appears, use V initial + ΔV or V initial - ΔV as the trigger level and the unique pulse width value as the trigger condition to send to the FPGA, and the trigger setting ends; otherwise, enter step (8); (8) Adjust the slope trigger condition; (8.1) Set the high and low level adjustment step ΔV' = (V max + V min ) / 32, and set the adjustment range to [V min , V max ; (8.2) Calculate the variances of the positive and negative slope values obtained in step (6) respectively. If the variance of the positive slope is large, within the adjustment range [V min , V max , simultaneously expand the high and low level thresholds V h , V l by ΔV'; otherwise, simultaneously reduce the high and low level thresholds V h , V l by ΔV', and then re - execute steps (6.2) to (6.4). If a unique slope value appears, use V h + ΔV', V l + ΔV' or V h - ΔV', V l - ΔV' as the trigger level and the unique slope value as the trigger condition to send to the FPGA, and the trigger setting ends; otherwise, return to step (7); (9) Quartile method intelligently sets trigger conditions; If no unique pulse width value or unique slope value is found within the adjustment range [V min , V max , then, with the level V last of the last adjustment as the reference, steps (5.1) to (5.3) are re-executed to count the positive pulse width values of each positive pulse; Use the quartile method to detect whether the positive pulse width value of each positive pulse is an outlier: set the outlier threshold ρ, when the positive pulse width value of a positive pulse is greater than the outlier threshold ρ, then determine that the positive pulse width value is an outlier; Count the number of statistical outliers. If only the positive pulse width value of one positive pulse is greater than the outlier threshold ρ, then use V last as the trigger level and this positive pulse width value as the trigger condition. If the positive pulse width values of multiple positive pulses are greater than the outlier threshold ρ, then select the maximum positive pulse width value from the multiple positive pulse width values greater than the outlier threshold ρ, and then use V last as the trigger level and the maximum positive pulse width value as the trigger condition to send to the FPGA, and the trigger setting ends.

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