Method for improving mura defect of MEMS (Micro Electro Mechanical System) mask

Abstract

The method for improving the mura defect of the MEMS mask comprises the following steps: S1, testing an MEMS semi-finished product on which chips are distributed on a wafer, displaying a Map image of the whole wafer, and determining a mura pattern type; s2, if the mura pattern type of one chip is twill, all the chips are twill and the distribution rule of the twill forms an integral divergent shape, spin coating is adjusted from a process end, if the mura pattern type of one chip is twill and twill appears on all the chips in an interlaced manner, whether a high aspect ratio pattern exists is judged, and if yes, the step S3 is executed; the improvement is realized by adjusting the glue thickness at the process end, optimizing the pattern uniformity at the design end or upgrading the plate-making end mask plate-making; s3, if the mura pattern type is a vertical pattern and all chips are vertical patterns, performing plate-making upgrading on the plate-making end mask plate; and S4, in a certain row, some chips have the mura types of inclined grains and other chips have vertical grains, observing the inclined grain mura distribution rule of all the chips, if the inclined grain mura distribution rule is similar to the inclined grain mura distribution rule in the step S2, adopting the same mode in the step S2, and if the inclined grain mura distribution rule in the step S2 is not the inclined grain mura distribution rule in the step S2, carrying out plate making upgrading on the plate making end mask plate.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and more particularly to a method for improving mura defects of a MEMS mask Background Art

[0002] Mura defects are one of the more numerous and difficult-to-detect defects. The name "mura" comes from a Japanese word and specifically refers to panel defects, which are used to characterize the non-uniformity of the display area when the display shows a constant brightness, and it has an obvious negative impact on the display image quality. The Spatial Enhancement Mura Uniform Specification (SEMI Mura, SEMI D31-1102) proposed by the International Semiconductor Equipment and Materials International (SEMI) in 2002 is a basic tool for evaluating the degree of mura. When SEMU (Semi Mura) > 1, mura defects can be perceived by the human eye. The larger the value, the more obvious the feeling, and the more serious the mura defects

[0003] Mura is a phenomenon that appears due to poor picture uniformity in the display area. This kind of bad phenomenon is generally generated during the manufacturing process of the array process. The array process production requires repeated key processes such as deposition, exposure, lithography, and etching. Due to the relatively complex production process and high integration, there are many sources of mura defects

[0004] There are many reasons for the generation of mura defects. Some are caused by the array process. For example, the non-uniformity of film thickness, the misalignment between layers, the uniformity of material distribution, etc. Some are foreign objects introduced during the production process, which are related to material equipment process parameters and front-end design. It can be seen that in terms of process and design, the mura bad phenomenon almost revolves around one keyword: uniformity. Whether it is film thickness material or design, high consistency and uniformity must be pursued to avoid introducing mura defects

[0005] In the mask industry, mura defects are one of the many defects on the mask field frequency, and most of them are manifested as linear mura. Since the mask is a lithography master mold, the mura defects on the mask will be reflected in the final product terminal Summary of the Invention

[0006] In view of the problems existing in the background art, an object of the present disclosure is to provide a method for improving mura defects of a MEMS mask, which can improve mura defects and thereby improve the MEMS imaging quality

[0007] Accordingly, a method for improving MEMS mask mura defects includes the following steps: S1, testing the MEMS semi-finished products with chips distributed on the wafer. The testing end responds to the MEMS semi-finished products to display the Map image of the entire wafer, and observes and determines whether the mura pattern type of each chip is diagonal mura or vertical mura from the Map image; S2, if the mura pattern type of a chip is diagonal mura, the mura pattern types of all chips are diagonal mura, and the distribution rule of the diagonal mura of all chips is that the diagonal mura of all chips forms an overall divergent shape, then it is determined that the cause of the mura formation of this chip is the spin coating process, and the uniformity of the spin-coated glue thickness is adjusted from the process end. If the mura pattern type of a chip is diagonal mura and the distribution rule of the mura patterns of all chips is that diagonal mura appears alternately, then for each chip in the rows where diagonal mura appears, it is judged whether there is a high aspect ratio pattern on the diagonal path of the diagonal mura of this chip. If there is a high aspect ratio pattern, it is improved by adjusting the glue thickness from the process end, optimizing the pattern uniformity from the design end, or upgrading the mask plate making at the plate making end; S3, if the mura pattern type is vertical mura and all chips are vertical mura, it is improved by upgrading the mask plate making at the plate making end; S4, among the chips in a certain row on the wafer, the mura type of some chips is diagonal mura while the mura type of other chips is vertical mura. Observe the distribution rule of the diagonal mura among all chips. If the distribution rule of the diagonal mura among all chips is similar to that in step S2, it is processed in the same way as in step S2. If the distribution rule of the diagonal mura among all chips is not the rule in step S2, it is directly improved by upgrading the mask plate making at the plate making end.

[0008] The beneficial effects of the present disclosure are as follows: In the method for improving MEMS mask mura defects according to the present disclosure, through steps S1 to S4, the mura defects can be improved, and thus the MEMS imaging quality can be improved. Description of the Drawings

[0009] Figure 1 is a flowchart of the method for improving MEMS mask mura defects according to the present disclosure.

[0010] Figure 2 is a mura pattern distribution of the Map image of the entire wafer displayed by the testing end in response to the MEMS semi-finished products, wherein the mura pattern type is diagonal mura and the distribution rule of the diagonal mura of all chips is that the diagonal mura of all chips forms an overall divergent shape.

[0011] Figure 3It is another mura pattern distribution in which the test end responds to the MEMS semi-finished product to display the Map image of the entire wafer. Among them, the mura pattern type is diagonal mura, and the distribution rule of diagonal mura for all chips is that diagonal mura appears alternately.

[0012] Figure 4 It is yet another mura pattern distribution in which the test end responds to the MEMS semi-finished product to display the Map image of the entire wafer. The mura pattern type is vertical mura, and all chips are vertical mura.

[0013] Figure 5 It is an explanatory diagram for optimizing the pattern uniformity by using a dummy pattern for diagonal mura at the design end.

[0014] Figure 6 It is a test end response display photo of a single chip with mura improvement after using a dummy pattern.

[0015] Figure 7 It is an explanatory diagram for optimizing the pattern uniformity by deleting unnecessary patterns for diagonal mura at the design end.

[0016] Figure 8 It is a test end response display photo of a single chip with mura improvement after deleting unnecessary patterns. Specific implementation manners

[0017] It will be understood that the disclosed embodiments are merely examples of the present disclosure, and the present disclosure can be implemented in various forms. Therefore, the specific details disclosed herein should not be construed as limiting, but only as a basis for the claims and as a representative basis for teaching those of ordinary skill in the art to implement the present disclosure in various ways.

[0018] Refer to Figures 1 to 8 , the method for improving the mura defect of the MEMS mask according to the present disclosure includes the steps:

[0019] S1, test the MEMS semi-finished product with chips distributed on the wafer. The test end responds to the MEMS semi-finished product to display the Map image of the entire wafer, and observe and determine whether the mura pattern type of each chip is diagonal mura or vertical mura from the Map image;

[0020] S2, if the mura pattern type of a chip is diagonal mura, the mura pattern types of all chips are diagonal mura, and the distribution rule of diagonal mura for all chips is that the diagonal mura of all chips forms an overall divergent shape, then it is determined that the cause of mura formation is the spin coating process, and adjust the uniformity of the spin-coated glue thickness from the process end.

[0021] If the mura pattern type of a chip is diagonal mura and the distribution pattern of the mura patterns of all chips is that diagonal mura appears alternately, for each chip in the rows where diagonal mura appears, determine whether there are high aspect ratio patterns on the diagonal path of the diagonal mura of the chip. If there are high aspect ratio patterns, improve it by adjusting the photoresist thickness at the process end, optimizing the pattern uniformity at the design end, or upgrading the mask plate manufacturing at the mask plate manufacturing end;

[0022] S3, if the mura pattern type is vertical mura and all chips have vertical mura, improve it by upgrading the mask plate manufacturing at the mask plate manufacturing end;

[0023] S4, among the chips in a certain row on the wafer, the mura type of some chips is diagonal mura while the mura type of some other chips is vertical mura. Observe the distribution pattern of the diagonal mura among all chips. If the distribution pattern of the diagonal mura among all chips is similar to that in step S2, process it in the same way as in step S2. If the distribution pattern of the diagonal mura among all chips is not the pattern in step S2, choose to directly improve it by upgrading the mask plate manufacturing at the mask plate manufacturing end.

[0024] In step S1, for a chip, it can be observed from the Map image whether the chip has mura patterns and if the chip has mura patterns, it can be determined whether the mura pattern type of the chip is diagonal mura or vertical mura. Figure 2 、 Figure 3 and Figure 4 give three example cases of the mura pattern distribution of the entire wafer. In Figure 2 , each chip has mura patterns and the mura pattern type of each chip is diagonal mura; in Figure 3 , the chips in the middle three rows have no mura patterns, and the chips in the other rows have mura patterns and the mura pattern type is diagonal mura; in Figure 4 , each chip has mura patterns and the mura pattern type of each chip is vertical mura. In addition, for the case where a chip has mura patterns, there may also be a situation where the mura patterns of the chip are a mixture of diagonal mura and vertical mura, such as the chip in the upper right corner of Figure 4 . For the case of a mixture of diagonal mura and vertical mura, it will be determined whether the mura pattern of the chip is diagonal mura or vertical mura based on the severity of the diagonal mura and vertical mura in the image of the mura patterns of the chip. Similarly, taking the chip in the upper right corner of Figure 4 as an example, in Figure 4The vertical stripe mura in the chip at the upper right corner is more serious than the diagonal stripe mura. Therefore, the mura stripe type is classified as vertical stripe mura. That is to say, when the mura stripes of a chip are a mixture of diagonal stripe mura and vertical stripe mura, if the diagonal stripe mura is serious in the mura stripes of the chip, the mura stripe type of the chip is classified as diagonal stripe mura; if the vertical stripe mura is serious in the mura stripes of the chip, the mura stripe type of the chip is classified as vertical stripe mura.

[0025] After determining the mura stripes of each chip in step S1, subsequent analysis and processing are carried out in two routes according to whether the mura stripe type is diagonal stripe and whether the mura stripe type is vertical stripe (i.e., step S2 and step S3).

[0026] In step S2, if the mura stripe type of a chip is diagonal stripe mura, the mura stripe conditions of all chips are observed together to analyze the formation reason of the diagonal stripe mura of the chip.

[0027] For example, in Figure 2 the example, the mura stripe type of a chip is diagonal stripe mura, the mura stripe types of all chips are diagonal stripe mura, and the distribution rule of the diagonal stripe mura of all chips is that the diagonal stripe mura of all chips forms an overall divergent shape. At this time, it is judged that the formation reason of the mura of the chip is the spin coating process, and then the uniformity of the spin-coated glue thickness can be adjusted from the process end. Of course, in Figure 2 the case where the mura stripe types of all chips are diagonal stripe mura and the distribution rule of the diagonal stripe mura of all chips is that the diagonal stripe mura of all chips forms an overall divergent shape, the diagonal stripe mura of all chips will be improved together by adjusting the uniformity of the spin-coated glue thickness from the process end.

[0028] Another example, in Figure 3 the example, the mura stripe type of a chip is diagonal stripe mura, and the distribution rule of the mura stripes of all chips is that diagonal stripe mura appears alternately (that is, there is no mura stripe in the rows of chips adjacent to the row where the diagonal stripe mura is located). In Figure 3In the example, the chips in the middle three rows have no mura patterns, while the chips in other rows have mura patterns and the mura pattern type is diagonal mura. During the spin coating process, since the spin coating starts from the center of the wafer and the wafer rotates, centrifugal force is generated on the wafer. When the spin-coated glue passes through the high aspect ratio pattern of this chip, it may form along the high aspect ratio pattern in the direction of the centrifugal force. Because before the spin coating process, after multiple CMP processes or via holes, the step differences in the via area or the pure dielectric layer area accumulate layer by layer, and there are obvious differences in the step differences at the high aspect ratio pattern of the glue coating substrate, resulting in an uneven glue coating substrate, which in turn causes uneven spin coating. The uneven spin coating will lead to differences in exposure, development, and etching. Therefore, it is possible to determine whether there is a high aspect ratio pattern on the diagonal path of the diagonal mura of this chip along the diagonal path of the diagonal mura of this chip. If there is a high aspect ratio pattern on the diagonal path of the diagonal mura of this chip, the mura defect can be improved by adjusting the glue thickness at the process end, optimizing the pattern uniformity at the design end, or upgrading the mask plate manufacturing at the mask plate manufacturing end.

[0029] The improvement of the mura defect by adjusting the glue thickness at the process end in step S2 can be achieved by using a glue thickness greater than the product step difference in the spin coating process.

[0030] Compared with adjusting the glue thickness at the process end in step S2, optimizing the pattern uniformity at the design end in step S2 can overcome the deficiency that the limitation that the glue thickness used in the spin coating process at the process end is greater than the product step difference will reduce the process window.

[0031] The optimization of the pattern uniformity at the design end in step S2 can be carried out in various ways. For example, in step S2, the optimization of the pattern uniformity at the design end is achieved by adding the same dummy pattern in the current layer and ensuring that the step difference is controlled within the acceptable range of the product function, such as Figure 5 shown. The result after optimizing the pattern uniformity at the design end using the dummy pattern method is as shown in Figure 6 shown. This chip shows that the mura defect has been eliminated. Another example is that in step S2, the optimization of the pattern uniformity at the design end is achieved by deleting unnecessary isolated patterns in the current layer and ensuring that the step difference is controlled within the acceptable range of the product function, such as Figure 7 shown. The result after optimizing the pattern uniformity at the design end by deleting unnecessary isolated patterns is as shown in Figure 8 shown. This chip shows that the mura defect has been eliminated. Comparing Figure 8 and Figure 6 , the effect of eliminating the mura defect by optimizing the pattern uniformity at the design end by deleting unnecessary isolated patterns is better than the effect of eliminating the mura defect by optimizing the pattern uniformity at the design end using the dummy pattern method.

[0032] Although optimizing the pattern uniformity at the design end has advantages compared to adjusting the photoresist thickness at the process end, with the development of MEMS technology, the critical dimension (CD) of each layer determined during product design is becoming more and more extreme. The design rule of CD < 1μm has become very common, and optimizing the pattern uniformity at the design end will reach a bottleneck due to the limitation of the hardware of the mask. For the same CD line width, the pattern CD uniformity of laser lithography plate making is dozens of nanometers different from that of electron beam lithography plate making. However, the cost of electron beam lithography plate making is relatively expensive compared to laser lithography plate making. Considering the comprehensive cost performance, using upgraded electron beam lithography plate making for the critical layer and un-upgraded laser lithography plate making for the other layers can be used as a way to upgrade the mask plate making at the plate making end. Of course, even for the same laser lithography plate making, it is also possible to upgrade from making a mask with a lower production level to making a mask with a higher production level, using a mask with a higher production level for the critical layer and a mask with a lower production level for the other layers. In this way, the mask plate making upgrade at the plate making end can fundamentally optimize the mura phenomenon without adding too much cost.

[0033] For the case where the mura pattern type in step S3 is vertical mura and all chips are vertical mura, as Figure 4 shown in the figure, since no rule can be found and the specific reason cannot be determined from the relationship between the spin coating of the photoresist during centrifugation and the product step difference and the high aspect ratio pattern during photoresist coating, and it is found from the production practice at the process end that the improvement effect at the process end is very little, for the case where the mura pattern type is vertical mura and all chips are vertical mura, the mura defect is directly improved by upgrading the mask plate making at the plate making end. The mask plate making upgrade at the plate making end can also adopt the method of step S2, that is, using upgraded electron beam lithography plate making for the critical layer and un-upgraded laser lithography plate making for the other layers, or for the same laser lithography plate making, upgrading from making a mask with a lower production level to making a mask with a higher production level.

[0034] Regarding the situation in step S4 where among the chips in a certain row on the wafer, the mura type of some chips is diagonal mura and the mura type of some other chips is vertical mura, the distribution rule of the diagonal mura in all chips can be observed. If the distribution rule of the diagonal mura in all chips is similar to that in step S2, the same method as in step S2 is adopted. If the distribution rule of the diagonal mura in all chips is not the rule in step S2, it is directly selected to improve by upgrading the mask plate making at the plate making end.

[0035] In summary, in the method for improving the mura defect of the MEMS mask according to the present disclosure, through steps S1 to S4, the mura defect can be improved, and thus the MEMS imaging quality can be improved.

[0036] Multiple exemplary embodiments are described with the above detailed description, but the present disclosure is not intended to be limited to the explicitly disclosed combinations. Thus, unless otherwise stated, the various features disclosed herein may be combined together to form multiple additional combinations not shown for the sake of brevity.

Claims

1. A method for improving MEMS mask mura defects, characterized in that, Including steps: S1. Test the MEMS semi-finished products with chips distributed on the wafer. The test end responds to the MEMS semi-finished products to display the Map image of the entire wafer, and observe and determine whether the mura pattern type of each chip is diagonal mura or vertical mura from the Map image; S2. If the mura pattern type of a chip is diagonal mura, the mura pattern types of all chips are diagonal mura, and the distribution rule of the diagonal mura of all chips is that the diagonal mura of all chips forms an overall divergent shape, then it is determined that the cause of the mura of this chip is the spin coating process, and adjust the uniformity of the spin-coated glue thickness from the process end; If the mura pattern type of a chip is diagonal mura and the distribution rule of the mura of all chips is that diagonal mura appears alternately, then for each chip in the row where diagonal mura appears, determine whether there is a high aspect ratio pattern on the diagonal path of the diagonal mura of this chip. If there is a high aspect ratio pattern, improve it by adjusting the glue thickness from the process end, optimizing the pattern uniformity from the design end, or upgrading the mask plate manufacturing of the mask plate from the mask plate manufacturing end; S3. If the mura pattern type is vertical mura and all chips are vertical mura, improve it by upgrading the mask plate manufacturing of the mask plate from the mask plate manufacturing end; S4. Among the chips in a certain row on the wafer, the mura types of some chips are diagonal mura while the mura types of other chips are vertical mura. Observe the distribution rule of the diagonal mura among all chips. If the distribution rule of the diagonal mura among all chips is similar to that in step S2, then process it in the same way as in step S2. If the distribution rule of the diagonal mura among all chips is not the rule in step S2, then choose to directly improve it by upgrading the mask plate manufacturing of the mask plate from the mask plate manufacturing end.

2. The method for improving the mura defect of the MEMS mask plate according to claim 1, characterized in that In step S2, optimizing the pattern uniformity from the design end is achieved by adding the same dummy pattern in the current layer and ensuring that the step difference is controlled within the acceptance range of the product function.

3. The method for improving the mura defect of the MEMS mask plate according to claim 1, characterized in that In step S2, optimizing the pattern uniformity from the design end is achieved by deleting unnecessary isolated patterns in the current layer and ensuring that the step difference is controlled within the acceptance range of the product function.

4. The method for improving the mura defect of the MEMS mask plate according to claim 1, characterized in that The upgrade of the mask plate manufacturing of the mask plate is: using an upgraded electron beam lithography machine for manufacturing the key layer while using an un-upgraded laser lithography machine for manufacturing the remaining layers, or for the same laser lithography machine for manufacturing, upgrading from the mask plate with a lower manufacturing level to the mask plate with a higher manufacturing level.

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