Implementation method based on passive time service of satellite navigation receiver

Abstract

The invention relates to the field of satellite navigation receiver time service application, and particularly discloses a passive time service implementation method based on a satellite navigation receiver, which comprises the following steps: S1, after a Beidou third-generation baseband chip receives a satellite and positions, calculating clock difference information of the satellite navigation receiver, regulating and controlling the crystal oscillator frequency of the receiver through hardware, and after continuous adjustment for several times, calculating the clock difference information of the satellite navigation receiver; after the clock synchronization with the Beidou navigation system is achieved, pulse per second is output, and time information is sent to the FPGA through a serial port; and S2, after the accurate second pulse output by the Beidou third-generation baseband chip is received, correcting the counting of the punctuality clock in the FPGA, placing the time information received by the serial port in a time counter, and carrying out accurate time maintenance according to the counting of the punctuality clock in the FPGA. According to the passive time service implementation method based on the satellite navigation receiver, through a software handshake and hardware pulse interruption mechanism, the core problems that in a traditional active time service technology, a user cannot trigger according to needs, and the resource utilization rate is low are solved.

Description

Technical Field

[0001] The present invention relates to the field of time service applications of satellite navigation receivers, and particularly to a method for implementing passive time service based on satellite navigation receivers. Background Art

[0002] As Figure 2 shown, current satellite navigation time service technologies mainly rely on receivers to actively output second pulses (1PPS) and UTC time information, complete positioning, speed measurement, and time service (PVT solution) by continuously tracking satellite signals, and use hardware to regulate the oscillator frequency to achieve synchronization with the satellite system clock; for example, Beidou-2 and GPS receivers calculate clock difference information and periodically output time signals to calibrate the clocks of external devices. Such technologies have been widely applied in key fields such as communication and power, relying on the global coverage and high-precision characteristics of the satellite system; However, the core mode of the existing technology is active time service, that is, the receiver outputs time signals at fixed intervals. Users need to rely on external devices to continuously receive and maintain time synchronization, and cannot be triggered on demand. Users cannot actively obtain real-time time information at any time, but can only passively receive periodic signals, resulting in response delays in scenarios with sudden time service requirements (such as power fault recording and military command synchronization); transmission redundancy and resource waste, continuously outputting time signals occupies communication bandwidth and power consumption, and causes energy waste for application scenarios that do not require high-frequency synchronization (such as field monitoring devices).

[0003] Therefore, it is necessary to propose a method for implementing passive time service based on satellite navigation receivers to solve the above problems. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome the defects existing in the prior art. The present invention proposes an implementation method for passive time service based on a satellite navigation receiver, which solves the problems existing in the prior art in the background technology. To achieve the above object, the technical solution adopted by the present invention is as follows: An implementation method for passive time service based on a satellite navigation receiver, including the following steps: S1: After the BeiDou-3 baseband chip acquires satellites and locates, calculate the clock error information of the satellite navigation receiver, regulate the oscillator frequency of the receiver through hardware, and after several consecutive adjustments, when it reaches synchronization with the BeiDou navigation system clock, output a second pulse and send the time information to the FPGA through the serial port; S2: After receiving the accurate second pulse output by the BeiDou-3 baseband chip, correct the internal timekeeping clock count of the FPGA, and at the same time place the time information received by the serial port in the time counter, and perform accurate time maintenance according to the internal timekeeping clock count of the FPGA; S3: When the user has a time service requirement, send a time query instruction through the communication interface connected to the BeiDou-3 satellite navigation receiver; S4: After the BeiDou-3 satellite navigation receiver receives the instruction sent by the user, make a response feedback; S5: After the user accurately receives the feedback instruction of the BeiDou-3 satellite navigation receiver, generate a synchronization pulse for the satellite navigation receiver and record the time at the moment when the pulse is generated; S6: The BeiDou-3 satellite navigation receiver responds to the first correct synchronization pulse after the response feedback, latches the time information and clock count corresponding to the rising edge of the synchronization pulse, and at the same time feeds back the time information to the user.

[0005] Preferably, the implementation steps for the BeiDou-3 baseband chip to acquire satellites and locate are as follows: The baseband chip receives the BeiDou-3 B1I, B2I, and B3I signals. After suppressing noise through a low-noise amplifier and a band-pass filter, convert the RF signal into a baseband signal through digital down-conversion, and complete signal acquisition based on the FFT parallel code phase search algorithm. Subsequently, use a phase-locked loop and a delay-locked loop to jointly track the carrier and pseudo-code phase.

[0006] Preferably, the clock error of the satellite navigation receiver is solved by the least squares method, and the receiver clock error formula is: , where is the signal transmission time of the th satellite, is the local recorded time when the signal of the th satellite arrives at the receiver, and are the ionospheric and tropospheric delay correction values corrected by the Klobuchar model and the Saastamoinen model respectively,

[0007] Preferably, the regulation of the oscillator frequency is dynamically adjusted through the PI control algorithm, and the oscillator frequency formula is: , representing the real-time clock error, , represents the proportional gain coefficient, , represents the integral gain coefficient, is the start time of the control algorithm; when the clock difference fluctuates continuously 5 times , it is determined that the synchronization is completed, and 1PPS and UTC time are output to the FPGA.

[0008] Preferably, when the FPGA receives the 1PPS and UTC time from the baseband chip, it initializes a 32-bit counter, and the count value is every 100ms.

[0009] Preferably, in step S2, the current time is calculated in real time through the time interpolation algorithm, and the formula for the current accurate time is: , where , represents the counter clock frequency, , represents the crystal oscillator drift compensation amount, is the counter count value after the last second pulse, is the UTC reference time provided by the baseband chip; the second pulse of the baseband chip is forced to be synchronized every 60 seconds to eliminate the cumulative error of the crystal oscillator. If the synchronization fails continuously 3 times, switch to the backup oven-controlled crystal oscillator and trigger an alarm.

[0010] Preferably, in step S3, the user sends a time service request instruction through the RS-422 interface, and the instruction format includes the following fields: start symbol: fixed as "GET_TIME"; serial number: 4-byte cyclic count; timestamp: user local time; check code: 1-byte exclusive OR check code.

[0011] Preferably, in step S4, after the Beidou-3 satellite navigation receiver receives the instruction sent by the user, the steps for answering and feedback are: the FPGA parses the instruction and checks it. If the check fails, it returns an error status code. After the check is successful, if the receiver is in the idle state, it immediately returns a ready response. If it is busy, the instruction is stored in the FIFO queue.

[0012] Preferably, in S5, the user terminal generates a standard synchronization pulse, which is transmitted to the receiver through a shielded twisted pair. The pulse transmission delay is calculated through a pre-calibration formula, and the formula is: , where is the wire length, is the dielectric constant, is the speed of light; the user terminal uses a GPS-tamed rubidium clock to record the pulse generation time.

[0013] Preferably, in step S6, after the FPGA detects the rising edge of the pulse, it latches the counter value , and calculates the accurate time: , where , represents the system inherent delay, , represents the temperature compensation amount, Represents the counter value latched by the FPGA; the feedback data includes the UTC whole second time and the nanosecond-level offset. After the user side verifies, if the deviation > 500 ns, the timing is re-triggered.

[0014] Compared with the prior art, the beneficial effects of the present invention include: The implementation method of passive timing based on a satellite navigation receiver solves the core problems of the traditional active timing technology, such as the inability of users to trigger on demand and low resource utilization rate, through software handshake and hardware pulse interruption mechanisms. Through dynamic crystal oscillator frequency adjustment and temperature compensation technology, the timing accuracy is improved, significantly better than the prior art. While retaining the advantages of global coverage and high reliability of satellite timing, a core breakthrough of user-independent triggering and on-demand resource allocation is achieved, with the advantages of high precision, low redundancy, and strong adaptability. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The disclosure of the present invention will be described with reference to the accompanying drawings. It should be understood that the drawings are only for illustrative purposes and are not intended to limit the scope of protection of the present invention. In the drawings, the same reference numerals are used to refer to the same components. Among them: Figure 1 Schematically shows the flowchart of the method steps of the present invention; Figure 2 Schematically shows the working block diagram of the prior art satellite navigation receiver for active timing; Figure 3 Schematically shows the working block diagram of the Beidou-3 satellite navigation receiver for passive timing of the present invention; Figure 4 Schematically shows the detailed flowchart of the Beidou-3 satellite navigation receiver for passive timing of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0016] It is easy to understand that according to the technical solution of the present invention, without changing the essence of the present invention, those of ordinary skill in the art can propose various structural ways and implementation ways that can be mutually replaced. Therefore, the following detailed description and the accompanying drawings are only exemplary descriptions of the technical solution of the present invention, and should not be regarded as all of the present invention or as a limitation or restriction on the technical solution of the present invention.

[0017] Such as Figure 1 、 Figure 3 、 Figure 4As shown in the figure, a method for realizing passive timing based on a satellite navigation receiver includes the following steps: Step 1: The Beidou-3 baseband chip receives satellite signals for positioning. Specifically, the baseband chip receives Beidou-3 B1I, B2I, and B3I signals. After suppressing noise through a low-noise amplifier and a band-pass filter, the radio frequency signal is converted into a baseband signal through digital down-conversion with a decimation rate of 10 MS / s. Based on the FFT parallel code phase search algorithm, signal acquisition is completed, and the acquisition time is <2 seconds. Subsequently, a phase-locked loop and a delay-locked loop are used to jointly track the carrier and pseudo-code phase. Then, the clock error information of the satellite navigation receiver is calculated. Specifically, the clock error of the satellite navigation receiver is solved by the least squares method, and the receiver clock error formula is: where is the signal transmission time of the th satellite, is the local recorded time when the signal of the th satellite arrives at the receiver, and are the ionospheric and tropospheric delay correction values corrected by the Klobuchar model and the Saastamoinen model respectively, is Gaussian noise; then, the frequency of the receiver crystal oscillator is adjusted by hardware. After several consecutive adjustments and synchronization with the Beidou navigation system clock, a one-second pulse is output, and the time information is sent to the FPGA through the serial port. Specifically, the adjustment of the crystal oscillator frequency is dynamically regulated by the PI control algorithm, and the crystal oscillator frequency formula is: where represents the real-time clock error, represents the proportional gain coefficient, represents the integral gain coefficient, is the start time of the control algorithm. When the clock error fluctuation is <1 ns for 5 consecutive times, it is determined that the synchronization is completed, and 1PPS and UTC time are output to the FPGA; it also supports multi-system compatibility to improve the redundancy and reliability of timing. Specifically, the baseband chip hardware supports the input of Beidou B1I, B2I, B3I, and GPS L5 frequency signals. During the signal acquisition stage, Beidou and GPS signals are processed in parallel, and the signal with a higher signal-to-noise ratio is preferentially selected. The time weighted fusion formula is: where is the fused time, is the time solved by Beidou-3, is the time solved by the GPS L5 signal, is the weight of the Beidou system, and the calculation formula is: where is the signal-to-noise ratio of the Beidou signal, is the maximum signal-to-noise ratio supported by the system, is the weight of the GPS system, and the calculation method is the same as .

[0018] Step 2: After receiving the accurate second pulse output from the Beidou-3 baseband chip, correct the internal timing clock count of the FPGA. At the same time, place the time information received through the serial port in the time counter, and perform accurate time maintenance according to the internal timing clock count of the FPGA. The specific implementation method is as follows. Specifically, when the FPGA receives the 1PPS and UTC time from the baseband chip, initialize a 32-bit counter. The clock source is a 10MHz temperature-compensated crystal oscillator with ±0.1ppm. The count value every 100ms is , and calculate the current time in real time through the time interpolation algorithm. The formula for the current accurate time is: , where represents the counter clock frequency, represents the crystal oscillator drift compensation amount, is the counter count value after the previous second pulse, is the UTC reference time provided by the baseband chip. Force the synchronization of the second pulse of the baseband chip every 60 seconds to eliminate the cumulative error of the crystal oscillator. If the synchronization fails 3 times in a row, switch to the backup oven-controlled crystal oscillator and trigger an alarm. If there is no user time service request for 5 consecutive minutes, the FPGA sends a control signal to turn off the RF front-end of the baseband chip, and only maintains the operation of the timing counter, which can reduce the system power consumption. During the receiver sleep period, the system can be awakened through a GPIO interrupt. The wake-up process is as follows: The FPGA detects the interrupt signal, restores the power supply of the RF module, and the baseband chip restarts signal acquisition and tracking.

[0019] Step 3: When the user has a time service requirement, send a time query instruction through the communication interface connected to the Beidou-3 satellite navigation receiver. Specifically, the user sends a time service request instruction through the RS-422 interface. The instruction format includes the following fields: Start symbol: Fixed as "GET_TIME"; Serial number: 4-byte cyclic count, hexadecimal; Timestamp: User local time, Unix format, reserved field; Check code: 1-byte exclusive OR check code, calculated byte by byte from the start symbol to the end symbol; The communication protocol adopts a sliding window mechanism, the window size = 3, supports instruction retransmission and out-of-order processing, the baud rate is 115200bps, the instruction frame adds CRC-32 check, and suppresses channel noise through an adaptive filter.

[0020] Step 4: After the Beidou-3 satellite navigation receiver receives the instruction sent by the user, it makes a response feedback. The specific implementation method is as follows: The FPGA parses and validates the instruction. If the validation fails, it returns an error status code. After successful validation, if the receiver is in the idle state, it immediately returns a ready response. If it is busy, it stores the instruction in the FIFO queue.

[0021] Step 5: After the user accurately receives the feedback instruction of the Beidou-3 satellite navigation receiver, a synchronization pulse is generated for the satellite navigation receiver, and the time at the moment when the pulse is generated is recorded. Specifically, the user terminal generates a standard synchronization pulse, which is transmitted to the receiver via a shielded twisted pair. The pulse transmission delay is calculated by a pre-calibration formula, and the formula is: , where is the wire length, is the dielectric constant, is the speed of light; the user terminal uses a GPS-tamed rubidium clock to record the pulse generation moment, and an EMI filter is deployed in the pulse path to suppress interference above 30 dBm.

[0022] Step 6: The Beidou-3 satellite navigation receiver responds to the first correct synchronization pulse after the response feedback, latches the time information corresponding to the rising edge of the synchronization pulse and the clock count, and at the same time feeds back the time information to the user. After the FPGA detects the rising edge of the pulse, it latches the counter value , and calculates the accurate time: , where represents the inherent delay of the system, represents the temperature compensation amount, represents the counter value latched by the FPGA. The feedback data includes the UTC whole second time and the nanosecond-level offset. If the deviation > 500 ns after the user terminal verification, the time service is re-triggered, and the data can also feedback the time source identifier, the source is Beidou-3 or GPS, supporting multi-system compatibility.

[0023] After the user receives the time information feedback from the Beidou-3 satellite navigation receiver, the accurate time at the received moment can be obtained through processing, achieving the purpose of time service.

[0024] In use, the user sends a time service request instruction through the communication interface to trigger the receiver to enter the time service preparation state. The baseband chip captures the Beidou satellite signal in real time, solves the clock offset and dynamically adjusts the crystal oscillator frequency, generates a high-precision second pulse and UTC time and transmits them to the FPGA. The FPGA maintains the local time using a temperature-compensated crystal oscillator and realizes microsecond-level timekeeping through an interpolation algorithm. After the user terminal generates a synchronization pulse, the receiver latches the current time information, combines the pre-calibrated transmission delay and temperature compensation, and feeds back an accurate time stamp. The whole process realizes a closed-loop time service of "trigger-on-demand - precise latch - dynamic compensation" through software and hardware collaboration, breaking through the traditional fixed cycle limit and meeting the bursty and high-precision time service requirements.

[0025] The technical scope of the present invention is not limited to the content described above. Those skilled in the art can make various deformations and modifications to the above embodiments without departing from the technical idea of the present invention, and these deformations and modifications should all fall within the protection scope of the present invention.

Claims

1. Implementation method for passive timekeeping based on a satellite navigation receiver, characterized in that, Including the following steps: S1: After the BeiDou-3 baseband chip acquires satellite positioning, it calculates the clock error information of the satellite navigation receiver, regulates the oscillator frequency of the receiver through hardware. After several consecutive adjustments, when it reaches synchronization with the BeiDou navigation system clock, it outputs a one-pulse-per-second (1PPS) signal and sends the time information to the FPGA through a serial port; S2: After receiving the accurate 1PPS signal output by the BeiDou-3 baseband chip, correct the internal timing clock count of the FPGA. At the same time, place the time information received through the serial port in the time counter, and perform accurate time maintenance according to the internal timing clock count of the FPGA; S3: When the user has a timing requirement, send a time query command through the communication interface connected to the BeiDou-3 satellite navigation receiver; S4: After the BeiDou-3 satellite navigation receiver receives the command sent by the user, it makes an answer and feedback; S5: After the user accurately receives the feedback command from the BeiDou-3 satellite navigation receiver, generate a synchronization pulse for the satellite navigation receiver and record the time at the moment when the pulse is generated; S6: The BeiDou-3 satellite navigation receiver responds to the first correct synchronization pulse after the answer and feedback, latches the time information and clock count corresponding to the rising edge of the synchronization pulse, and at the same time feeds back the time information to the user.

2. The implementation method based on passive time service of a satellite navigation receiver according to claim 1, characterized in that: The implementation steps for the BeiDou-3 baseband chip to acquire satellite positioning are as follows: The baseband chip receives the BeiDou-3 B1I, B2I, and B3I signals. After suppressing noise through a low-noise amplifier and a band-pass filter, the radio frequency signal is converted into a baseband signal through digital down-conversion, and signal acquisition is completed based on the FFT parallel code phase search algorithm. Subsequently, a phase-locked loop and a delay-locked loop are used to jointly track the carrier and the pseudo-code phase.

3. The implementation method of passive time service based on a satellite navigation receiver according to claim 1, characterized in that: The satellite navigation receiver clock error is solved by the least squares method, and the receiver clock error formula is: , where is the signal transmission time of the -th satellite, is the local recorded time when the signal of the -th satellite arrives at the receiver, and are the ionospheric and tropospheric delay correction values corrected by the Klobuchar model and the Saastamoinen model respectively, is Gaussian noise.

4. The implementation method of passive timing based on a satellite navigation receiver according to claim 1, wherein: The regulation of the crystal oscillator frequency is dynamically adjusted through the PI control algorithm. The formula for the crystal oscillator frequency quantity is: , where represents the real-time clock difference error, represents the proportional gain coefficient, represents the integral gain coefficient, is the start time of the control algorithm; When the clock error fluctuation is <1 ns for 5 consecutive times, it is determined that the synchronization is completed, and 1PPS and UTC time are output to the FPGA.

5. The implementation method of passive time service based on a satellite navigation receiver according to claim 4, wherein: After the FPGA receives the 1PPS and UTC time from the baseband chip, it initializes a 32-bit counter, and the count value is per 100 ms.

6. The implementation method of passive time service based on a satellite navigation receiver according to claim 5, wherein: In step S2, the current time is calculated in real time through a time interpolation algorithm, and the formula for the current exact time is: , where represents the counter clock frequency, represents the crystal oscillator drift compensation amount, is the counter value after the pulse in the previous second, is the UTC reference time provided by the baseband chip; the second pulse of the baseband chip is forced to be synchronized every 60 seconds to eliminate the cumulative error of the crystal oscillator. If the synchronization fails three times in a row, switch to the backup oven-controlled crystal oscillator and trigger an alarm.

7. The implementation method of passive time service based on a satellite navigation receiver according to claim 2, wherein: In step S3, the user sends a timing request command through the RS-422 interface. The command format includes the following fields: Start symbol: Fixed as "GET_TIME"; Serial number: 4-byte cyclic count; Time stamp: The user's local time; Check code: 1-byte exclusive-or check code.

8. The implementation method for passive timing based on a satellite navigation receiver according to claim 7, wherein: In step S4, after the BeiDou-3 satellite navigation receiver receives the command sent by the user, the steps for making an answer and feedback are as follows: The FPGA parses the command and performs verification. If the verification fails, it returns an error status code. After successful verification, if the receiver is in an idle state, it immediately returns a ready answer. If it is busy, the command is stored in the FIFO queue.

9. The implementation method of passive timing based on a satellite navigation receiver according to claim 1, characterized in that: In S5, the client generates a standard synchronization pulse, which is transmitted to the receiver via shielded twisted-pair cables. The pulse transmission delay is calculated using a pre-calibrated formula: , where is the wire length, is the dielectric constant, is the speed of light; the client uses a GPS-disciplined rubidium clock to record the pulse generation time.

10. The implementation method of passive time service based on a satellite navigation receiver according to claim 6, characterized in that: In step S6, after the FPGA detects the rising edge of the pulse, it latches the counter value , and calculates the precise time: , where represents the inherent delay of the system, represents the temperature compensation amount, represents the counter value latched by the FPGA; the feedback data includes the UTC whole second time and the nanosecond-level offset. If the deviation is >500 ns after verification by the user side, the timing is re-triggered.

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