Linear voltage regulator circuit

Abstract

The present application discloses a linear voltage stabilization circuit, which belongs to the field of integrated circuit technology and includes: an amplifying unit, a voltage regulating unit, and a voltage dividing unit, wherein the amplifying unit, the voltage regulating unit, and the voltage dividing unit are connected in sequence; the amplifying unit, the voltage dividing unit, and the fourth transistor of the voltage regulating unit constitute a voltage feedback slow loop; the second capacitor, the third transistor, and the second transistor of the voltage regulating unit constitute a fast response loop. The present application uses a capacitor to quickly couple a voltage drop signal to a transistor, further regulates the voltage by regulating the current flowing through the transistor, reduces common-mode noise interference, and only has a built-in on-chip compensation capacitor of the picofarad level to achieve a faster transient response when the output voltage changes rapidly. The circuit's own characteristics are used to effectively offset common-mode noise, and have an excellent power supply rejection ratio in both low-frequency and high-frequency environments.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a linear voltage regulator circuit. Background Art

[0002] Digital isolators are electronic devices used to transmit digital signals under electrical isolation conditions. They transmit digital signals through an isolation barrier (such as optical, magnetic, or capacitive coupling), enabling transmission between two circuit systems without a physical connection, blocking interference such as high voltage and noise. They are widely used in electrical isolation applications. Capacitively coupled isolators are particularly popular due to their small size and strong interference resistance.

[0003] Common-mode transient immunity (CMTI) is a key specification for digital isolators. GND voltage changes at the receiving end of a digital isolator can generate common-mode noise within the chip. This noise is then transmitted to the transmitting end via the isolation capacitor, pulling down the voltage of the low-dropout linear regulator (LDO), affecting the operation of the chip's internal circuits. Traditional low-dropout linear regulators have low inherent gain and a low power supply rejection ratio. If a disturbance occurs on the power supply, the output voltage V OUT Offsets may occur, making it difficult to cope with high-frequency common-mode noise and unable to guarantee normal transmission of high-frequency signals of the digital isolator.

[0004] Existing technologies use PMOS power transistors to address high-frequency common-mode noise, but this suffers from response speed issues and often requires additional capacitance at the output voltage to improve stability, making on-chip low-dropout linear voltage regulators impossible to implement. Furthermore, conventional low-dropout linear voltage regulators use a five-transistor over-the-air (OTA) structure, resulting in low gain and power supply rejection ratio (PSRR). This makes the output voltage susceptible to drift during power supply disturbances, and a single feedback loop cannot offset common-mode noise during rapid voltage transitions at the receiving end, resulting in a drop in output voltage and making them unsuitable for use in digital isolators. Summary of the Invention

[0005] The present application aims to provide a linear voltage stabilization circuit that can offset common-mode noise and suppress output voltage deviation when the output voltage changes rapidly.

[0006] To achieve the above objectives, the technical solution of this application is:

[0007] A linear voltage stabilizing circuit comprising:

[0008] The amplifying unit, the voltage regulating unit and the voltage dividing unit are connected in sequence;

[0009] Among them, the voltage regulating unit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a second capacitor and a first resistor; the first terminal of the first resistor is connected to the second terminal of the second transistor and the first terminal of the third transistor, the third terminal of the second transistor is connected to the second terminal of the fourth transistor, the first terminal of the second capacitor and the second terminal of the first transistor, the first terminal of the fourth transistor is connected to the first terminal of the first capacitor, the third terminal of the fourth transistor is connected to the second terminal of the second capacitor and the third terminal of the third transistor, and the third terminal of the first transistor is connected to the second terminal of the first capacitor.

[0010] Optionally, the amplifying unit includes: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor;

[0011] the first terminals of the fifth transistor and the sixth transistor, the seventh transistor and the eighth transistor, the ninth transistor and the tenth transistor, and the eleventh transistor and the twelfth transistor are respectively connected, the second terminal of the fifth transistor is connected to the second terminal of the sixth transistor, the third terminal of the fifth transistor is connected to the second terminal of the seventh transistor, the third terminal of the sixth transistor is connected to the second terminal of the eighth transistor, the third terminal of the seventh transistor is connected to the third terminal of the ninth transistor, the first terminal of the eleventh transistor, and the first terminal of the twelfth transistor, the third terminal of the eighth transistor is connected to the third terminal of the tenth transistor, the second terminal of the ninth transistor is connected to the third terminal of the eleventh transistor, the second terminal of the tenth transistor is connected to the third terminal of the twelfth transistor, and the second terminal of the eleventh transistor is connected to the second terminal of the twelfth transistor;

[0012] A first terminal of the fourteenth transistor is connected to a reference voltage, a second terminal of the thirteenth transistor is connected to the second terminal of the fourteenth transistor, a third terminal of the thirteenth transistor is connected to a midpoint of a series connection of the third terminal of the sixth transistor and the second terminal of the eighth transistor, a third terminal of the fourteenth transistor is connected to a midpoint of a series connection of the third terminal of the fifth transistor and the second terminal of the seventh transistor, a first terminal of the fifteenth transistor is connected to the first terminal of the eleventh transistor, a second terminal of the fifteenth transistor is connected to the second terminal of the eleventh transistor, and a third terminal of the fifteenth transistor is connected to a midpoint of a series connection of the second terminal of the thirteenth transistor and the second terminal of the fourteenth transistor.

[0013] Optionally, the second terminal of the first resistor is connected to the second terminal of the sixth transistor, the first terminal of the fourth transistor is connected to the series midpoint of the third terminal of the eighth transistor and the third terminal of the tenth transistor, the first terminal of the second transistor is connected to the first terminal of the tenth transistor, the first terminal of the first transistor is connected to the first terminal of the twelfth transistor, and the second terminal of the first capacitor is connected to the second terminal of the twelfth transistor.

[0014] Optionally, the voltage divider unit includes: a second resistor, a third resistor and a third capacitor; the first terminal of the second resistor is connected to the first terminal of the third capacitor, and the second terminal of the second resistor is connected to the first terminal of the third resistor and the second terminal of the third capacitor.

[0015] Optionally, the first terminal of the second resistor is connected to the second terminal of the second capacitor, the second terminal of the third resistor is connected to the second terminal of the first transistor, the first terminal of the third resistor is connected to the first terminal of the thirteenth transistor, and the first terminal of the third capacitor is connected to the output voltage.

[0016] Optionally, the third transistor and the fourth transistor are PMOS transistors, and the first transistor and the second transistor are NMOS transistors.

[0017] Optionally, the thirteenth transistor and the fourteenth transistor are NMOS transistors.

[0018] Optionally, the thirteenth transistor and the fourteenth transistor are PMOS transistors.

[0019] Optionally, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are PMOS transistors, and the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor are NMOS transistors.

[0020] Optionally, the magnitudes of the first capacitor and the second capacitor include picofarads.

[0021] This application designs a fast response loop of a linear voltage regulator circuit under conventional monolithic integration technology, uses capacitors to quickly couple the voltage drop signal to the transistor, and further regulates the voltage by regulating the current flowing through the transistor, thereby reducing common-mode noise interference. Without relying on large off-chip load capacitors, only pico-farad-level on-chip compensation capacitors are built in, which can effectively reduce the output voltage V caused by rapid changes in the GND voltage. OUT Achieve faster transient response during rapid changes and effectively offset common-mode noise; the linear voltage regulator circuit provided in this application has an excellent low-frequency power supply rejection ratio (about 130dB), and the power supply rejection ratio is still 38dB at a high frequency of 1MHz, which can still effectively reduce the common-mode noise interference generated by the power supply voltage.

[0022] In order to make the above features and advantages of the application more obvious and easy to understand, the following embodiments are given and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a structural diagram of the linear voltage stabilization circuit provided in this application.

[0024] Figure 2 This is a circuit diagram of the first specific embodiment of the linear voltage stabilization circuit provided by this application.

[0025] Figure 3 This is the transient simulation waveform of the traditional linear voltage regulator circuit when the load current is 0-10mA.

[0026] Figure 4 This is the transient simulation waveform of the traditional linear voltage regulator circuit when the load current is 10mA-0.

[0027] Figure 5 This is a simulation waveform diagram of the fast loop of the linear voltage stabilization circuit provided in this application.

[0028] Figure 6 This is a simulation waveform diagram of the voltage feedback slow loop of the linear voltage stabilization circuit provided in this application.

[0029] Figure 7 This is the overall simulation waveform diagram of the linear voltage stabilization circuit provided in this application.

[0030] Figure 8 This is a simulation waveform diagram of the power supply rejection ratio of the linear voltage regulator circuit provided in this application. DETAILED DESCRIPTION

[0031] To make the purpose and technical solutions of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be clearly and completely described below in conjunction with the drawings of the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the described embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0032] This application provides a linear voltage stabilization circuit. Figure 1 , Figure 1 This is a structural diagram of the linear voltage stabilization circuit provided by this application. The linear voltage stabilization circuit provided by this application includes:

[0033] The amplifying unit 11 , the voltage regulating unit 12 and the voltage dividing unit 13 are connected in sequence.

[0034] As an example, see Figure 2 , Figure 2 The circuit diagram of the first specific embodiment of the linear voltage stabilization circuit provided by the present application. The amplifying unit 11 includes: a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M 10 , the eleventh transistor M 11 , the twelfth transistor M 12 , the thirteenth transistor M 13 , the fourteenth transistor M 14 and the fifteenth transistor M 15 .

[0035] The fifth transistor M5 and the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8, the ninth transistor M9 and the tenth transistor M 10 , the eleventh transistor M 11 and the twelfth transistor M 12 The first terminals of the fifth transistor M5 and the sixth transistor M6 are connected respectively, the second terminal of the fifth transistor M5 is connected to the second terminal of the sixth transistor M6, the third terminal of the fifth transistor M5 is connected to the second terminal of the seventh transistor M7, the third terminal of the sixth transistor M6 is connected to the second terminal of the eighth transistor M8, the third terminal of the seventh transistor M7 is connected to the third terminal of the ninth transistor M9 and the eleventh transistor M 11 The first terminal and the twelfth transistor M 12 The first terminals of the eighth transistor M8 and the tenth transistor M are connected respectively. 10 The third terminal of the ninth transistor M9 is connected to the eleventh transistor M 11 The third terminal of the tenth transistor M is connected 10 The second terminal of the twelfth transistor M 12 The third terminal of the eleventh transistor M is connected 11 The second terminal of the twelfth transistor M 12 The second terminal is connected.

[0036] The fourteenth transistor M 14 The first terminal is connected to the reference voltage V REF Connect the thirteenth transistor M 13 The second terminal of the fourteenth transistor M 14 The second terminal of the thirteenth transistor M is connected 13 The third terminal of the fourth transistor M is connected to the series midpoint of the third terminal of the sixth transistor M6 and the second terminal of the eighth transistor M8. 14 The third terminal of the fifth transistor M5 is connected to the series midpoint of the third terminal of the fifth transistor M5 and the second terminal of the seventh transistor M7. 15 The first terminal of the eleventh transistor M11 The first terminal of the fifteenth transistor M is connected 15 The second terminal of the eleventh transistor M 11 The second terminal of the fifteenth transistor M is connected 15 The third terminal of the transistor M11 is connected to the second terminal of the thirteenth transistor M13 and the fourteenth transistor M 14 the series midpoint connection of the second terminal;

[0037] As an example, the voltage regulating unit 12 includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first capacitor C1, a second capacitor C2 and a first resistor R1; the first terminal of the first resistor R1 is connected to the third terminal of the second transistor M2 and the first terminal of the third transistor M3, the second terminal of the second transistor M2 is connected to the third terminal of the fourth transistor M4, the first terminal of the second capacitor C2 and the third terminal of the first transistor M1, the first terminal of the fourth transistor M4 is connected to the first terminal of the first capacitor C1, the third terminal of the fourth transistor M4 is connected to the second terminal of the second capacitor C2 and the third terminal of the third transistor M3, and the second terminal of the first transistor M1 is connected to the second terminal of the first capacitor C1.

[0038] The second terminal of the first resistor R1 is connected to the second terminal of the sixth transistor M6, the first terminal of the fourth transistor M4 is connected to the third terminal of the eighth transistor M8 and the tenth transistor M 10 The third terminal of the second transistor M2 is connected in series with the midpoint of the third terminal of the second transistor M2. 10 The first terminal of the first transistor M1 is connected to the first terminal of the twelfth transistor M 12 The first terminal of the first capacitor C1 is connected to the first terminal of the twelfth transistor M 12 The second terminal is connected.

[0039] As an example, the voltage dividing unit 13 includes: a second resistor R2, a third resistor R3 and a third capacitor C3; the first terminal of the second resistor R2 is connected to the first terminal of the third capacitor C3, and the second terminal of the second resistor R2 is connected to the first terminal of the third resistor R3 and the second terminal of the third capacitor C3.

[0040] The first terminal of the second resistor R2 is connected to the second terminal of the second capacitor C2, the second terminal of the third resistor R3 is connected to the second terminal of the first transistor M1, and the first terminal of the third resistor R3 is connected to the thirteenth transistor M 13 The first terminal of the third capacitor C3 is connected to the output voltage V OUT The first terminal of the third capacitor C3 and the first terminal of the third resistor R3 are connected to the current source DC.

[0041] As an example, a first terminal of the first capacitor C1 is grounded.

[0042] As an example, the first transistor M1, the second transistor M2, the ninth transistor M9, the tenth transistor M 10 , the eleventh transistor M 11 , the twelfth transistor M 12 , the thirteenth transistor M 13 , the fourteenth transistor M 14 and the fifteenth transistor M 15 It is an NMOS tube.

[0043] As an example, the third transistor M3 , the fourth transistor M4 , the fifth transistor M5 , the sixth transistor M6 , the seventh transistor M7 and the eighth transistor M8 are PMOS transistors.

[0044] As an example, the first terminal of each transistor is its gate, the second terminal of each transistor is its source, and the third terminal of each transistor is its drain.

[0045] Next, continue to combine Figure 2 Explain how this application works.

[0046] As an example, in this application, the amplifying unit 11, the voltage dividing unit 13 and the fourth transistor M4 form a voltage feedback slow loop. 13 and the fourteenth transistor M 14 As the input pair tube, the output voltage V OUT The current is converted into current, and the current passes through the output load of the folded current mirror structure composed of the ninth transistor M9 to the fifteenth transistor M15 to output the output voltage V OUT Amplification is performed, and at the same time, the output load of the folded current mirror structure improves the DC gain and power supply rejection ratio, and has a larger DC gain and a larger power supply rejection ratio (PSRR) than traditional operational amplifiers. A PMOS source follower, that is, the fourth transistor M4, is used as the output stage of the amplifier unit 11. The second transistor M2, which is also a PMOS tube, serves as the load of the output stage to buffer the pre-amplified signal and drive the post-stage transistor. In the voltage divider unit 13, the output voltage V OUT The voltage divided by the second resistor R2 and the third resistor R3 is combined with the reference voltage V REF Comparison is made so that the output voltage V OUT With reference voltage V REFThe voltage feedback slow loop is proportional to the voltage of the amplifier unit 11, thereby achieving stable control of the voltage feedback slow loop. At the same time, in the voltage feedback slow loop, since the fourth transistor M4 is the output stage of the amplifier unit 11, the gate of the fourth transistor M4 is a high-resistance point, and a large main pole is formed at the gate of the fourth transistor M4. However, the parasitic capacitance of the fourth transistor M4 is small. In order to meet sufficient loop phase margin, the first capacitor C1 is added to the gate of the fourth transistor M4 to push the main pole to a lower frequency, thereby maintaining the stability of the linear voltage regulator circuit. Furthermore, the area of ​​the input transistor pair and the current mirror structure is increased to ensure that the linear voltage regulator circuit has a low offset and maintains a low offset voltage.

[0047] As an example, the second capacitor C2, the third transistor M3 and the second transistor M2 form a fast response loop. The function of the voltage feedback slow loop is to maintain normal circuit feedback and ensure that the output voltage has normal offset adjustment capability. However, the response speed of the voltage feedback slow loop is slow and cannot offset the interference caused by high-frequency noise in the linear voltage regulation circuit. Therefore, a fast response loop is added to offset high-frequency common-mode noise. The second capacitor C2 is used to quickly couple the voltage change signal to the transistor in the fast response loop for feedback. By regulating the current flowing through the third transistor M3 and the second transistor M2, different voltage drops are formed at the first resistor R1, and the gate-source voltage V of the third transistor M3 is further adjusted. GS3 , using the circuit's own characteristics to quickly change the GND voltage to cause the output voltage V OUT Achieve faster transient response during rapid changes and reduce common-mode noise interference.

[0048] When the output voltage V OUT When rising rapidly, the voltage of the second resistor R2 and the third resistor R3 of the voltage divider unit 13 increases, the gate voltage of the input transistor in the amplifier unit 11 increases, the drain voltage decreases, the gate voltage of the fourth transistor M4 decreases, and the gate-source voltage V GS4 Increases, the current I1 flowing through the fourth transistor M4 increases; since the current copied by the folded current mirror structure is constant, the current I3 flowing through the first transistor M1 is constant, that is, the sum I3 of the current I1 flowing through the fourth transistor M4 and the current I2 flowing through the second transistor M2 is fixed. When I1 increases, the current I2 flowing through the second transistor M2 decreases, so the current I4 on the first resistor R1 decreases, and the gate-source voltage V GS3 The channel opened by the third transistor M3 becomes smaller, resulting in the output voltage V OUT When the output voltage V OUT When rising rapidly, the fast response loop can use the circuit's own characteristics to regulate the current and then regulate the voltage, effectively offsetting the output voltage V OUT The effect of rapid rise reduces the common mode noise. Similarly, when the output voltage VOUT When the output voltage drops rapidly, the fast response loop can also effectively offset the output voltage V OUT The impact of rapid decline.

[0049] As an example, the first capacitor C1 and the second capacitor C2 include on-chip compensation capacitors in the picofarad (pF) level.

[0050] Specifically, the current flowing through each transistor is expressed as follows:

[0051] (1)

[0052] Where I is the current flowing through the transistor; μ is the electron mobility, in cm² / V·s, which reflects the mobility of carriers in the channel; Cox is the capacitance per unit area of ​​the gate oxide layer, in F / cm²; W is the width of the transistor; L is the length of the transistor; V GS Represents the gate-source voltage of the transistor, that is, the voltage difference between the gate and source of the transistor; V th Represents the threshold voltage of the transistor itself.

[0053] The output voltage is expressed as follows:

[0054] (2)

[0055] The operational amplifier gain of the linear voltage regulator circuit is expressed as follows:

[0056] (3)

[0057] in, AV represents the op amp gain, gN Indicates the transconductance parameter of the input pair tube, ron Represents the on-resistance of the NMOS tube in the current mirror, rop Represents the on-resistance of the PMOS tube in the current mirror.

[0058] In one embodiment of the present application, the gain bandwidth of the voltage feedback slow loop is approximately 160KHz, which maintains the stability of the output DC voltage value, and the gain bandwidth product of the fast response loop is approximately 250MHz, which realizes the fast response of the linear voltage regulator circuit and avoids the interference of common-mode noise.

[0059] See also Figure 3 , Figure 3 Represents the load current I of the traditional linear voltage regulator circuit DC The transient response curve when switching between 0-10mA is obtained by switching the current source DC between 0-10mA and detecting the load current I DC Test the stability of the linear voltage regulator circuit. Figure 3 It can be seen that in the traditional linear voltage regulator circuit, when the load current IDC When the current rises from 0 to 10mA within 1us, the output voltage V OUT An undershoot of about 70mV occurs and the voltage recovers to a stable level of 1.8V after 0.6us.

[0060] See also Figure 4 , Figure 4 Represents the load current I of the traditional linear voltage regulator circuit DC The transient response curve when switching between 10mA and 0 is shown in Figure 2. DC When the current drops from 10mA to 0 within 1us, the output voltage V OUT An overcharge voltage of about 160mV was generated and recovered to a stable voltage of 1.8V after 0.7us.

[0061] Further, see Figure 5 , Figure 5 The frequency characteristics of the fast response loop of the linear voltage regulator circuit provided in this application are shown. When simulating a circuit with multiple loops, in order to accurately analyze the frequency characteristics of the loops, it is necessary to open different loop ports and analyze their frequency characteristics separately. For the linear voltage regulator circuit provided in this application, during the simulation of the fast loop, it is necessary to set the first end of the fourth transistor M4 to an AC disconnect, and then apply an excitation signal to the first end of the second transistor M2. The resulting simulation results represent the frequency characteristics of the fast response loop.

[0062] See also Figure 6 , Figure 6 The frequency characteristics of the voltage feedback slow loop of the linear voltage regulator circuit provided in this application are shown. When simulating the voltage feedback slow loop, it is necessary to set the first terminal of the second transistor M2 to an AC disconnect circuit, and then apply an excitation signal to the first terminal of the fourth transistor M4. The obtained simulation results show the frequency characteristics of the voltage feedback slow loop.

[0063] See also Figure 7 , Figure 7 When simulating the frequency characteristics of the linear voltage regulator circuit, the first terminal of the fourth transistor M4 is disconnected and an excitation signal is applied. The simulation results show the overall frequency characteristics of the linear voltage regulator circuit.

[0064] Please continue reading Figures 5 to 7 The bandwidth of the fast response loop of the linear voltage regulator circuit provided by the present application is 250MHz, the phase margin is 57°, the bandwidth of the voltage feedback slow loop is 160KHz, the phase margin is 80°, the bandwidth of the overall linear voltage regulator circuit is 460KHz, the phase margin is 82°, and the output voltage V OUTDuring fast transitions, the fast response loop can respond to voltage disturbances more effectively.

[0065] See also Figure 8 , Figure 8 The power supply rejection ratio characteristics of the linear voltage regulator circuit provided in the present application are represented. The linear voltage regulator circuit provided in the present application has a power supply rejection ratio of 130dB at low frequency and a power supply rejection ratio of 38dB at a high frequency of 1MHz. It has a good suppression effect on the noise of the power supply voltage at both low and high frequencies.

[0066] As an example, the topological deformation of the operational amplifier of the amplifying unit 11 of the linear voltage regulator circuit provided in the present application, such as using PMOS as the input pair tube, but still not deviating from the principle of achieving circuit stability through a fast response loop and a voltage feedback slow loop also falls within the scope of protection of the present application.

[0067] As an example, the fast response loop and voltage feedback slow loop of the linear voltage regulator circuit provided in this application are applicable to a variety of topological structures, such as digital isolators, high-frequency drive circuits, high-frequency DC-DC circuits, etc., and are not limited to the situations proposed in this application.

[0068] This application designs a fast response loop of a linear voltage regulator circuit under conventional monolithic integration technology, uses capacitors to quickly couple the voltage drop signal to the transistor, and further regulates the voltage by regulating the current flowing through the transistor, thereby reducing common-mode noise interference. Without relying on large off-chip load capacitors, only pico-farad-level on-chip compensation capacitors are built in, which can effectively reduce the output voltage V caused by rapid changes in the GND voltage. OUT A faster transient response is achieved during rapid changes, and the circuit's own characteristics are used to regulate current and then voltage, effectively offsetting common-mode noise; the linear voltage regulator circuit provided in this application has an excellent low-frequency power supply rejection ratio (about 130dB), and the power supply rejection ratio is still 38dB at a high frequency of 1MHz, which can still effectively reduce the common-mode noise interference generated by the power supply voltage.

[0069] Although the present application has been disclosed above with reference to the embodiments, they are not intended to limit the present application. Anyone with ordinary knowledge in the technical field may make slight changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be determined by the scope of the appended patent application.

Claims

1. A linear voltage stabilizing circuit, characterized in that: include, The amplifying unit, the voltage regulating unit and the voltage dividing unit are connected in sequence; The voltage regulating unit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a second capacitor, and a first resistor; the first terminal of the first resistor is connected to the second terminal of the second transistor and the first terminal of the third transistor, the third terminal of the second transistor is connected to the second terminal of the fourth transistor, the first terminal of the second capacitor, and the second terminal of the first transistor, the first terminal of the fourth transistor is connected to the first terminal of the first capacitor, the third terminal of the fourth transistor is connected to the second terminal of the second capacitor and the third terminal of the third transistor, and the third terminal of the first transistor is connected to the second terminal of the first capacitor; a second terminal of the first resistor connected to the second terminal of the sixth transistor of the amplifying unit, a first terminal of the fourth transistor connected to a midpoint of a series connection of the third terminal of the eighth transistor of the amplifying unit and the third terminal of the tenth transistor of the amplifying unit, a first terminal of the second transistor connected to the first terminal of the tenth transistor of the amplifying unit, a first terminal of the first transistor connected to the first terminal of the twelfth transistor of the amplifying unit, and a second terminal of the first capacitor connected to the second terminal of the twelfth transistor of the amplifying unit; The voltage dividing unit includes: a second resistor, a third resistor and a third capacitor; the first terminal of the second resistor is connected to the first terminal of the third capacitor, and the second terminal of the second resistor is connected to the first terminal of the third resistor and the second terminal of the third capacitor; The first terminal of the second resistor is connected to the second terminal of the second capacitor, the second terminal of the third resistor is connected to the second terminal of the first transistor, the first terminal of the third resistor is connected to the first terminal of the thirteenth transistor of the amplification unit, and the first terminal of the third capacitor is connected to the output voltage.

2. The linear voltage stabilizing circuit according to claim 1, wherein: The amplifying unit includes: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor; the first terminals of the fifth transistor and the sixth transistor, the seventh transistor and the eighth transistor, the ninth transistor and the tenth transistor, and the eleventh transistor and the twelfth transistor are respectively connected, the second terminal of the fifth transistor is connected to the second terminal of the sixth transistor, the third terminal of the fifth transistor is connected to the second terminal of the seventh transistor, the third terminal of the sixth transistor is connected to the second terminal of the eighth transistor, the third terminal of the seventh transistor is connected to the third terminal of the ninth transistor, the first terminal of the eleventh transistor, and the first terminal of the twelfth transistor, the third terminal of the eighth transistor is connected to the third terminal of the tenth transistor, the second terminal of the ninth transistor is connected to the third terminal of the eleventh transistor, the second terminal of the tenth transistor is connected to the third terminal of the twelfth transistor, and the second terminal of the eleventh transistor is connected to the second terminal of the twelfth transistor; A first terminal of the fourteenth transistor is connected to a reference voltage, a second terminal of the thirteenth transistor is connected to the second terminal of the fourteenth transistor, a third terminal of the thirteenth transistor is connected to a midpoint of a series connection of the third terminal of the sixth transistor and the second terminal of the eighth transistor, a third terminal of the fourteenth transistor is connected to a midpoint of a series connection of the third terminal of the fifth transistor and the second terminal of the seventh transistor, a first terminal of the fifteenth transistor is connected to the first terminal of the eleventh transistor, a second terminal of the fifteenth transistor is connected to the second terminal of the eleventh transistor, and a third terminal of the fifteenth transistor is connected to a midpoint of a series connection of the second terminal of the thirteenth transistor and the second terminal of the fourteenth transistor.

3. The linear voltage stabilizing circuit according to claim 1, wherein: The third transistor and the fourth transistor are PMOS transistors, and the first transistor and the second transistor are NMOS transistors.

4. The linear voltage stabilizing circuit according to claim 2, wherein: The thirteenth transistor and the fourteenth transistor are NMOS transistors.

5. The linear voltage stabilizing circuit according to claim 2, wherein: The thirteenth transistor and the fourteenth transistor are PMOS transistors.

6. The linear voltage stabilizing circuit according to claim 2, wherein: The fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are PMOS transistors, and the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor are NMOS transistors.

7. The linear voltage stabilizing circuit according to claim 1, wherein: The first capacitor and the second capacitor have magnitudes of picofarad.

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