Loss equalization scheme based on randomized parameters

Abstract

The invention relates to a loss equalization scheme based on randomized parameters. In some implementations, a memory device may receive, from a host device, a write command indicating that the memory device writes host data to a portion of memory associated with a logical address. The memory device may determine a physical location of the memory associated with the logical address by mapping the logical address to the physical location of the memory using a wear leveling algorithm, where the portion of the memory is associated with a wear leveling pool, and wherein the wear leveling algorithm maps the logical address to a portion of the wear leveling pool based on randomization parameters. The memory device may write the host data to the physical location of the memory.

Description

[0001] Cross - Reference to Related Applications

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 621,510, filed on January 16, 2024, titled "Wear Leveling Schemes Based on Randomized Parameters" and assigned to its assignee. The disclosure of the prior application is considered part of this patent application and is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to memory devices, memory device operations, and, for example, wear leveling schemes based on randomized parameters. Background Art

[0004] Memory devices are widely used to store information in various electronic devices. A memory device includes memory cells. A memory cell is an electronic circuit capable of being programmed to a data state among two or more data states. For example, a memory cell can be programmed to a data state representing a single binary value (commonly represented by binary "1" or binary "0"). As another example, a memory cell can be programmed to a data state representing a fractional value (e.g., 0.5, 1.5, or the like). To store information, an electronic device can write to or program a set of memory cells. To access the stored information, the electronic device can read from or sense the stored state of the set of memory cells.

[0005] There are various types of memory devices, including random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), holographic RAM (HRAM), flash memory (e.g., NAND memory and NOR memory), and others. Memory devices can be volatile or non-volatile. Non-volatile memory (e.g., flash memory) can store data for a long time even in the absence of an external power source. Volatile memory (e.g., DRAM) loses stored data over time unless the volatile memory is refreshed by a power source. In some instances, a memory device can be associated with a Compute Express Link (CXL). For example, a memory device can be a CXL-compliant memory device and / or can include a CXL interface. Summary of the Invention

[0006] One aspect of the present disclosure relates to a memory device, comprising: one or more components configured to: receive, from a host device, a write command indicating that the memory device writes host data to a portion of a memory associated with a logical address; determine, by using a wear leveling algorithm, a physical location of the memory associated with the logical address to map the logical address to the physical location of the memory, wherein the wear leveling algorithm is based on a randomization parameter; and write the host data to the physical location of the memory.

[0007] Another aspect of the present disclosure relates to a method, comprising: receiving, by a memory device and from a host device, a write command indicating that the memory device writes host data to a portion of a memory associated with a logical address; determining, by the memory device and by using a wear leveling algorithm, a physical location of the memory associated with the logical address to map the logical address to the physical location of the memory, wherein the portion of the memory is associated with a wear leveling pool, and wherein the wear leveling algorithm maps the logical address to a portion of the wear leveling pool based on a randomization parameter; and writing, by the memory device, the host data to the physical location of the memory.

[0008] Yet another aspect of the present disclosure relates to a non-transitory computer-readable medium storing a set of instructions, the set of instructions comprising: one or more instructions that, when executed by one or more processors of a memory device, cause the memory device to: receive, from a host device, a write command indicating that the memory device writes host data to a portion of a memory associated with a logical address; determine, by using a wear leveling algorithm, a physical location of the memory associated with the logical address to map the logical address to the physical location of the memory, wherein the wear leveling algorithm is associated with one of a periodic wear leveling scheme based on a time threshold or an activity-based wear leveling scheme based on an activity threshold, and wherein the wear leveling algorithm randomizes one of the time threshold or the activity threshold; and write the host data to the physical location of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a diagram illustrating an example system capable of performing a wear leveling scheme based on a randomization parameter.

[0010] Figure 2 is a diagram of example components included in a memory device.

[0011] Figures 3A - 3B is a diagram illustrating an example of a logical-to-physical mapping.

[0012] Figures 4A - 4GA diagram of an example associated with an wear leveling scheme based on a randomization parameter.

[0013] Figure 5 A flowchart of an example method associated with an wear leveling scheme based on a randomization parameter. Detailed Description

[0014] A memory device may use an wear leveling scheme, such as for distributing read / write operations across a portion of a memory (e.g., an wear leveling pool) to extend the life of the memory. Wear leveling may refer to changing the logical-to-physical (L2P) mapping of the memory over time to distribute read / write cycles among a number of physical locations of the memory. In such an example, if a hacker or similar entity attempts to hammer a single memory location, the hammering is to be distributed among multiple physical locations, thereby thwarting the attack and / or otherwise extending the life of the memory device.

[0015] Some wear leveling techniques employ a start-gap algorithm to define the L2P mapping of the memory, where the L2P mapping is defined by two pointers: a start pointer and a gap pointer. The physical location pointed to by the gap pointer may change after each wear leveling step event, and the physical location pointed to by the start pointer may change after an iteration of the gap pointer, such that the physical memory locations containing data elements change over time, thereby distributing read / write operations among a number of physical locations of the wear leveling pool. For example, a wear leveling step event may correspond to a time period or the number of accesses to the wear leveling pool. The gap pointer may rotate and decrease over the wear leveling pool in each wear leveling step event, and the position of the start pointer may rotate and increase over the wear leveling pool after each round of the gap pointer. Thus, if a hacker attempts to hammer a particular logical address, the hammering will be distributed across the wear leveling pool, thereby extending the life of the memory device.

[0016] However, known wear leveling schemes (e.g., wear leveling schemes employing the start-gap algorithm or characteristics) may be deterministic and / or may be based on a deterministic wear leveling algorithm. For example, because the start-gap algorithm is based on a deterministic function, if a hacker or similar entity knows the various parameters associated with the stop-gap algorithm, the hacker or similar entity is able to hammer a single physical location of the memory. For example, if the hacker correctly identifies the values of the start pointer, the gap pointer, the time period corresponding to the wear leveling step event, and / or the number of wear leveling pool accesses corresponding to the wear leveling step event, the hacker may mimic the dynamic L2P table, thereby rendering the wear leveling scheme ineffective and thus causing the memory life to be shortened.

[0017] Some embodiments described herein enable a memory device to employ an unpredictable wear leveling scheme, thereby preventing attacks that would otherwise succeed against a deterministic wear leveling scheme. In some instances, the wear leveling scheme and / or wear leveling algorithm may be based on randomized parameters, such as a randomized time threshold associated with a wear leveling step event and / or a randomized activity threshold associated with a wear leveling step event. More specifically, the randomized time threshold and / or the randomized activity threshold may change in a random and / or unpredictable manner in each wear leveling step event, thereby preventing a hacker from hammering a single physical location of the memory device. Thus, based on employing a wear leveling scheme associated with randomized parameters, some embodiments described herein may more efficiently distribute read / write operations across the memory, thereby increasing the useful life of the memory device, and / or may improve the reliability of host data stored in the memory, thereby reducing the power, computation, and other resource consumption required to correct corrupted data.

[0018] Figure 1 FIG. is a diagram of an example system 100 capable of performing a wear leveling scheme based on randomized parameters. System 100 may include one or more devices, apparatuses, and / or components for performing the operations described herein. For example, system 100 may include a host device 110 and a memory device 120. Memory device 120 may include a controller 130 and a memory 140. Host device 110 may communicate with memory device 120 (e.g., controller 130 of memory device 120) via a host interface 150. Controller 130 and memory 140 may communicate via a memory interface 160.

[0019] System 100 may be any electronic device configured to store data in a memory. For example, system 100 may be a computer, a mobile phone, a wired or wireless communication device, a network device, a server, a device in a data center, a device in a cloud computing environment, a vehicle (e.g., a car or an airplane), and / or an Internet of Things (IoT) device. Host device 110 may include one or more processors configured to execute instructions and store data in memory 140. For example, host device 110 may include a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), and / or another type of processing component.

[0020] The memory device 120 can be any electronic device configured to store data in a memory. In some embodiments, the memory device 120 can be an electronic device configured to temporarily store data in a volatile memory. For example, the memory device 120 can be a random access memory (RAM) device, such as a dynamic RAM (DRAM) device or a static RAM (SRAM) device. In this case, the memory 140 can include a volatile memory that requires power to maintain the stored data and loses the stored data after the memory device 120 is powered off. For example, the memory 140 can include one or more latches and / or RAM, such as DRAM and / or SRAM. In some embodiments, the memory 140 can include a non-volatile memory configured to maintain the stored data after the memory device 120 is powered off, such as a NAND memory or a NOR memory. For example, the non-volatile memory can store persistent firmware or other instructions for the controller 130 to execute.

[0021] The controller 130 can be any device configured to communicate with a host device (e.g., via the host interface 150) and the memory 140 (e.g., via the memory interface 160). Additionally or alternatively, the controller 130 can be configured to control the operation of the memory device 120 and / or the memory 140. For example, the controller 130 can include control logic, a memory controller, a system controller, an ASIC, an FPGA, a processor, a microcontroller, and / or one or more processing components. In some embodiments, the controller 130 can be a high-level controller that can communicate directly with the host device 110 and can instruct one or more low-level controllers to perform memory operations in conjunction with the memory 140. In some embodiments, the controller 130 can be a low-level controller that can receive instructions regarding memory operations from a high-level controller that directly interfaces with the host device 110. As an example, the high-level controller can be a solid state drive (SSD) controller, and the low-level controller can be a non-volatile memory controller (e.g., a NAND controller) or a volatile memory controller (e.g., a DRAM controller). In some embodiments, a set of operations described herein as being performed by the controller 130 can be performed by a single controller (e.g., the entire set of operations can be performed by a single high-level controller or a single low-level controller). Alternatively, a set of operations described herein as being performed by the controller 130 can be performed by more than one controller (e.g., a first subset of the operations can be performed by the high-level controller and a second subset of the operations can be performed by the low-level controller).

[0022] The host interface 150 implements communication between the host device 110 and the memory device 120. The host interface 150 may include, for example, a Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA) interface, Peripheral Component Interconnect Express (PCIe) interface, NVMe interface, Universal Serial Bus (USB) interface, Universal Flash Storage (UFS) interface, and / or Embedded MultiMediaCard (eMMC) interface.

[0023] In some examples, the memory device 120 may be a Compute Express Link (CXL)-compliant memory device 120. For example, the memory device 120 may include a PCIe / CXL interface (e.g., the host interface 150 may be associated with the PCIe / CXL interface). CXL is a high-speed CPU-to-device and CPU-to-memory interconnect designed to accelerate next-generation performance. CXL technology maintains memory coherence between the CPU memory space and the memory on the attached device, which allows resource sharing for higher performance, reduced software stack complexity, and reduced total system cost. CXL is designed as an industry open standard interface for high-speed communication. CXL technology builds on the PCIe infrastructure to provide advanced protocols, such as input / output (I / O) protocols, memory protocols, and coherence interfaces, in the area by leveraging the PCIe physical and electrical interfaces.

[0024] The memory interface 160 implements communication between the memory device 120 and the memory 140. The memory interface 160 may include a non-volatile memory interface (e.g., for communicating with non-volatile memory), such as a NAND interface or a NOR interface. Additionally or alternatively, the memory interface 160 may include a volatile memory interface (e.g., for communicating with volatile memory), such as a Double Data Rate (DDR) interface.

[0025] In some embodiments, Figure 1 one or more systems, devices, apparatuses, components, and / or controllers may be configured to: receive, from a host device, a write command indicating that the memory device 120 is to write host data to a portion of the memory associated with a logical address; determine, by using a wear leveling algorithm, a physical location of the memory associated with the logical address to map the logical address to the physical location, wherein the wear leveling algorithm is based on a randomization parameter; and write the host data to the physical location of the memory.

[0026] In some embodiments, Figure 1One or more systems, devices, apparatuses, components, and / or controllers may be configured to: receive, from a host device, a write command indicating that the memory device 120 write host data to a portion of the memory associated with a logical address; determine a physical location of the memory associated with the logical address to map the logical address to the physical location by using an wear leveling algorithm, wherein the portion of the memory is associated with an wear leveling pool, and wherein the wear leveling algorithm maps the logical address to a portion of the wear leveling pool based on a randomization parameter; and write the host data to the physical location of the memory.

[0027] In some embodiments, Figure 1 One or more systems, devices, apparatuses, components, and / or controllers may be configured to: receive, from a host device, a write command indicating that the memory device 120 write host data to a portion of the memory associated with a logical address; determine a physical location of the memory associated with the logical address to map the logical address to the physical location by using an wear leveling algorithm, wherein the wear leveling algorithm is associated with one of a periodic wear leveling scheme based on a time threshold or an activity-based wear leveling scheme based on an activity threshold, and wherein the wear leveling algorithm randomizes one of the time threshold or the activity threshold; and write the host data to the physical location of the memory.

[0028] As indicated above, Figure 1 is for illustration only. Other examples may differ from what is Figure 1 described.

[0029] Figure 2 is a diagram of example components included in the memory device 120. As described above in connection with Figure 1 the memory device 120 may include a controller 130 and a memory 140. As Figure 2 shown in

[0030] the memory 140 may include one or more non-volatile memory arrays 205, such as one or more NAND memory arrays and / or one or more NOR memory arrays. Additionally or alternatively, the memory 140 may include one or more volatile memory arrays 210, such as one or more SRAM arrays and / or one or more DRAM arrays. The controller 130 may transmit signals to and receive signals from the non-volatile memory arrays 205 using a non-volatile memory interface 215. The controller 130 may transmit signals to and receive signals from the volatile memory arrays 210 using a volatile memory interface 220.The controller 130 can control the operation of the memory 140, for example, by executing one or more instructions. For example, the memory device 120 can store one or more instructions as firmware in the memory 140, and the controller 130 can execute the one or more instructions. Additionally or alternatively, the controller 130 can receive one or more instructions from the host device 110 via the host interface 150 and can execute the one or more instructions. In some embodiments, a non-transitory computer-readable medium (such as volatile memory and / or non-volatile memory) can store a set of instructions (such as one or more instructions or code) for the controller 130 to execute. The controller 130 can execute the set of instructions to perform one or more operations or methods described herein. In some embodiments, executing the set of instructions by the controller 130 causes the controller 130 and / or the memory device 120 to perform one or more operations or methods described herein. In some embodiments, hardwired circuitry is used instead of or in combination with one or more instructions to perform one or more operations or methods described herein. Additionally or alternatively, one or more components of the controller 130 and / or the memory device 120 can be configured to perform one or more operations or methods described herein. Instructions are sometimes referred to as "commands".

[0031] For example, the controller 130 can transmit signals to and / or receive signals from the memory 140 based on one or more instructions, such as transferring (e.g., writing or programming) data to all or a part of the memory 140 (such as one or more memory cells, pages, sub-blocks, blocks, or planes of the memory 140), transferring (e.g., reading) data from all or the part of the memory 140, and / or erasing all or the part of the memory 140. Additionally or alternatively, the controller 130 can be configured to control access to the memory 140 and / or provide a translation layer between the host device 110 and the memory 140 (e.g., for mapping logical addresses of the memory array to physical addresses). In some embodiments, the controller 130 can translate host interface commands (such as commands received from the host device 110) into memory interface commands (such as commands for performing operations on the memory array).

[0032] As Figure 2 shown, the controller 130 can include a memory management component 225, an wear-leveling component 230, and / or a write component 235. In some embodiments, one or more of these components are implemented as one or more instructions (such as firmware) executed by the controller 130. Alternatively, one or more of these components can be implemented as an application specific integrated circuit distinct from the controller 130.

[0033] The memory management component 225 may be configured to manage the performance of the memory device 120. For example, the memory management component 225 may perform wear leveling, bad block management, block retirement, read disturbance management, and / or other memory management operations. In some embodiments, the memory device 120 may store (e.g., in the memory 140) one or more memory management tables. The memory management tables may store information that can be used or updated by the memory management component 225, such as information about the age of memory blocks, the erase count of memory blocks, and / or error information associated with memory partitions (e.g., memory cells, memory rows, memory blocks, or the like).

[0034] The wear leveling component 230 may be configured to control wear leveling operations at the memory device 120. In some instances, the wear leveling component 230 may be configured to change the L2P mapping of the memory device 120 over time such that read and / or write operations associated with a given logical address may be distributed across multiple physical locations of the device. In some instances, the wear leveling component 230 may be configured to map logical addresses to physical locations of the memory 140 using a wear leveling algorithm (e.g., a stop-gap algorithm or a similar wear leveling algorithm). Additionally or alternatively, the wear leveling component 230 may be configured to perform a periodic wear leveling scheme, an activity-based wear leveling scheme, and / or other types of wear leveling schemes.

[0035] The write component 235 may be configured to program or write host data to the memory 140. In some embodiments, the write component 235 may be configured to write host data to the memory 140 based on the L2P mapping defined by a wear leveling scheme and / or a wear leveling algorithm (e.g., based on one of a periodic wear leveling scheme, an activity-based wear leveling scheme, or a similar wear leveling scheme). The write component 235 is capable of applying a voltage to a memory cell, e.g., for the purpose of storing a threshold voltage corresponding to a binary value in the memory cell.

[0036] Figure 2 One or more of the devices or components shown may be configured to perform the operations described herein, such as one or more of the operations and / or methods described in connection with FIGS. 3-5. For example, the controller 130, the memory management component 225, the wear leveling component 230, and / or the write component 235 may be configured to perform one or more operations and / or methods on the memory device 120.

[0037] Figure 2 The number and arrangement of components shown are for illustration only. In fact, there may be additional components, fewer components, different components, or a different arrangement of components as compared to Figure 2 the components shown. Additionally, Figure 2 two or more of the components shown may be implemented within a single component, orFigure 2 The individual components shown in Figure 2 can be implemented as multiple distributed components. Additionally or alternatively, Figure 2 a group of components (e.g., one or more components) shown in Figure 2 can perform one or more operations described as being performed by Figure 2 another group of components shown in Figure 2 .

[0038] Figures 3A - 3B is a diagram of an instance 300 of an L2P mapping. For example, Figure 3A depicts an example of using an L2P table 305 for memory address translation, and Figure 3B depicts a wear-leveling scheme for defining values of an L2P table (e.g., L2P table 305) for each wear-leveling step event in a wear-leveling scheme.

[0039] As Figure 3A shown in Figure 3A , a memory system can store one or more address translation tables. The address translation table can be referred to as an L2P mapping table, an L2P address table, or an L2P table, and can be used to translate a logical memory address into a physical memory address. For example, the memory system can receive a command (e.g., from a host device 110), and the command can indicate a logical memory address (e.g., a logical block address (LBA)), which is sometimes referred to as a host address. The memory system can use one or more address translation tables to identify the physical memory address (sometimes referred to as a physical address) corresponding to the logical memory address. For example, a read command can indicate the LBA from which data is to be read, or a write command can indicate the LBA to which data is to be written (or for overwriting data previously written to the LBA). The memory system can use the L2P table (or tables) to translate the LBA (or LBAs) into a physical address associated with the memory system (e.g., a physical address in a memory array). The physical address can indicate a physical location in the memory, such as a die, plane, block, page, and / or a portion of the page where the data is located.

[0040] In some embodiments, the memory system can use a logical address referred to as a translation unit (TU), which can correspond to one or more LBAs. For example, an entry in the L2P table can indicate a mapping between the TU (e.g., indicated by a TU index value) and the physical address where data associated with the TU is stored. In some embodiments, the physical address can indicate the die, plane, block, and page of the TU. In other instances, the physical address can indicate the die, plane, block, and / or page to which data associated with the LBA is written or programmed.

[0041] The memory system may use the L2P table 305 to perform L2P address translation. For example, the L2P table 305 may map a logical address (such as an LBA) to a physical address in the non-volatile memory of the memory system (such as a physical address in one or more memory arrays of the memory system). Although the LBA is described herein as an example of the logical address included in the L2P table 305, other logical addresses or logical units (such as TUs or a group of LBAs and other examples) may be used in a similar manner as described herein. In some embodiments, the L2P table 305 may be the entire L2P table. In other embodiments, the L2P table 305 may be a part of the L2P table (such as a group of entries of the L2P table and / or an address range associated with the L2P table) and / or a physical page table (PPT) associated with the L2P table and other examples. For example, the L2P table 305 may include a group of LBA and physical address pairs (e.g., the pair may include an LBA and a corresponding physical address in the non-volatile memory associated with the LBA).

[0042] In some instances, the memory device 120 may use the L2P table 305 or a similar L2P mapping as part of an wear-leveling scheme. The wear-leveling scheme may be associated with techniques for extending the life of the memory device 120 (such as a memory device 120 associated with a memory technology having limited durability). In some instances, the durability of the memory device 120 may be expressed as the maximum number of read / write cycles that the memory device 120 can sustain before failure. Thus, if the traffic applied addresses a single memory location and the number of read / write cycles contained in the traffic exceeds the maximum number of read / write cycles that can be sustained by the memory device 120, then the application may cause the memory device 120 to fail. For example, a hacker attempting to break the memory device 120 may hammer a physical memory location with numerous read / write commands in order to exceed the maximum number of read / write cycles that can be sustained by the memory device 120, thereby causing the memory device 120 to fail.

[0043] In some instances, the memory device 120 may use wear-leveling techniques in order to distribute read / write operations among numerous physical memory locations, thereby extending the life of the memory device 120. Wear leveling may refer to changing the L2P mapping of the memory device 120 (such as the L2P table 305) over time in order to distribute read / write cycles among numerous physical locations of the memory device 120. In such instances, if a hacker or a similar entity attempts to hammer a single memory location, then the hammering may be distributed among multiple physical locations, thereby foiling the attack and / or otherwise extending the life of the memory device 120.

[0044] As Figure 3BAs shown in, in some wear leveling techniques, the memory device 120 may use a start-gap algorithm to define the L2P mapping of the memory device. For an example based on the start-gap algorithm, the L2P mapping may be defined by two pointers: a start pointer ( Figure 3B shown as S in) and a gap pointer ( Figure 3B shown as G in). The memory device 120 may use the start-gap algorithm to map a logical address to a physical location in the wear leveling pool 310 of the memory 140. In the example Figure 3B shown in, the wear leveling pool 310 may include a set of 17 physical memory locations (indexed from 0 to 16) for maintaining a set of 16 data elements, shown as data elements A through P. As indicated by reference numeral 315, at the start of the operation of the start-gap algorithm, data elements A through P may be stored in consecutive memory locations of the wear leveling pool 310, starting from memory location 0 labeled as the "start" location and extending through memory location 15. Memory location 16 may be unused and / or may be labeled as a "gap" location. In such an example, the start pointer (e.g., S) may point to the first memory location (e.g., memory location 0), and the gap pointer (e.g., G) may point to a location where no data is stored (e.g., memory location 16) and / or a location that is skipped during read / write operations. Thus, in the first iteration, memory locations 0 through 15 may contain data elements A through P, while location 16 may be unused ( Figure 3B shown using cross-hatching in).

[0045] The position of the start pointer and / or the gap pointer may change after each wear leveling step event associated with the wear leveling algorithm, such that the memory locations containing data elements and / or the locations reserved as unused (e.g., the location associated with the gap pointer) change over time, thereby distributing read / write operations among the numerous physical locations of the wear leveling pool 310. For example, the wear leveling step event may correspond to a time period (e.g., for a periodic wear leveling scheme) or the number of accesses to the wear leveling pool 310 (e.g., for an activity-based wear leveling scheme) and other examples. Aspects of the periodic wear leveling scheme and the activity-based wear leveling scheme are described in more detail below in connection with Figure 4A and 4B . In such examples, the gap pointer (e.g., G) may rotate and decrease over the wear leveling pool 310 in each wear leveling step event, and the position of the start pointer may rotate and increase over the wear leveling pool 310 after each round of the gap pointer (e.g., after the gap pointer rotates to each memory location of the wear leveling pool 310).

[0046] More specifically, as indicated by reference numeral 320, after the first wear leveling step event, the gap pointer may rotate to memory location 15, and thus data elements A through O may be stored in memory locations 0 through 14 respectively, and data element P may be stored in memory location 16, where memory location 15 remains unused at the new gap position. In this regard, before decreasing the memory location of the gap pointer (e.g., G), the data in memory location G-1 is copied into the memory location associated with G. More specifically, in the example shown in Figure 3B before moving the gap pointer to memory location 15 (e.g., G-1), the data in memory location 15 is copied and moved to memory location 16. Over time, the gap position travels or rotates to successive lower addresses between iterations.

[0047] As indicated by reference numeral 325, after a plurality (e.g., 16) of wear leveling step events, the gap position will have rotated all the way to memory location 0, and memory locations 1 through 16 may thus be used to store data elements A through P, where memory location 0 remains unused. As shown by reference numeral 330, in the next iteration of the start-gap algorithm, the gap position wraps around to memory location 16, and the start position is incremented by 1 to memory location 1 (e.g., the position of the gap pointer rotates and decreases over each wear leveling step event on wear leveling pool 310 and the position of the start pointer rotates and increases over each round of the gap pointer on wear leveling pool 310). In this regard, data elements may be stored in memory locations 0 through 15, where data element A is now stored at memory location 1 (e.g., the position of the start pointer) and data element P is stored at memory location 0, where memory location 16 (e.g., the location associated with the gap pointer) remains unused. In this regard, over time (e.g., over a plurality of wear leveling step events), data elements A through P may rotate through all of the different memory locations of wear leveling pool 310, such that frequently written and / or read data elements rotate through all memory locations and / or such that the memory is effectively wear leveled. For example, if memory device 120 is hacked and a particular logical address is hammered by the hacker, then the hammering may be distributed across wear leveling pool 310 (e.g., across memory locations 0 through 16 in the above example), thereby distributing read / write access across memory 140 and thus extending the life of memory 140.

[0048] However, because the start-gap algorithm is based on a deterministic function, if a hacker or similar entity knows the various parameters associated with the stop-gap algorithm, then the hacker or similar entity can hammer a single physical location of the memory 140. For example, if the hacker correctly identifies the values of S, G, and / or the period of the wear leveling step event corresponding to the periodic wear leveling scheme or the number of wear leveling pool accesses of the wear leveling step event corresponding to the activity-based wear leveling scheme, then the hacker can mimic the dynamic L2P table to hammer a specific physical location, thereby invalidating the wear leveling scheme and thus causing the memory life to be shortened and / or data storage to be unreliable.

[0049] Some of the techniques and devices described herein enable the memory device 120 to employ an unpredictable wear leveling scheme, thereby preventing attacks that would otherwise be successful against deterministic wear leveling schemes. In some instances, the wear leveling scheme and / or wear leveling algorithm can be based on randomized parameters (such as a randomized time threshold for a periodic wear leveling scheme and / or a randomized activity threshold for an activity-based wear leveling scheme) so that a hacker or similar entity cannot predict the wear leveling scheme. Implementations associated with wear leveling schemes implementing randomized parameters are described in more detail below in conjunction with Figures 4A - 4G more detailed description.

[0050] As indicated above, Figures 3A - 3B for illustration only. Other instances may be different from what is described with respect to Figures 3A - 3B what is described.

[0051] Figures 4A - 4G is a diagram of an example associated with a wear leveling scheme based on randomized parameters. The operations described in conjunction with Figures 4A - 4G can be performed by the memory device 120 and / or one or more components of the memory device 120 (such as the controller 130 and / or one or more components of the controller 130).

[0052] In some embodiments, the memory device 120 may receive a write command from the host device 110 indicating that the memory device 120 is to write host data to a portion of the memory 140 associated with a logical address. In such embodiments, the memory device 120 may map the logical address to a physical location of the memory, for example, by using an L2P table (such as the L2P table 305) or a similar mapping technique. Thereby, the memory device 120 can utilize a wear leveling scheme and / or wear leveling algorithm to identify the physical location for writing the host data, such as for distributing read / write commands across the memory 140 (such as across the wear leveling pool 310 of the memory 140). In some embodiments, instead of using a deterministic function (such as described above in conjunction with Figure 3BRather than determining a physical location as described in the example of, the memory device 120 can map a logical address to a physical location of the memory 140 based on a randomization parameter. In other words, the memory device 120 can determine the physical location of the memory 140 associated with the logical address to map the logical address to the physical location of the memory 140 by using an wear-leveling algorithm, where the wear-leveling algorithm is in turn based on a randomization parameter (e.g., a randomization time threshold and / or a randomization activity threshold, described in more detail below). In this regard, the memory device 120 can be configured to distribute read / write commands between physical locations of the memory 140 (e.g., across the wear-leveling pool 310 of the memory 140) in a random and / or unpredictable manner, thereby invalidating deterministic attacks and thus increasing the useful life cycle of the memory device 120.

[0053] In some embodiments, the wear-leveling algorithm can be based on a periodic wear-leveling scheme, such as the periodic wear-leveling scheme illustrated by reference numeral 400 in Figure 4A As indicated by reference numeral 402, the periodic wear-leveling scheme can be associated with a number of wear-leveling step events, the number can be associated with the movement of a start pointer and / or a gap pointer, as described above in connection with Figure 3B described. In such embodiments, the memory device 120 can be configured to move the gap pointer after each wear-leveling step event and / or the memory device 120 can be configured to move the start pointer after each round of the gap pointer (e.g., after the gap pointer rotates through each memory location associated with the wear-leveling pool), where the wear-leveling step event is associated with a time threshold (sometimes referred to herein as T). In such embodiments, the memory device 120 can determine whether the period of time elapsed since the previous wear-leveling step event meets the time threshold (e.g., T), and if so, can execute the steps of the wear-leveling algorithm, such as moving the gap pointer (e.g., G), as described above in connection with Figure 3B described. For example, the time threshold can be associated with the number of clock cycles, and thus the memory device 120 can count the number of clock cycles that have occurred since the last wear-leveling step event and compare the count to the time threshold (e.g., T) to determine whether a wear-leveling step event will occur, as described in more detail below in connection with Figure 4E described.

[0054] As Figure 4A further shown in, the time threshold (e.g., T) for each respective wear-leveling step event can vary randomly and / or unpredictably such that the wear-leveling step events occur at randomized intervals and / or in an unpredictable manner. For example, Figure 4Ashown as T1 and a first time threshold, indicated by reference numeral 404-1, may be different from a second time threshold (e.g., T2 indicated by reference numeral 404-2), and the second time threshold may in turn be different from a third time threshold (e.g., T3 indicated by reference numeral 404-3), and so on until Figure 4A the sixth time threshold (e.g., T6 indicated by reference numeral 404-6) in the example shown in. In this way, for embodiments in which the wear leveling algorithm is associated with a periodic wear leveling scheme in which corresponding wear leveling step events are performed after a time threshold is met (e.g., after a number of clock cycles have elapsed), the time threshold may be randomized in each wear leveling step event.

[0055] As Figure 4B shown and indicated by reference numeral 406, in some embodiments, the wear leveling algorithm may correspond to an activity-based wear leveling scheme. As indicated by reference numeral 408, the activity-based wear leveling scheme may be associated with the number of wear leveling step events, which may be associated with the movement of the start pointer and / or the gap pointer, as described above in connection with Figure 3B described. In such embodiments, each wear leveling step event may be associated with an activity threshold (sometimes referred to as TH). In such embodiments, the memory device 120 may determine whether the amount of activity that has occurred since the previous wear leveling step event meets the activity threshold (e.g., TH), and if so, the memory device 120 may perform a step of the wear leveling algorithm, such as moving the gap pointer (e.g., G) described above in connection with Figure 3B described. In some embodiments, the activity threshold (e.g., TH) may be associated with the number of read / write operations associated with the wear leveling pool, the number of accesses to the wear leveling pool, or the like, and thus the memory device 120 may count the number of read / write operations associated with the wear leveling pool, the number of accesses to the wear leveling pool, or the like, and compare the count with the activity threshold (e.g., TH) to determine whether a wear leveling step event will occur, as described in more detail below in connection with Figure 4E described.

[0056] As shown in the plot indicated by reference numeral 410, the activity level associated with the wear leveling pool may vary over time, where high activity periods are associated with relatively steep slopes in the plot shown in connection with reference numeral 410, and where low activity periods are associated with relatively flat slopes in the plot shown in connection with reference numeral 410. When the cumulative activity level of a given wear leveling step event reaches the activity threshold (e.g., TH), the memory device 120 may execute a program associated with the wear leveling algorithm, such as moving the gap pointer (e.g., G) associated with the start-gap algorithm. As Figure 4BAs shown, the activity threshold (e.g., TH) for each corresponding wear leveling step event can vary randomly and / or unpredictably, such that the wear leveling step events occur at randomized intervals and / or in an unpredictable manner. For example, Figure 4B the first activity threshold shown as TH1 and indicated by reference numeral 412-1 can be different from the second activity threshold shown as TH2 and indicated by reference numeral 412-2, and the second activity threshold can in turn be different from the third activity threshold shown as TH3 and indicated by reference numeral 412-3. In this way, for an implementation in which a wear leveling algorithm is associated with an activity-based wear leveling scheme where corresponding wear leveling step events are performed after an activity threshold is met, the activity threshold can be randomized in each wear leveling step event.

[0057] In an implementation in which the time threshold associated with a periodic wear leveling scheme is randomized as described above in connection with Figure 4A and / or in an implementation in which the activity threshold associated with an activity-based wear leveling scheme is randomized as described above in connection with Figure 4B the wear leveling scheme can be unpredictable, thereby increasing the robustness of the wear leveling scheme in the face of a failed attack. In this way, after receiving a write command (e.g., from host device 110) indicating that the memory device is to write host data to a portion of the memory associated with a logical address, the memory device 120 can determine the physical location of the memory associated with the logical address to map the logical address to the physical location of the memory by using a wear leveling algorithm, where the wear leveling algorithm is based on randomized parameters (e.g., randomized T and / or TH), and can thus write the host data to the physical location of the memory determined using the randomized parameters.

[0058] In some implementations, the randomized parameters can be symmetrically distributed around an average value, e.g., for the purpose of maintaining the effectiveness of the wear leveling scheme as compared to a scheme that employs constant parameters (e.g., constant T or TH). For example, in some implementations, the wear leveling algorithm can be associated with a plurality of wear leveling step events (e.g., the plurality of wear leveling step events shown in connection with reference numeral 402 in Figure 4A and / or the plurality of wear leveling step events shown in connection with reference numeral 408 in Figure 4B and a plurality of examples of randomized parameters (e.g., the plurality of T values shown in connection with reference numeral 404 in Figure 4A and / or the plurality of TH values shown in connection with reference numeral 412 in Figure 4B ), where each wear leveling step event is associated with a corresponding example of a randomized parameter. In such implementations and as shown by Figure 4CReference numeral 420 in shows that multiple examples of the randomization parameter (indicated by reference numeral 422) may be symmetrically distributed about the mean of the multiple examples of the randomization parameter (indicated by reference numeral 424). In some embodiments, the mean of the multiple examples of the randomization parameter (e.g., multiple examples of T and / or TH) may correspond to a constant value of a conventional wear leveling scheme (e.g., the value of T when T remains constant for each wear leveling step event of the conventional wear leveling scheme and / or the value of TH when TH remains constant for each wear leveling step event of the conventional wear leveling scheme).

[0059] In some embodiments, the randomization parameter (e.g., T and / or TH) may be symmetrically distributed about the mean of the randomization parameter based on a particular distribution scheme. For example, as Figure 4D shown in and indicated by reference numeral 426, in some embodiments, the randomization parameter may be symmetrically distributed about the mean based on a uniform distribution. In some other embodiments, as indicated by reference numeral 432, the randomization parameter may be symmetrically distributed about the mean based on a triangular distribution. In some other embodiments, as indicated by reference numeral 438, the randomization parameter may be symmetrically distributed about the mean based on an inverse triangular distribution. And in some other embodiments, as indicated by reference numeral 444, the randomization parameter may be symmetrically distributed about the mean based on a Gaussian distribution.

[0060] As Figure 4E shown in and indicated by reference numeral 450, in some embodiments, the memory device 120 may be configured to determine whether to move from one wear leveling step event of the wear leveling algorithm to the next wear leveling step event of the wear leveling algorithm by comparing a counter 452 with a corresponding value of the randomization parameter of the current wear leveling step event (e.g., one of the randomized T or the randomized TH). More specifically, in each wear leveling step event, the memory device 120 may redefine the randomization parameter and / or store a new value of the randomization parameter in a register (e.g., Figure 4E the threshold register 454 shown in), and / or the memory device 120 may reset the counter 452 to 0. Thus, as indicated by reference numeral 456, the counter 452 may increment as events to be counted occur at the wear leveling pool. For example, in a periodic wear leveling scheme, the event to be counted may be a clock cycle associated with the memory device 120, and for an activity-based wear leveling scheme, the event to be counted may be an access to the wear leveling pool (e.g., a read / write operation associated with the wear leveling pool). In other words, the counter 452 may be associated with either the number of clock cycles associated with the corresponding wear leveling step event or the number of accesses to a portion of the memory (e.g., the wear leveling pool) associated with the corresponding wear leveling step event.

[0061] Using a comparator 458 or similar component, the memory device 120 can compare the counter 452 with the threshold register 454 to see if the corresponding wear leveling step event meets the randomization threshold (e.g., one of T or TH). If so, the memory device can perform operations associated with the wear leveling algorithm (e.g., moving the gap pointer G and / or the start pointer S and other examples), reset the counter 452, and / or generate new randomization parameters (e.g., new T and / or TH) and store the new randomization parameters in the threshold register 454. Aspects associated with generating new randomization parameters are described in more detail below in conjunction with Figure 4F and 4G described in more detail. The memory device 120 can then continue to count events (e.g., clock cycles or accesses to the wear leveling pool) and compare the counter 452 with the new randomization parameters in a similar manner as described above for the next wear leveling step event.

[0062] As Figure 4F shown, in some embodiments, the memory device 120 can be configured to determine the randomization parameters by using a pseudo-random vector generator (PRVG), e.g., a PRVG based on an identifier (ID) associated with the memory device 120 (e.g., the unique device ID of the memory device 120). For example, as indicated by reference numeral 460, in some embodiments, the initial value of the PRVG 464 (sometimes referred to as the seed of the PRVG) can be derived from the unique device ID 462 of the memory device 120, e.g., by using a concatenation of a finite field and / or Galois field associated with the unique device ID 462 as the initial value of the PRVG 464. In such embodiments, the next content of the PRVG (e.g., the value of the PRVG for a subsequent wear leveling step event) can then be obtained by the memory device 120 triggering an update of the PRVG. In some other embodiments, the initial value of the PRVG 464 can be determined using a certain function based on the unique device ID 462. For example, in the embodiment shown by reference numeral 466, the initial value of the PRVG 464 can be derived by adding certain values and / or fields of the unique device ID 462 and concatenating the result to obtain the initial value of the PRVG 464.

[0063] Figure 4GAn example of how the PRVG can be used to determine randomization parameters for a wear leveling scheme is shown, such as the randomization time threshold (e.g., T) for a periodic wear leveling scheme and / or the activity threshold (e.g., TH) for an activity-based wear leveling scheme. In some embodiments and as indicated by reference numeral 470, the PRVG is capable of generating a value associated with n bits, which can be used to determine a randomization parameter whose average value is associated with N bits. In such embodiments and as indicated by reference numeral 480, the memory device 120 can determine the randomization parameter in each wear leveling step event by adding the value generated by the PRVG to the minimum value associated with the randomization parameter (e.g., the minimum value of T or TH), such that the resulting randomization parameter falls between the minimum value associated with the randomization parameter (e.g., when the result of the PRVG is 0) and the maximum value associated with the randomization parameter (e.g., equal to the minimum value of the randomization parameter plus 2 n values). In other words, in embodiments where the PRVG generates a value with n bits and the average value of the randomization parameter (e.g., the average value of T and / or TH) has N bits, the randomization parameter can be determined in each wear leveling step event by adding the value generated by the PRVG to the average value of the randomization parameter minus 2 n-1 added (e.g., 111…1, where the number of 1s is equal to n - 1).

[0064] As indicated above, Figures 4A - 4G is for illustration only. Other examples may be different from what is described with respect to Figures 4A - 4G what is described.

[0065] Figure 5 is a flowchart of an example method 500 associated with a wear leveling scheme based on randomization parameters. In some embodiments, a memory device (e.g., memory device 120) can execute or can be configured to execute method 500. In some embodiments, another device or a group of devices separate from or including the memory device (e.g., system 100) can execute or can be configured to execute method 500. Additionally or alternatively, one or more components of the memory device (e.g., controller 130, memory management component 225, wear leveling component 230, and / or write component 235) can execute or can be configured to execute method 500. Thus, the means for performing method 500 can include the memory device and / or one or more components of the memory device. Additionally or alternatively, a non-transitory computer-readable medium can store one or more instructions that, when executed by a memory device (e.g., controller 130 of memory device 120), cause the memory device to execute method 500.

[0066] As Figure 5As shown in Figure 500, the method 500 may include receiving a write command from a host device indicating that the memory device writes host data to a portion of the memory associated with a logical address (block 510). For example, the controller 130 and / or the write component 235 may receive a write command from the host device indicating that the memory device writes host data to a portion of the memory associated with a logical address. As Figure 5 Further shown in Figure 500, the method 500 may include determining a physical location of the memory associated with the logical address by using an wear-leveling algorithm to map the logical address to the physical location of the memory, where the portion of the memory is associated with an wear-leveling pool, and where the wear-leveling algorithm maps the logical address to a portion of the wear-leveling pool based on a randomization parameter (block 520). For example, the controller 130 and / or the wear-leveling component 230 may determine a physical location of the memory associated with the logical address by using an wear-leveling algorithm to map the logical address to the physical location of the memory. As Figure 5 Further shown in Figure 500, the method 500 may include writing the host data to the physical location of the memory (block 530). For example, the controller 130 and / or the write component 235 may write the host data to the physical location of the memory.

[0067] The method 500 may include additional aspects, such as any individual aspect or any combination of aspects described below and / or in combination with one or more other methods or operations described elsewhere herein.

[0068] In a first aspect, the wear-leveling algorithm is associated with a periodic wear-leveling scheme, the periodic wear-leveling scheme is associated with a wear-leveling step event that is executed after a time threshold is met, and the randomization parameter is the time threshold.

[0069] In a second aspect, either alone or in combination with the first aspect, the wear-leveling algorithm is associated with an activity-based wear-leveling scheme, the activity-based wear-leveling scheme is associated with a wear-leveling step event that is executed after an activity threshold is met, and the randomization parameter is the activity threshold.

[0070] In a third aspect, either alone or in combination with one or more of the first and second aspects, the wear-leveling algorithm is associated with a plurality of wear-leveling step events and a plurality of examples of the randomization parameter, where each wear-leveling step event in the plurality of wear-leveling step events is associated with a corresponding example of the randomization parameter in the plurality of examples of the randomization parameter, and the plurality of examples of the randomization parameter are symmetrically distributed around an average value of the plurality of examples of the randomization parameter.

[0071] In a fourth aspect, either alone or in combination with one or more of the first through third aspects, multiple examples of the randomization parameter are symmetrically distributed about the mean of the multiple examples of the randomization parameter based on one of a uniform distribution, a triangular distribution, an inverse triangular distribution, or a Gaussian distribution.

[0072] In a fifth aspect, either alone or in combination with one or more of the first through fourth aspects, a wear leveling algorithm is associated with multiple wear leveling step events, and method 500 includes determining whether to move from a first wear leveling step event among the multiple wear leveling step events to a second wear leveling step event among the multiple wear leveling step events by comparing a counter with the randomization parameter. For example, controller 130 and / or wear leveling component 230 may determine whether to move from a first wear leveling step event among the multiple wear leveling step events to a second wear leveling step event among the multiple wear leveling step events by comparing a counter with the randomization parameter.

[0073] In a sixth aspect, either alone or in combination with one or more of the first through fifth aspects, the counter is associated with either the number of clock cycles associated with a wear leveling step event among the multiple wear leveling step events or the number of accesses to a portion of the memory associated with the wear leveling step event.

[0074] In a seventh aspect, either alone or in combination with one or more of the first through sixth aspects, method 500 includes determining the randomization parameter by using a pseudo-random vector generator based on an identifier associated with the memory device. For example, controller 130 and / or wear leveling component 230 may determine the randomization parameter by using a pseudo-random vector generator based on an identifier associated with the memory device.

[0075] In an eighth aspect, either alone or in combination with one or more of the first through seventh aspects, determining the randomization parameter by using a pseudo-random vector generator includes determining the randomization parameter based on adding a value generated by the pseudo-random vector generator to a minimum value associated with the randomization parameter.

[0076] Although Figure 5 example blocks of method 500 are shown, in some embodiments, method 500 may include additional blocks, fewer blocks, different blocks, or a different arrangement of blocks compared to the Figure 5 blocks depicted therein. Additionally or alternatively, two or more of the blocks of method 500 may be executed in parallel. Method 500 is an example of one method executable by one or more of the devices described herein. The one or more devices may execute or may be configured to execute one or more other methods based on the operations described herein.

[0077] In some embodiments, a memory device includes one or more components configured to: receive, from a host device, a write command indicating that the memory device is to write host data to a portion of memory associated with a logical address; determine a physical location of the memory associated with the logical address to map the logical address to the physical location of the memory by using a wear leveling algorithm, wherein the wear leveling algorithm is based on a randomization parameter; and write the host data to the physical location of the memory.

[0078] In some embodiments, a method includes: receiving, by a memory device and from a host device, a write command indicating that the memory device is to write host data to a portion of memory associated with a logical address; determining, by the memory device, a physical location of the memory associated with the logical address to map the logical address to the physical location of the memory by using a wear leveling algorithm, wherein the portion of the memory is associated with a wear leveling pool, and wherein the wear leveling algorithm maps the logical address to a portion of the wear leveling pool based on a randomization parameter; and writing, by the memory device, the host data to the physical location of the memory.

[0079] In some embodiments, a non-transitory computer-readable medium storing a set of instructions includes one or more instructions that, when executed by one or more processors of a memory device, cause the memory device to: receive, from a host device, a write command indicating that the memory device is to write host data to a portion of memory associated with a logical address; determine a physical location of the memory associated with the logical address to map the logical address to the physical location of the memory by using a wear leveling algorithm, wherein the wear leveling algorithm is associated with one of a periodic wear leveling scheme based on a time threshold or an activity-based wear leveling scheme based on an activity threshold, and wherein the wear leveling algorithm randomizes one of the time threshold or the activity threshold; and write the host data to the physical location of the memory.

[0080] The foregoing disclosure provides illustration and description, but is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. Modifications and variations may be made in light of the above disclosure or may be acquired from practice of the embodiments described herein.

[0081] As used herein, depending on the context, "meeting a threshold" may refer to a value being greater than a threshold, greater than or equal to a threshold, less than a threshold, less than or equal to a threshold, equal to a threshold, not equal to a threshold, or the like.

[0082] Even though particular combinations of features are recited in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of the embodiments described herein. Many of these features may be combined in ways not expressly recited in the claims and / or not expressly disclosed in the specification. For example, the present disclosure includes each dependent claim in a claim set in combination with every other individual claim in the claim set and every combination of multiple claims in the claim set. As used herein, a phrase referring to "at least one" of a list of items refers to any combination of the items, including a single member. As an example, "at least one of a, b, or c" is intended to cover a, b, c, a + b, a + c, b + c, and a + b + c, as well as any combination with multiple identical elements (e.g., a + a, a + a + a, a + a + b, a + a + c, a + b + b, a + c + c, b + b, b + b + b, b + b + c, c + c, and c + c + c or any other ordering of a, b, and c).

[0083] When "a component" or "one or more components" (or another element, such as "a controller" or "one or more controllers") is described or claimed (within a single claim or across multiple claims) as performing multiple operations or being configured to perform multiple operations, such language is intended to broadly cover various architectures and environments. For example, unless otherwise expressly claimed (e.g., by using "a first component" and "a second component" or other language that differentiates components in the claims), such language is intended to cover a single component performing or being configured to perform all operations, a group of components jointly performing or being configured to perform all operations, a first component performing or being configured to perform a first operation and a second component performing or being configured to perform a second operation, or any combination of components performing or being configured to perform the operations. For example, when a claim has the form "one or more components are configured to: perform X; perform Y; and perform Z," the claim should be interpreted to mean "one or more components are configured to perform X; one or more (possibly different) components are configured to perform Y; and one or more (also possibly different) components are configured to perform Z."

[0084] None of the components, acts, or instructions used herein should be construed as critical or essential unless expressly described as such. Also, as used herein, the article "a" is intended to include one or more items and may be used interchangeably with "one or more." Further, as used herein, the article "the" is intended to include one or more items referred to in conjunction with the article "the" and may be used interchangeably with "the one or more." When only one item is desired, the phrase "only one," "single," or similar language is used. Also, as used herein, the term "having" or the like is intended to be an open-ended term with respect to the component it modifies (e.g., a component "having" A may also have B). Further, unless expressly stated otherwise, the phrase "based on" is intended to mean "at least partially based on." As used herein, the term "multiple" may be replaced with "a plurality of," and vice versa. Also, as used herein, unless expressly stated otherwise (e.g., if used in combination with "either... of" or "only one of..."), the term "or" when used in a series is intended to be inclusive and may be used interchangeably with "and / or."

Claims

1. A memory device, comprising: One or more components configured to: Receive a write command from a host device indicating that the memory device is to write host data to a portion of the memory associated with a logical address; Determine a physical location of the memory associated with the logical address to map the logical address to the physical location of the memory by using an wear-leveling algorithm, wherein the wear-leveling algorithm is based on a randomization parameter; And Write the host data to the physical location of the memory.

2. The memory device according to claim 1, wherein the wear-leveling algorithm is associated with a periodic wear-leveling scheme, Wherein the periodic wear-leveling scheme is associated with a wear-leveling step event that is executed after a time threshold is met, and Wherein the randomization parameter is the time threshold.

3. The memory device according to claim 1, wherein the wear-leveling algorithm is associated with an activity-based wear-leveling scheme, Wherein the activity-based wear-leveling scheme is associated with a wear-leveling step event that is executed after an activity threshold is met, and Wherein the randomization parameter is the activity threshold.

4. The memory device according to claim 1, wherein the wear-leveling algorithm is associated with a plurality of wear-leveling step events and a plurality of examples of the randomization parameter, wherein each wear-leveling step event among the plurality of wear-leveling step events is associated with a corresponding example of the randomization parameter among the plurality of examples of the randomization parameter, and Wherein the plurality of examples of the randomization parameter are symmetrically distributed about an average of the plurality of examples of the randomization parameter.

5. The memory device according to claim 4, wherein the plurality of examples of the randomization parameter are symmetrically distributed about the average of the plurality of examples of the randomization parameter based on one of the following: Uniform distribution, Triangular distribution, Inverse triangular distribution, or Gaussian distribution.

6. The memory device according to claim 1, wherein the wear-leveling algorithm is associated with a plurality of wear-leveling step events, and Wherein the one or more components are further configured to determine whether to move from a first wear-leveling step event among the plurality of wear-leveling step events to a second wear-leveling step event among the plurality of wear-leveling step events by comparing a counter with the randomization parameter.

7. The memory device according to claim 6, wherein the counter is associated with either the number of clock cycles associated with a wear-leveling step event among the plurality of wear-leveling step events or the number of accesses to the portion of the memory associated with the wear-leveling step event.

8. The memory device according to claim 1, wherein the one or more components are further configured to determine the randomization parameter by using a pseudo-random vector generator based on an identifier associated with the memory device.

9. The memory device according to claim 8, wherein, in order to determine the randomization parameter by using the pseudo-random vector generator, the one or more components are configured to determine the randomization parameter based on adding a value generated by the pseudo-random vector generator to a minimum value associated with the randomization parameter.

10. A method, comprising: receiving, by a memory device and from a host device, a write command instructing the memory device to write host data to a portion of a memory associated with a logical address; determining, by the memory device, a physical location of the memory associated with the logical address to map the logical address to the physical location of the memory by using a wear leveling algorithm, wherein the portion of the memory is associated with a wear leveling pool, and wherein the wear leveling algorithm maps the logical address to a portion of the wear leveling pool based on a randomization parameter; and writing, by the memory device, the host data to the physical location of the memory.

11. The method according to claim 10, wherein the wear leveling algorithm is associated with a periodic wear leveling scheme, wherein the periodic wear leveling scheme is associated with a wear leveling step event executed after a time threshold is met, and wherein the randomization parameter is the time threshold.

12. The method according to claim 10, wherein the wear leveling algorithm is associated with an activity-based wear leveling scheme, wherein the activity-based wear leveling scheme is associated with a wear leveling step event executed after an activity threshold is met, and wherein the randomization parameter is the activity threshold.

13. The method according to claim 10, wherein the wear leveling algorithm is associated with a plurality of wear leveling step events and a plurality of examples of the randomization parameter, wherein each wear leveling step event in the plurality of wear leveling step events is associated with a corresponding example of the randomization parameter in the plurality of examples of the randomization parameter, and wherein the plurality of examples of the randomization parameter are symmetrically distributed about an average value of the plurality of examples of the randomization parameter.

14. The method according to claim 13, wherein the plurality of examples of the randomization parameter are symmetrically distributed about the average value of the plurality of examples of the randomization parameter based on one of the following: a uniform distribution, a triangular distribution, an inverse triangular distribution, or a Gaussian distribution.

15. The method according to claim 10, wherein the wear leveling algorithm is associated with a plurality of wear leveling step events, further comprising determining whether to move from a first wear leveling step event in the plurality of wear leveling step events to a second wear leveling step event in the plurality of wear leveling step events by comparing a counter with the randomization parameter.

16. The method according to claim 15, wherein the counter is associated with either a number of clock cycles associated with a wear leveling step event in the plurality of wear leveling step events or a number of accesses to the portion of the memory associated with the wear leveling step event.

17. The method according to claim 10, further comprising determining the randomization parameter by using a pseudo-random vector generator based on an identifier associated with the memory device.

18. The method according to claim 17, wherein determining the randomization parameter by using the pseudo-random vector generator includes determining the randomization parameter based on adding a value generated by the pseudo-random vector generator to a minimum value associated with the randomization parameter.

19. A non-transitory computer-readable medium storing a set of instructions, the set of instructions including: one or more instructions that, when executed by one or more processors of a memory device, cause the memory device to: receive, from a host device, a write command indicating that the memory device is to write host data to a portion of a memory associated with a logical address; determine a physical location of the memory associated with the logical address to map the logical address to the physical location of the memory by using a wear leveling algorithm, wherein the wear leveling algorithm is associated with one of a periodic wear leveling scheme based on a time threshold or an activity-based wear leveling scheme based on an activity threshold, and wherein the wear leveling algorithm randomizes one of the time threshold or the activity threshold; and write the host data to the physical location of the memory.

20. The non-transitory computer-readable medium according to claim 19, wherein the wear leveling algorithm is associated with a plurality of wear leveling step events and a plurality of examples of one of the time threshold or the activity threshold, wherein each wear leveling step event of the plurality of wear leveling step events is associated with a corresponding example of one of the time threshold or the activity threshold of the plurality of examples of one of the time threshold or the activity threshold, and wherein the plurality of examples of one of the time threshold or the activity threshold are symmetrically distributed about an average value of the plurality of examples of one of the time threshold or the activity threshold.

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