Detection and correction device and method based on RISC-V architecture

Abstract

The invention discloses a detection and correction device and method based on an RISC-V architecture, belongs to the technical field of processor micro-architectures, and aims to solve the technical problem of how to carry out error detection and correction on an instruction execution process, hardware resources, system reliability, instruction storage, a data path and related system performance in the RISC-V architecture. Comprising a computing core, a cross validation module, a dynamic voting module, a lock step execution module and a hardware multiplexing module, the processor is used for comparing and checking the instruction execution results output by the three calculation cores based on a triple modular redundancy technology and a dynamic voting fault-tolerant technology, and determining the instruction execution result with correct voting through a two-out-of-three voting mode; the lock step execution module is used for controlling lock step execution and assembly line rollback operation of the calculation core; and the hardware multiplexing module is used for multiplexing the same RISC-V pipeline to process normal execution, lock step and rollback operations.

Description

Technical Field

[0001] The present invention relates to the technical field of processor microarchitecture, and more specifically to a detection and correction device and method based on the RISC-V architecture. Background Art

[0002] With the wide application of electronic systems in key fields such as aerospace and nuclear energy, the reliability of processors has become a core requirement.

[0003] Transient faults such as single-event upsets may cause data errors. Traditional fault-tolerant technologies (such as triple modular redundancy and Hamming codes) have problems such as large hardware overhead, limited error correction ability, architectural redundancy, and low recovery efficiency.

[0004] How to detect and correct errors in the instruction execution process, hardware resources, system reliability, instruction storage and data path, and related system performance in the RISC-V architecture is a technical problem that needs to be solved. Summary of the Invention

[0005] The technical task of the present invention is to address the above deficiencies and provide a detection and correction device and method based on the RISC-V architecture to solve the technical problem of how to detect and correct errors in the instruction execution process, hardware resources, system reliability, instruction storage and data path, and related system performance in the RISC-V architecture.

[0006] In a first aspect, a detection and correction device based on the RISC-V architecture according to the present invention includes a computing core, a cross-verification module, a dynamic voting module, a lock-step execution module, and a hardware reuse module;

[0007] There are a total of three computing cores. Each computing core includes an instruction memory, a recovery register, and an ALU + data path. The instruction register is used to obtain instructions in the RISC-V pipeline and store the instructions. A single-error correction and double-error detection algorithm is integrated in the RISC-V pipeline. By extending the 39-bit encoding and adding redundant bits, the detection and correction of single-bit errors and the detection of double-bit errors are achieved. The recovery register is used to store the status information of the computing core in the lock-step stage. The ALU + data path is used to execute instructions and process data. The three computing cores are used to execute the same instructions in parallel in the same order and output the instruction execution results;

[0008] The cross-verification module and the dynamic voting module cooperate to compare and verify the instruction execution results output by the three computing cores based on the triple modular redundancy technology and the dynamic voting fault-tolerant technology, and determine the correctly voted instruction execution results through a two-out-of-three voting method;

[0009] The lock-step execution module is used to control the lock-step execution and pipeline rollback operations of the computing cores. Among them, in the lock-step phase, the lock-step execution module is used to control three computing cores to execute instructions synchronously. At the same time, the core state without errors is written into the recovery register. In the rollback phase, if multi-core faults are detected in the three computing cores, the lock-step execution module is used to read the most recent correct state from the recovery register, restore the most recent correct state to the computing cores, and re-execute the instructions;

[0010] The hardware multiplexing module is used to multiplex the same RISC-V pipeline to process normal execution, lock-step, and rollback operations. The data source is switched through a multiplexer, and predefined read and write instructions are used to simulate the recovery process. The data sources include memory and the recovery register.

[0011] Preferably, for the single error correction and double error detection algorithm integrated in the RISC-V pipeline, it is used to implement single error correction and double error detection through the following operations:

[0012] Encode and expand the RISC-V instructions and data, expanding to a 39-bit encoding. In the 39-bit encoding, D0-D31 are 32 data bits, and P1-P7 are parity bits;

[0013] Among the 7 parity bits, P1-P6 are based on the Hamming code rules and cover the parity checks of specific data bits. Among them, P1 covers D0, D1, D3, D4, D6, D8, D10, D11, D13, D15, D17, D19, D21, D23, D25, D27, D29, D31, P2 covers D0, D2, D3, D5, D6, D9, D10, D12, D13, D16, D17, D20, D21, D24, D25, D28, and D29, and P3-P6 are recursively calculated according to similar rules to cover the remaining data bits;

[0014] Among the 7 parity bits, P7 is the global parity bit, covering all data bits D0-D31 and parity bits P1-P6;

[0015] The parity bit calculation logic is implemented using an exclusive-or tree, that is, P1 = D0^D1^D3^D4^D6^...^D31, P7 = D0^D1^D2^……^D31^P1^P2^...^P6;

[0016] The receiving end recalculates P1'-P7' and generates 7-bit syndrome bits S1-S7 by exclusive-oring with the original parity bits. That is, S1 = P1^P1', S2 = P2^P2'……S7 = P7^P7';

[0017] For single error correction implementation, if S7 = 0 and S1-S6 are not all 0, the error location is the data bit or parity bit corresponding to the binary value of S1-S6;

[0018] Double error detection implementation. If S7 = 1, it is marked as an uncorrectable error and the pipeline rollback is triggered.

[0019] Preferably, the cross - verification module and the dynamic voting module cooperate to perform the following operations:

[0020] Three computing cores share the same clock source, and the bus arbiter ensures that the three computing cores receive the same instruction stream and input data;

[0021] At the end of each instruction execution cycle, the cross - verification module compares and verifies the instruction execution results of the three computing cores. If the analysis and comparison results are inconsistent, the dynamic voting module votes according to the two - out - of - three rule. At the same time, the faulty computing core is identified through the analysis and comparison results.

[0022] Preferably, when the cross - verification module compares and verifies the instruction execution results of the three computing cores, the signals for comparison include the output results of the ALU + data path, the read and write values of the register file, the program counter, the memory address, and the branch prediction results. If the output results of the three computing cores are inconsistent, the dynamic voting module votes according to the two - out - of - three rule and identifies the faulty computing core according to the analysis and comparison results. If the output results of the three computing cores are consistent, the dynamic voting module determines that the data is valid. If the output of a single computing core is abnormal, the computing core is marked as a faulty core. If the output results of the three computing cores are all inconsistent, the pipeline rollback is triggered. When a single - core fault is detected, a reset signal is sent to the faulty computing core to make the faulty computing core reload the state from the recovery register.

[0023] Preferably, the lock - step execution module is used to perform the following lock - step execution and pipeline rollback operations:

[0024] Lock - step execution implementation: When the dynamic voting module detects a single - core fault in a computing core, a dedicated instruction is triggered to save the normal context, and the values of the general registers, the value of the program counter, and the pipeline stage flag of the normal computing cores are written into the recovery register;

[0025] Pipeline rollback implementation: Read the PC value from the recovery register, reload the faulty instruction stream from the instruction memory, and switch the input source of the ALU + data path from the memory to the recovery register through a multiplexer; A flush signal is generated during rollback to clear all uncommitted instructions in the pipeline. In the next clock cycle, re - fetch instructions starting from the recovered PC value to ensure the continuity of the instruction stream.

[0026] Preferably, the hardware multiplexing module is used to implement hardware multiplexing as follows: a multiplexer is used to switch data sources. During the normal execution phase, the multiplexer connects the data source to the memory, and the computing core reads instructions and data from the memory for execution; during the lockstep phase, the multiplexer can still be connected to the memory, and at the same time, the core state is written to the recovery register; during the rollback phase, the multiplexer switches the data source to the recovery register, and the computing core reads the status information from the recovery register for recovery; the recovery process is simulated through predefined read and write instructions, and the predefined read and write instructions can trigger corresponding control signals, causing the multiplexer to switch to the correct data source and controlling the read and write operations of the data.

[0027] Preferably, the hardware multiplexing module is used to support the following operations: the same set of ALU + data path and register file are multiplexed during the normal execution, lockstep, and rollback phases. Time-division multiplexing is used to avoid redundant hardware. In the error-free state, the clock signals of redundant computing cores are turned off to reduce power consumption, and only one core remains active.

[0028] In a second aspect, a detection and correction method based on the RISC-V architecture according to the present invention is optimized for error detection and correction through a detection and correction device based on the RISC-V architecture as described in any item of the first aspect, so as to optimize the instruction execution process, hardware resources, system reliability, instruction storage, data path, and related system performance in the RISC-V architecture.

[0029] The detection and correction device and method based on the RISC-V architecture of the present invention have the following advantages: high reliability and low resource consumption are achieved through hardware multiplexing and instruction simulation. Description of the Drawings

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0031] The present invention will be further described below with reference to the drawings.

[0032] Figure 1 It is a structural block diagram of a detection and correction device based on the RISC-V architecture for Embodiment 1;

[0033] Figure 2 It is a schematic diagram of the error detection and correction process of a detection and correction device based on the RISC-V architecture for Embodiment 1. Detailed Embodiment

[0034] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, so that those skilled in the art can better understand the present invention and be able to implement it. However, the specific embodiments cited are not intended to limit the present invention. Without conflict, the embodiments of the present invention and the technical features in the embodiments can be combined with each other.

[0035] The embodiment of the present invention provides a detection and correction device and method based on the RISC-V architecture, which is used to solve the technical problem of how to detect and correct errors in the instruction execution process, hardware resources, system reliability, instruction storage, data path, and related system performance in the RISC-V architecture.

[0036] Embodiment 1:

[0037] A detection and correction device based on the RISC-V architecture of the present invention includes a computing core, a cross-verification module, a dynamic voting module, a lock-step execution module, and a hardware reuse module.

[0038] There are three computing cores in total. Each computing core includes an instruction memory, a recovery register, and an ALU + data path. The instruction register is used to obtain instructions in the RISC-V pipeline and store the instructions. A single-error correction and double-error detection algorithm is integrated in the RISC-V pipeline. By extending the 39-bit encoding and adding redundant bits, the detection and correction of single-bit errors and the detection of double-bit errors are realized. The recovery register is used to store the status information of the computing core in the lock-step stage. The ALU + data path is used to execute instructions and process data. The three computing cores are used to execute the same instructions in parallel in the same order and output the instruction execution results.

[0039] In this embodiment, for the single-error correction and double-error detection algorithm integrated in the RISC-V pipeline, the single-error correction and double-error detection are realized through the following operations:

[0040] (1) Encoding and expanding the RISC-V instructions and data, expanding to 39-bit encoding. In the 39-bit encoding, D0 - D31 are 32 data bits, and P1 - P7 are parity bits;

[0041] (2) Among the 7 parity bits, P1 - P6 are based on the Hamming code rule and cover the parity check of specific data bits. Among them, P1 covers D0, D1, D3, D4, D6, D8, D10, D11, D13, D15, D17, D19, D21, D23, D25, D27, D29, D31, P2 covers D0, D2, D3, D5, D6, D9, D10, D12, D13, D16, D17, D20, D21, D24, D25, D28, and D29, and P3 - P6 are recursively calculated according to a similar rule to cover the remaining data bits;

[0042] (3) Among the 7 parity bits, P7 is the global parity bit, covering all data bits D0 - D31 and parity bits P1 - P6;

[0043] (4) The parity bit calculation logic is implemented using an exclusive - or tree, i.e., P1 = D0^D1^D3^D4^D6^...^D31, P7 = D0^D1^D2^……^D31^P1^P2^...^P6;

[0044] (5) At the receiving end, P1' - P7' are recalculated and exclusive - or'd with the original parity bits to generate 7 - bit syndrome S1 - S7. That is, S1 = P1^P1', S2 = P2^P2'……S7 = P7^P7';

[0045] (6) For single - error correction implementation, if S7 = 0 and S1 - S6 are not all 0, the error location is the data bit or parity bit corresponding to the binary value of S1 - S6;

[0046] (7) For double - error detection implementation, if S7 = 1, it is marked as an uncorrectable error and the pipeline rollback is triggered.

[0047] The cross - verification module and the dynamic voting module cooperate to compare and verify the instruction execution results output by the three computing cores based on the triple - modular redundancy technology and the dynamic voting fault - tolerance technology, and determine the correct instruction execution result through a two - out - of - three voting method.

[0048] In this embodiment, the cross - verification module and the dynamic voting module cooperate to perform the following operations:

[0049] (1) The three computing cores share the same clock source, and the bus arbiter is used to ensure that the three computing cores receive the same instruction stream and input data;

[0050] (2) At the end of each instruction execution cycle, the cross - verification module compares and verifies the instruction execution results of the three computing cores. If the analysis and comparison results are inconsistent, the dynamic voting module votes according to the two - out - of - three rule. At the same time, the faulty computing core is identified by analyzing the comparison results.

[0051] Among them, when the cross-check module compares and checks the instruction execution results of the three computing cores, the signals for comparison include the output results of the ALU + data path, the read and write values of the register file, the program counter, the memory address, and the branch prediction result. If the output results of the three computing cores are inconsistent, the dynamic voting module votes according to the two-out-of-three rule and identifies the faulty computing core based on the analysis and comparison results. If the output results of the three computing cores are consistent, the dynamic voting module determines that the data is valid. If the output of a single computing core is abnormal, the computing core is marked as a faulty core. If the output results of the three computing cores are all inconsistent, the pipeline is rolled back. When a single-core fault is detected, a reset signal is sent to the faulty computing core to cause the faulty computing core to reload its state from the recovery register.

[0052] The lockstep execution module is used to control the lockstep execution and pipeline rollback operations of the computing cores. Among them, in the lockstep stage, the lockstep execution module is used to control the three computing cores to execute instructions synchronously. At the same time, the state of the error-free core is written into the recovery register. In the rollback stage, if a multi-core fault is detected in the three computing cores, the lockstep execution module is used to read the most recent correct state from the recovery register and restore the most recent correct state to the computing cores, and then re-execute the instructions.

[0053] In this embodiment, the lockstep execution module is used to perform the following lockstep execution and pipeline rollback operations:

[0054] (1) Lockstep execution implementation: When the dynamic voting module detects a single-core fault of a computing core, a special instruction is triggered to save the normal context. The values of the general registers, the value of the program counter, and the pipeline stage flag of the normal computing core are written into the recovery register;

[0055] (2) Pipeline rollback implementation: Read the PC value from the recovery register, reload the faulty instruction stream from the instruction memory again, and switch the input source of the ALU + data path from the memory to the recovery register through a multiplexer; generate a flush signal during rollback to clear all uncommitted instructions in the pipeline. In the next clock cycle, start fetching instructions again from the restored PC value to ensure the continuity of the instruction stream.

[0056] The hardware multiplexing module is used to multiplex the same RISC-V pipeline to process normal execution, lockstep, and rollback operations. The data source is switched through a multiplexer, and predefined read and write instructions are used to simulate the recovery process. The data sources include the memory and the recovery register.

[0057] In this embodiment, the hardware reuse module is used to implement hardware reuse as follows: A multiplexer is used to switch data sources. During the normal execution phase, the multiplexer connects the data source to the memory, and the computing core reads instructions and data from the memory for execution. During the lockstep phase, the multiplexer can still be connected to the memory while writing the core state to the recovery register. During the rollback phase, the multiplexer switches the data source to the recovery register, and the computing core reads the status information from the recovery register for recovery. The recovery process is simulated through predefined read and write instructions, which can trigger corresponding control signals to make the multiplexer switch to the correct data source and control the read and write operations of data.

[0058] For the hardware reuse in this embodiment, the data selection signal is controlled by the voting status code, selecting the memory data bus in the normal mode and the recovery register data bus in the rollback mode. The instruction stream switching signal switches to the pre-stored recovery instruction sequence during rollback. The same set of ALU and register file is reused in the normal execution, lockstep, and rollback phases, and time-division multiplexing is used to avoid redundant hardware. In the error-free state, the clock signals of redundant cores are turned off to reduce power consumption, and only one core remains active.

[0059] The device in this embodiment integrates a single error correction and double error detection algorithm in the RISC-V pipeline, extends the 39-bit encoding, and detects and corrects single-bit errors and detects double-bit errors by adding redundant bits.

[0060] The triple modular redundancy and dynamic voting fault tolerance technology are adopted. Three computing cores execute the same instructions in parallel in the same order, compare the output results of the three computing cores, and take two out of three, with the majority of the same outputs as the correct output of the voting system. Since the three computing cores are independent of each other and compare the outputs in real time to identify the faulty core, the probability of two computing cores having errors simultaneously is extremely low, so the credibility of the system can be greatly improved.

[0061] The sampling lockstep execution and pipeline rollback technologies are adopted. During the lockstep phase, the core state without errors is written to the recovery register. During the rollback phase, if there are multi-core faults, roll back to the nearest correct state from the recovery register and re-execute the instructions.

[0062] The hardware reuse technology is adopted. The same pipeline is reused to process normal execution, lockstep, and rollback operations, and the data source (memory / recovery register) is switched through a multiplexer. The predefined read and write instructions simulate the recovery process, reducing the additional hardware overhead.

[0063] Embodiment 2:

[0064] A detection and correction method based on the RISC-V architecture according to the present invention optimizes error detection and correction through the device disclosed in Embodiment 1, so as to optimize the instruction execution process, hardware resources, system reliability, instruction storage, data path, and related system performance in the RISC-V architecture.

[0065] The above has introduced in detail the detection and correction device and method based on the RISC-V architecture provided by the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A detection and correction device based on the RISC-V architecture, characterized in that, It includes a computing core, a cross-validation module, a dynamic voting module, a lock-step execution module, and a hardware multiplexing module; There are three computing cores in total. Each computing core includes an instruction memory, a recovery register, and an ALU + data path. The instruction register is used to obtain instructions in the RISC-V pipeline and store the instructions. The single-error correction and double-error detection algorithm is integrated in the RISC-V pipeline. By extending the 39-bit encoding and adding redundant bits, it realizes the detection and correction of single-bit errors and the detection of double-bit errors. The recovery register is used to store the status information of the computing core in the lock-step stage. The ALU + data path is used to execute instructions and process data. The three computing cores are used to execute the same instructions in parallel in the same order and output the instruction execution results; The cross-validation module and the dynamic voting module cooperate to compare and verify the instruction execution results output by the three computing cores based on the triple modular redundancy technology and the dynamic voting fault tolerance technology, and determine the correctly voted instruction execution results by a two-out-of-three voting method; The lock-step execution module is used to control the lock-step execution and pipeline rollback operations of the computing core. Among them, in the lock-step stage, the lock-step execution module is used to control the three computing cores to execute instructions synchronously. At the same time, it writes the core state without errors into the recovery register. In the rollback stage, if it is detected that there are multi-core faults in the three computing cores, the lock-step execution module is used to read the most recent correct state from the recovery register, restore the most recent correct state to the computing core, and re-execute the instructions; The hardware multiplexing module is used to multiplex the same RISC-V pipeline to process normal execution, lock-step, and rollback operations. It switches the data source through a multiplexer and predefines read and write instructions to simulate the recovery process. The data sources include memory and the recovery register.

2. The detection and correction device based on the RISC-V architecture according to claim 1, wherein For the single-error correction and double-error detection algorithm integrated in the RISC-V pipeline, it realizes single-error correction and double-error detection through the following operations: Encode and extend the RISC-V instructions and data, extend the 39-bit encoding. In the 39-bit encoding, D0 - D31 are 32 data bits, and P1 - P7 are parity bits; Among the 7 parity bits, P1 - P6 are based on the Hamming code rule and cover the parity check of specific data bits. Among them, P1 covers D0, D1, D3, D4, D6, D8, D10, D11, D13, D15, D17, D19, D21, D23, D25, D27, D29, D31, P2 covers D0, D2, D3, D5, D6, D9, D10, D12, D13, D16, D17, D20, D21, D24, D25, D28, and D29, and P3 - P6 are recursively calculated according to a similar rule to cover the remaining data bits; Among the 7 parity bits, P7 is the global parity bit, covering all data bits D0 - D31 and parity bits P1 - P6; The parity bit calculation logic is implemented by an exclusive-OR tree, that is, P1 = D0 ^ D1 ^ D3 ^ D4 ^ D6 ^... ^ D31, P7 = D0 ^ D1 ^ D2 ^ …… ^ D31 ^ P1 ^ P2 ^... ^ P6; The receiver recalculates P1'-P7' and XORs them with the original parity bits to generate 7-bit syndrome S1-S7. That is, S1 = P1^P1', S2 = P2^P2'... S7 = P7^P7'; For single error correction implementation, if S7 = 0 and S1-S6 are not all 0, the error location is the data bit or parity bit corresponding to the binary value of S1-S6; For double error detection implementation, if S7 = 1, it is marked as an uncorrectable error and the pipeline rollback is triggered.

3. The detection and correction device based on the RISC-V architecture according to claim 1 or 2, characterized in that The cross-verification module and the dynamic voting module cooperate to perform the following operations: The three computing cores share the same clock source, and the bus arbiter ensures that the three computing cores receive the same instruction stream and input data; At the end of each instruction execution cycle, the cross-verification module compares and verifies the instruction execution results of the three computing cores. If the analysis and comparison results are inconsistent, the dynamic voting module votes according to the two-out-of-three rule. At the same time, the faulty computing core is identified through the analysis and comparison results.

4. The detection and correction device based on the RISC-V architecture according to claim 3, wherein When the cross-verification module compares and verifies the instruction execution results of the three computing cores, the signals for comparison include the output results of the ALU + data path, the read and write values of the register file, the program counter, the memory address, and the branch prediction results. If the output results of the three computing cores are inconsistent, the dynamic voting module votes according to the two-out-of-three rule and identifies the faulty computing core based on the analysis and comparison results. If the output results of the three computing cores are consistent, the dynamic voting module determines that the data is valid. If the output of a single computing core is abnormal, the computing core is marked as a faulty core. If the output results of the three computing cores are all inconsistent, the pipeline rollback is triggered. When a single-core fault is detected, a reset signal is sent to the faulty computing core to make the faulty computing core reload the state from the recovery register.

5. The detection and correction device based on the RISC-V architecture according to claim 4, characterized in that, The lockstep execution module is used to perform the following lockstep execution and pipeline rollback operations: Lockstep execution implementation: When the dynamic voting module detects a single computing core fault, a special instruction is triggered to save the normal context, and the values of the general registers, the value of the program counter, and the pipeline stage flags of the normal computing core are written into the recovery register; Pipeline rollback implementation: Read the PC value from the recovery register, reload the faulty instruction stream from the instruction memory again, and switch the input source of the ALU + data path from the memory to the recovery register through the multiplexer; A flush signal is generated during rollback to clear all uncommitted instructions in the pipeline. In the next clock cycle, fetch instructions again starting from the recovered PC value to ensure the continuity of the instruction stream.

6. The detection and correction device based on the RISC-V architecture according to claim 4, characterized in that The hardware multiplexing module is used to perform the following hardware multiplexing implementation: The multiplexer is used to switch the data source. During the normal execution stage, the multiplexer connects the data source to the memory, and the computing core reads instructions and data from the memory for execution; During the lockstep stage, the multiplexer can still be connected to the memory, and at the same time, the core state is written into the recovery register; In the rollback stage, the multiplexer switches the data source to the recovery register, and the computing core reads the status information from the recovery register for recovery; the predefined read and write instructions are used to simulate the recovery process, and the predefined read and write instructions can trigger the corresponding control signals, so that the multiplexer switches to the correct data source and controls the read and write operations of the data.

7. The detection and correction device based on the RISC-V architecture according to claim 6, characterized in that, The hardware multiplexing module is used to support the following operations: normal execution, lockstep, and multiplexing the same set of ALU + data path and register file during the rollback stage. Time-division multiplexing is used to avoid redundant hardware. In the error-free state, the clock signals of the redundant computing cores are turned off to reduce power consumption, and only one core remains active.

8. A detection and correction method based on the RISC-V architecture, characterized in that, Error detection and correction optimization are performed through a detection and correction device based on the RISC-V architecture according to any one of claims 1-7, so as to optimize the instruction execution process, hardware resources, system reliability, instruction storage, data path, and related system performance in the RISC-V architecture.

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