Time delay optimization method and device of network interconnection system, electronic equipment and medium

Abstract

The invention discloses a time delay optimization method and device of a network interconnection system, electronic equipment and a medium, and relates to the field of network communication, and the method comprises the steps: adjusting the BAR resource window size of a non-transparent bridge processor in a BIOS based on a firmware file of a target processor, and re-burning the adjusted BIOS to a BMC processor, and initializing each DMA channel in the non-transparent bridge processor to obtain a physical address of each DMA channel, identifying the minimum physical address as a mapping initial address of the BAR, and mapping the mapping initial address and the BAR address space sum to a virtual address space of a user mode so as to access each DMA channel. The problem that the requirements for the overall bandwidth and low delay of the storage controller cannot be met when one DMA channel is started is solved, the data concurrent processing capacity of the non-transparent bridge processor is improved by enabling the four DMA channels and mapping the four DMA channels to the user mode, and therefore the interconnection bandwidth of the controllers is higher, and the interconnection delay of the controllers is lower.

Description

Technical Field

[0001] This application relates to the field of network communication technologies, and particularly to a method, apparatus, electronic device, and medium for optimizing the latency of a network interconnection system. Background Art

[0002] With the continuous upgrade and iteration of the CPU (Central Processing Unit), the performance requirements for the bandwidth, latency, etc. of the interconnection between unified storage controllers are also getting higher and higher. As Figure 1 shown, PCIe (Peripheral Component Interconnect Express) is the main bus communication protocol in a computer system, and NTB (Non-Transparent Bridge) is a special PCIe bridge device that connects two host systems and performs status and data exchange, providing isolation between the memory areas of the remote host and the local host. Therefore, how to improve the bandwidth of the NTB link and reduce the communication link latency in high-performance scenarios needs to be considered and solved.

[0003] In the related art, the NTB interconnection between two host systems is mainly provided based on the following two methods: (1) an on-chip NTB processing unit encapsulated in the CPU; (2) an independent NTB processor, such as the PEX8733 processor, etc.

[0004] However, although the PEX8733 processor supports 4 DMA (Direct Memory Access) channels for data interaction between two host systems, the kernel driver only enables one of the DMA channels during NTB initialization, which may lead to problems of insufficient bandwidth and increased latency in high-performance scenarios and urgently needs to be solved. Summary of the Invention

[0005] This application provides a method, apparatus, electronic device, and medium for optimizing the latency of a network interconnection system, so as to at least solve the problem in the related art that the requirements for the overall bandwidth and low latency of the storage controller cannot be met when only one DMA channel is enabled.

[0006] This application provides a method for optimizing the latency of a network interconnection system, including:

[0007] Determine the target processor firmware file of the non-transparent bridge, adjust the BAR (Base Address Register) resource window size of the non-transparent bridge processor in the BIOS (Basic Input / Output System) based on the target processor firmware file, and re-burn the adjusted BIOS to the BMC (Baseboard Management Controller) processor;

[0008] Initialize each DMA channel in the non-transparent bridge processor to obtain the physical address of each DMA channel, identify the minimum physical address among the physical addresses of each DMA channel, and use the minimum physical address as the mapping start address of the BAR;

[0009] Determine the total sum of the BAR address spaces of all DMA channels in the non-transparent bridge processor, and map the mapping start address of the BAR and the total sum of the BAR address spaces to the virtual address space of the user mode to access each DMA channel through the user mode.

[0010] This application also provides a latency optimization device for a network interconnection system, including:

[0011] An adjustment module, configured to determine the target processor firmware file of the non-transparent bridge, adjust the BAR resource window size of the non-transparent bridge processor in the BIOS based on the target processor firmware file, and re-burn the adjusted BIOS to the BMC processor;

[0012] An identification module, configured to initialize each DMA channel in the non-transparent bridge processor to obtain the physical address of each DMA channel, identify the minimum physical address among the physical addresses of each DMA channel, and use the minimum physical address as the mapping start address of the BAR;

[0013] A mapping module, configured to determine the total sum of the BAR address spaces of all DMA channels in the non-transparent bridge processor, and map the mapping start address of the BAR and the total sum of the BAR address spaces to the virtual address space of the user mode to access each DMA channel through the user mode.

[0014] This application also provides an electronic device, including: a memory, configured to store a computer program; a processor, configured to implement the steps of any one of the above latency optimization methods for a network interconnection system when executing the computer program.

[0015] The present application also provides a computer-readable storage medium storing a computer program, where the computer program, when executed by a processor, implements the steps of any one of the above-mentioned latency optimization methods for a network interconnection system.

[0016] The present application also provides a computer program product including a computer program, where the computer program, when executed by a processor, implements the steps of any one of the above-mentioned latency optimization methods for a network interconnection system.

[0017] Through the present application, since the BAR resource window size of the non-transparent bridge processor in the BIOS is adjusted based on the target processor firmware file, and the adjusted BIOS is reflashed to the BMC processor, each DMA channel in the non-transparent bridge processor is initialized to obtain the physical address of each DMA channel, and the minimum physical address is identified as the mapping start address of the BAR. The mapping start address and the total BAR address space are mapped to the virtual address space in the user state, so as to access each DMA channel, solving the problems such as the requirement of the overall bandwidth and low latency of the storage controller not being met when enabling one DMA channel. By enabling four DMA channels and mapping them to the user state, the data concurrent processing ability of the non-transparent bridge processor is improved, so that the bandwidth of the interconnection between the controllers is higher and the latency is lower. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] To more clearly illustrate the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0019] Figure 1 It is a block diagram of data exchange in the related art;

[0020] Figure 2 It is a flowchart of a latency optimization method for a network interconnection system provided by an embodiment of the present application;

[0021] Figure 3 It is a flowchart of data exchange in a network interconnection system according to an embodiment of the present application;

[0022] Figure 4 It is a block diagram of a latency optimization device for a network interconnection system according to an embodiment of the present application;

[0023] Figure 5 It is a schematic structural diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without making creative efforts belong to the protection scope of the present application.

[0025] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and not to describe a specific order or sequence.

[0026] In order to enable those skilled in the art of the present technology to better understand the solution of the present application, the following will further describe the present application in detail with reference to the accompanying drawings and specific embodiments.

[0027] The embodiments of the present application provide a method for optimizing the delay of a network interconnection system. The method will be described in detail in combination with the execution process of the method for optimizing the delay of the network interconnection system.

[0028] Before introducing the embodiments of the present invention, the specific implementation methods of related technologies will be introduced first, such as Figure 1As shown, PCIe NTB is a technology for implementing direct communication between two independent systems. It allows the CPU of one host system to directly access the memory and peripherals of another host system, thus avoiding protocol conversion and multiple data copies in traditional communication methods. NTB consists of two PCIe devices, each configured in Type0 mode and connected via a bridge. These two Type 0 PCIe devices are called two non-transparent endpoints, and each NTB endpoint has its own independent address domain, which means that there are independent address spaces on both sides of the bridge. There are two ways to provide NTB interconnection between two host systems: one is the on-chip NTB processing unit encapsulated in the CPU, and the other is an independent NTB processor. Among them, NTB is configured with EEPROM (Electrically Erasable Programmable Read-Only Memory) before production and installation, mainly including register definitions, configuration space size, control register size, DMA channel quantity (related to the NTB processor package), etc. After the controller is powered on, the NTB processor initializes according to the configuration information in the EEPROM. Taking the PEX8733 processor as an example, the initialization process of the NTB processor is roughly as follows;

[0029] (1) Processing logic of the PEX8733 processor in the BIOS process: When the storage controller is powered on, the BIOS first scans and enumerates the PCI-E bus, configures the address space of the PCIe device, such as the BAR register address space, resource window allocation range, etc., and NTB automatically performs link detection and negotiation.

[0030] (2) Processing flow of the PEX8733 processor in the kernel driver: When the PEX8733 driver is loaded, it first scans the pci_bus to find devices of the PCI_CLASS_BRIDGE_OTHER type for subsequent initialization. Devices of this type represent PCIe bridge devices, and NTB is a special PCIe bridge device. Initialize the struct pex_device_t structure, including the physical starting address of each BAR register, etc., and finally allocate memory space for different registers. The range of this memory space is defined in the BIOS.

[0031] (3) Application of the PEX8733 processor DMA engine: Mainly initialize the bus number, device number, function number, and physical starting address of the DMA of the DMA engine, which can be expressed as:

[0032]

[0033] (4) Mapping of the DMA engine: Map the physical starting address dma_phys_addr_start of the DMA engine in the processor and the size of the control register to the user space through mmap to provide an interface for user-mode programs to communicate using the DMA engine of the NTB.

[0034] However, the PEX8733 processor hardware package supports a maximum of 4 DMA channels for data interaction between two PCIe host systems. Currently, when the kernel driver initializes the DMA engine, only one DMA channel is initialized and mapped to the user space. In most cases, one DMA channel can meet the performance requirements of the storage controller. However, in business scenarios with high requirements for latency and bandwidth, one DMA channel cannot meet the overall bandwidth and low-latency requirements of the storage controller. Therefore, in high-pressure scenarios, one DMA channel may cause bandwidth and latency problems.

[0035] Therefore, to improve the bandwidth of the PEX8733 processor under high pressure and reduce communication latency, the above solution is optimized by enabling all 4 DMA channels of the PEX8733 processor and mapping them to the user state to improve the data concurrent processing ability of the NTB processor, making the bandwidth between the controllers higher and the latency lower. The specific structure is summarized as follows:

[0036]

[0037] That is to say, it is necessary to define macro definitions related to the DMA channel number and the size of the DMA register in the driver code, and it is necessary to define a PCI device array and a DMA channel address array in the pex_device_t device structure for subsequent user-state traversal.

[0038] The specific implementation steps will be described in detail in the following embodiments.

[0039] Specifically, Figure 2 It is a schematic flowchart of a method for optimizing the latency of a network interconnection system provided by an embodiment of the present invention.

[0040] As Figure 2 shown, the method for optimizing the latency of the network interconnection system includes the following steps:

[0041] In step S201, determine the target processor firmware file of the non-transparent bridge, adjust the size of the BAR resource window of the non-transparent bridge processor in the BIOS based on the target processor firmware file, and rewrite the adjusted BIOS to the BMC processor.

[0042] According to an embodiment of the present application, determining the target processor firmware file of the non-transparent bridge includes: modifying the DMA channel association register of the processor firmware of the non-transparent bridge based on a preset modification strategy, and enabling all DMA channels of the non-transparent bridge after the modification is completed; adjusting the initial BAR address space of the processor firmware of the non-transparent bridge based on all the enabled DMA channels, and obtaining the target BAR address space of the processor firmware of the non-transparent bridge according to the adjusted initial BAR address space; generating a target processor firmware file based on the target BAR address space, and re-burning the target processor firmware file to the target register of the non-transparent bridge.

[0043] Wherein, the preset modification strategy can be set according to actual test requirements, and no specific limitation is made here. In the embodiment of the present application, the preset modification strategy is to modify the processor firmware of the non-transparent bridge.

[0044] Specifically, as Figure 3 shown, to improve the bandwidth of the non-transparent bridge processor (NTB processor) under high pressure and reduce the communication delay, the embodiment of the present application first needs to modify the processor firmware of the non-transparent bridge, mainly to modify the DMA channel association register of the processor firmware of the non-transparent bridge, and after the modification is completed, enable all available DMA channels of the non-transparent bridge through the DMA channel association register. The number of available DMA channels can be obtained by querying the processor manual. For example, the non-transparent bridge processor used in the present application is the PEX8733 processor, which is an integrated circuit and supports 4 DMA channels. That is to say, after the modification is completed, 4 DMA channels of the non-transparent bridge can be enabled through the DMA channel association register.

[0045] Secondly, after enabling the 4 DMA channels of the non-transparent bridge, it is necessary to adjust the initial BAR address space of the processor firmware of the non-transparent bridge, that is, it is necessary to further expand the size of the BAR (remote control register window) to allocate an independent physical address window for each DMA channel to ensure that there is no conflict in the multi-DMA channel address space. For example, if the initial BAR address space of a processor firmware is 16KB, after enabling 4 DMA channels, the initial BAR address space of the processor firmware of the non-transparent bridge is adjusted to 64KB, so as to obtain the target BAR address space of the processor firmware of the non-transparent bridge according to the adjusted initial BAR address space.

[0046] Finally, generate a target processor firmware file based on the adjusted target BAR address space, and re-program the target processor firmware file into the target register of the non-transparent bridge, i.e., the EEPROM of the PEX8733 processor. For example, the modified processor firmware code can be compiled using a tool (such as the PLX SDK (PLX Software Development Kit)) to generate a binary file, and then the target processor firmware file can be re-programmed into the EEPROM of the PEX8733 processor through a programmer or a processor debug interface (such as JTAG (Joint Test Action Group)), and the machine is restarted to make it effective, providing a data basis for the following modification of the BIOS layer.

[0047] Thus, by modifying the processor firmware of the non-transparent bridge, it is possible to enable all DMA channels (e.g., the 4 DMA processors supported by the PEX8733 processor), achieve multi-channel parallel transmission, linear growth of bandwidth (number of channels × single-channel rate), maximize bandwidth utilization, and at the same time, reduce data queuing waiting time, especially in the scenario of small packet high concurrency. In addition, DMA shares the CPU data transfer load, reduces the interrupt frequency, and reduces the latency.

[0048] Furthermore, after adjusting the processor firmware of the non-transparent bridge to obtain a target processor firmware file, to ensure that sufficient PCIe resources are allocated when the host system starts, it is necessary to further modify the BIOS and perform relevant configurations. For example, adjust the BAR resource window size of the non-transparent bridge processor in the BIOS to ensure that hardware resources are fully and effectively utilized, thereby optimizing system performance while maintaining system stability and compatibility.

[0049] Specifically, as Figure 3 shown, first, restart the system and press the specified key during the startup process to enter the BIOS setup interface; second, find the option related to PCIe configuration or NTB in the BIOS setup menu, find the setting item responsible for allocating the BAR resources to the NTB device, and adjust its size according to the previous calculation results. For example, manually expand the BAR to 64KB in the BIOS setup (consistent with the above-mentioned processor firmware modification), which may involve directly entering a new value or selecting a suitable configuration from the preset options; finally, after completing all necessary changes, re-program the adjusted BIOS into the BMC processor, exit the BIOS, and the host system will restart and become effective according to the adjusted BIOS configuration.

[0050] According to an embodiment of the present application, before re - burning the target processor firmware file to the target register of the non - transparent bridge, it further includes: obtaining the digital signature of the target processor firmware file; verifying the digital signature to determine whether the digital signature is consistent with the predefined digital signature; if the digital signature is consistent with the predefined digital signature, then re - burning the target processor firmware file to the target register, otherwise, generating an error log and giving an exception reminder.

[0051] Specifically, before re - burning the target processor firmware file to the target register of the non - transparent bridge, to ensure that the host system can start normally and there are no problems caused by improper BAR resource configuration, it is also necessary to use appropriate tools or applications to test the performance of the NTB device, confirm whether the bandwidth and latency have been improved as expected, and it is also necessary to detect the security of the target processor firmware file. For example, obtain and verify the digital signature of the target processor firmware file, determine whether the digital signature is consistent with the predefined digital signature. If the digital signature is consistent with the predefined digital signature, then re - burn the target processor firmware file to the target register, otherwise, generate an error log and give an exception reminder, and trigger a security interrupt to lock the non - transparent bridge processor.

[0052] Thus, by determining the security of the target processor firmware file, it can be ensured that the firmware has not been tampered with by an unauthorized third party, which is crucial for maintaining the stability and reliability of the system. At the same time, security verification mechanisms (such as digital signatures, hash checks, etc.) help detect and defend against potential firmware attacks, such as firmware injection attacks or rollback attacks, which provide an additional layer of security protection for the hardware, especially important in application scenarios involving sensitive data processing.

[0053] In step S202, each DMA channel in the non - transparent bridge processor is initialized to obtain the physical address of each DMA channel, and the minimum physical address among the physical addresses of each DMA channel is identified, and the minimum physical address is used as the mapping start address of the BAR.

[0054] Specifically, as Figure 3 shown, to give full play to the data - processing ability of the hardware, for the purpose of improving data - transmission efficiency and reducing communication latency, and to ensure the stability and reliability of the host system, the embodiment of the present application also needs to further initialize each DMA channel in the non - transparent bridge processor, thereby improving the concurrency of data processing, which can not only accelerate the data - transmission process, but also more effectively allocate system resources and avoid a single DMA channel becoming a bottleneck.

[0055] According to an embodiment of the present application, initializing each DMA channel in the non-transparent bridge processor includes: initializing the DMA management device in each DMA channel according to each DMA channel in the non-transparent bridge processor.

[0056] According to an embodiment of the present application, initializing the DMA management device in each DMA channel according to each DMA channel in the non-transparent bridge processor includes: obtaining the PCIe device pointer information corresponding to each DMA channel; storing the PCIe device pointer information into the DMA management device of the corresponding DMA channel to initialize the PCIe device pointer information of the DMA management device.

[0057] Specifically, first, confirm the non-transparent bridge processor model through the PCIe device ID and vendor ID, and obtain the number of supported DMA channels (such as 4 channels for PEX8733), and obtain the PCIe device pointer information corresponding to each DMA channel. For example, the pointer of the core data structure used to manage and operate the DMA channel in the kernel driver to provide an access interface to the hardware resources. This pointer information mainly includes the host device identifier (pci_dev->vendor, pci_dev->device), BAR address space, configuration space, etc. Among them, the host device identifier can confirm the non-transparent bridge processor model (such as PEX8733), the BAR address space can obtain the physical base address of the DMA channel register for DMA transmission, and the configuration space can read and write the PCIe configuration register of the DMA channel (such as DMA Channel Association Register), and store the PCIe device pointer information into the DMA management device (i.e., the dma_dev device) of the corresponding DMA channel to initialize the PCIe device pointer information of the DMA management device according to the number of DMA channels, and obtain the physical address of each DMA channel.

[0058] Secondly, identify the minimum physical address among the physical addresses of each DMA channel in all DMA channels to provide a unified reference point for subsequent memory mapping operations, so as to simplify the access logic of the user-space program to multiple DMA channels. At the same time, using the minimum physical address also helps to more efficiently manage the limited host system resources. For example, when mapping the DMA device to the user space, knowing the minimum physical address can help better plan the address space, ensure that the addresses between channels do not overlap, and make full use of the available address range. After identifying the minimum physical address, use the minimum physical address as the mapping start address dma_phys_addr_start of the BAR for subsequent mapping.

[0059] Thus, by initializing each DMA channel in the non-transparent bridge processor to ensure that the system can correctly identify, configure, and use these devices, efficient data transmission is achieved. Moreover, based on the minimum physical address as the mapping start address of the BAR, a unified reference point is provided to improve the management efficiency of the host system resources.

[0060] In step S203, determine the total sum of the BAR address spaces of all DMA channels in the non-transparent bridge processor, and map the mapping start address of the BAR and the total sum of the BAR address spaces to the virtual address space in the user state, so as to access each DMA channel through the user state.

[0061] Specifically, to enhance the flexibility, stability, and security of the host system and provide a solid foundation for applications in a high-performance computing environment, in the embodiments of the present application, by allocating and mapping the physical addresses of each DMA channel, multiple DMA channels can be enabled simultaneously for data transmission, enabling the system to process more data transmission tasks at the same time and improving the overall data throughput.

[0062] According to an embodiment of the present application, determining the total sum of the BAR address spaces of all DMA channels in the non-transparent bridge processor includes: determining the maximum supported number of DMA channels and the BAR address space of each DMA channel; calculating the total sum of the BAR address spaces of all DMA channels based on the maximum supported number of DMA channels and the BAR address space of each DMA channel.

[0063] Specifically, as Figure 3 shown, first, determine the maximum supported number of DMA channels (for example, 4 DMA channels) PLX_DMA_ENGINE_CHANNEL_MAX and the BAR address space PLX_DMA_ENGINE_BAR_SIEZE of each DMA channel, so as to calculate the total sum of the BAR address spaces of all DMA channels based on the maximum supported number of DMA channels and the BAR address space of each DMA channel, that is, calculate based on the product of the maximum supported number of DMA channels and the BAR address space of each DMA channel to obtain the total sum of the BAR address spaces of all DMA channels. The expression for the total sum of the BAR address spaces is PLX_DMA_ENGINE_CHANNEL_MAX * PLX_DMA_ENGINE_BAR_SIEZE, and map the mapping start address of the BAR and the total sum of the BAR address spaces to the virtual address space in the user state. In this way, the user state can access different DMA channels according to the mapping start address of the DMA engine and the BAR address space of each DMA channel, thus achieving efficient data transmission and resource utilization. At the same time, the flexibility, stability, and security of the system are also enhanced, providing a solid foundation for applications in a high-performance computing environment.

[0064] According to an embodiment of the present application, accessing each DMA channel through the user space includes: determining the first DMA channel among all the DMA channels, and marking the first DMA channel to obtain the management channel of the non-transparent bridge; initializing the management channel, and after the management channel is initialized, initializing the other DMA channels of the non-transparent bridge, and processing the hardware information and link status of the non-transparent bridge processor according to the initialized management channel and other DMA channels.

[0065] Specifically, after mapping the mapping start address of the BAR and the total BAR address space to the virtual address space of the user space, each DMA channel can be accessed through the user space. During the access process, the non-transparent bridge processor and its DMA channels need to be initialized in a certain order. First, determine the first DMA channel (DMA channel) among all the DMA channels, and mark the first DMA channel to obtain the management channel (admin channel) of the non-transparent bridge, and process the operations related to the hardware and link of the non-transparent bridge processor through the management channel (admin channel); secondly, initialize the management channel (admin channel), and after the management channel (admin channel) is initialized, initialize the other DMA channels of the non-transparent bridge, and process the hardware information and link status of the non-transparent bridge processor according to the initialized management channel (admin channel) and other DMA channels. That is to say, first initialize the first DMA channel, and monitor the status of the non-transparent bridge link through the management channel (admin channel) until it is confirmed that the link has been successfully established (LINK_UP). Once the management channel (admin channel) reports that the link is ready, then initialize the other DMA channels, that is, other DMA channels must wait until the admin channel is initialized and LINK_UP before they can work properly.

[0066] Thus, the first DMA channel is designated as the admin channel, which is specifically used to process the operations related to the hardware and link of the non-transparent bridge processor, so as to ensure the stability and reliability of the system. It not only guarantees the correct order of hardware initialization and link establishment, but also simplifies the design of the user space program, enabling developers to focus more on the implementation of application-level functions. In addition, it helps to optimize the use of system resources and prevent potential conflicts caused by concurrent access.

[0067] It should be noted that this application is applicable to non-transparent bridge processors that support multiple DMA channels, not limited to independent non-transparent bridge processors or on-chip non-transparent bridge processing units. This solution can give full play to the data processing capabilities of the processor hardware, significantly improve the bandwidth of the multi-controller interconnection system, reduce the latency of data transfer between controllers. At the same time, according to different processor packages, the pex_device data structure of the kernel driver and the DMA engine initialization logic are redesigned to give full play to the data parallel processing capabilities of the NTB hardware, thereby improving the performance of the multi-controller interconnection system.

[0068] This application also redefines the basic logic architecture of user-space programs that communicate using non-transparent bridge processors. When a user-space program transfers data through multiple DMA channels of a non-transparent bridge processor, it needs to specify the first DMA channel as the admin channel for handling NTB hardware events. Other DMA channels can only be used normally after the admin channel is initialized and LINK_UP.

[0069] According to the method for optimizing the latency of a network interconnection system proposed in an embodiment of the present invention, the BAR resource window size of the non-transparent bridge processor in the BIOS is adjusted based on the target processor firmware file, and the adjusted BIOS is reflashed to the BMC processor. Each DMA channel in the non-transparent bridge processor is initialized to obtain the physical address of each DMA channel, and the minimum physical address is identified as the mapping start address of the BAR. The mapping start address and the total BAR address space are mapped to the virtual address space of the user space, so as to access each DMA channel, solving the problem that the requirements of the overall bandwidth and low latency of the storage controller cannot be met when enabling one DMA channel. By enabling four DMA channels and mapping them to the user space, the data concurrent processing capabilities of the non-transparent bridge processor are improved, so that the bandwidth of the interconnection between controllers is higher and the latency is lower.

[0070] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases the former is a better implementation.

[0071] An embodiment of this application also provides a device for optimizing the latency of a network interconnection system.

[0072] Figure 4 is an embodiment of this application

[0073] such as Figure 4 shown, the device 10 for optimizing the latency of the network interconnection system includes: an adjustment module 100, an identification module 200, and a mapping module 300.

[0074] Among them, an adjustment module 100 is configured to determine a target processor firmware file of the non-transparent bridge, adjust the BAR resource window size of the non-transparent bridge processor in the BIOS based on the target processor firmware file, and re-burn the adjusted BIOS to the BMC processor;

[0075] An identification module 200 is configured to initialize each DMA channel in the non-transparent bridge processor to obtain the physical address of each DMA channel, identify the minimum physical address in the physical addresses of each DMA channel, and use the minimum physical address as the mapping start address of the BAR;

[0076] A mapping module 300 is configured to determine the total sum of the BAR address spaces of all DMA channels in the non-transparent bridge processor, and map the mapping start address of the BAR and the total sum of the BAR address spaces to the virtual address space of the user mode, so as to access each DMA channel through the user mode.

[0077] According to an embodiment of the present application, the adjustment module 50 includes:

[0078] A modification unit is configured to modify the DMA channel association register of the processor firmware of the non-transparent bridge based on a preset modification policy, and enable all DMA channels of the non-transparent bridge after the modification is completed;

[0079] A first acquisition unit is configured to adjust the initial BAR address space of the processor firmware of the non-transparent bridge based on all enabled DMA channels, and obtain the target BAR address space of the processor firmware of the non-transparent bridge according to the adjusted initial BAR address space;

[0080] A burning unit is configured to generate a target processor firmware file based on the target BAR address space, and re-burn the target processor firmware file to the target register of the non-transparent bridge.

[0081] According to an embodiment of the present application, before re-burning the target processor firmware file to the target register of the non-transparent bridge, the burning unit further includes:

[0082] An acquisition subunit is configured to acquire the digital signature of the target processor firmware file;

[0083] A judgment subunit is configured to verify the digital signature and judge whether the digital signature is consistent with a predefined digital signature;

[0084] A generation subunit is configured to, if the digital signature is consistent with the predefined digital signature, re-burn the target processor firmware file to the target register, otherwise, generate an error log and perform an exception reminder.

[0085] According to an embodiment of the present application, the identification module 200 includes:

[0086] A first initialization unit for initializing each DMA management device in each DMA channel according to each DMA channel in a non-transparent bridge processor.

[0087] According to an embodiment of the present application, the initialization unit includes:

[0088] A second acquisition unit for acquiring PCIe device pointer information corresponding to each DMA channel;

[0089] An initialization subunit for storing the PCIe device pointer information into the DMA management device of the corresponding DMA channel to initialize the PCIe device pointer information of the DMA management device.

[0090] According to an embodiment of the present application, the mapping module 300 includes:

[0091] A first determination unit for determining the maximum supported number of DMA channels and the BAR address space of each DMA channel;

[0092] A calculation unit for calculating the total sum of the BAR address spaces of all DMA channels according to the maximum supported number of DMA channels and the BAR address space of each DMA channel.

[0093] According to an embodiment of the present application, the mapping module 300 includes:

[0094] A second determination unit for determining the first DMA channel among all DMA channels and marking the first DMA channel to obtain the management channel of the non-transparent bridge;

[0095] A second initialization unit for initializing the management channel, initializing other DMA channels of the non-transparent bridge after the management channel is initialized, and processing the hardware information and link status of the non-transparent bridge processor according to the initialized management channel and other DMA channels.

[0096] In summary, for the description of the features in the corresponding embodiments of the latency optimization device of the network interconnection system, reference can be made to the relevant description of the corresponding embodiments of the latency optimization method of the network interconnection system of the network system, which will not be elaborated here one by one.

[0097] An embodiment of the present invention also provides an electronic device, which may include:

[0098] A memory 501, a processor 502, and a computer program stored on the memory 501 and executable on the processor 502.

[0099] When the processor 502 executes the program, it implements the latency optimization method of the network interconnection system of the network system provided in the above embodiments.

[0100] Further, the electronic device further includes:

[0101] A communication interface 503 for communication between the memory 501 and the processor 502.

[0102] The memory 501 is used to store computer programs that can run on the processor 502.

[0103] The memory 501 may include high-speed RAM memory and may also include non-volatile memory, such as at least one disk memory.

[0104] If the memory 501, the processor 502, and the communication interface 503 are implemented independently, the communication interface 503, the memory 501, and the processor 502 can be interconnected through a bus and communicate with each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of simplicity, Figure 5 only a thick line is shown in the figure, but it does not mean that there is only one bus or one type of bus.

[0105] Optionally, in a specific implementation, if the memory 501, the processor 502, and the communication interface 503 are integrated on a single processor, the memory 501, the processor 502, and the communication interface 503 can communicate with each other through an internal interface.

[0106] The processor 502 may be a Central Processing Unit (CPU), or an Application Specific Integrated Circuit (ASIC), or one or more processors configured to implement the embodiments of the present invention.

[0107] Embodiments of the present invention also provide a computer-readable storage medium storing a computer program, where the computer program is configured to execute the steps in any of the embodiments of the method for optimizing the delay of the network interconnection system of the above network system when running.

[0108] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: various media such as USB flash drives, read-only memory (ROM for short), random access memory (RAM for short), external hard drives, magnetic disks, or optical discs that can store computer programs.

[0109] An embodiment of the present invention also provides a computer program product. The above computer program product includes a computer program. When the computer program is executed by a processor, it implements the steps in any of the above embodiments of the method for optimizing the delay of the network interconnection system of the network system.

[0110] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Skilled professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0111] The above has introduced in detail a method for optimizing the delay of the network interconnection system of a network system provided by the present invention. Specific examples are used herein to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims

1. A method for optimizing the delay of a network interconnection system, characterized in that, The steps include: Determine the target processor firmware file of the non-transparent bridge, adjust the BAR resource window size of the non-transparent bridge processor in the BIOS based on the target processor firmware file, and re-burn the adjusted BIOS to the BMC processor; Initialize each DMA channel in the non-transparent bridge processor to obtain the physical address of each DMA channel, identify the minimum physical address among the physical addresses of each DMA channel, and use the minimum physical address as the mapping start address of the BAR; Determine the total sum of the BAR address spaces of all DMA channels in the non-transparent bridge processor, and map the mapping start address of the BAR and the total sum of the BAR address spaces to the virtual address space of the user state to access each DMA channel through the user state.

2. The method according to claim 1, wherein The determination of the target processor firmware file of the non-transparent bridge includes: Modify the DMA channel association register of the processor firmware of the non-transparent bridge based on a preset modification policy, and enable all DMA channels of the non-transparent bridge after the modification; Adjust the initial BAR address space of the processor firmware of the non-transparent bridge based on all enabled DMA channels, and obtain the target BAR address space of the processor firmware of the non-transparent bridge according to the adjusted initial BAR address space; Generate the target processor firmware file based on the target BAR address space, and re-burn the target processor firmware file to the target register of the non-transparent bridge.

3. The method according to claim 2, wherein Before re-burning the target processor firmware file to the target register of the non-transparent bridge, it further includes: Obtain the digital signature of the target processor firmware file; Verify the digital signature to determine whether the digital signature is consistent with a predefined digital signature; If the digital signature is consistent with the predefined digital signature, re-burn the target processor firmware file to the target register, otherwise, generate an error log and give an exception reminder.

4. The method according to claim 1, wherein The initialization of each DMA channel in the non-transparent bridge processor includes: Initialize the DMA management device in each DMA channel according to each DMA channel in the non-transparent bridge processor.

5. The method according to claim 4, wherein The initialization of the DMA management device in each DMA channel according to each DMA channel in the non-transparent bridge processor includes: Obtain the PCIe device pointer information corresponding to each DMA channel; Store the PCIe device pointer information in the DMA management device corresponding to the DMA channel to initialize the PCIe device pointer information of the DMA management device.

6. The method according to claim 1, wherein The determination of the total sum of the BAR address spaces of all DMA channels in the non-transparent bridge processor includes: Determine the maximum supported number of DMA channels and the BAR address space of each DMA channel; Calculate the total sum of the BAR address spaces of all DMA channels according to the maximum supported number of DMA channels and the BAR address space of each DMA channel.

7. The method according to claim 1, characterized in that The access to each DMA channel through the user state includes: Determine the first DMA channel among all the DMA channels, and mark the first DMA channel to obtain the management channel of the non-transparent bridge; Initialize the management channel, and after the management channel is initialized, initialize the other DMA channels of the non-transparent bridge, and process the hardware information and link status of the non-transparent bridge processor according to the initialized management channel and other DMA channels.

8. A device for optimizing the delay of a network interconnection system, characterized in that, Comprising: An adjustment module, configured to determine a target processor firmware file of the non-transparent bridge, and adjust the size of the BAR resource window of the non-transparent bridge processor in the BIOS based on the target processor firmware file, and rewrite the adjusted BIOS to the BMC processor; An identification module, configured to initialize each DMA channel in the non-transparent bridge processor to obtain the physical address of each DMA channel, and identify the minimum physical address in the physical addresses of each DMA channel, and use the minimum physical address as the mapping start address of the BAR; A mapping module, configured to determine the total sum of the BAR address spaces of all the DMA channels in the non-transparent bridge processor, and map the mapping start address of the BAR and the total sum of the BAR address spaces to the virtual address space in the user state, so as to access each DMA channel through the user state.

9. An electronic device, characterized in that, Comprising: A memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor executes the program to implement the steps of the method for optimizing the delay of the network interconnection system according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, wherein when the computer program is executed by a processor, the steps of the method for optimizing the delay of the network interconnection system according to any one of claims 1 to 7 are implemented.

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